Edn Design Ideas 2004

design
Edited by Bill Travis
ideas The best of
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5V power supply teams

low-dropout regulator, charge pump
Jim Christensen, Maxim Integrated Products, Sunnyvale, CA
uxiliary power of 3.3V is replacing
A the 5V auxiliary power that “silver

boxes”supply in most computer sys-
tems, but some circuits still require a 5V
TABLE 1—POWER-SUPPLY PARAMETERS WITH ALL 1-F CAPACITORS
VOUT
(V)
5.06
IOUT
(mA)
10
POUT
(mW)
50.6
IIN at VIN=3.3V
(mA)
20.9
PIN
(mW)
68.8
Efficiency VOUT low-dropout
(%)
73.5
regulator (V)
2.71
VRIPPLE
(mV p-p)
358
supply. Such systems impose the messy 5.01 20 100.2 41.1 135.6 73.9 2.86 312
task of creating a central 5V auxiliary 4.9 30 147 62.2 205.3 71.6 3.02 420
supply from the 3.3V auxiliary supply
and then routing 5V power throughout
the motherboard. An alternative exists, TABLE 2—POWER-SUPPLY PARAMETERS WITH ALL 3-F CAPACITORS
VOUT IOUT POUT IIN at VIN=3.3V P IN Efficiency VOUT low-dropout VRIPPLE
however, for systems in which only a few (V) (mA) (mW) (mA) (mW) (%) regulator (V) (mV p-p)
ICs need 5V: Employ inexpensive charge 4.99 10 49.9 20.37 68.8 74.2 2.63 154
pumps as low-power 3.3V-to-5V con- 4.99 20 99.8 40.4 133.3 74.9 2.76 104
verters and place them directly at the 5V 4.98 30 149.4 60.6 200 74.7 2.89 154
loads. Regulated charge pumps do this 4.93 40 197.2 80.5 265.7 74.2 3.02 192
job,but they are uncommon, and they of- 4.9 45 220.5 90.5 298.7 73.8 3.09 214
ten command a premium price. You can

build a regulated charge pump by com- for at least 7V, because an unregulated voltage regulator. The low-dropout reg-
bining an unregulated charge pump with charge pump can deliver 7V when its ulator, IC1, reduces the 3.3V input to a
a low-dropout regulator that reduces the 3.3V input goes to the upper limit of tol- lower value, and the unregulated charge
voltage to 5V. Unfortunately, that method erance. That fact eliminates the possibil- pump, IC2, doubles that value to 5V. To
requires a low-dropout regulator rated ity of using the latest low-cost, low- cancel the voltage drop that charge-
dropout regulators, whose pump output impedance causes, the cir-
3.3V small geometry limits their cuit feeds the 5V output back to the low-
INPUT
maximum input to 6.5V. dropout regulator, which alters its output
1 or 3 F 3
IN
You can reverse the order to maintain output regulation. The avail-
IC1 by placing the low-dropout able headroom of at least 1V allows out-
1
MAX8863
4 regulator in front of the put currents to approximately 30 mA or
SHDN OUT
charge pump, thereby re- even higher with larger capacitors. Al-
5
SET ducing the 3.3V to 2.5V be- though it requires two ICs instead of a
2 fore doubling it. That ap- single regulated charge pump, this ap-
proach allows the use of a proach can be cheaper because high-vol-
Figure 1
low-cost, low-voltage, low-
4 dropout regulator, but the
1 or 3 F 5V power supply teams low-dropout
IN charge-pump output im-
5 regulator, charge pump ..............................59
C1+ pedance then becomes an
2 5V AT
1 or 3 F
3
OUT
30 OR issue. A low-cost charge Four-quadrant power supply provides
C1– IC
2
1 or 3 F
30k 45 mA pump, such as the MAX- any-polarity voltage and current ..............60
MAX1683
1683, operating with 1-F
1 Simple circuit controls
10k capacitors exhibits a typical
stepper motors................................................64
output impedance of 35,
making it unusable at cur- Simple dc/dc converter increases available
This 5V supply, which you obtain by reducing the 3.3V input rents above a few milliamps. power in dual-voltage system ....................66
with a low-dropout regulator and doubling that output with a The circuit of Figure 1 Publish your Design Idea in EDN . See the
shows a better way to cas- What’ s Up sect ion a t w ww.edn .com.
charge pump, minimizes the charge-pump output impedance
by feeding 5V back to the regulator. cade the charge pump with a
www.edn.com J a n ua r y 8 , 2 0 0 4 | ed n 59

design
ideas
ume applications use unregulated charge a regulated-charge-pump circuit. capacitors are 3 F. As you can see, load
pumps and low-current, low-voltage, Table 1 demonstrates the circuit’s abil- current does not affect efficiency, which
low-dropout regulators. Furthermore, ity to maintain output-voltage regulation is approximately equal to the output volt-
because the low-dropout regulator and and deliver currents as high as 30 mA; the age divided by twice the input voltage.
charge pump are available in SOT-23 input, output, and flying capacitors are Capacitor values affect the ripple voltage
packages, the overall footprint of the cir- all 1 F. Similarly, Table 2 shows the reg- and available output current but have lit-
cuit in Figure 1 is comparable to that of ulation for output currents to 45 mA; all tle effect on efficiency.
Four-quadrant power supply provides

any-polarity voltage and current
Jon Munson, Linear Technology, Milpitas, CA
conventional power supply oper- the LT1970 power op amp to manage the ed 17V bulk power source (not shown).
A ates only in the first quadrant; posi- operation, thanks to its built-in, closed- You configure the user-control poten-
tive-voltage output and current are loop, current-limiting features.
sourced to a load or, with a deliberately
tiometers, VSET and ILIMIT, to provide
The four-quadrant supply provides at buffered command signals: VCONTROL and
miswired output,
17V
statically in the third IRF9540
+
quadrant as a “mi- 10 µF
0.1 µF 150 1 nF
35V 10k
nus” supply. The
conventional supply CURRENT-
1.5k
LIMIT LED
cannot,however,op- 330 pF
erate in either the
second quadrant as 7 TO VOLTAGE
3.01k 15 10k
DIGITAL PANEL METER
an adjustable load 8
VCC 16 +VIN
 EN 17 47 pF
for a minus supply, ICONTROL ISRC 19
CW ISNK 261
for example, or the VCSNK 12 V LT1970CFE V+ 3
10k CSNK V
fourth quadrant as a 10k 13 V
CSRC S
S+
2 100
discharge-testing a CW
FILTER 4
220 pF
OUTPUT
VCSRC 9 VEE 6 IRLZ24
battery with a specif- 10k
+
5
ic constant current, 10k
1, 10, 10
for example. It also 11, 20
cannot transition 2 µF 0.1 µF

3.01k 10k BAV99TA
seamlessly between VCONTROL
100 1 nF +
4.7 µF
the various modes as 50V
a function of load 17V
condition or control 10 µF 0.1 µF
RETURN
35V +
input. The circuit in 0.1
Figure 1 achieves full 1W VOLTAGE DIGITAL
CURRENT PANEL METER VIN
four-quadrant capa- COMMON DIGITAL PANEL METER
bility with an output VIN CURRENT DIGITAL
PANEL METER +VIN
topology simi-
Figure 1
lar to that of an
ordinary audio pow- You can obtain four-quadrant power-supply operation by using a power op amp in the output section.
er amplifier by using
a “complementary” pass-transistor con- least 16V adjustability with as much as ICONTROL, respectively ( Figure 2). You can
figuration. The complementary section 2A output capability. Figure 1 shows adjust VCONTROL from 5 to 5V, and the
may be the basic op-amp output in low- the basic LT1970-based regulator section. LT1970 regulator circuit amplifies it to
er current designs or use external power Figure 2 shows the user-control analog form the nominal 16.5V output range.
MOSFETs in cases involving higher pow- section, using an LT1790-5 reference and You can adjust ICONTROL from 0 to 5V; 5V
er. Controlling the output in the various an LT1882 quad-precision op amp. The represents the maximum user current-
modes is a simple matter when you use entire circuit operates from a preregulat- limit command. The VCSNK and VCSRC
60 ed n | J a n ua r y 8 , 2 0 0 4 www.edn.com

design
ideas
trimmers attenuate the ICONTROL signal to to compensating the op amp for minimal Schottky diode, such as a 1N5821 cath-
set the precise full-scale currents for sink overshoot under all loading conditions. ode, to the more positive connection, to
and source modes,respectively (Figure 1). As with most op amps, the LT1970’s in- the output binding posts. Alternatively,
A 0.1 resistor in the load return sens- ner- and outer-loop feedback accomplish you could use a disconnect relay and pow-
es the output current and provides the capacitive-load tolerance. In this situa- er sequencer in the design to protect the
LT1970 with feedback during current- tion, the op amp itself is resistively de- load from any energetic reverse transients
limiting operation. With this sense re- coupled from the load. The dc feedback during turn-on and turn-off of the main
sistance, setting the current-limit trim- for the LT1970 uses differential voltage bulk supply.
mers to 100% would allow the LT1970 to sensing to eliminate the regulation error An adjustable power supply is an in-
limit at approximately 5A,but,because that would otherwise occur with the cur- dispensable tool in any electronics lab. It
this application requires
a 2A maximum current,
CW
you set the trimmers to ILIMIT
1k 10
approximately 40% ro- 50k +
1/4 8 ICONTROL
tation when calibrated. LT1882
100k 9 _
To prevent internal con-
trol contention at low
output current, the LT- CW
VSET
1970 sets a minimum- 100k
1k
0.1 F
current-limit threshold 10-TURN 5
17V +
that corresponds to ap- 1k 1/4 7
VCONTROL
proximately 40 mA for 4 3 1 F 100k 6 _
LT1882
12 + 1/4
the sense resistance. An- 5V +
1/4 1
REFERENCE 14 LT1882
other nice feature of the LT1882 2 _
13 _
LT1970 is the availabili- 11
ty of status flags, which,
in this case, provide a 49.9k 49.9k
simple means of driving 17V
1k
a front-panel LED to in-
dicate when current- 0.1 F 5V REFERENCE
2k 4 6
limiting is active. The 17V LT1790-5
LT1970 features 1 F 1 F
split power con- Figure 2 1 2
nections that allow you

to power the internal
output section inde-
pendently from the ana-
log-control portion.The The user-control section allows you to set the voltage range and current-limit parameters for the output section in
flexibility of this config- Figure 1.
uration allows direct
sensing of the op amp’s output current rent-sense and lead resistances in series can be even more useful in many circum-
via resistance in the V (Pin 19) and V with the load. You can connect a pair of stances if it provides the ability to adjust
(Pin 2) connections. This feature gives a inexpensive digital panel meters to the continually through 0V to the polarity,
convenient means of establishing Class output to monitor the output conditions adjustably limit current, or both in either
B operation of the MOSFET-output de- in real time (Figure 1). (The two digital the source or the sink directions. These
vices using a current-feedback method, panel meters do not share “common”con- additional capabilities provide convenient
in which the op-amp output current is nections, which may complicate their methods of driving or loading circuits
converted to a gate-drive potential,there- powering.) Note that the selected current- that are under development or test that
by having the MOSFETs turn on only to sense resistance optimizes a digital-pan- might otherwise require very special or
the extent needed to help the op amp el-meter display with the usual 200-mV custom equipment, such as active-load
provide the output demand. full-scale sensitivity to present as much as units or dc-offset generators. You can
Because power supplies inherently 1.999A, for example. One word of cau- readily obtain these features if you base
must drive heavy capacitive loads— tion: When you use this supply in place the linear-regulator design on the versa-
namely, circuits with high-value bypass of a conventional single-quadrant supply tile LT1970 power op amp, which includes
capacitors—and any overvoltage could to power sensitive electronics, it’s good built-in adjustable- closed-loop current-
damage the circuit, pay careful attention practice to connect a reverse-biased limiting functions.

design
ideas
Simple circuit controls stepper motors
Noel McNamara, Analog Devices, Limerick, Ireland
tepper motors are
S
STEP 5V 12V
5V
useful in many con-
sumer, industrial, 5V
5 2 3 7 8
and military applica- 15
4 Q
tions. Some, such as per- J
sonal-transportation 13 14
11 8
systems, require precise IC1 10
GND 9 IC1 IC2
speed control. Stepper- 12
motor controllers can be
16 14
simple (Figure 1), but K Q
they require a variable-
MOTOR
frequency square wave 16 WINDING
for the clock input. The 9 11
J Q
AD9833 low-power
DDS (direct-digital-syn- 2
3 5
thesis) IC with an on- IC1
6 IC1
4 IC2
chip, 10-bit DAC is ideal 1
7
for this task, because you 12 10
K Q
need no external com-
ponents for setting the
clock frequency (Figure 13
2). The de-

Figure 1
vice contains
a 28-bit accumulator, NOTES: IC1: SN74HC86.
which allows it to gener- A stepper-motor controller requires only a few logic circuits. IC2: SN74LS76A.
ate signals with 0.1-Hz

resolution when you operate it with a 25- Figure 3 shows the complete sys- square wave that serves as the clock input
MHz MCLK (master clock). In addition, tem.The most significant bit of the on- to the stepper-motor controller. Writing
the circuit can easily stop the motor if you chip DAC switches to the VOUT pin of the to the frequency-control registers via a
program a 0-Hz output frequency. AD9833, thus generating the 0-to-VDD simple, three-wire interface sets the clock
AGND DGND VDD CAP/2.5V
ONBOARD
REFERENCE
MCLK REGULATOR
AVDD/ FULL-SCALE
COMPARATOR
DVDD CONTROL
2.5V
MULTIPLEXER
FREQUENCY 0 REGISTER 10-BIT

28-BIT PHASE 12 SIN
ACCUMULATOR  ROM
DAC
FREQUENCY 1 REGISTER
MSB
MULTIPLEXER
PHASE0 REG
PHASE1 REG DIVIDE
VOUT
BY 2
Figure 2 MULTIPLEXER
MULTIPLEXER 200
CONTROL REGISTER
SERIAL INTERFACE
AND CONTROL LOGIC
AD9833
F SYN C S CLK SDATA
The AD9833 DDS IC generates frequencies with 0.1-Hz resolution.

design
ideas
frequency. Writing a 0 to the frequency
VDD
register stops the clock,thereby stopping OV
the stepper motor.When you are not us-
ing the DAC, you can power it down by
writing to a control register. This pow- FSYNC
er-down action results in the AD9833’s SCLK VOUT STEPPER- STEPPER
MICROCONTROLLER AD9833 MOTOR
drawing only 2 mA from the supply. Re- SDATA MOTOR
CONTROLLER
ducing the MCLK frequency can further MCLK
reduce the supply current. The AD9833

is available in a tiny,10-lead pack-
Figure 3
age, so you can assemble the
complete control system on a very small The complete stepper-motor controller uses a DDS IC to generate the variable frequencies
pc board. for the circuit in Figure 1.
Simple dc/dc converter increases

available power in dual-voltage system
David Kim, Linear Technology, Milpitas, CA
he schematic in Figure 1 shows a
T way to increase the power available

from a current-limited 5V supply by
adding power from a 5V supply. The
5V,
300-mA
INPUT
C2
1
N=1:1
3
D1
MBRS140 12V,
150-mA
OUTPUT
R1 C1
dc/dc converter generates a single 12V, 4.7 F 11.3k 4.7 F
150-mA (1.8W) output from two regu- D2
6V ZENER  5V INPUT 2 4
lated and current-limited input sources
at 5V, 300 mA (1.5W) and 5V, 300 mA 6 5
(1.5W). Because the input uses VIN SW
different-polarity voltage sources, F i g u r e 1 3 2 Q1
SHDN FB
FMMT3906
the design uses a flyback dc/dc convert- LT1946
8 1
SS VC
er to avoid a system-grounding prob- R2
GND COMP R3 R4
lem. Level-shifted feedback sensing us- 100k 4 7 15k 1.24k
C3
ing a pnp transistor, Q1, references the C4
100 nF
feedback signal to the negative input –5V, 2.2 nF
voltage. You calculate the feedback-re- 300-mA

INPUT
sistor divider by using the formula
R 1R 4(VOUTVBE)/VREF, where R 1 con- Combining two opposite-polarity power supplies can increase the available power from a flyback
nects to the emitter of Q1, R 4 connects regulator.
to the collector of Q1, VBE is the base-
emitter voltage of Q1, and VREF is the the input capacitor and dc/dc regulator current-limited power supplies, you can
feedback reference voltage of the switch- input must be able to handle a maximum convert the two supplies into a single sup-
ing regulator. input voltage of 10V, resulting from the ply that has more power-handling capa-
To simplify the circuit,the flyback con- calculation VIN1(MAX)|VIN2(MAX)|. In bility than either of the two inputs.A fly-
verter in Figure 1 uses an LT1946 mono- an event of fault-current conditions, such back topology based on an LT1946
lithic switching regulator. The voltage as shorted input or output, a zener diode, monolithic converter offers a simple ap-
rating of the monolithic regulator has to D2, creates the undervoltage-lockout proach to the grounding problem and the
be greater than the maximum switching threshold to turn off the LT1946 when- feedback-sensing problem inherent in a
voltage of the flyback converter, calculat- ever either input source is in current lim- dual-input power supply. Sharing the
ed by [(VIN1|VIN2|)MAX VOUT(MAX)/(T1 it or the input voltage (VIN1|VIN2|) power between two input sources not
turns ratio)]VSPIKE. The maximum drops below 6V to help the input supply only adds output-power capability, but
switching voltage is approximately 25V recover when the fault condition is re- also increases the overall flexibility of the
for the circuit in Figure 1. Note also that moved. In a system with two available system.

design
ideas The best of
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Force/sense connection eliminates

multiplexer on-resistance error
Stephen Woodward, Marine Sciences, Chapel Hill, NC
igitally controlled gain is an the gain-setting multiplexer would be to Force/sense connection eliminates
D everyday analog-design element.

You frequently find this element in
an op-amp-based, transimpedance cur-
take the converter’s output directly from
the op amp’s output pin (IC1, Pin 6).The
trouble with this method is that the on-
multiplexer on-resistance error ..................79
Analog multiplexer uses
flying capacitors ............................................80
rent-to-voltage converter. When you de- resistance of the multiplexer would then FPGA-configuration scheme
sign digital gain control into such a con- be effectively in series with the selected is flexible ..........................................................82
verter, the usual scheme is to arrange feedback resistance. In cases such as this
things such that a digital multiplexer se- one, in which the feedback resistance Add fault protection to
lects the appropriate feedback resistor for ranges as low as a few hundred ohms or a 4- to 20-mA loop supply ..........................84
each gain figure. In Figure 1, op amp IC1 less, the resulting gain error can be large. Publish your Design Idea in EDN . See the
is connected in a typical topology but For example, the on-resistance of the What’ s Up sect ion a t ww w.edn. com.
with a twist. The normal way to arrange HC4052 in Figure 1 can exceed 100 .
1k* 47
OUT
15V
Figure 1
6 _ 8
10 µF 7
4.22k* 6V 1k* IC4
1k* 3.01k*
+ +
5 4
5V 15V +15
MCT4052 OP37 15V
2 7 GP 2 S2 4
4 _ _
1k LF353N
HEAT SINK 3 6 1
2 2 2k IC IC3
3 2
221 C 3 + 3 +
24V 7815 15V 51 V 4
D 390 pF 2
1 0 S1
0.1 200 kHz LF353N
+ + 100* 15V
47 µF 220 µF 39 F
+
11
25V 16V 3 B
9 66.5*
+
10 22 µF
402* A
+ 15 0.1 6V
220 µF 2 1.33k* S3
16V + 22 µF F
200* VE
16V 20k 7
16
1620* 14
5V
Q1 1 13
C
2N4403 5V
6.49k* HCT14
15V 12
0
13k* 15V IN914 6 14 5 4 3 2 1 1k
8 6 G0
MCT +
2 7
_ 22 µF 11 12 13 1k
BIAS 6 16V 8 9 10
220 + IC1 G1
µF Q2 MULTIPLEXER
3 7
6V 2k +
4 2N3094
DETECTOR 220 +
µF 15V
15V 10k 10k
6V
OP37GP GAIN S1 S2 S3
OR 1k
LT1028 15V 1 O C O
CN8 5V 2 C C O O=OPEN=OFF.
390 + 4 O O O C=CLOSED=ON.
220 µF 8 C O O
6V 16 O C C
32 C C C
GREEN 64 O O C
GND LED 128 C O C
+
+ + 220 µF 220 µF
47 µF 2.4k 6V
25V 16V NOTES: *=1% METAL FILM.
5V
24V 7915 15V
100 5.1k
15V
In this programmable-gain circuit, the on-resistance of the gain-setting multiplexer plays no role in the determination of gain.
www.edn.com J a n ua r y 2 2 , 2 0 0 4 | ed n 79

design
ideas
That figure is equal to that of the lowest result is a gain product that is insensitive gain, 128-to-1 (42-dB) manual-switch-
gain-setting resistor and, therefore, the to on-resistance. The remainder of the settable gain, approximately 200-kHz
source of 100% error. The obvious ap- circuit surrounding IC1 comprises a bandpass response, and approximately
proach, using larger resistors, works high-performance bias and preamplifier 700-nV rms input-referred noise of less
poorly when you need high-frequency circuit for a cryogenic (liquid-nitrogen- than 1 nV/Hz). One trick that helps
performance. The resulting RC delay cooled), mercury-cadmium-telluride in- achieve this noise performance, other
products can cause frequency peaking, frared detector. These broadband, pho- than the use of the superquiet LT1028 op
ringing, and, sometimes, outright oscil- toconductive optical sensors are popular amp for IC1, is the cascaded-inverter
lation. in IR spectrometers.They are particular- HCT14 structure. The HCT14s serve no
This Design Idea offers an approach ly popular in Fourier-transform-type purpose other than to block entry of
that makes the current-to-voltage con- spectrometers. Their popularity stems noise, which might be present on the
verter gain independent of multiplexer from their low noise, wide optical-wave- digital gain-setting lines, into the gain-
resistance. The idea is to use two multi- length responsivity, and electrical resetting-multiplexer circuitry. Without
plexers in a force/sense topology such sponse of faster than 1 MHz. these inverters, any such digital noise, a
that the output comes from the “force” Notable features of the circuit in Fig- common cause of gremlins in high-gain,
end of the selected gain resistance, rather ure 1, besides the force/sense gain-set- computer-controlled analog circuitry,
than directly from the op amp’s output. ting topology, include dynamic biasing could easily become capacitively coupled
Assuming that that the load presented to (via Q1 and Q2) of the MCT detector, 64- to the ac signal path.
the “sense”output is reasonably high,the to-1 (36-dB) digitally programmable
Analog multiplexer uses flying capacitors

Dick Cappels, Mesa, AZ
his Design Idea describes a
T way to increase the number of

analog inputs to your micro-
controller for cases in which
ATMEL
AT90S1200A
VDD 20
5V
adding an analog-multiplexer chip 0.33 F

or upgrading to a microcontroller R1 D1
with more inputs might be im- 100k 1N916
V1 14 PB3
practical. If the microcontroller
4.7k
you’re using has some spare I/O PB5 17
pins and at least one of them is C1 LED1
bidirectional or is amenable to 0.01 F
tristating,you can configure a sim-
ple analog multiplexer using
4.7k
switched capacitors. Figure 1 PB4 16
shows a two-input multiplexer. A LED2
12 +
typical switched-capacitor multi- PB0/COMP
5V
plexer completely disconnects the 
C2
capacitor from the sensed voltage 0.01 F
before sampling the voltage across R2
13 50k
COMP
REFERENCE
the capacitor. 100k
V2 VOLTAGE
To use a typical microcon- 15 PB2
D2 GND 10
troller’s I/O ports, one terminal of
1N916
the capacitor remains connected
to the input source through a
resistor. During most of the Figure 1
operating time, pins 12, 14, and 15
are configured as output pins and The LEDs in this circuit indicate when the sampled input voltages are above the reference voltage on
are held at logic 0. Diodes D1 and Pin 13.
D2 do not conduct, so capacitors
C1 and C2 charge to the values of the in- tors, pin 12 becomes an input, and the parator compares the voltage on Pin 12
put voltages V1 and V2, respectively. To pin associated with each channel switch- with the reference voltage. Listing 1,
sample the voltage stored in the capaci- es high while the microcontroller’s com- which is available on the Web version of
80 ed n | J a n ua r y 2 2 , 2 0 0 4 www.edn.com

design
ideas
5V
this Design Idea at www. With the 1-MHz con-
edn.com, gives the code frag- A troller in Figure 1, sam-
ment that samples the inputs. A pling time is a total of 6
The voltage on Pin 12 is A+ sec for the two channels;
V PIN12 V DD  V DIODE V IN , B
using a 16-MHz controller,
where VPIN12 is the voltage ap- B
the total sampling time
plied to the analog input of B+ would be only 375 nsec.
the comparator; VDD is the When you expand the cir-
power-supply voltage (5V in cuit for more inputs (for
12 +
this example); VDIODE is the example, using the four-in-
voltage across the 
put multiplexer in Figure
diode, and VIN is Figure 1 2a), you must take the ex-
the voltage applied to input of tra sampling time into ac-
(a)
the RC filter. During the sam- count. To maintain a low
pling of one input, the voltage duty cycle and thus allow
on the positive terminals of 5V the RC filters to charge to
the capacitors exceeds VDD; the full input voltage, the
thus, D1 and D2 are in series software should infre-
A
with microcontroller pins 14 quently call the sampling
and 15 to block voltages above B
routine. An interrupt every
VDD and prevent C1 and C2 2048 clock cycles calls the
from discharging into the C sampling routine in this
power supply. Also during example. The voltage at Pin
sampling, C1 and C2 are in se- D 12 in Figure 2a is inverted,
ries with the filter resistor of and, because of the isola-

the input undergoing sam- tion diodes, the maximum
+
pling, causing the capacitors 12 input voltage is a diode
to discharge through the re- drop below VDD (approxi-
sistor. For this reason, it is im- mately 4.4V). If you mul-
portant to keep the RC time (b)
tiplex both inputs, the cir-
constant with respect to the cuit compensates for both
sampling period. The worst- the polarity and the diode
case voltage error occurs in The technique lends itself to variations, such as switching sets of inputs (a) drop (Figure 2b). Listing 2
the second channel to be sam- and expanding to more than two inputs (b). in the Web version of this
pled,when both V1 and V2 are Design Idea (www.edn.
at 0V: where TSAMPLE is the time one of the com) gives the microcontroller assem-
diodes’ anodes switches to VDD (3 sec bly code for the multiplexer scheme. You
in this example). This sampling time can download the software from the
uses the assumptions R 1R 2, C1C2, Web version of this Design Idea at
and the fact that the sampling periods www.edn.com.
for each channel are the same.
FPGA-configuration scheme is flexible

Zhe Lou, Ghent University, Ghent, Belgium
PGAs are popular in circuit design advisable to put a large amount of exter- functions and keep others unchanged, it
F because of their flexibility and effi- nal memories near the FPGAs. The
ciency. You need to program an memory consumes a lot of area and in-
FPGA by loading configuration data into creases the difficulty of the pc-board lay-
is unwise to reprogram all FPGAs, be-
cause it takes a lot of time and can cause
unexpected problems in the related cir-
designated configuration memory. Be- out. Consider Xilinx (www.xilinx.com) cuits. This Design Idea describes how to
cause most FPGAs have no internal non- FPGAs. Xilinx offers daisy-chaining individually program multiple FPGAs
volatile memory, you must store the con- techniques to program multiple FPGAs with limited resources. It uses a serial
figuration files in external devices. When from a single source. However, when port of the Analog Devices (www.ana
you use many FPGAs in a design, it is in- you want to change only one FPGA’s log.com) ADSP21065L to arbitrarily

design
ideas
program four FPGAs (Figure CLK because the Init and Done
1). FPGA 1 are output signals from the
A DSP processor, the AD- FPGAs, which you cannot
CLK
SP21065L, serves as a micro- DATA
merge together. Therefore,
FPGA 2
controller to program the FP- PROGRAM the “buffer” you are look-
GAs. The configuration bus INIT SWITCHBOARD ing for should have multi-
ADSP21065L
DONE (74FST3253)
consists of the Clk, Data, Pro- plexing or demultiplexing
gram, Init, and Done signals. CONTROL FPGA 3 capabilities. This design
LOGIC
The output data from the uses the 74FST3253 dual
ADSP21065L is syn- FPGA 4 4-to-1 multiplexer/demul-
chronous with the Clk Figure 1 tiplexer bus switch from
B1
signal, and the Pro- On Semiconductor (www.
A B2
gram (output), Init (input), Separately programming onsemi.com) to imple-
S0 B3
Done (input),and two control FPGAs sometimes makes ment this function. By
S1 B4
signals (output) are the more sense than using a connecting two control
74FST3253
ADSP21065L’s I/O flags. The daisy-chain technique. signals to the two select in-
rest of the circuit comprises puts, S0 and S1, you can
four FPGAs from Xilinx. The arrows to some bidirectional buffers, for example, cause I/O Signal A to connect to I/O lines
the FPGAs represent the configuration 74LVT16245s, would seem suitable for B1, B2, B3, or B4, respectively, if the val-
bus. The trick is in the so-called switch- this requirement by linking the control ue of the two control signals are 00, 01,
board, which traces the configuration bus signals to OE and T/R pins of the buffers. 10, or 11.
to an FPGA according to the ADSP- But after taking a closer look at the sit-
21065L’s control signals. At first thought, uation, this approach would be difficult
Add fault protection to a 4- to 20-mA loop supply

Mark Pearson, Maxim Integrated Products, Sunnyvale, CA
4- to 20-mA current loop consists put,VOUT, can directly drive external me-
A of a power source and a current-

measuring device at the control end
and a field transmitter that senses
24V
DC
+
4- TO 20-mA
FIELD TRANSMITTER
0 TO
100˚
ters, strip-chart recorders, and A/D-con-
verter inputs.
The R 2-R 3 voltage divider sets the se-
process-variable information, such as _ lected fault-current trip point for IC1’s
4 TO
temperature or pressure, and converts it 20 mA
first internal comparator at 0.6V. Setting
CURRENT-
to a current (Figure 1). Most such indus- SENSE the trip point for a 50-mA fault, for in-
trial current loops are powered by 24V dc, RESISTOR stance, establishes the following relation-
but that voltage can range from 12 to 36V. ship between R 1 and R 2: R 2/(R 1R 2)
The loop voltage in older systems can be 0.6V/(R 1100IFAULT), so R 115.67R 2.
even higher. Many such applications re- When faults occur, the COUT1 output as-
quire current limiting, fault protection, sumes a high-impedance state and is
STRIP-CHART
or both. For example, a short circuit or RECORDER pulled high by R 3. The noninverting cas-
another high-current fault in one of sev- caded-transistor pair Q2-Q3 provides an
eral loops powered by a single source Industrial applications widely interface to the high loop voltage and
Figure 1
can produce a power-supply failure use the basic structure of a 4- preserves a proper logic polarity for con-
that disables all transmitters powered by to 20-mA current loop. trolling the gate of Q1. Q1 is held in the off
that source. Intrinsically safe loops,on the state until pushbutton PB1 or another re-
other hand,include a barrier module that er supply of a 4- to 20-mA loop.It also in- set signal resets IC1’s first comparator.(To
limits current and voltage to the trans- cludes circuitry for recovering a digital disable this comparator’s latched output,
mitter. Fault-protected sources can add signal superimposed on that loop. IC1, a tie the Reset# pin to ground.) Zener
another level of system safety. Setting a high-side current-sense amplifier with diode ZD1 protects Q1’s gate-source junc-
current limit on each loop lets you accu- comparator and reference, senses the loop tion from overvoltage.
rately size the power supply without overcurrent in R 1 as an 8- to 40-mV voltage IC2 and its associated circuitry can re-
specifying it. Figure 2 shows one form of and amplifies it by 100, producing an out- cover any digital information imposed on
flexible fault protection for the 24V pow- put-voltage range of 0.8 to 4V. That out- the 4- to 20-mA loop current by modu-

design
ideas
2
TO FIELD TRANSMITTER
24V DC R1
lation. The High- 4– TO 20–mA LOOP
way-Addressable Q1 2.2k 102k

ZD1
Remote Transduc- 5.1V
RFD10P03L
5V
er Protocol, for in- 5V _
stance, typically 5V
uses FSK (fre- 2.6k +
5V 10k IC2
quency-shift key- 0.1  F MAX4322
10k 10k 10k
ing) of 1200 to IC1
10k 10k 10 9 R2
2400 Hz to modu- RS RS R3
MAX4375 154k 10k
1 2
late the loop cur- +VCC VOUT
6 3
rent between the Q2
RESET# CIN1
7 4
0.5mA levels. 2N3904
8
COUT2 CIN2
5
(For this circuit, COUT1 GND
the modulat- Q3 PB1

Figure 2 2N3904
ed signal at FAULT RESET
LOOP RETURN
VOUT (Pin 2 of IC1)
is 0.1V.) VOUT DIGITAL-SIGNAL OUTPUT
from IC1 is capac-

TO PROCESS-INDICATOR PANEL OR ADC
itively coupled to
IC2 and amplified This circuit provides fault protection and digital-signal recovery for a 4- to 20-mA current loop.
by that device to
recover such digital signals. IC1 includes version in IC2’s digital-signal output. covered digital signal as a clean rectan-
a second comparator with inverting in- Though not essential, this comparator gular waveform for driving external cir-
put, which you can use to cancel the in- output (COUT2) can also present the re- cuitry.

design
ideas The best of
design ideas
www.edn.com
Double DAC rate by using mixers as switches

Randall Carver, Analog Devices, Greensboro, NC
ou can effectively double the ble the effective throughput of the over-
Y sample rate of a DAC by interleaving

two DACs into a single unit. Updat-
ing each DAC on an alternating basis and
all system. It is essential to overall per-
formance that you use a high-quality,
high-speed switch in the multiplexing of
Double DAC rate by using mixers
as switches ......................................................69
DDS IC plus frequency-to-voltage converter
switching to the appropriate output dou- the DACs’ outputs. The current-mode make low-cost DAC........................................70
DACs in this Design Idea allow for cur-
Low-noise ac amplifier has digital control
OUTP rent-steering implementation of the out-
of gain and bandwidth ................................72
OUTN
put switch. Current steering uses two dif-
ferential-transistor pairs cross-coupled in 1-kV power supply produces
the form of a four-quadrant multiplier a continuous arc ............................................76
SEL SEL SEL SEL
(Figure 1). In this topology, the satura- Publish your Design Idea in EDN . See the
tion voltages of the transistors are mini- What ’s Up sect ion at w ww.ed n.com .
mal, voltage swings are small, and switch-
INP INN ing speeds are high.
The 2.5-GHz AD8343 mixer contains circuitry internal to the AD8343 sets the
You can use cross-coupled a complete four-quadrant-multiplier dc voltage at the emitters to approxi-
Figure 1
differential transistor pairs as structure that you can use as a high- mately 1.2V, which in turn sets the com-
current-mode switches. speed, current-mode switch. The bias pliance voltage necessary at the DAC
5V
Figure 2
50
DATA BUS A D0-D9 IOUT INP
OUTP
IC1 IOUT
INN IC5
AD9731 IC3 AD8343
10-BIT, 90LV027A LOP 2.5-GHz MIXER
170M-SAMPLE/SEC CLK
10 OUTN
DAC REF_IN
CLK
CLK CA_OUT LON
CA_IN
50 RSET REF_OUT
1.96k
OUT
5V
50
DATA BUS B D0-D9 IOUT INP OUTP
IC2 IOUT IC4 INN IC6
AD9731 90LV027A AD8343
10-BIT, LOP 2.5-GHz MIXER
170M-SAMPLE/SEC CLK
DAC 10 OUTN
REF_IN
CLK
CLK CA_OUT LON
CA_IN
50 RSET REF_OUT
1.96k
“Ping-ponging” the outputs of two DACs effectively doubles the throughput rate.
www.edn.com F e b r ua r y 5 , 2 0 0 4 | ed n 69

design
ideas
outputs. With only a minimal drive sig- present a single-ended back-termina-
nal at the base connections,the emitters tion impedance of 50. This configura-
appear as a virtual ac ground. The re- tion allows the circuit to drive a re-
duced voltage swing at these nodes min- motely located, 100, differential load
imizes the effect of any parasitic capac- via two 50 coaxial cables. The low-lev-
itances. This Design Idea uses two el clock signals at the LO inputs come
AD8343 mixers as high-speed switches from high-speed LVDS buffers termi-
to multiplex the differential output cur- nated in resistances of 10. The ap-
rents derived from two AD9731 DACs proximate 3.5-mA p-p drivers pro-
(Figure 2). On the output side of the duce roughly 70-mV p-p drive at
mixers, the termination resistors allow the LO inputs. Figure 3 shows Figure 3
for a dc path to the supply, provide for that the circuit provides output rise and The circuit in Figure 2 produces outputs with
the current-to-voltage conversion, and fall times faster than 200 psec. less-than-200-psec rise and fall times.
DDS IC plus frequency-to-voltage converter

make low-cost DAC
Noel McNamara, Analog Devices, Limerick, Ireland
recision DACs are es-
P
VOUT
sential in many con-
sumer, industrial, and R3
military applications, but 1 14
high-resolution DACs can INPUT
CINT OFFSET 20k
be costly. Frequency-to- +
OP TRIM
voltage converters have 2
AMP
13 250k
R1 _
good nonlinearity specifi-
cations—typically, 0.002% 15V
for the AD650—and are in- 3 12
herently monotonic. This
0.1 F
Design Idea shows how you S1
can use a frequency-to- 4 11
AD650
voltage converter and a V
S 1 mA ANALOG
DDS (direct-digital-syn- GROUND
0.6V
thesizer) chip for precise 15V 5 10
V 500 560 pF
S
digital-to-analog conver- 0.1 F fIN
OUT
+
sion. The DDS chip gener- IN
ates a precision frequency FREQUENCY ONE 2k 500
6 9 5V
proportional to its digital SHOT OUT _
COS 1N914
input. This frequency COMPARATOR
serves as the input to a volt-
age-to-frequency converter, 7 8
thereby generating an 18-

bit analog voltage pro-
portional to the origi- Figure 1
nal digital input. Figure 1 This circuit shows the AD650 in a frequency-to-voltage configuration.
shows how the AD650 is
configured for frequency-to-voltage con- Resolution of 18 bits requires a pro- tor, which allows it to generate signals
version. With R 1R 320 k  and grammable clock source with a frequen- with 0.1-Hz resolution when you operate
COS620 pF, a full-scale input frequency cy resolution of 0.38 Hz (100 kHz/ it with a 25-MHz master clock. Figure 2
of 100 kHz produces a full-scale output 262,144). The AD9833 low-power DDS shows a block diagram of the AD9833
voltage of 10V. (See Analog Devices IC with on-chip 10-bit DAC is ideal for DDS chip. Figure 3 shows the complete
(www.analog.com) application note AN- this task, because setting the clock fre- system. The most significant bit of the
279 for more details on using the AD650 quency requires no external components. on-chip DAC switches to the VOUT pin of
as a frequency-to-voltage converter.) The device contains a 28-bit accumula- the AD9833, thus generating the 0V-to-
70 e dn | F e b ru a ry 5 , 2 0 0 4 www.edn.com

design
ideas
AGND DGND VDD CAP/2.5V
ONBOARD
REFERENCE
MCLK REGULATOR
FULL-SCALE
AVDD/ COMPARATOR
CONTROL
DVDD
2.5V MULTIPLEXER
FREQUENCY0 REGISTER 10-BIT

28-BIT PHASE 12 SIN
ACCUMULATOR  ROM
DAC
FREQUENCY1 REGISTER
MSB
MULTIPLEXER
PHASE0 REG
PHASE1 REG
VOUT
DIVIDE
MULTIPLEXER
BY 2
Figure 2 200
CONTROL REGISTER
MULTIPLEXER
SERIAL INTERFACE
AND CONTROL LOGIC
AD9833
FS YNC SC LK S DATA
This DDS chip generates signals with 0.1-Hz resolution from a 25-MHz clock.
VDD square wave that serves as the clock

FSYNC AD650
input to the AD650 voltage-to-frequen- SCLK VOUT fIN VOLTAGE- VOUT=0 TO 10V,
cy converter. Writing to frequency-con- MICROCONTROLLER SDATA AD9833
TO-FREQUENCY 18-BIT RESOLUTION
DDS
trol registers via a simple three-wire in- MCLK CONVERTER
terface sets the clock frequency,
thus programming the voltage out- Figure 3
put. This DAC system delivers 0 to 10V output with 18-bit resolution.
Low-noise ac amplifier has

digital control of gain and bandwidth
Philip Karantzalis, Linear Technology, Milpitas, CA
n low-noise analog circuits,a high-
I gain amplifier serves at the input to

increase the SNR. The input signal
level determines the input-stage gain; VIN
C1 R1
R2
C2
_
low-level signals require the highest gain. _
_
It is also standard practice in low-noise +
_ VOUT
+
analog-signal processing to +
Figure 1 +
make the circuit’s bandwidth GAIN-
as narrow as possible to pass only the CONTROL PGA
(GAIN A) BANDWIDTH-
CONTROL PGA GAIN=–1
useful input-signal spectrum. The opti-
(GAIN B)
mum combination of an amplifier’s gain
NOTES:
and bandwidth is the goal of a low-noise VOUT=(GAIN A)VIN.
design. In a data-acquisition system,dig-
1 1
<
_ BANDWIDTH < _ .
ital control of gain and bandwidth pro- 2 R1C1 R2
2 C2
vides dynamic adjustment to variations (GAIN B)
in input-signal level and spectrum. Fig-
ure 1 shows a simplified circuit for an ac This ac-amplifier configuration offers both gain and bandwidth control.

design
ideas
C1 R1 R2
VOUT
10 F 15.8k 15.8k
Figure 2
V V V
0.1 F 0.1 F 0.1 F
C2
1 8 8 1 8
1
1 F R4
2 IC1 7 2 IC2 7 2 IC3 7
LTC6910-1 LT1884 15.8k LTC6910-1
VIN 3 6 6 3
3 6
0.1 F R3 0.1 F
0.1 F
4 5 4 5 15.8k 4
5
GAIN BANDWIDTH
V CONTROL V V CONTROL
GN2 GN1 GN0 BW2 BW1 BW0

VOUT1VIN 0 0 1 BANDWIDTH1 TO 10 Hz 0 0 1
VOUT100VIN 1 1 1 BANDWIDTH1Hz TO 1 kHz 1 1 1
This detailed implementation of the circuit in Figure 1 operates with dual power supplies.
amplifier with control of 10 to provide high SNR. For ex-

both gain and bandwidth. ample, the SNR is 76 dB for
The amplifier’s input is a 0 a 10-mV peak-to-peak signal
BW2 BW1 BW0
PGA (programmable-gain with a gain of 100 and 100-
10
amplifier) providing gain Hz bandwidth or 64 dB for
control (Gain A). Following a 100-mV peak-to-peak sig-
20
the input PGA is a first-or- nal with a gain of 10 and 1-
der highpass filter formed 30 kHz bandwidth. With an
with capacitor C1 and input GAIN LT1884 dual op amp (gain-
resistor R 1 of an integrator (dB) 40 BW2 BW1 BW0 bandwidth product of 1
circuit. Inside the integra- 0 0 1 MHz), the circuit’s upper
tor’s feedback path, the gain 50 frequency response can in-
of a second PGA (Gain B) crease to 10 kHz by reducing
60
multiplies the integrator’s BW2 BW1 BW0 the value of C2. (The lower
3-dB frequency, thus pro- 70
1 0 0 3-dB frequency increases
viding bandwidth control. by reducing the value of C1.)
Figure 2 shows a com- 80 The circuit in Figure 2 oper-
plete circuit implementa- 1 10 100 1k 10k 100k
ates with 5.5V dual power
tion using two LTC6910-1 supplies. You can convert it
FREQUENCY (Hz)
digitally controlled PGAs to a single-supply 2.7 to 10V
and an LT1884 dual The frequency response of Figure 2’s circuit shows unity gain circuit by grounding Pin 4 of
op amp. The input Figure 3 and three digital bandwidth-control inputs. IC1, IC2, and IC3; connecting
LTC6910-1, IC1, provides a 1-F capacitor from Pin 2
digital gain control from 1 to 100 using The integrator’s digital gain control be- of IC1 to ground; and connecting Pin 2
a 3-bit digital input to select gains of 1, comes digital bandwidth control, which of IC1 to pins 3 and 5 of IC2 and Pin 2 of
2, 5, 10, 20, 50, and 100. The circuit’s low- provides an upper 3-dB frequency IC3. Figure 3 shows the frequency re-
er 3-dB frequency is fixed and set to 1 control of 10 Hz to 1 kHz. The circuit’s sponse of the circuit in Figure 2 with
Hz. A second LTC6910-1, IC3, is inside low-noise LT1884 op amp and LTC6910- unity gain and three digital bandwidth-
an LT1884-based (IC2) integrator loop. 1 (9 nV/Hz for each device) combine control inputs.

design
ideas
1-kV power supply produces a continuous arc
Robert Sheehan, Linear Technology, Milpitas, CA
esigning a high-voltage switch- through the transformer
D ing power supply that can produce

a sustained arc can be challenging.
This compact and efficient design deliv-
and rectifier, D1, by the
voltage across C 1. The
transformer is well-cou-
ers 1 kV at 20W and can withstand a con- pled, so the leakage in-
tinuous arcing, or short-circuit, condi- ductance creates little
tion (Figure 1). It uses standard, com- voltage spike. A small RC
mercially available components. R 1 sets snubber across the pri-
the LTC1871 switching-regulator con- mary winding damps the
troller for a nominal operating frequen- ringing and reduces EMI
cy of 120 kHz. The circuit operates as a (electromagnetic inter-
discontinuous flyback structure, produc- ference).
ing 333V across C1. The diode/capacitor For current-limit pro-
charge-pump multiplier triples this volt- tection, the circuit These are the switching waveforms for the circuit
age to create 1000V at the output. Figure in Figure 1 contains Figure 2
in Figure 1. Channel 1is the primary-switch volt-
2 shows the switching waveforms. When two active circuits and age at T , Pin 12; Channel 2 is the primary-switch current into Q
1 1
the primary switch, Q1, is on, the output one passive element. The drain (10A/division); Channel 3 is the secondary-switch voltage
rectifiers are reverse-biased, and energy is voltage across the cur- at T , Pin 2 (200V/division); Channel 4 is the voltage across R .
1 3
stored in the transformer, T1. When Q1 rent-sense resistor, R 2, (Secondary-switch current=2V/1.5=1.33A/division.)
turns off, energy transfers to the second- limits peak primary cur-
ary winding, and C2 and C3 pump up the rent to 7.5A. Q2 provides secondary-side 2 in Figure 2. This bump coincides with
output voltage through the rectifiers.The current limit. Notice the bump on the the positive excursion of the voltage
primary voltage goes high and is clamped leading edge of the current ramp of Trace across R 3 in Trace 4, which is the refresh
WARNING: LETHAL VOLTAGE POTENTIALS!
C2 C3
Figure 1
0.022 F 0.022 F R4
500V 500V 100
VIN 9 TO 18V DC D1 D2 D3 D4 D5 1 kVOUT
5W
1 T1 2
33
10 F 10 F 10 F 1/4W
4.99M
25V 25V 25V 12 11
220 pF 0.022 F 0.022 F
68.1k 200V 3 500V 500V
C1 0.01 F 0.01 F
4.99M 10 0.022 F 1500V 1500V
4 500V
100
1 10 9
RUN SENSE
5
2 9
ITH IC1 VIN
Q1
LTC1871 8
3 8 Si7456DP
FB INTVCC 6
1 nF
4 7
FREQ GATE
33k R1 Q2 7
220k VN2222
12.4k 5 6
MODE GND
6.8 nF
12.4k
R2
0.02 R3
4.7 F
1.5
NOTES: D1, D2, D3, D4, D5: MURS160.

T1: COPPER VP5-0155.
This circuit delivers 1 kV from a low-voltage input and can produce continuous arcing.

design
ideas
current for C2 and C3. 1000
When the circuit is over-
800
loaded, this slug of cur-
rent becomes high 600
enough to enhance Q2, VOUT (V)
400
folding back the load cur-
rent (Figure 3). A hard 200 12VIN
short circuit results in rel-
0
atively low power dissipa- 0 0.01 0.02 0.03 0.04
tion.Omitting Q2 for the
IOUT (A)
secondary-side current
Figure 3
limit results in substan- The circuit in Figure 1 has a foldback
tially increased short-cir- current-limiting characteristic.
cuit current and internal
power dissipation, resulting in failure of ging. (Yes, a hearty explosion elicits a
the primary switch Q1. R 4 provides a load round of applause from the lab crew.)
impedance for the power supply. Arcing is the most stressful condition,
This load helps to limit the peak-cur- and the output capacitor constantly
rent stress in the multiplier capacitors charges and discharges (Figure 4). As a
and diodes. Don’t skimp on the power final figure of merit, the circuit is effi-
rating for R 4, because dissipation during cient (Figure 5). The efficiency reaches
a continuous arc can be substantial. 87.3% at 12V input and a full load of
Should R 4 fail open, the feedback circuit 20W and increases to 87.7% with an
forces a full duty cycle with catastrophic overload of 24W.
results. Too low a value for R 4 can result So what is this circuit good for? A bat-
in charred circuits and hours of debug- tery-operated bug zapper,perhaps. And,
like raking a live wire
across a grounded file,
this is a great tool for be-
fuddling the AM-radio
listeners on the produc-
tion floor. The circuit
probably doesn’t deliver
enough energy for use as
an ion generator for a
plasma cutter, though
one engineer I knew was
willing to give it a try. A
previous version of the
circuit used a monolith-
Figure 4 These waveforms represent the output ic switcher, and with the
voltage of the circuit in Figure 1 when arcing occurs. right materials for ba-
nana jack and plug, cre-
90 ated a bright orange
85
glow and enough heat to
raise thoughts about the
80
fire extinguisher (plenty
EFFICIENCY 75 of ozone, too). I’d stay
(%)
70 away from using this cir-
65
12V
IN
cuit as a cat trainer or an
electric fence. The cir-
60
0 5 10 15 20 25 cuit does generate a
POUT (W) lethal voltage potential,
and lawsuits can be quite
Figure 5 The conversion efficiency of the costly.Prototype this cir-
circuit in Figure 1 is well over 85%. cuit at your own risk. 

design
ideas The best of
design ideas
www.edn.com
Solid-state relays simplify

monitoring electric-car battery voltage
Robert Krause, Fairchild Semiconductor, San Jose, CA
shows the propulsion sys-
F
igure 1
300V,
tem of an electric vehicle.It includes 100A MOTOR
DRIVE
MOTOR TRA NSMISSION WHEEL
BATTERY
an electric motor, drive electronics,
a mechanical transmission, vehicle con-
trol/power management, a charging sys- AC VEHICLE
MAINS CHARGING BRAKING
CONTROL
tem, and a battery. The long-term per-
formance of the electric vehicle depends
on ensuring the electrical health of
Figure 1
the battery and its charging system. OPERATOR
The battery system in an electric or a hy-
brid-electric car comprises a series con- The components of a typical electric vehicle include an electric motor, drive electronics, a mechani-
nection of 75 to150 individual 2V cells. cal transmission, vehicle control/power management, a charging system, and a battery.
This series connection generates a po-
tential voltage of 150 to 300V. The meas- 300V. This high dc potential requires the SSR(N1), where (N) is the cell number
urement of an individual cell’s terminal use of an isolated voltage-measurement you are currently measuring. You make
voltage creates a testing dilemma. The system.A microcontroller-based isolated Cell 1’s voltage measurement by closing
high electrical potential precludes the use voltmeter and isolated switch controller SSR 1 and SSR 2 and leaving all the re-
of standard differential op amps con- do not provide this function. The cell- maining 149 relays off, or open. Closure
nected across each cell. The measurement measurement system comprises a switch- of the two SSRs connects Cell 1’s positive
of each cell’s voltage entails using a ing array of 151 of Fairchild Semicon- potential to Node A of the absolute con-
switching network that interconnects an ductor’s (www.fairchildsemi.com) HSR- verter through the output of SSR 1, and
isolated or floating A/D converter be- 412 SSRs (solid-state relays), which pro- the cell’s negative potential to Node B
tween the two terminals of each cell in the vide an off-state blocking voltage of 400V. through SSR 2. You measure the second
string. A measurement method also Each relay is an SPST (single-pole, single- cell in the stack by opening SSR 1 and clos-
needs a switching system to sequence this throw), NO (normally open), optically ing SSR 3 while SSR 2 remains on (closed).
“voltmeter” across each of the 150 cells. activated switch. As little as 3 mA, or 5 This sequence connects Cell 2’s positive
The functional block diagram is an ex- mW, of LED-drive current energize these potential to Node B through the output
ample of an electric car’s battery system relays. This low turn-on power con- of SSR 2 and the cell’s negative potential
(Figure 2). The battery comprises a series sumption eliminates the need for relay- to Node A through the output of SSR 3.
connection of 150 2V cells. This config- driver ICs. The process then repeats until all cells
uration provides a combined potential of The first step in measuring the cell’s have been measured. At this time, the
potential is to connect
TABLE 1—THE ALTERNATING POLARITY OF THE A AND the isolated voltmeter Solid-state relays simplify
B NODES AS THE INDIVIDUAL CELLS ARE MEASURED across each cell. A clos- monitoring electric-car battery voltage ....83
SSR on SSR on er look at Figure 2 re-
Scheme provides high-side current sensing
Cell (positive cell (negative cell Voltage at Voltage at veals how to effect this
number terminal terminal) Point A Point B for white-LED drivers ....................................86
connection. The input
1 1 2 1 2
to the isolated volt- Simple technique makes low-cost
2 2 3 2 1 pc-board shields ............................................86
meter connects to a
3 3 4 1 2
two-wire measure- Lowpass filter has
4 4 5 2 1
ment bus. The termi- improved step response ..............................88
5 5 6 1 2
* * * * * nals of this bus are des- Fault-latch circuit
* * * * * ignated A and B. The protects switchers ..........................................90
148 148 149 1 2 test points across the Publish your Design Idea in EDN . See the
149 149 150 2 1 various battery cells are What’ s Up sect ion a t w ww.edn .com.
150 150 151 1 2 designated SSR(N) and
www.edn.com F e b ru a ry 1 9 , 2 0 0 4 | ed n 83

design
ideas
ISOLUTED VOLTMETER
voltmeter returns to Cell 1 and
restarts the process. SOLID-STATE-RELAY MATRIX
ABSOLUTE CONVERTER BLOCK MICROCONTROLLER
Table 1 shows the alternat- HSR412 CELL

ADDRESS
ing polarity of A and B wires as SSR(N) A _
the cells are measured. To +

ADC
measure the voltage of an in- 2V + MEMORY

V1 B
dividual cell (N), SSR(N) and –
_
SSR(N1) are energized and SSR(N+1)

+
all other SSRs are off, or open.
I/O PORTS
The alternating polarity of the 2V +
measurement lines requires the V2
–
addition of an absolute-value
converter between the bus lines EIGHT CHANNELS TWO CHANNELS
5V
and the microcontroller’s ana- ISOLATED
2V +
log-to-digital input. The mi- V3
– POWER SUPPLY
crocontroller controls the se-
HCPL2631 HCPL0600
quence of measurement
events. To measure a cell, the
microcontroller sends out a 8 2
DATA CAN BUS
discrete 8-bit digital address
corresponding to the cell being
measured. This address goes to
151 11 TIMES
a decoding block composed of 74HC154
2V +
11 74HC154 multiplexers. The V148
– DECODING BLOCK
data is transmitted through an
array of eight channels of high-
speed HCPL2631 optocou-
plers. The optocouplers pro- 2V +
V149
vide the common-mode vol- –
tage isolation between the

300V battery voltage and the
chassis ground. The dual- 2V +
V150
channel density of the HCPL- –
2631 optoisolator reduces
component count in the block
to four. The system addresses
the individual cells every 3
msec. This time is how long it
NOTE: N=CELL BEING MEASURED.
takes to turn on and turn off
the HSR412 SSR. A cell-
Figure 2 An SSR-based switch matrix allows you to measure individual cells in an electric car’s battery.
voltage measurement takes
place 600 sec after the cell has
been addressed. The SSR’s turn-on time ranges from 2 to 300V, depending on the value of the cell voltage and stores this
is less than 500 sec, thus permitting a cell under measurement. This 300V value and cell number in its onboard
100- sec acquisition time for the micro- common-mode voltage is well within the memory. At the conclusion of an entire
controller’s 10-bit A/D converter. The 400V off-state blocking voltage of the measurement cycle, the microcontroller
sum of the turn-on and -off times of an HSR412. The switch-matrix-control cir- formats the data to comply with a stan-
SSR times the number of cells measured cuits must also be able to accommodate dard automotive serial-bus format. An
determines the cycle time. When you use this 300V common-mode voltage. The example is CAN Bus. Once formatted,the
the HSR412, the measurement time for SSR easily solves this problem. The LED- data routes to the vehicle-control com-
150 cells is less than 450 msec. to-SSR switch isolation voltage is 4 kV puter via a bidirectional, optically isolat-
When you measure an individual cell, rms, which is more than adequate for a ed link. This link uses two high-speed
the V(N)-to-V(N1) bus potential is ap- 300V system. The 300V common-mode HCPL-0600 logic-compatible optocou-
proximately 2V. This figure is the differ- voltage requires that an isolated dc/dc plers. Once that data is received and ac-
ential-mode voltage. The V(N)-to- converter powers the microcontroller. knowledged, the measurement cycle can
V(N1) potential to chassis ground The microcontroller records the absolute repeat.
84 ed n | F e b ru ar y 1 9 , 2 0 0 4 www.edn.com

design
ideas
Scheme provides high-side current sensing
for white-LED drivers
Dimitry Goder, Sipex Corp, San Jose, CA
hite LEDs find Node 1. As a result, the
W
2.7 TO 5.5V
wide use in back- voltage across resistor R 2
lighting color-LCD matches the drop across
R1
screens in most portable 5 10 H R 1 and produces Q1 emit-
15
devices, such as cel- VIN 1% NODE 1 ter current that equals
Figure 1 1
lular phones,PDAs, SW VR1/R 2. This current
and MP3 players. Multiple 2.2  F R2 flows to Q1’s collector
SP6690
33.2k
LEDs often connect in se- PWM and creates a voltage
1%
DIMMING
ries to ensure that the same 4
SHDN
drop across R 3. The
MMDT3906
current flows through every boost-regulator SP6690
Q1 Q2
LED. To forward-bias these regulates the voltage
LEDs,a voltage of 10 to 16V 3
across R 3 at 1.22V, the
VFB
comes from an inductor- R3
IC’s internal reference
GND R4
based boost regulator, such 2 133k
1M
voltage. R 4 provides cur-
as an SP6690. However, 1%
VIN rent bias for Q2. The val-
white LEDs are behind the ue of R 4 allows the Q1 and
display, whereas boost reg- This circuit provides high-side current sensing for driving a string of white LEDs. Q2 collector currents to
ulators are on the main pc match. You calculate the
board, and it is important to minimize fect a “single”-wire connection.The sim- value of R 1 as follows: R 1R 3(V OUT
the number of interconnects. You can ob- ple circuit in Figure 1 shows the imple- VINVBE)/1.22, where V OUT is the com-
tain the best results if you implement mentation of the idea. bined LED forward voltage. The output
high-side and differential-current sens- R 1 acts as a current-sense resistor. The current is IOUT0.3A/R 1. The circuit in
ing. In this case,the boost regulator’s out- diode-connected Q2 level-shifts the volt- Figure 1 sets IOUT at 20 mA, but you can
put looks like a high-voltage true current age at Node 1 and applies it to the base adjust it by using a different R 1 value.
source. Of course, LEDs need to connect of Q1. These transistors come in one Note that you could return R 4 to ground,
to ground at some point, but it is unim- package and provide closely matched VBE but it instead connects to VIN. This con-
portant where they connect. For exam- voltage when they operate at the same nection removes quiescent current
ple, the display itself can locally pick up current. Because the V BE values match, the through the resistor and Q1/Q2 when the
ground. This approach allows you to ef- emitter of Q1 is at the same voltage as SP6690 is in shutdown mode.
Simple technique makes low-cost pc-board shields

Steve Hageman, Windsor, CA
any pc-board assemblies require from Hammond Manufacturing (www.
M shields to reduce susceptibility to

interference from electromagnet-
ic fields. A classic example is a radio re-
hammondmfg.com). These boxes come
in sizes from 22 in. to more than
74 in. You turn the project box Figure 1
ceiver, in which the front end usually into a shield by sandwiching the pc board
needs high isolation from the tuning syn- between the top and the bottom of the
thesizer. Historically, shields for low-vol- box, thus completely enclosing the sen-
ume or low-cost applications involve sitive circuitry.
trade-offs. You can’t justify the cost of a The basic idea is to choose a box that
custom-cast shield, and shields machined is big enough to fit the sensitive circuit-
from aluminum burn through money as ry that you want to shield. Then, lay out
fast as the end mills go dull. You can make the circuit in such a way that you can
a simple shield for just a few dollars by us- sandwich the board between the cover You should place a ground track on the top and
ing commonly available die-cast alu- and the body of the project box. To have the bottom of the pc board where the project-
minum “project boxes,” such as those a continuous ground around the lip of box shield sits.

design
ideas
the box, place a 1/8- to 1/4-in.-wide ground need to notch the box’s body with a mill
track all the way around the area where or file (Figure 2) to provide clearance to
the box will sit on the top and the bot- the resistor or traces. Note,however,
Figure 2
tom sides of the board. Then, add that this notch acts as a waveguide
mounting holes in the corner so that you for RF signals, so keep the following in
can assemble the box around the pc mind: The longest dimension of any gap
board and screw it together (Figure 1). should be much less than one-quarter of
To get signals into and out of the shield a wavelength at the highest frequency of
on a multilayer board is easy: Just use the interest. In high-performance shielding
inner layers and go under the ground work, strive to keep the gaps below one- You can mill small notches in the shield to pro-
track. On a double-sided board, you can twentieth of a wavelength. If you want to vide signal access. As a side benefit, you can use
break the track for traces, or—better “fill up”the gap, you can buy conductive the shield as a heat sink for TO-220 regulators.
yet—you can use a 0.25W resistor to foam or metal gaskets from 3M and WL
bridge the track. The 0.25W-resistor Gore (www.3m.com and www.gore. as a heat sink. By placing TO-220 regu-
method serves two purposes. First, it al- com); you can use these gaskets to fill in lators outside the box, you can attach the
lows a signal to get over the ground track any gap to make it electrically smaller. regulators’ heat sink to the enclosure.
without cutting it. Second, it is a perfect Likewise, any gaps in the box-to-pc- Thus, you have not only a shield, but also
place to add impedance to the signal line board contact as it sits on the ground a heat sink (Figure 2).
and hence obtain high-frequency filter- track also act as waveguides. Depending
ing. This method can help to prevent on the required frequency of operation, Reference
stray signals from getting into the sensi- these gaps may or may not cause a loss of 1. Ott, Henry, Noise-reduction tech-
tive circuitry you are trying to protect. shielding effectiveness (Reference 1).As niques in electronic systems, Wiley-Inter-
For both the methods mentioned, you a side benefit, you can also use the shield science, 1988, ISBN 0-471-85068-3.
Lowpass filter has improved step response

John Guy and Robert Nicoletti, Maxim Integrated Products, Sunnyvale, CA
common problem that arises when
A you design lowpass filters for signal

conditioning is the filters’effect on the
system’s time-domain response. Because
1
J
BNC
2
1
1
2
3
4
COM
IN
GND
IC 1
CLK
SHDN
OS
8
7
6
5
V cc
1
J
BNC
2
pushing the cutoff frequency lower slows VDD OUT

V
MAX7409 cc 2
the step response, the system may fail to
V
recognize significant changes within a rea- cc
C C 1 2
sonable amount of time.The circuit in Fig- Q 4

Q
V
3
27 nF 270 nF
2N3906 2N3906 cc
ure 1 accommodates lower cutoff fre- C 4
0.1 F  7
quencies without sacrificing the step- 3
+
1
response time. A window comparator R
4
– IC
3 2A
monitors the delta (difference) between 430 2 MAX966
V cc
the filter’s input and output. When the V
C cc
delta exceeds 50 mV, the filter increases R 0.1 F R
5
 5
2
10k
its slew rate by increasing the cutoff fre- R 4
430
7
6
+
quency by an order of magnitude. The 510k C
8 Q 5
3 5 2N3904
switched-capacitor filter,IC1, normally op- 1 nF – IC 2B
R 2 MAX966
erates as a self-clocked device. Capacitors 33k
1
C1 and C2 set the cutoff frequency at 0.1

Q Q
Hz, and other circuitry forms a dynamic 2N3904
1
2N3904
2
window comparator. Transistor

Figure 1
pairs Q1-Q2 and Q3-Q4 form a
complementary current mirror whose This lowpass filter maintains a fast step response by dynamically adjusting its cutoff frequency.
output flows through R 2 and R 3, creating
a delta of 50 mV. Connecting the output upper threshold at VOUT50 mV and the 312-Hz cutoff frequency that reduces
voltage to the center tap of the two resis- lower threshold at VOUT50 mV. sensitivity to momentary glitches. The fil-
tors centers the delta on the output voltage. R 4 and C3 provide lowpass-filtering to tered input drives the window compara-
You therefore set the window comparator’s the original input signal, producing a tor’s input. If that input is outside the

design
ideas
50-mV window, comparator IC2A or tom trace shows the filter’s unmodified
2.5V
IC2B asserts its output low. The low out- response. The optimized response in-
put drives Q5 into cutoff, causing its col- cludes a slight perturbation during the
lector to assume a high impedance. Be- cutoff-frequency transition, but is five 1.5V
cause Q5’s collector no longer grounds times faster than that of the unmodified
capacitor C2, the filter’s cutoff frequency circuit. The circuit in Figure 1 is config-
increases by a factor of 10. When the sys- ured for low cutoff frequencies,but
Figure 2
tem’s output changes to within 50 mV of you can rescale it for higher fre-
the input, the cutoff frequency throttles quencies by changing C1 and C2. You can
back to its quiescent state. Figure 2’s os- also modify R 2 and R 3 for different win-
400 mSEC/DIV
cilloscope photo shows the effect. The dow values,for which the delta equals the
top trace is a step from 1.5 to 2.5V, the resistance multiplied by 115 A. The These traces show the time-domain response for
middle trace is the output with opti- comparator must be an open-drain the circuit in Figure 1 with optimization circuitry
mization circuitry enabled, and the bot- type. (middle trace) and without it (bottom trace).
Fault-latch circuit protects switchers

Craig Varga, National Semiconductor, Phoenix, AZ
1
any power-supply designers like mine.If the output does not reach
M
5 mSEC
5V
to have a regulator latch off in the its normal operating voltage be-
2
event of an overcurrent situation or fore the Pin 5 voltage drops to less 5 mSEC
5V
other fault condition. Yet, many PWM than 3V, IC1 pulls its output low
controllers do not internally support this and latches the regulator off. 3
5 mSEC
2V
latch-off function. Most do, however, If, however, the output comes
have a power-good output and an enable into regulation before the latch 4
5 mSEC
function. The circuit in Figure 1 adds that times out, PGOOD goes high and C1 2V
latch-off capability at low cost in little ad- begins to discharge, raising the
ditional space.The design is based on the voltage on Pin 5 and keeping the
LMS33460, which is a power-supply supply enabled.R 2 provides a cou- 1 5 0.5V mSEC BWL
DCX10
1 mSEC/SEC
monitor in a tiny, five-lead SC-70 pack- ple of volts to IC1 to keep the IC 23 0.5V DCX10
0 .5 V D CX1 0 2 DC 2.4V STOPPED
age.You just need to combine it with a few alive in the event of a latch condi- 4 0 .5 V D CX1 0
small passive parts, and the circuit is com- tion,and D1 pulls down on the Figure 2
This circuit shows a normal start-up
plete. When the Enable Input signal goes PWM’s Enable when the sys- sequence for the circuit in Figure 1.
high, the voltage at the top of C1 rises tem-enable command switches
quickly to 5V. Because the output voltage low. C1 can be a small tantalum or 1
5 mSEC
is not yet alive, PGOOD stays low, charging ceramic capacitor. If you use a ce- 5V
C1 through R 1. Because the voltage on C1 ramic unit, choose a good dielec- 2
5 mSEC
is zero at the instant of turn-on, Pin 5 of tric,such as X5R.Also,the 5V sup- 5V
IC1 pulls up to 5V and begins to drop at ply’s rising in less than 1 msec or 3
5 mSEC
a time constant that C1, R 1, and R 2 deter- so may eliminate the Enable, and 2V
the whole circuit 4
5 mSEC
simply runs from the 2V
ENABLE
5V supply . Figure 2
C1 R2 DI
INPUT shows a normal start, 5 mSEC BWL
22 F
R
3k
1N4148 and Figure 3 shows 12 0.5V DC 10
0.5V DC 10
PGOOD 1 1 mSEC/SEC
start-up with the sec- 3 0.5V DC10 2 DC 2.4V NORMAL
PWM 1k 4 0.5V DC 10
ENABLE ond output of a two-
output regulator These traces represent start-up with
Figure 3
VIN IC1 VOUT shorted. In both the second output of a two-output
5 LMS33460MG 4 cases, the top trace is regulator shorted.
2 3
the system-enable
Figure 1 signal, the second trace is regulator’s output voltage. You can see in
IC1’s Pin 5, the third trace is Figure 3 that IC1’s Pin 5 decays to 3V, at
This circuit adds a latch-off function to PWM controllers lack- the PWM Enable at IC1’s Pin which point it pulls the PWM Enable low,
ing this feature. 4, and the bottom trace is the latching off the regulator.

design
ideas The best of
design ideas
www.edn.com
Circuit provides efficient fan-speed control

John Guy, Maxim Integrated Products, Sunnyvale, CA
s Moore’s Law plunges us into the conditions, the system is susceptible to
A
14
realm of multigigahertz processors failure when conditions deteriorate. If,
12
and PCs with gigabytes of RAM, en- on the other hand, you select the fan to
OUTPUT 10
gineers face the task of removing the maintain acceptable operating temper- VOLTAGE
heat that these state-of-the-art compo- atures under worst-case conditions, the (V) 8
nents produce. Cooling such systems fan may produce an annoying level of 6
poses a dilemma. If you optimize the fan sound. Controlling fan speed is the ob- 4
size and speed for nominal operating vious solution. If the system includes a 25 30 35 40 45 50 55 60
TEMPERATURE (˚C)
system-management bus, you can add
one of the many available sophis-
Figure 2
Circuit provides ticated ICs for controlling fan Output voltage for the circuit in
efficient fan-speed control ..........................69 speed. But if such a bus is unavailable, Figure 1 varies with temperature.
Simple circuit forms you need a stand-alone fan-speed con-
multichannel temperature monitor ..........70 troller (Figure 1). and increases to 12V at approximately
Power comes from the 12V supply, 47C (Figure 2). You can easily select the
PWM controller drives LEDs and a dc/dc converter, IC1, steps down ratio of resistors R 1, R 2, and RT1 by us-
from high-voltage lines ................................72 the input voltage to an intermediate volt- ing a spreadsheet. Note that thermistor
Circuit forms satellite-dish age for powering the fan. The transfer manufacturers’ tables of resistance ratio
command decoder ........................................72 function of this voltage is a function of versus temperature are easier to use than
resistors R 1 and R 2 and thermistor RT1. are the cumbersome equations for ther-
Use a microcontroller
The thermistor is an NTC (negative- mistor resistance.
to design a boost converter ........................74
temperature-coefficient) type, so the Because the circuit in Figure 1 does not
Publish your Design Idea in EDN . See the output voltage increases with increasing monitor fan speed or current, it includes
What’ s Up sect ion a t ww w.edn. com.
temperature. The output voltage is ap- R 3, C1, and D1 to ensure that the fan starts
proximately 5.5V at room temperature turning during start-up. The time con-
12V
1 1
2 2
3 39 F + L1 3
4 16V BEAD 0.1 F
0.1 F
OSCON 33 H
1 16 DT3316 + 180 F
CVH PGND OSCON
2 15
AIN SHDN 16V 1
3 IC1 14
IN LX 2
4 13
CVL MAX1685 LX 3
5 12
6
AGND BOOT
11 BEAD 0.1 F
REF STBY
7 10 MBRS130
FB ILIM
8 9
0.1 F 1 F 0.1 F CC SYNC
1
2
0.01 F
3
BEAD 0.1 F
15 pF R1
27k
Figure 1 D1 R3
1N4148 15k 1
12V 2
RT1 3
C1 + R2
10k BEAD 0.1 F
100 F 6V 47k
ALUMINUM NTC
ELECTROLYTIC
To control fan speed, thermistor RT 1 adjusts the output voltage of this dc/dc converter.
www.edn.com M a rc h 4 , 2 0 04 | ed n 69

design
ideas
stant of R 3 and C1 serves that purpose by portant criterion in selecting a dc/dc con- 1A output current, which is enough to
causing IC1’s output to overshoot during verter is the ability to operate at 100% drive one to four standard fans. As an
the first few seconds of operation. After duty cycle. IC1 satisfies that requirement added benefit, its high efficiency helps to
the fan starts, it easily sustains rotation and offers the convenience of an internal minimize the heat that the circuit re-
at the lower operating voltages. An im- power MOSFET. IC1 supplies as much as moves.
Simple circuit forms

multichannel temperature monitor
Susan Pratt, Analog Devices, Limerick, Ireland
ou can use an ADT7461 single-
Y
VCC
channel temperature monitor, an
ADG708 low-voltage, low-leakage D+ ALERT TO HOST
CMOS 8-to-1 multiplexer, and three 2N3906 2N3906 2N3906
standard 2N3906 pnp transistors to

ADT7461
ADG708
measure the temperatures of three sepa-
S1
rate remote thermal zones (Figure 1).
S2 SDA
Multiplexers have an inherent-resistance S3 D D– TO HOST
SCL
on-resistance; the channel matching and S4
flatness of this resistance normally results A2 A1 A0

in a varying temperature offset. The
ADT7461 temperature monitor in MULTIPLEXER CONTROL
Figure 1
this system can automatically can-
cel resistances in series with the external This system measures the temperatures of three remote thermal zones.
temperature sensors. The resulting sys-
tem is a multichannel temperature mon- their emitters connected together con- The ADT7461 measures the tempera-
itor. The resistance is automatically can- nect to the D input of the ADT7461, ture of the selected sensor without inter-
celled, so on-resistance flatness and and each of the base-collector junctions ference from the other transistors. Figure
channel-to-channel variations have no connects to a separate multiplexer input 2 shows the results of measuring the tem-
effect. Resistance associated with the pc- (S1 to S3). You effect the connection of perature of three remote temperature
board tracks and connectors is also can- the selected remote transistor to the D sensors. The sensor at address 000 is at
celled, thus allowing you to place the re- input by addressing the multiplexer, room temperature, the sensor at address
mote temperature sensors some distance which is digitally controlled by address 001 is at a low temperature, and the sen-
from the ADT7461. The system requires bits, A2, A1, and A0. The ADT7461 then sor at address 010 is at a high tempera-
no user calibration; therefore, you can measures the temperature of whichever ture. When you select no external sensor,
connect the ADT7461 directly to the transistor connects through the multi- the “open-circuit” flag in the ADT7461
multiplexer. plexer. register activates, and the Alert interrupt
The ADT7461 digital output asserts. You can
temperature monitor can 200 expand the system to in-
measure the temperature ADDRESS CHANGED HERE clude as many external
150
of an external sensor with ADDRESS =010 temperature sensors as
1C accuracy. The re- 100
you require. The limiting
mote sensor can be a sub- ADDRESS =000
factor on the number of
TEMPERATURE
strate-based or discrete (˚C) 50 external sensors is the
transistor and normally ADDRESS =001 time available to measure
0
connects to the D and 1 18 35 52 69 86 103 120 137 154 171 188 205 222 239 256 273 290 all temperature sensors. If
D pins on the ADT- –50 you require two-wire seri-
7461. In addition to the al control of the multi-
remote-sensor-measure- –100 REMOTE TEMPERATURE LOCAL TEMPERATURE plexer, you can use an
ment channel, the ADG728 in place of the
ADT7561 has an on- Figure 2 The ADT7461 measures the temperature of the selected sensor ADG708.
chip sensor. The diode- without interference from the other transistors with these results for ambient-,
connected transistors with hot-, and cold-temperature measurements.
70 ed n | M a rc h 4, 2 0 0 4 www.edn.com

design
ideas
PWM controller drives LEDs from high-voltage lines
Christophe Basso, On Semiconductor, Toulouse, France
owering LEDs from a wide L1 2.5/3.3/4.7161 mA.
P dc range—say, 30 to 380V—
without wasting a lot of
power in the regulating block, is
30 TO 80V DC 10 mH
D1
In this application, the line goes
as high as 380V dc. At steady state,
L1 and VIN dictate the on-time,
LEDS
a difficult task when the 1N4937 IN whereas the reset voltage applied
Figure 1 SERIES
LED current needs to be to L1 fixes the current decrease
constant. Dedicated LED drivers during off-time. This reset volt-
are available,but they usually im- 1 8
age, VFTOTAL , equals the total LED
VFB
plement boost structures and are 2 7 forward voltage plus the forward
IC1
thus inadequate for high-voltage 3 NCP1200A 6 drop of the freewheeling diode.
inputs. The NCP1200A, a high- 4 5
Q1 The total reaches approximately
voltage controller from On Semi- R IRF820 12V in this example. It can obvi-
R1 2
conductor (www.onsemi.com), 12k 39 ously vary,depending on the type
can serve as a constant-current of LED you want to drive, espe-
R3
generator if you add a simple coil C1 CVCC 4.7
cially with white LEDs that incur
470 pF
in series with a power MOSFET. 10 F significant forward drops of ap-
If you insert diodes between the proximately 3V. To help derive the
coil and the MOSFET, the circuit inductance value corresponding
becomes an economical light A high-voltage controller makes an ideal off-line LED driver. to your needs, a few lines of alge-
generator. Furthermore, there is bra suffice: tOFFL1(I/V FTOTAL)
no need for a transformer or any kind of voltage-feedback level; keeping it lower and tONL1(I/VIN), where I is the rip-
external supply, because the controller di- than 3.3V prevents the NCP1200A’s inter- ple current in L1, VFTOTAL is the previous-
rectly connects to the rectified high volt- nal short-circuit protection from tripping. ly described reset voltage, and VIN is the
age and thus supplies itself (Figure 1). In the example, the feedback voltage of dc input voltage.Because the circuit runs
The circuit forces a current to build up 2.5V thus imposes a peak current of in continuous-current mode, the sum of
in the L1 coil and the LEDs until the volt- on-time and off-timegives the switching
age developed across R 3 reaches VFB/3.3V. period of the 1200AP60:L 1(I/VFTOTAL)
At this point, power switch Q1 turns off, L1(I/VIN)1/f S, where f S is the switching
and the magnetizing current keeps circu- frequency. Extracting L1 yields L1(1/f S)
lating in the coil and LEDs,thanks to free- [(VFTOTALVIN)/(VFTOTALVIN)](1/I).
wheeling diode D1. To maintain a “clean” If you select a ripple current of 20 mA
current in the LEDs, L1 must be large peak-to-peak at 380V dc, then L1
enough to keep the ripple to an acceptable 16.6611.6509.6 mH.From this val-
value and to avoid pushing the controller ue, you can check the minimum on-time
to the minimum on-time (400 nsec) in using the equation: tON9.6mH0.02/
high-line conditions. Because of the poor 380508 nsec, above the minimum lim-
TRR (reverse-recovery time) of the it. Figure 2 portrays typical signals cap-
Figure 2
LEDs,you must add an external filter, tured on the prototype supplied with low
comprising R 2 and C1 to the IC’s internal The prototype with low line voltage pro- line voltage.
leading-edge-blanking circuitry.R 1 sets the vides these typical signals.
Circuit forms satellite-dish command decoder

Mark Giebler, Oakdale, MN
y decoding the commands sent protocol. The technique uses only the 1.5 msec and bit values as shown in Fig-
B by a direct-broadcast satellite re-

ceiver that uses the DISEQC (digi-
tal-satellite-equipment-control) proto-
coaxial cable between the receiver and
the dish to send commands for actions
such as changing the low-noise-block
ure 1, the timing diagram of bit modu-
lation on the coaxial cable. The signal’s
ac portion is a 22-Hz burst whose am-
col, you can troubleshoot the com- frequency range or switching between plitude ranges from 300 to 600 mV. A
mands or simply listen in. Eutelsat Corp dishes for multisatellite reception. The voltage-doubler circuit detects the 22-
(www.eutelsat.com) offers the DISEQC DISEQC protocol specifies a bit time of Hz portion, producing a pulse stream in
72 ed n | M a rc h 4 , 2 0 04 www.edn.com

design
ideas
ZERO DATA BIT ONE DATA BIT
which constant-voltage pulses until its value exceeds 120
having amplitudes of 0.6 to and then perform a loop
1.2V replace the 22-Hz bursts. while doing analog-to-dig-
Decoding this bit stream into ital conversions. If the loop
ASCII hex values is an ideal job count reaches 24 with
for a low-cost 8-bit microcon- 1 mSEC 0.5 mSEC 0.5 mSEC 1 mSEC ADC values greater than
troller. Using a microcontroller 120, the bit is a zero. If the
with onboard flash mem- pulse has gone away, the
Figure 1
ory,such as the NEC Elec- The DISEQC protocol specifies a bit time of 1.5 msec bit is a one. Any extra de-
tronics PD78F9418A (www. and these bit values. lay from executing in-
necelam.com), eliminates the structions in the loop has
need for external memory. The only ex- pulse. Set the A/D converter’s conversion little effect, because the bit windows leave
ternal components are a few discrete de- time to 28.8 sec and wait to detect a plenty of margin.
vices for the signal detector and the coax- pulse edge by reading the A/D converter
ial-cable loop-through (Figure 2). You
can add an RS-232 driver if you want to VDD
display the ASCII codes on a laptop com- 22-kHz VOLTAGE-
DOUBLING DETECTOR
puter via HyperTerminal. You can also SATELLITE IF
LOOP-THROUGH
use the PD78F9418A’s onboard LCD CONNECTORS
TO MICROPROCESSOR
controller to display the codes on a ded- ADC INPUT J1
icated display. F CONNECTOR
TO LOW-NOISE
FERRITE
One of the PD78F9418A microcon- 0.01 F BEAD
BLOCK
troller’s 10-bit A/D converters performs 10k 0.01 F
SIX TURNS
J2
pulse detection and acts as a simple
Figure 2 F CONNECTOR
timing device. Using a reference TO SET-TOP BOX
voltage of 5V, the converter provides ap- FERRITE

proximately 4.88 mV per step. An A/D- BEAD
SIX TURNS
converter conversion value greater than
120 counts (585 mV) represents a valid This circuit enables the microcontroller to decode the DISEQC-protocol bit stream.
Use a microcontroller to design a boost converter

Ross Fosler, Microchip Technology, Chandler, AZ
oost converters, like other and analog circuitry and makes it easier You can design a simple boost con-
B switchers, have traditionally re-

ceived their control signals from a
dedicated circuit. However, a recent trend
to build simple power supplies. The pro-
gramming capability of a microcon-
troller is an added benefit in power-sup-
verter with the following conditions:
VIN9V, VOUT18V, R LOAD72, F1/
T62.5 kHz, 70%, and VDROP50
is to integrate simple switching-power- ply designs, especially when you want to mV, where F is the switching frequency,
supply building blocks into generic de- experiment with the supplies. Figure 1 il-  is the efficiency,and VDROP is the out-
vices, such as microcontrollers.An excel- lustrates a simple boost-converter design put ripple voltage. You can calculate the
lent example of this concept is a using a microcontroller; the basic boost on-time, current, ramp-down time, and
microcontroller that combines digital topology in Figure 1 is a type of flyback the total period in terms of inductance:
circuit. The basic concept is
L
VIN
D
VOUT
easy to understand. When the
MOSFET, Q, turns on,the cur-
Q
RVF1
+
rent flowing through the in-
PWM ductor, L, begins to ramp up
VVF C
CONTROL linearly (Figure 2), resulting in
Figure 1 VIG energy storage in the inductor.
RVF2
RIF The MOSFET turns off before
the inductor saturates. At this
time, the inductor releases its Then, you calculate the peak current
This circuit block represents the basic topology of a boost energy to the storage capaci- through the inductor and the inductance
converter. tor, C, and the load. value:

design
ideas
gram. You may be able
tON t R tD IPEAK
to design an adaptive
power-control system by
adjusting the phase and SWITCH CURRENT
gain to meet the desired
Finally, you calculate the capacitance needs of a system.
based on the ripple voltage: Firmware placement
within the control loop
is not the only possibili- DIODE CURRENT
ty; you could use a com-
Note that the design is slightly altered bination of firmware
to use readily available components, by and hardware to moni-
using a 33-H inductor and a 220-F ca- tor the system. Be- These curves show the switch and diode
Figure 2
pacitor. The difference in the inductor cause the analog currents in the circuit of Figure 1.
value is absorbed in the dead time, as is information is visible
the power loss. and the analog functions are controllable change the functions without changing
The control circuit can take many within the PIC16C782 device, you can hardware. This approach eases experi-
forms, especially if you choose a device monitor an active system for perform- mentation; you simply changing
such as the PIC16C782 microcontroller. ance and function. In essence, the system firmware rather than spending hours in
This device integrates a built-in analog can have self-diagnostic capabilities to the lab adding or changing parts.
peripheral set, diverse analog visibility, check stability, load, input and output Figures 4 and 5 are oscilloscope pho-
and a mixed-signal PWM block. The conditions, or anything else a system may tos from a working example of the boost
control circuit in Figure 3 demonstrates require.You can also obtain Information converter implementing the basic topol-
how the analog and ogy in Figure 1 and the
pulse-width modulation control block in Figure 3.
is contained within –
The peak current in the in-
Figure 3
the PIC16C782, with ductor is 0.3 mV0.2
+ VI CURRENT
the exception of the FET TC4427 –
CONTROL 1.5A (Figure 4). The on-
driver. This control cir- TO POWER PSMC time is approximately 5.9
SWITCH DAC ADC
FIRMWARE
+ VV VOLTAGE
cuit combines analog CONTROL sec. The output voltage is
current control and 18V into a 72 load (Fig-
firmware voltage control. A microcontroller contains all the elements necessary for boost-converter ure 5). The efficiency is ap-
The interesting part is the control. proximately 90%. These
firmware, which is direct- boost-converter design and
ly in the voltage-feedback path of the about the system, through a serial port or control ideas are just a few of the many
control loop. Through firmware,you can some other means,by routing the data to possible ones using a PIC16C782 de-
alter the dynamics of the control loop by a terminal or computer display. Even bet- vice.
changing the functions within the pro- ter, the firmware allows the design to
A working example of the boost converter The example shows the duty cycle (top) and
Figure 4 Figure 5
implementing the basic topology of Figure 1 the output voltage (bottom) of the circuit in
shows the duty cycle (top) and the current-ramp-down waveform (bot- Figure 1.
tom) for the circuit in Figure 1.

design
ideas The best of
design ideas
www.edn.com
Motor uses simple reverse-battery protection

Dongjie Cheng, Allegro Microsystems, Warminster, PA
his Design Idea
T
POWER SUPPLY
presents a low-
side, reverse-bat- +
GND
tery-protection tech- _
V1
nique for a dc-motor VBB VIN VDRAIN VCP CP1 CP2
40V DC
system.The system in ENABLE GHA
100 nF Q0 Q1
Figure 1 incorporates CONTROL PHASE CA
MODE SA
INPUTS
two protection op- SR GLA
1 H
tions. The common RESET
GHB
A B
A3940 MOTOR
practice of using a VREG5 CB 100 nF
SB
diode for reverse-bat- 30k GLB
tery protection does C2 VDSTH
100 nF IDEAD VREG13 Q2 Q3
not work with dc mo- LONG FAULT
tors’ inductive loads. 20k OVSET
12k
GND LSS
In Figure 1, an Alle- 50k
10 F
gro (www.allegromi OPTION A
cro.com) A3940, a
low-cost power MOS-
FET controller,
drives a dc mo- Figure 1 OPTION B Q5 Q6 D1
tor. An H-bridge for

driving the motor Using MOSFETs instead of a diode for
comprises the n- reverse-battery protection prevents inductive-
channel MOSFETs Q0 kick problems in motor-drive circuits.
to Q3. To change the
motor’s direction from forward (current age, E, produced by a change in current ther Option A (solid line) or Option B
flowing from Phase A to Phase B) to re- is EL(di/dt), where L is the inductance, (broken line) to complete the circuit pro-
verse, the direction of current in the mo- and di/dt is the rate of change of the cur- tection. If you use Option A, remove Q5.
tor winding must reverse. This reversal rent. The induced voltage opposes any If you use Option B,you should cut open
means that Q0 and Q3 switch from on to change in current. Therefore, after the the bold trace marked “Option A.” In
off, and Q1 and Q2 switch from off to on. switches attempt a current reversal, cur- both options, Q6 is connected such that
For an inductive load, the induced volt- rent continues to flow forward (forced by its source connects to the H bridge, its
the induced voltage) from ground back to drain to the power-supply ground,and its
the power supply through Q2 and Q1.The gate to the VREG13 output (a regulated
Motor uses simple current gradually decays to zero and then 13.5V). At power-up, the body diode of
reverse-battery protection............................99 reverses direction. If a reverse-battery- Q6, D1, is forward-biased and provides
Simple setup tests bit-error rate ..............100 protection diode is present in the current the dc current path that allows the IC to
path, the decaying current is blocked and power up.As the VREG13 regulator pow-
Solar-powered motor runs
a large voltage can develop across the pro- ers up, it turns on Q6, which provides a
on 10 nA ........................................................102
tection diode. Thus, the normal current lower resistance path to ground than does
Photovoltaic switch disables recirculation meets interference. Further, the body diode, D1.Thus,Q6 connects the
unused LEDs ................................................104 the protection diode may break down, IC’s ground and the power supply’s
Boost converter works with and potentially destructive voltages can ground. In normal operation, the motor
wide-range negative-input supply ..........106 appear on the FETs and the IC. current in the H bridge can flow from the
Figure 1 shows how to implement re- power supply to ground or from ground
Publish your Design Idea in EDN . See the
What’ s Up sect ion a t ww w.edn. com. verse-battery protection using the n- back to the power supply through Q6. In
channel MOSFET, Q6, at the ground (low the case of a reverse-battery condition, Q6
side) of a power supply. You can use ei- stays off, because the VREG13 voltage is
www.edn.com M a r ch 1 8 , 2 0 04 | ed n 99

design
ideas
not available and the Q6 body diode, D1, not low enough. By opening the connec- Q6, and, in this configuration, you may
is reverse-biased,preventing any reverse- tion labeled Option A, you isolate the IC relax the on-resistance requirements for
current flow. ground from the potentially noisier con- Q6. Experiments have demonstrated that
We devised Option B because of a connection at the source of Q6. Q5 is config- both options work equally well if you
cern that switching noise may appear at ured and operates in the same fashion as carefully choose Q6’s on-resistance.
the IC’s ground if Q6’s on-resistance is Q6. Q5 can have higher on-resistance than
Simple setup tests bit-error rate

Israel Schneiderman, Rosslare Israel Ltd, Rosh Ha’ayin, Israel
raditionally, the reception quali-
T ty of a digital receiver is expressed in

terms of BER (bit-error rate). This
figure is the proportion of received bit er-
SQUARE
WAVE IN
rors in a given period. Typically, you

DELAYED
measure the BER in the lab by applying WAVE
an RF signal, modulated by a pseudo-
random code, to the receiver under test.
This Design Idea suggests an alternative SAMPLING
CLOCK
method based on the use of a simple
square wave.This method may not be su-
perior to the usual technique, but it is
RAW
simple to implement and gives a reliable DATA
result. The simplicity of the method is
based on the fact that it requires no com-
plex synchronization. Admittedly, a
square wave is not truly representative of SAMPLED
the data a receiver encounters in normal DATA
use (Figure 1). The square wave to mod-

ulate the RF carrier is phase-shifted to al-
DELAYED
low for the delay in the receiver. An ex- ONE BIT
clusive-OR gate produces a sampling
pulse at each bit transition—typically,
ERROR
10% of the data-bit width. This sample DETECT
pulse samples the raw data the receiver

generates, producing clean data.
Figure 1 This timing diagram illustrates the operating principles of a simple BER tester.
The key to understanding this
technique is to keep in mind that a string
of two successive ones or zeros indi- ceiver. Error pulses appear on the oscillo-
cates an error. A D flip-flop imple- scope. If you wish, for example, to set the
menting a 1-bit delay detects the error. RF level for a BER of 1-to-100,you reduce
RF UNIT
GENERATOR UNDER TEST You can display error pulses on an os- the RF level to the receiver such that, in a
cilloscope or count them by using a fre- 100-msec sweep you see, on average, one
RECEIVED quency counter. Figure 2 shows a typi- error pulse per sweep.
DATA
MODULATION
INPUT
cal test setup. You modulate the RF In Figure 3, IC1 and potentiometer P1
generator at the prescribed data rate. form the basis of an adjustable phase
ERROR Note that a 500-Hz square wave is shifter.R 2 provides hysteresis, and R 1, C1,
BER-TEST OUTPUT
FUNCTION BOARD equivalent to a baud rate of 1 kbps.Both and IC2 form a differentiator that pro-
GENERATOR
the modulating signal and the received vides a sampling pulse train. The first
data feed into the BER-test board. You flip-flop clocked by the sampling pulse
Figure 2 adjust the sampling signal to be near the makes a hard decision concerning each
end of the received-data pulse.In many bit. The next D flip-flop, together with
The BER tester uses a signal generator with digital receivers, this arrangement yields exclusive-OR gate IC2B detects the oc-
OOK (on/off-key) modulation. a fair approximation to a correlation re- currence of two successive identical bits.
100 ed n | M a r ch 1 8 , 2 0 04 www.edn.com

design
ideas
R1
VCC VCC
22k
VCC
220k R2
4.7k
220k IC2A
0.1 F 47k C1 1
8 3
1 nF 2
P1 3
+ CLOCK
1 74HC86
10k
3 1 2
– IC1
1k LM393
SQ_IN 22 nF 4
2 VCC
VCC
1k
VCC
VCC IC2B
14 10 3
5 CCV RP R3 ERROR
6 12 9 2
IC4A 4 D Q
14 10 IC2B 14 4 CLOCK 11 8 10k
CLK Q Q1
CCV RP CCV RP 74HC86 1
12 9 2 5 2N222
DNG LC
D Q D Q
CLOCK 11 8 C LO CK 3 6 7 13 74HC74
DATA_IN CLK Q CLK Q
VCC
DNG LC DNG LC
7 13 74HC74 7 1 74HC74
VCC VCC
Figure 3
The simple BER tester uses an adjustable phase shifter and a differentiator.
This situation constitutes an error. A fi- under test was a Melexis (www.melexis. implementing OOK. Most RF generators
nal D flip-flop and a transistor ensure com) TH7122 at 868.35 MHz in the provide AM.Thus, you must remove 3 dB
that the Error output is clean. The con- OOK-modulation mode. Adjust the RF from the displayed RF value. You can use
struction of the system follows the circuit level to vary the error rate. This design this technique for other types of binary
diagram in Figure 3. It sets an HP8647 RF obtains an RF level of 107 dBm for a 1- modulation, such as FSK (frequency-shift
signal generator at 868.35 MHz, and a to-1000 BER and 108 dBm for a BER of keying), for example.
function generator provides OOK 1-to-100, levels consistent with the data
(on/off-key) modulation. The receiver sheet. You should take care when you’re
Solar-powered motor runs on 10 nA

Stepan Novotill, Victoria, BC, Canada
esigns for solar-powered appli-
D cations with low-duty-cycle re-

quirements can often rely on ca-
pacitors for energy storage in place of less
C2
10 nF
1N4007 1N4007
Q1
reliable batteries.Typical applications in- 2N4403 R2
100
Q4
clude solar positioning, telemetry trans- 1k 2N4403
FOUR- OR
mitters, chemical pumps, data loggers, EIGHT- +
C1
and solar-powered toys. The circuit in ELEMENT 10V Q3
CALCULATOR ENERGY 4700 F 2N4403
Figure 1 can run a small pager motor SOLAR CELL STORAGE R3
from the output of a small calculator- 1k M
type solar cell in near darkness. The cir- +
SMALL
cuit works by repeatedly charg- Q2
PAGER
ing a 4700-F capacitor, C1, to F i g u r e 1 SMALL 2N4401 MOTOR
GREEN
1N4007
1.75V and then dumping the charge into LED
the motor. Only the self-leakage current

of the solar cell limits low-light opera- By repeatedly charging a storage capacitor and then dumping its charge into a small motor, this
tion. The circuit itself has such low leak- circuit can run the motor on only 10 nA of current.

design
ideas
age currents and trigger-current require- Q2. However, the nanoamp-magnitude ac because of the voltage loss in the emit-
ments that it can run the motor on 10 nA disturbance at the collector of Q2 couples ter-collector junctions of Q1 and Q3.The
of current if you use a low-leakage ener- into the base of Q1 via C2, causing fierce 100 resistor and the reverse charge on
gy-storage capacitor. Transistors Q1 and regenerative action. You achieve nano- C2 drive Q1 into cutoff and another en-
Q2 form a regenerative pair similar to a amp triggering and charging of C1 ergy-storage-capacitor charging cycle be-
thyristor. The 1N4007 diodes take the through the use of leakage diodes in place gins. Substitute a blue LED for the green
place of pullup and pulldown resistors, of pullup resistors, through isolation of one or add diodes in series with the LED
and the diodes bypass the leakage current the load at the start of regeneration, and to increase circuit-firing voltage beyond
of the transistors and LED. through the dc isolation of Q1’s bias volt- 1.75V. You can use 10-M resistors in
As the C1’s charge approaches 1.75V, age from the collector of Q2 at start of replace of 1N4007 diodes to improve noise
the green LED starts to conduct, causing generation. As regenerative action con- immunity if you don’t need less-than-1-
Q1 to turn on and feed current to the base tinues, a dc latching path appears be- A operation. Capacitors become leaky
of Q2. The amplified base current appears tween the base of Q1 and the collector of if you leave them in storage. You may
as a disturbance at the collector of Q2. Q2 through transistor Q3. At this point, need to condition such capacitors by ap-
The emitter-base drop of output transis- output transistor Q4 also enters satura- plying a 9V battery to the capacitor for a
tor Q4 isolates the collector of Q2 from the tion, and the motor runs. few days. Use two solar panels in series
output transistor, and the emitter-base- The high motor load quickly dis- to provide enough voltage for very-low-
drop of Q3 and the 10-nF capacitor, C2, charges C1 toward 1.1V, at which point Q1 light operation.
isolate Q2 from the dc bias at the base of can no longer sustain regenerative action
Photovoltaic switch disables unused LEDs

Lance McBride, Monterey Bay Aquarium Research Institute, Moss Landing, CA
n many applications, it’s desirable to
I disable LEDs used for system verifica-

tion. Many options are available for the
disabling function, including manual
12V
1 PHOTODIODE
12V
750
1%
0.25W
3.3V
60.4
1%
0.1W
VS
SPST (single-pole single-throw) switches, WITH
SSL-LX15GC-RP-TR SSL-LX15GC-RP-TR
3 AMPLIFIER NC1
enhancement- and depletion-mode 8
V–
NC2
COMMON
MOSFETs, bipolar-junction transistors, 2
IN– 1M_FDBK
and JFETs. The circuit in Figure 1 auto-
OUTPUT
matically disables the LEDs when a me- DRTN
G G
chanical housing encloses the circuit card, OPT101P-J IRLML2803TR

IRLML2803TR
thereby preventing you from accidentally 10k

0.1%
leaving the LEDs on to waste power. The 0.1W
main switch portion of the circuit
comprises an amplified photovolta- Figure 1
ic cell (photodiode) and a small, n-chan-
nel MOSFET. The amplified photodiode This circuit configuration turns off unneeded LEDs when it’s dark.
signal provides drive to the MOSFET’s
gate when enough light is available. Be- plifier, the circuit can function in both be 8.7V when the switch is off. This re-
cause the photodiode generates its own bright and dim applications. I use mul- verse voltage exceeds the absolute max-
power from the available light, the ampli- tiple MOSFETs for unique voltage imum rating for many LEDs. If you need
fied photodiode IC consumes only mi- ranges in which the LED would suffer to control status LEDs using a micro-
crowatts in a unity-gain configuration. damage from excessive reverse-bias volt- controller or some other logic-level de-
Originally, I considered using a series ages. This precaution is important in a vice, add another MOSFET between the
string of photodiodes to directly drive design with multiple power-supply volt- LED and the light-switch circuit. This
the MOSFET’s gate. However, the inte- ages. For instance, if you used only one configuration allows the light switch to
grated OPT101 design provides reliable MOSFET to control the LEDs in a de- act as a master on/off switch and the
operation under a number of light con- sign using 3.3 and 12V supplies, the re- logic device to act as a secondary on/off
ditions. If you adjust the gain of the am- verse voltage across the 3.3V LED would control. 

design
ideas
Boost converter works
with wide-range negative-input supply
Mike Wong, Intersil Corp, Milpitas, CA
L1
ssume that a design requires posi-
A
10 H D1
tive voltage,but only a negative-volt- VOUT
5V
age power source is available. Using C1 R4 C2
10 F 1k
a standard boost-converter IC in the cir- 1 PGND LX 10 47 F
R2
cuit of Figure 1, you can efficient-
Figure 1 C4 37.5k
ly generate a positive voltage from 2 SGND VDD 9 0.1 F
a negative source. The boost converter R3 Q1 Q2
generates an output voltage that’s higher 100k EL7515

VIN 3 RT FB 8
than the input voltage. Because the out- –2 TO –12V C3 R1 R5
20 nF
put voltage—5V in this example—is 10k 40k
4 EN SS 7
higher than the negative-input-voltage
ground level, the circuit does not violate
5 LBI LBO 6
the boost-converter principle. The circuit
in Figure 1 uses the EL7515, a standard
boost converter. The ground pins of the By using its ground terminals as the negative-voltage input, a boost converter can efficiently gener-
converter IC connect to a negative-volt- ate a positive output voltage.
age input source. Ground becomes the
“positive”input source. VOUT is as follows: with the nominal input-voltage applied. boost converter’s internal power FET
VOUTVFB(R 2/R 1)1.33V (37.5k / Figure 2 shows the line-regulation re- drain-to-source breakdown voltage
10k )5V. The Q1 and Q2 pnp transis- sults. The maximum output-to-input (VDS). For the EL7515, the maximum VDS
tors form a translator that scales the 5V voltage difference must be within the is 18V. For the 5V output, the minimum
output voltage (referred to (most negative) input voltage is
5.1
ground) to a feedback voltage 5.08
12V. A 1V safety margin com-
referred to the negative input. 5.06 pensates for the D1 diode drop
The transistor pair also elimi- 5.04 and any voltage spikes on the
nates temperature-change and 5.02 drain of the power FET. Figure 3
V 5
voltage-drop effects.As the neg- (V) 4.98
OUT
shows the load-regulation test re-
ative input voltage decreases,Q2 4.96
sults. The maximum output cur-
runs at an increasingly higher 4.94 rent is a function of the input-to-
current than Q1, causing addi- 4.92 output voltage ratio and cur-
tional transistor-offset mis- 4.9
–14 –12 –10 –8 –6 –4 –2 0 rent-limit setting of the boost
match. V (V) IN
converter. As Figure 4 shows, the
For optimal line regula- Figure 2 circuit yields greater than 80% ef-
tion, you should set Q1 and Q2 The line regulation is within 40 mV over the full range of ficiency at 200-mA output.
to operate at the same currents negative inputs.
4.98 82
81
4.975 80
79
4.97
78
77
VOUT 4.965 EFFICIENCY
(%) 76
(V)
4.96 75
74
4.955 73
72
4.95 71
0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 350 400
Iout (mA) IOUT (mA)
Figure 3 Figure 4
The output voltage varies by less than 14 mV over the full The efficiency of the circuit peaks at 81% for medium output
range of output currents. current (200 mA).

design
ideas The best of
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Positive feedback yields fast amplifier

with precision dc offset
Steve Woodward, Chapel Hill, NC
ome signal-processing applica- quency device that befits the dc circuit it
S tions require a high-speed, low-

noise, dc-coupled amplifier that in-
corporates a precision dc-offset ad-
occupies. But the mismatch between the
frequency responses of IC2 and IC1A cre-
ates the need for the novel topology of
Positive feedback yields fast amplifier
with precision dc offset..................................91
justment. Examples include oscillo- Figure 1. An obvious way to couple IC1A Buck regulator forms high-power,
scopes, in which the offset adjustment and IC2A, which might seem to allow the inverting  5V supply ..................................92
typically acts as a “position” control), addition of dc offset,would be to omit R 1, Low-loss circuit powers solar lantern........94
ADC-input gain blocks, and scanning- R 2, R 5, and C1 and simply connect IC1A as
ion-beam-microscopy deflection circuit- a unity-gain buffer providing the termi- RC network quashes auxiliary winding
ry. Figure 1 illustrates the circuit con- nation for the gain-set resistor, R 3. Un- in quasiresonant converter..........................98
cepts. Op amp IC2A is a 70-MHz, fortunately, this scheme wouldn’t work, Low-power CMOS oscillator has
high-slew-rate device configured with a because the output impedance of the push-pull output ..........................................100
fixed gain of 3 (9.5 dB) and a 10V pre- pokey IC1A starts rising at frequencies far Publish your Design Idea in EDN . See the
cision offset adjustment. Op amp IC1A below the capabilities of the speedy IC2. What’ s Up sect ion a t ww w.edn. com.
buffers and thereby linearizes the offset This drawback would ruin the high-
potentiometer. IC1A is a low-cost,low-fre- frequency performance of the composite
R4*
2k 20 X
OUT
10V
12V X GAIN
2
IC2B 1
CCW 2.5k CW V2 3
4
R7 R10* R5*
0.1 F R3*
402 0.1 F 150k
1k 12V
8
6 12V R1*
7 R11*
V1 IC2A
IN 5 200 4990
3600
X R8*
R2*
825
X.5 C1 100 X AND Y 5V VR1=VR2=
2
ADJ 1 OFFSET VR1
R9* 1 F V3 LM4040 –5
IC1A 3
470k 500 CCW 12V
R6 CCW
20k 20k
X10
ADJ 2k
100* 14 12 CW CW
IC1B VR2
13
1 F –5V LED
1k*
4990* 3600
Y GAIN
Figure 1 2 –12V
IC3B 1 12V
CCW 2.5k CW 3 –12V
7824 OFF
12V R10* 4 R5* 0 1
0 ON
402 0.1 F 150k +
100 F 2N4401
12V 16V
10k
0.1 F R11* 20k + DC
2k* 20 Y 100 F
200 OUT 0.01 F INPUT
8 35V
6 10V
IC3A 7
5 4 24V
IN
NOTES:
7 0.4A
Y IC1C
IC1=LM324. 6
825* 11 62
IC2, IC3=LT1364. 5
1W
100 F 2N4403
FOR 0.1- F BYPASSES
16V 20k
470k 500 ON LT1364 SUPPLIES, USE
SEVERAL IN PARALLEL.
*=1% TOLERANCE. –12V
In this circuit, positive feedback makes it possible to obtain wide-range dc offset without compromising bandwidth.
www.edn.com A p r il 1, 2 0 0 4 | ed n 91

design
ideas
amplifier. You could (partially) avoid this components than for ac. The circuit compromising the LT1364s’ 20-MHz ca-
problem by using another LM1364 in avoids this effect by using positive feed- pability, the control potentiometer, R 7, is
place of the LM324, but the result would back that R 1 and R 5 provide. connected such that its resistance element
be a significantly noisier circuit because The dc gain that R 1 and R 5 provide gen- serves two circuit functions. The left half
of the summation of IC1A’s output noise erates a compensation-voltage compo- forms a variable-gain (1 to 3.330 to 10.5
with the signal at point V2. This Design nent that nulls the voltage drop across R 2. dB) feedback network around IC2A. The
Idea offers a different approach, in which This action cancels the tendency of the right half forms a variable-loss (1 to
C1 provides a robust, low-impedance ter- R 3C1 node to track IC2A’s input and makes 0.1670 to 15.5 dB) circuit. The net re-
mination for R 3, and the R 2C2 time con- IC2’s output accurately equal to sult, when you combine it with the fixed
stant isolates the signal path from noise VOUTV2(1R 4/R 3)V3(R 4/R 3)3V22 9.5-dB gain of IC2A, is an overall gain vari-
originating in either IC1A or the VR 1 and V3. The rest of the schematic illustrates the able from (015.59.5)6 dB when
VR 2 voltage references.Unfortunately, this use of the offset circuit in a dual-channel you adjust R 7 to one extreme to
approach creates a problem arising from amplifier. In this amplifier, the variable- (10.509.5)20 dB when you adjust
R 2’s dc resistance. C1 holds down the bot- gain front ends incorporate a pseudolog- R 7 to the other extreme. IC1C finishes the
tom end of R 3 for ac-signal frequencies arithmic gain adjustment spanning gains gain-block subsystem by generating
higher than 1 kHz or so. But near dc, R 2 of 0.5 to 10 (6 to 20 dB). To achieve tracking 12V rails, by splitting the
and R 3 tend to sum, and the summing ac- this wide gain-control range with a sin- ground of the 7824 24V regulator. This
tion would make the closed-loop gain of gle-turn potentiometer and maintain rea- regulator uses as its source an inexpensive,
IC2 approximately 10% less for dc-signal sonable adjustment resolution without unregulated wall-socket power supply.
Buck regulator forms

high-power, inverting 5V supply
Bruce Denmark, Maxim Integrated Products, Sunnyvale, CA
onfiguring a step-down switch-
C
12V
ing-converter IC as an inverter
yields an efficient, high-power, 4.7 F
5V supply that can of deliver currents 10
20
as high as 4.5A at the 12V input or 3.2A –5V
10 F
13 14 10 F 10 F 10 F
at the 5V input (Figure 1). Convention- 4.7 F V+ VL
CENTRAL
SEMICONDUCTOR
al inverting power supplies do their VCC 12 CMPSH-3 LOW ESR
SHDN* 4
switching using a p-channel MOSFET SKIP* 20
SYNC 8
(Figure 2). That configuration works
17 FDS9412
well at lower currents, but has limited use BST
18 FAIRCHILD
DH
above approximately 2A, depending on IC1 2 H
0.1 F PANASONIC 0.008
the input and output voltage levels and MAX1663 1W
1 2
LX 19
the MOSFET you use. If you compare a ETQP6F2R0
N2
standard buck circuit with the circuit in FDS6680
15 FAIRCHILD
Figure 1, you can see that the converter’s 3 DL STPS2L250
RESET* ST MICROELECTRONIC
“output”in Figure 1 connects to ground, R1
CSH 1
and what used to be ground becomes the 1 F

CSL 2
10k
7 FB 3
5V output (Figure 3). Because the on- REF
6
resistance of an n-channel MOSFET is CC R2
lower than that of a comparably sized p- 1500 pF 2.80k
channel device, a power supply with n- 5

OVP
channel MOSFETs usually provides GND PGND GND
9 16 10
more current at higher efficiency. To turn
on, however, an n-channel device re- 470 F 470 F 470 F 470 F –5V, 4.5A
quires a gate voltage approximately
LOW ESR
4V higher than the source voltage, Figure 1
which is usually the supply voltage.
The circuit in Figure 1 achieves high By configuring this high-power dc/dc step-down converter as an inverter, you can obtain 4.5A at
output current and high efficiency by re- 5V from a 12V input or 3.2A at 5V from a 5V input.
92 ed n | A p r il 1, 2 0 0 4 www.edn.com

design
ideas
POSITIVE VIN
VIN
Figure 2 V+ SHDN OVP
VL
NEGATIVE VCC
VOUT
VL IN
EXT
Figure 3
MAX1846 CC DH
MAX1847
BST
COMP CS LX
MAX1636
DL
FREQ PGND SKIP

PGND
SYNC
CSH
REF FB
GND
GND CSL
REF FB
RESET TO MICROPROCESSOR
GND
This conventional inverting power supply uses a relatively

inefficient p-channel MOSFET. IC1 in Figure 1 normally operates as a high-power buck converter.
configuring a high-power buck convert- small penalty on maximum output cur- (www.maxim-ic.com).The kit includes a
er, IC1, as an inverter, thus exploiting an rent.) Input and output ripple voltages small pc board with optimized layout
all-n-channel design. Efficiency is 90% directly relate to the input and output ca- and all components necessary for oper-
with a 12.35V input, 5.02V output, and pacitors’ ESR (equivalent series resist- ating the MAX1636. Because the board’s
4.7A load. The efficiency is 84% with a ance),so you should carefully select these layout is similar to the one required in
4.56V input, 5.02V output, and 3.3A capacitors. Circuit layout is also ex- Figure 1, the kit can serve as a rough lay-
load. You can easily accommodate 5.2V tremely important, as for all dc/dc con- out guide for this Design Idea.
applications by changing the values of R 1 verters. You may want to consider the
and R 2. (Operation at 5.2V incurs a MAX1636 evaluation kit from Maxim
Low-loss circuit powers solar lantern

Ramsesh Kumar, Bangalore, India
he solar-lantern circuit in Figure as a reliable, compact, portable light load condition, the discharged battery
T 1 is a low-loss configuration that uses

a 7W, four-pin CFL (compact fluores-
cent lamp) and a 12V, 7-Ahr, sealed, main-
source and in urban areas as an emer- voltage is approximately 12.2V. Hence,the
gency-lighting system. The shunt charge- circuit provides a deep-discharge reset
controller circuit comprises IC1, a low- level of 12.3V to avoid oscillations. Red
tenance-free battery. The inverter features current, voltage-reference 2.5V LM385, LED1 indicates a low-battery condition.
greater-than-85% efficiency, less-than-2- and IC2, an LM324 comparator. IC2A,with IC2B with resistors R 9 through R 14 and
mA quiescent current, and a shunt-charge resistors R 1 through R 8 and transistor Q1, transistor Q2 provides protection against
controller with deep-discharge and over- provides protection against deep discharge overcharging the battery. Q2 switches on
charge protection for the battery. The low of the battery.
quiescent current and the deep-discharge The circuit switches off the TABLE 1— WINDING DETAILS FOR TRANSFORMER
and overcharge protection ensure long life load, including the inverter Start pin End pin Wire gauge Turns Inductance
for the battery. The preheating feature in and the lamp, when the battery 2 1 26 21 28 mH
the inverter avoids the blackening of the voltage falls below 10.8V and 3 4 26 21 28 mH
end of the CFL,thereby ensuring long life. thus protects the battery from 6 10 38 380 17 mH
The circuit finds application in rural areas deep discharge. Under a no- Core: EE25/13/7

design
ideas
and shunts the solar array when the bat-condition. Green LED3, along
TABLE 3— WINDING DETAILS FOR INDUCTOR L 1
tery voltage exceeds 14.8V and thus pro-with IC2C and resistors R 15
Wire gauge Turns
tects the battery from overcharging. Q2 through R 20, provides an indi-
26 100
turns off when the battery voltage dropscation of charging.
Core: Ferrite rod, 5-mm diameter, 25 mm long.
below 12.5V and thus enables battery Tables 1, 2, and 3 give core
charging. D2 is a reverse-blocking diode.
and winding details for the magnetic kHz.Q6, along with resistors R 29, R 30,and
It prevents the discharge of the battery
components in the circuit. The inverter R 31 and capacitor C10, forms the pre-
through the solar cells when the cells are
uses a Class D, push-pull, force-driven heating circuit. In addition to the 12V, 7-
not generating electricity. Amber LED2 topology with MOSFETs as switching Ahr sealed,maintenance-free battery,the
indicates that the battery is in full-charge
devices. IC3, an SG3524, drives the in- circuit uses a 10W, 12V single-crys-
verter. The force-driven top- talline-silicon solar-cell panel. The
TABLE 2— WINDING DETAILS FOR INDUCTOR L 2 ology ensures trouble-free recorded backup time is approximately
Start pin End pin Wire gauge Turns Inductance start-up in all environmental eight to 10 hours for a fully charged bat-
1 2 27 215 8.2 mH conditions. The switching fre- tery with a light output of 370 lumens
Core: EE25/13/7 quency is approximately 26 using a 7W, four-pin CFL.
SOLAR BATTERY
D1 IN4007 R12 R14
470k 5
5W IN5408
R6 R8 D2
R9 R11
R1 R2 1k 3.3k 10k 5
100k
100k 100k LED1 +
7 + +
BATTERY
RED IC2B
R10 12V
6 Q2 _
2 _ 4 R7 2.2k _ _
VREG R13 7 AHR
MJE
R4 1 S1A 3.3k Q1 1k SOLAR
IC2A 3055
10k BC557 PANEL
3
+ LED2 12V
C1 IC1 11 10W
R3 AMBER
10 F LM385 26k A VREF
25V 2.5V
R5 X
L1 L2
470k V1 T1
1 2
LM324
SOLAR BATTERY IC2 S1B 2 3 6
BATTERY C5
R15 R18 D3 C6
FUSE + C2
180k 180k IN4007 10 µF 6.8 µF
1A 1000 µF 1 2kV 2kV
25V
12 R20 4
+ C3
14 1k 0.47 µF
IC2C
13 Q3 LAMP
_
R16 R21 IRFZ44 CFL
100 LED3 C4 7W/
10
GREEN D 0.47 µF FOUR
R19 D21 PIN
R17
180k R22 R23 C7
180k
100k D22 10 1 nF
E 1 kV
Q4
V1 RELAY
12V D23 IRFZ44
R32 CONTACTS
500 mW R24
A D24 V1
100k
R28 + C8 D4 B C
1k 100 µF IN4007
25V
10 15 D6
R26 13 IN6007 RELAY
D5
12 C10 12V
1k IN4007
Figure 1 IC3 1000 µF
13 D 25V
SG3524
7 11 E
C9 R33 Q5
10 nF 6 330 BC547
R25 R29 R30 R31
4 16
6.7k 820 33k 1k
53 1 2 89
B C11 R27
1 F 1k
C
NC
This solar-powered lantern driver can serve as an emergency lighting system.


design
ideas
RC network quashes auxiliary winding
in quasiresonant converter
Nicolas Cyr, On Semiconductor, Toulouse, France
VOUT
uasi-square-wave-resonant con-
Q verters, also known as QR (qua-

siresonant) converters, allow the de-
sign of flyback-type SMPSs (switch-
R1
+
+
mode power supplies) with a reduced
EMI (electromagnetic-interference) sig- GROUND
NCP1207
nature and improved efficiency. You can DMG
1 8
achieve so-called QR operation by au-
2 7
thorizing the turn-on of the switching MAINS
3 6
MOSFET when the drain voltage reach- C2 DRV
4 5
es its minimum—hence, the name valley
switching operation. The circuit usually
externally detects the minimum
drain voltage of an auxiliary Figure 1
winding, which delivers a voltage image
of the core’s internal flux activity. The cir- +
cuit in Figure 1 offers a solution that in-

corporates core-reset detection with the
aid of an auxiliary winding. As you can
see, the auxiliary winding solely performs
the function of core-reset detection. To In this configuration, an auxiliary winding performs the function of core-reset detection.
further simplify this schematic, you can
remove the auxiliary winding and use the with the internal resistor on the best valley detection possible. Because R 1
drain signal itself to generate the demag- NCP1207 demagnetization pin (Pin 1), has a relatively high value, it is essential
netization signal that Pin 1 of the creates a resistor divider. The divider that the component resides close to the
NCP1207 requires. Figure 2 shows this safely limits the voltage you apply on the controller’s Pin 1. The Figure 3 wave-
arrangement. Thanks to its use of high- controller when the drain swings high. forms show the final application results.
voltage technology, On Semiconductor’s C2 delays the signal to detect exactly the The waveforms are captured on a single-
(www.onsemi.com) NCP1207 QR con- drain signal valley. Compared with Fig- output, 30W SMPS delivering 16V. In
troller can derive its power directly from ure 1, where R 1 and C2 were present, the this application, C1220 pF/1 kV,
the rectified mains via its “dynamic-self- only addition is C1 (in replacement of R 11.5 M, and C2100 pF. By prop-
supply” feature. the auxiliary winding. Because capacitor erly adjusting the time constants, you
Capacitor C1 removes the dc compo- C1 touches the MOSFET drain, it must can obtain perfect valley switching.
nent of the drain signal. R 1, together sustain at least the same maximum volt-
age: A 220-pF, 1-kV or 1-nF, 1-
kV ceramic capacitor perfectly
fills the bill. The internal resist-
LPRI ance of NCP1207’s demagneti-
zation pin is 28 k . The value of
R1 C1
DMG R 1 ranges from 1 to 2 M if you
want to create a 5V signal with
a maximum drain voltage of 600
C2 and 900V. The value of capacitor
DRV C2 depends on the frequency of
the resonating network com-
prising the primary inductance,
Figure 2
LPRI, and the total capaci-
Figure 3
In this circuit, the MOSFET’s drain wave- tance of the drain node.You
form generates the demagnetization sig- adjust the values of R 1 and C2 di- These waveforms illustrate the operation of
nal for the controller IC. rectly on the board to reach the Figure 1’s circuit without the auxiliary winding.

design
ideas
Low-power CMOS oscillator has push-pull output
Shyam Sunder Tiwari, Sensors Technology Private Ltd, Gwalior, India
igital oscill ators often gener-
D ate TTL- or CMOS-level outputs,

referred to ground. Generating a
symmetric bipolar output with respect
3
74HC14
4
2.8V
to ground presents a challenge. In this

5 6 0V
design, four 1.5V flashlight 3V DC 74HC14
Figure 1
cells create 3V voltage
sources, and the midpoint of cells acts –2.8V
14
as the ground reference (Figure 1).The 1 2 9 8
74HC14 74HC14 OUTPUT
oscillator at the input, based on the
GROUND
R 1C1 time constant, generates a 2.8V
bipolar output. The symmetrical out-
R1
put waveform requires no dc-blocking C1
11
74HC14
10
capability to drive a piezoelectric

buzzer or loudspeaker. The circuit –3V DC
works well with 1 to 3V sources and

delivers a symmetrical output over the This oscillator uses multiple 13
74HC14
full range of source voltages. logic gates to deliver a 7

symmetrical bipolar output.
–3V DC

design
ideas The best of
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Data-acquisition system uses fault protection

Catherine Redmond, Analog Devices, Limerick, Ireland
ensitive systems, such as those When a fault condition occurs, the
S in aircraft, must withstand fault

conditions, thereby avoiding
component and system damage, be-
VSS
voltage on the input of the channel
protector exceeds a voltage set by the
supply-rail voltage minus the MOS-
cause a sensor failure could cause a FET’s threshold voltage.For a positive
PMOS
catastrophic event to occur. A channel overvoltage, this voltage is VDD
protector, comprising two n-channel NMOS NMOS VTN, where VTN is the threshold volt-
MOSFETs connected in series with a age of the NMOS transistor (typical-
p-channel MOSFET, can protect sen- ly, 1.5V). In the case of a negative over-
PMOS
sitive components from voltage tran- voltage, the voltage is VSSVTP, where
sients in the signal path, whether or VDD VSS VDD VTP is the threshold voltage of the
not the power supplies are present A channel protector can protect sensi- PMOS device (typically,2V).When
Figure 1
(Figure 1). The channel protector tive circuitry from voltage transients. the input of the channel protector ex-
acts as series resistor during normal ceeds either of these voltages, the pro-
operation. If the input exceeds the pow- tions in which correct power sequencing tector clamps the output within them.
er-supply voltages, one of the MOSFETs cannot be guaranteed and for hot-inser- These devices offer bidirectional fault and
turns off, clamping the output within the tion rack systems. Figure 2 shows an overvoltage protection, so you can use the
supply rails, thus protecting the circuitry ADG465 channel protector with an input inputs or outputs interchangeably. Figure
in the event of overvoltage or supply-loss signal that exceeds the power-supply volt- 3 shows the voltages and MOSFET states
conditions. Because channel protectors age. The protector clamps the output sig- for a positive-overvoltage event.
work regardless of the presence of the nal, protecting the sensitive components The output load limits the current
supplies, they are also ideal for applica- that follow the channel protector. during the fault condition to VCLAMP/R L
(Figure 4). If the supplies are off, the
VDD VSS
protector limits the fault current to
nanoamps. Figure 5 shows how you can
Figure 2 VD1 VS1
use the ADG466 channel protector to
VIN VOUT
protect the sensitive inputs of an instru-
ADG465
VIN
VOUT mentation amp from a sensor fault. In
applications that require a multiplexer in
VDD
VDD
Data-acquisition system
OUTPUT CLAMPED
uses fault protection......................................69
AT VDD1.5V
Take steps to reduce
antiresonance in decoupling ......................70
The channel protector clamps overvoltage transients to a safe level. Precision level shifter has
VDD–VTN excellent CMRR ..............................................72
13.5V
Celsius-to-digital thermometer works
with remote sensor........................................74
POSITIVE NMOS PMOS NMOS
OVERVOLTAGE Quasiresonant converter uses
(20V)
a simple CMOS IC..........................................74
SATURATED NONSATURATED NONSATURATED
Simple circuit serves
Figure 3 VDD VSS VDD as milliohmmeter ..........................................78
15V –15V 15V
NOTE: VTN = NMOS-THRESHOLD VOLTAGE (1.5V). What’ s Up sect ion a t ww w.edn. com.
The voltages and MOSFET states appear like this during a positive-overvoltage event.
www.edn.com A p r il 1 5, 2 0 04 | ed n 69

design
ideas
addition to channel protection, you can VD VG VS V
VDD
use the ADG439F fault-protected,four- 15V 13.5V
20V
channel analog multiplexer PMOS NMOS
Figure 4
(Figure 6). These multiplex-
N+ N+ N+ NONSATURATED
ers use a series n-channel,p-channel, n- OVERVOLTAGE EFFECTIVE OPERATION
RL VCLAMP
channel MOSFET connection. During OPERATION SPACE-CHARGE N-CHANNEL
(SATURATED) REGION IOUT
fault conditions, the inputs or outputs VG – VT =13.5V
VT = 1.5V P–
appear as open circuits, protecting the
sensor or signal source as well as the
output circuitry. The output load limits the current to V CLAMP /RL during a fault condition.
ADG439F
ADG466
–
SENSOR 1 ADC DSP SENSOR 1
+ –
ADC DSP
IN AMP +
SENSOR 4 IN AMP
ANALOG OUT DAC REFERENCE

TO ACTUATOR ANALOG OUT DAC REFERENCE
Figure 5 TO ACTUATOR
Figure 6
In this circuit, the ADG466 channel protector guards the sensi- A multiplexer in a data-acquisition system protects the signal source as well
tive inputs of an instrumentation amplifier from a sensor fault. as the output circuitry.
Take steps to reduce antiresonance in decoupling

Dale Sanders, X2Y Attenuators, LLC, Farmington Hills, MI
o maintain power integrity on pc
T
10
boards, you need multiple capaci- 0
tors to decouple the power-distri- 10
20
bution system. A typical configuration
VOLTAGE 30
might comprise five capacitors connect- (dBV) 40
ed in parallel between the power and the 50
ground traces or planes. To provide 60
broadband decoupling per- 70
Figure 2 80
formance, assume the indi- 10 kHz 10 kHz 1 MHz 10 MHz 100 MHz 1 GHz 10 GHz
vidual values of the capacitors are 470,
FIVE STANDARD CAPACITORS: 470, 1, 10, 100, ONE STANDARD 1206 1-nF CAPACITOR
1, 10, 100, and 220 nF (Figure 1). This 220-nF (801-nF TOTAL CAPACITANCE) ONE STANDARD 1206 1000-nF CAPACITOR
parallel network provides 801-nF total ONE STANDARD 1206 10-nF CAPACITOR ONE STANDARD 1206 470-nF CAPACITOR
capacitance to the power-distribution ONE STANDARD 1206 220-nF CAPACITOR
BOARD S21
system. If you measure each capacitor
POWER
Measurements with a vector-network analyzer reveal undesirable antiresonance effects.
0.801 F
TOTAL POWER
with a vector-network analyzer, you can A
470 nF 1 nF 10 nF 100 nF 220 nF
identify each capacitor’s SRF (self-res- G1 G2
400 nF
onant frequency). Figure 2 is a plot of (801 nF TOTAL)
each capacitor’s SRF, as well as the SRF B
GROUND of the overall parallel connection. Each RETURN
SRF can cause antiresonance in the par-
Figure 1
allel decoupling configuration. The
Figure 3
A typical decoupling configuration uses several antiresonance occurs when one ca-
multilayer-ceramic capacitors connected in pacitor is still capacitive, while another A 400-nF X2Y capacitor yields a total decou-
parallel. has become inductive. pling capacitance of 800 nF.
70 e dn | A p r i l 1 5 , 2 0 04 www.edn.com

design
ideas
A way to considerably reduce the an- 10
tiresonance effects is to use a single 400- 0
10
nF X2Y capacitor for decoupling. (Ca-
20
pacitors using X2Y technology are 30
available, for example, from Johanson VOLTAGE
40
(dBV)
Dielectrics (www.johansondielectrics. 50
com). You measure the capacitance rat- 60
70
ing for an X2Y component
Figure 4 80
from line to ground; in oth- 10 kHz 10 kHz 1 MHz 10 MHz 100 MHz 1 GHz 10 GHz
er words, from an A or a B terminal to BOARD S21
FIVE STANDARD CAPACITORS: 470, 1, 10, 100, 1 X2Y 1206 400 nF
either of the G1 or G2 terminals in Fig- 220nF (801-nF TOTAL CAPACITANCE)
ure 3. So, the total capacitance a 400-nF
X2Y component supplies, connected as The single X2Y decoupling capacitor displays no antiresonance effects.
in Figure 3 would be double the capac-
itance rating, or 800 nF. Figure 4 shows pling as the standard decoupling con- sizes as standard capacitors (1812, 1210,
that a single X2Y capacitor with the figuration but without the antireso- 1206, 0805, and 0603), the use of X2Y
same total capacitance as in Figure 1 nance effects. In addition, because X2Y components saves pc-board space and
provides the same broadband decou- components come in the same package reduces layout complexity. 
Precision level shifter has excellent CMRR

Ronald Mancini, Texas Instruments, Bushnell, FL
ost designers make VIN2VIN1VREF VNREF.
M level shifters with

op amps and 1%-
tolerance discrete resis- VIN1
–IN
25k 25k SENSE
to
Now, you need to elim-
inate the reference noise
obtain a clean level-
tors. Discrete-resistor shifted signal. You could
mismatching limits the connect the X end of C1 to
+V
op amp’s CMMR (com- ground to shunt the ref-
mon-mode rejection ra- _ erence noise to ground,
tio) to 40 dB, so you can- VOUT but this solution may be
25k
not use op amps in VIN2 + ineffective because the
+IN
circuits that require high source impedance of the
CMRR. Differential am- –V reference is low. When,
plifiers contain precision 25k however, you connect the
matched internal resis- INA133
X end of C1 to the VIN1 sig-
tors, so ICs such as the nal source,the differential
INA133 can readily VREF amplifier acts as a lowpass
achieve CMRRs of ap- filter and rejects the refer-
proximately 90 dB. They C1 ence noise. This circuit
can offer such high keeps the input imped-
CMRR by trim- Figure 1 X ance of the differential
ming internal matched amplifier low (approxi-
resistors. Assume that C1 allows the level shifter to act as a lowpass filter that rejects the reference noise. mately 25 k  for the
each input in the circuit of INA133) to facilitate
Figure 1 has an associated noise voltage noise cancellation. Careful cabling and matching. Thus, you must keep the signal
(VN1, VN2, and VNREF). The transfer func- differentially coupling the signal into the source impedance low to prevent gain er-
tion of the amplifier circuit is differential amplifier’s inputs force the rors. The source impedance should be
V OUT ( V REF V NREF )(V IN 2 V N2 ) noise on the signal inputs to be equal less than 1/1000 the input impedance to
(VIN1VN1). Note that the reference volt- (V N1VN2). The input noise is a com- minimize gain error. If this situation
age shifts the output signal, either single mon-mode signal, so the differential am- doesn’t occur naturally, then it is best to
or differential.Once this level shifting oc- plifier rejects it to the best of its ability buffer the inputs.
curs, you can turn your attention to the (nominally, 90 dB). Now, VOUT
72 e dn | A p r il 15 , 2 0 0 4 www.edn.com

design
ideas
Celsius-to-digital thermometer
works with remote sensor
Elana Lian and Chau Tran, Analog Devices, Wilmington, MA
ou can use a single- combination of R 1 and R 2
Y supply system to pre-

cisely measure the
temperature at a remote
R1
2k R3
50k
RF
50k
develops a 1V drop, and
you adjust R 2 to provide a
nominal current of 353.15
R2
location with less than VDD A. Thus, the current
1k
1C error over a 0 to _ through the feedback re-
100C range (Figure 1). IC1 OUT DIGITAL- sistor, R , varies from 80
VIN AD7476 DATA F
AD8541
The circuit includes T 1, a +
OUTPUT to 20 A as the temper-
low-cost AD590 tempera- ature varies from 0 to
GND
ture sensor; IC1, an LONG
R4
100C. The voltage across
WIRES
AD8541 rail-to-rail am- 200k this resistor varies from
plifier; four resistors; a 4 to 1V. The 4V offset
trimming potentiometer; causes the output voltage
T1
and an ADC. You can – + of the amplifier to vary
AD590
omit the ADC if you need from 0 to 5V.
an analog output. You To guarantee the accu-
Figure 1
could replace the trim- This system precisely measures temperature at a remote racy of 1C throughout
ming potentiometer with location, with less than 1 C error over a 0 to 100 C range. the range, you need to per-
an AD8400 or AD5273 form a calibration proce-
digital potentiometer for easier calibra- low-power, rail-to-rail operational am- dure. At a known temperature, such as
tion. The feedback resistor, R F, should be plifier.It has a high common-mode volt- 25C, adjust trimming potentiometer R 2
a precision resistor to minimize the scale- age range and extremely low bias cur- to obtain the desired voltage at the out-
factor error, but the accuracy of the re- rents. You can calibrate out its 1-mV put of the amplifier, 1.250V, or the de-
maining resistors is not critical. You can typical offset, the resistor, and AD590 er- sired code at the output of the ADC,
choose the grade of the AD590 sensor to rors. The output swing of the amplifier 400H. Once you perform the calibration,
achieve the required accuracy. is 25 mV to 4.965V with a single 5V pow- you can calculate the temperature in Cel-
The AD590 provides an output current er supply, limiting the output by about sius at any measured point inside the
proportional to absolute temperature (1 0.5C on either end. range by multiplying the output voltage
A/K).In this application, the circuit off- This circuit can derive its power from by 20. Because the sensor has a current
sets and scales the output to provide a a single 5V power supply. The output of output, it is immune to voltage-noise
full-scale range of 0 to 5V with a scale fac- the AD590 varies from 273.15 to 373.15 pickup and voltage drops in the signal
tor of 50 mV/C over the chosen tem- A as the temperature varies from 0 to leads; you can thus use it at a remote lo-
perature range of 0C—the freezing 100C. The positive input of the AD8541 cation. You should use a twisted-pair or
point of water—to 100C, the boiling has an offset of 4V to provide sufficient shielded cable.
point of water.The AD8541 is a low-cost, headroom for the AD590. The series
Quasiresonant converter uses a simple CMOS IC

Francesc Casanellas, Aiguafreda, Spain
shows a flyback power sup- voltage. The converter works in the keeps the gate input high. When the
F
igure 1
ply that has low noise and uses a sim- boundary between discontinuous and MOSFET is on, current increases linearly
ple CMOS 4093 IC for its control. continuous mode and switches on when until the base of Q5 starts to conduct,and
The electrical noise of a converter arises the drain voltage is at its lowest value. To this transistor turns the MOSFET off.The
mainly when current switches on. Diode avoid working with low gate voltages, flyback operation then starts, and the pri-
recovery and charging parasitic capaci- which would cause excessive MOSFET mary energy charges the output capaci-
tances create high di/dt,which is the main losses, ZD1 conducts and enables the in- tors. During this phase of operation, D5
cause of noise. The converter in Figure 1 put gate of the 4093 when the voltage is and R 6 keep Q5 conducting and the MOS-
(pg 76) has a low noise level, because it high enough.When the supply starts, the FET off. When the energy has discharged,
slowly switches current on at nearly zero auxiliary nonisolated winding through D3 (continued on pg 78)

design
ideas
VCC
C4
R4
D3
D6
R5 R3 C3
ZD1 + VOUT
10k D4 C7
4.7V
D5
D2 +
C5 5
33 F 14 R6
6 2222
D1 Q3
ZD3 8.2k
15V 14 Q1
1 8 R16
C1 3 10
1 F 2 9
R15 100
7 4093 Q2 R17
R2 4.7k R7
12
4.7k 11 R13
13 1k OC1
2907 C6
Q5 47 pF 4N35
C2 R8 R10
100 F R1 Q4 470
2369 22k C10
R9
1k 2369
R12
C9 R11
470k
1 nF
ZD2 C8
TL431
R14
Figure 1
Using a simple CMOS IC, this flyback power-supply circuit exhibits extremely low noise.

design
ideas
(continued from pg 74) has reached the minimum value. The charge slowly, further reducing switch-
D5 stops conducting,as do the secondary values are valid only for this case. The ing noise. The circuit around Q4 is op-
diodes, so no recovery problems exist. circuit of Figure 1 not only minimizes tional; you can use it in most power sup-
The time constant of R 5 and C5 keeps turn-on losses, but also reduces electri- plies. It kills the current glitch when Q3
the MOSFET off for a while. The output cal noise. Voltage regulation uses tradi- turns on. It is more effective than the
capacitance of the MOSFET plus the tional techniques, using a TL431. The usual RC circuit, and it allows a low duty
parasitic capacitance of the primary res- optocoupler current adds to the shunt cycle at low loads. Note that many of the
onate with the primary inductance and current. Because the MOSFET turns on component values in Figure 1 are un-
the voltage decreases. R 5 and C5 allow the when current is zero, the gate resistor designated; you should determine these
MOSFET to turn on when the voltage may be high, so parasitic capacitances values to fit the application.
Simple circuit serves as milliohmmeter

AM Hunt, Lancaster Hunt Systems Ltd, Shepperton, UK
hen I was recently debugging a found the answer in a manufacturer’s age regulators. These ICs provide 1.25V
W design, I discovered that a short

circuit existed from a ground
plane to a power plane.I did not have ac-
data sheet, which outlined the basic four-
wire method of making low-resistance
measurements. The method uses a volt-
between their VOUT and VADJ terminals, a
constant voltage to attack the constant-
current problem. The other problem to
cess to a milliohmmeter or an equivalent age-reference IC as the input stage for a attack was the output-voltage range of
tester for locating this type of short cir- controlled constant-current source. A the constant-current source. The circuit
cuit. So, I logged onto the Internet to find quick dig in the old component bucket I was working on used a 3.3V supply, so
an easily constructible milliohmmeter. I revealed a supply of LM317 variable-volt- I had to limit the voltage to 3.3V. An
78 e dn | A p r il 15 , 2 0 0 4 www.edn.com

design
ideas
S1A
LM317, configured as a DVM on a millivolt range.
Q1
constant-current source, The DVM reads a voltage
BD636
S1B
delivers an output voltage IC1
that is proportional to the
VIN V
equal to the in- LM317 OUT resistance under test. If you
put if the output Figure 1 VADJ calibrate the circuit as sug-
P1 P2
resistance is too high. Be- 100 10
gested, then the reading is
cause I wanted to use a 10/V on the 100-mA
bench supply or a 9V bat- 9V R1 R2 range and 100/V on the
+ + BATTERY 68 6.8
tery, the voltage would fry 3V
OR BENCH 10-mA range.
– BATTERY – SUPPLY
any 3.3V logic on the To track down pc-board
board. Ideally, I wanted short circuits, attach the
voltage to be limited to unit with test points A and
A
1.5V. So, I came up with the B across the suspected
configuration in Figure 1. shorted signals.Attach one
B
IC1 controls the base of DVM probe to test point A
the npn Darlington transis- Make your own milliohmmeter, using a voltage-regulator IC and some resistors. and use the other to
tor,Q1. The IC regulates the probe the circuit. Con-
voltage across the selected resistor to form tween test points A and B and measuring stant voltage along a trace indicates that
the constant-current source. The current the voltage across the resistor using a no current is flowing and that the trace is
source delivers either 10 or 100 mA, de- DVM (digital voltmeter). I used 5 and not the source of the short circuit. Look
pending on which emitter resistor is in the 10 and set one S2 position for 10 mA for high readings on the trace with the
circuit.The purpose of S1 is to give longer and the other for 100 mA. To measure a low reading and low readings on the trace
battery life. You can calibrate the current small resistance, you attach test points A with the high reading, to locate the
source by strapping a resistive load be- and B across the resistance. You set the source of the short circuit.
80 e d n | A p r il 1 5, 2 0 04 www.edn.com

design
ideas The best of
design ideas
www.edn.com
Transformerless dc/dc converter

produces bipolar outputs
David Kim, Linear Technology Corp, Milpitas, CA
he conventional way to produce
T dual (positive and negative) outputs

from a single positive input is to use
a transformer.Although such designs are
2.5 TO 10V
6
6.2 H
5
CDRH5D28-6R2
2.2 F
MBRM120LT3
5V
16V 28.7k
relatively simple, the transformer inher- VIN SW
ently introduces the problem of size. It 3 2 33 F
SHDN FB
can be challenging to fit a transformer 10V
4.7 F LT1946A
into an application in which it’s impor- 10V 8
SS VC
1
tant to minimize the circuit footprint 49.9k

CDRH5D28-6R2
9.53k
6.2 H
and height. The circuit in Figure 1 gen- 100 nF GND COMP
erates 5V from a 3 to 10V input and fits 4 7

1000 pF
into applications that lack the room to
accommodate a transformer. The circuit 2.2 F
16V MBRM120LT3
uses a topology that allows the dis-
Figure 1
connection of both outputs when 20 F
the dc/dc converter is in shutdown 10V
CDRH5D28-6R2
mode; thus, the quiescent current is low 6.2 H
during shutdown (standby) mode. The
5V
circuit also produces a regulated positive
and negative 5V, regardless of whether A simple circuit produces 5V from a single positive input without the need for a transformer.
the input is higher or lower than 5V.
Therefore, the circuit can operate from The 2.7-MHz switching frequency of not exceed the current rating of the dc/dc
various input sources, such as a 3 to 4.2V the dc/dc converter allows the use of converter.
lithium-ion battery or a 3.3 to 10V wall small, low-profile external components Cross-load regulation is another im-
adapter. By slightly modifying the circuit, (input/output capacitors and inductors). portant design consideration in this type
you can increase the input range to 2.5 Using three small inductors instead of of circuit. Because the 5V output does
to 16V and the output range to 3 to 12V. one bulky transformer not only reduces not have control of the dc/dc converter’s
the size and height of the converter, but PWM feedback, the 5V output voltage
also evenly distributes the power dissipa-
800
tion over the board, thus eliminating
700
concentrated hot spots. The output-cur- Transformerless dc/dc converter
600 rent capability of the circuit increases as produces bipolar outputs ............................79
OUTPUT 500 the input voltage increases (higher input Single processor pin controls
CURRENT
(mA) 400 voltage, lower input current). Figure 2 on/off function................................................80
300 shows the maximum output current ver-
sus the input voltage. The “both” curve Isolated MOSFET driver has
200 SINGLE
represents the maximum allowable out- wide duty-cycle range ..................................82
100 BOTH
put current of both 5V outputs when Optoelectronic position control
0
3 4 5 6 7 8 9 10 you load them with the same current. simplifies motor movements ......................84
VIN (V) The “single” curve represents the maxi-
Dual-polarity supply provides
Figure 2 mum allowable output current of each
12V from one IC ........................................86
output when you load either output
This graphic shows maximum output current alone.When the current from one output Publish your Design Idea in EDN . See the
What’ s Up sect ion a t w ww.edn .com.
versus input voltage for both outputs or a sin- decreases, the current capability of the
gle output. other output increases, as long as you do
www.edn.com A p r il 2 9, 2 0 0 4 | e dn 79

design
ideas
5.5 5.1 3V
IN
changes with output current. You can 5VIN
greatly improve the cross-load regulation 10VIN
by adding a 10- to 20-mA preload at each 5.3 NEGATIVE 4.9
NEGATIVE
output. The preload ensures that the 5V 5V
OUTPUT OUTPUT
dc/dc converter operates in continuous- (V) (V)
3VIN
conduction mode,in which the inductor 5.1 4.7
5VIN
current is stable enough to provide con- 10VIN
stant current. Figure 3 shows the 5V
4.9 4.5
output voltage regulation under different 0 200 400 600 800 0 200 400 600 800
POSITIVE 5V OUTPUT CURRENT (mA)
load conditions at the positive (Figure (a) (b) NEGATIVE 5V OUTPUT CURRENT (mA)
3a) and negative (Figure 3b) out-

Figure 3
puts. In this case, to improve cross-
load regulation, both the outputs connect These curves show the regulation of the 5V supply as a function of the 5V output current (a), and
to a 20-mA preload. the regulation of the same output as a function of the 5V output current (b).
Single processor pin controls on/off function

Michael Sirkis, Radio Systems, Logan Township, NJ
recent Design Idea prompted me er (Figure 1). It features an enable pin I/O pin configured as an output and
A to offer the simpler solution that I

used in a recent project (Reference
1). We needed a momentary power
(Pin 9), which, when you pull it low, not pulled high. This action keeps IC1’s Pin 9
only shuts down the converter, but also high and the converter running after the
completely removes the load from the release of the power switch.Every few mil-
switch with processor supervision. This battery. The processor is a PIC16F874. A liseconds, the processor’s I/O pin recon-
supervision would allow the processor to key element of the design is that you can figures as an input, and the processor
delay a power-down request from a press first configure the processor-I/O pin as an checks the switch for a high (pressed) or
of the power switch until all routines ex- output to keep the converter’s enable pin low (released) condition. The processor
ited properly. In addition, in periods of high and then reconfigure it to test the pin then returns to its previous output
inactivity, the processor could shut down logic level of the power switch. mode. Capacitor C4 holds IC1’s Pin 9 (en-
the product to conserve battery life. The When the circuit is not running, closing able) high to keep the converter running
project also required a boost converter to momentary power switch, S1 (push-on) while the switch undergoes testing. When
convert two or three AA batteries to 5V. pulls IC1’s Pin 9 high, thereby turning on you release the power switch from pow-
The design uses IC1, a Texas Instruments the converter and providing 5V to the er-up and then press it again, the proces-
(www.ti.com) TPS61032 boost convert- processor.The processor boots up with its sor begins the push-off sequence. After
performing whatever housekeeping it re-
5V quires, the processor pin configures itself
OUTPUT TO
L1 PROCESSOR as an input and remains an input. Capac-
1 13
SW1 VOUT1 itor C4 then completely discharges, bring-
6.8 H 2 14
SW2 VOUT2 ing IC1’s Pin 9 (enable) low, thereby shut-
6 15 +
VBAT VOUT3 C2 C3

8
SYNC 10 F 220 F
ting down the converter and the rest of the
12
BATTERY
C1
R1 IC1 FB circuitry. Diodes D1 and D2 allow the bat-
D1 D2 PACK TPS61032
1N4148 1N4148 
10 F
LBO
10 tery voltage to start the converter and the
7 LBI
3 processor to test the power switch using
9 PGND1
R2 EN 4 the higher output voltage from the con-
PGND2
PGND3 5
11 GND
verter. The TPS61032 also features a low-
S1
battery comparator whose trip point is a
D3 function of R 1 and R 2. A different proces-
1N4148 sor could read the comparator’s output
TO PROCESSOR I/O PIN (IC1, Pin 10) to perform a safe shutdown
R3
1k R4 R5 when the battery voltage gets too low.
1M C4 1M
0.01 F
Figure 1
Reference
1. Gehrke, Dirk,“Microcontroller or
DSP circuit controls on/off function,”
This circuit configuration provides a momentary power switch with processor supervision. EDN , Nov 13, 2003, pg 104.

design
ideas
Isolated MOSFET driver has wide duty-cycle range
Jesus Doval-Gandoy and Moises Pereira Martinez, ETSI Industriales, Vigo, Spain
he main application for the circuit
T in Figure 1 is for driving power

MOSFETs with signals ranging in fre-
quency from 1 Hz to 300 kHz and with
duty cycles from 0 to 100%. You achieve
this goal by using a coreless pc-board
transformer. The switching frequency in
most power-electronics circuits ranges
from a few hertz to a few hundred kilo-
hertz. To design a coreless transformer-
isolated gate drive that can switch in the
The top trace is the ac
range of frequencies lower than 300 kHz, Figure 2
signal across the trans- The input impedance
you implement the modulation of a Figure 4
former secondary; the bottom trace is the low- of the transformer
high-frequency carrier by a low-frequen-
frequency control voltage. peaks at 3 MHz.
cy control signal. The energy transfer
from the primary side occurs through the
use of a high-frequency carrier signal of
3 MHz. The control-gate signal couples
to the secondary output by the modula-
tion process. The binary counter, IC3,di-
vides the 24-MHz signal from clock-os-
cillator IC2 by eight to obtain 3 MHz. The
true/complementary buffer, IC6, yields
two complementary 3-MHz signals with
low delay between them. The NAND
gates, IC5, implement the modulation
process. The top trace is the
Figure 3 The prototype of the
The design uses the value of C3 to ob- gate-drive voltage to Figure 5
coreless transformer
tain maximum impedance at the work- the MOSFET; the bottom trace, the ac signal
has a wide duty-cycle range.
ing frequency. A voltage doubler (D1, D2, across the transformer secondary.
C4) furnishes the gate-drive voltage.This
design uses a 555, IC7, as a Schmitt trig- the transformer primary, thus charging and the input to IC7 goes low, thus turn-
ger because of its low power consump- capacitor C5 and energy-storage capaci- ing off the MOSFET. Figures 2 and 3
tion. D3 prevents the energy stored in C6 tor C6. The input to IC7 goes high, thus show the control voltage, the voltage
from discharging into R 1. As you can see turning on the MOSFET. When the con- across the transformer secondary, and the
in Figure 2, when the control voltage is trol voltage goes low, the voltage across gate voltage of the MOSFET.
high, a 3-MHz ac signal appears across the transformer primary drops to zero, The dimensions of the transformer
12V 5V
J1 7805
IC1 J3
1 IN OUT
2 GND 2
C1 C2 GND PWR 1
CON1 47 F 100 nF CON2
Figure 1 D2 D5 J4
1N4148 MUR420 2
12V 1
CON2
C4 C6 6
6 0.1 F
JUMPERS CD4011A 1 F
16 C5 8
5 2 7 Q1
10 9 4 2 7 T1 330 pF
2 TRG
VCC 10 9 1 8 IC5B
3 A QA 14 8
8 7
7 E 4 RST IC7 C9
4 B QB 13 6 5 3 A IC6 5 3 IC8
5 12 4 6 5 3 D1 OUT 1 nF
C IC QC 4 3 IC4A 1 6 TH
5V 6 11 2 1 3 4 1N4148 R1 7 4 5
D 3 QD 2 1 IC5A 5 IC7
IC2 15 2 2
RCC F C3 6.8k IRF630
8 V 5 2 680 pF 1 IC555 D4
CC OUT CLK
10 ENT CD4041A CD4011A MC34151
3 1N5819
7 ENP 3
4 1 74LS161A J2
GND NC 9 LOAD
CLOCK 5V GND CLR 1 MC34151
2 D3
8 1 1N4148
CON2 GND PWR
A modulation scheme makes it possible to obtain isolated gate drive for a power MOSFET over a wide duty-cycle range.

design
ideas
and the carrier frequency yield a good 0.3-mm-wide conductor. The circular a frequency plot of the input impedance
relationship between the secondary and spiral secondary winding is on top of the of the transformer with the secondary
the primary voltages and minimize the pc board. It has 15 turns and a 0.4-mm- winding terminated by C3. The network
input power of the gate drive.The trans- wide conductor. For both windings, the analyzer shows that the maximum im-
former has a circular spiral primary conductor thickness is 35 microns, and pedance occurs at approximately 3
winding on the bottom of the pc board. the outermost radius is 25 mm. The pc MHz. Figure 5 is a photograph of a
The primary winding has 20 turns of board is 1.54 mm thick. Figure 4 shows working prototype.
Optoelectronic position control simplifies

motor movements
Marie Rivera, Apex Microtechnology Corp, Tucson, AZ
he optoelectronic tech- the system continues on to
T nique for achieving po-

sition control provides
an inexpensive, easy- to-de-
CL RF1 CF
RCL+
the next index. If the value
of CF is too small, severe
overshoot or oscillation
sign method of achieving RL RF2 32V 0.68 can occur, resulting in
simple, repeatable move- V=28V drive-train failure or motor
ment using fixed index EMF=14V burnout.
+
points with linear- or ro- POWER MOTOR To help minimize over-
OP AMP
tary-motion components. _
RCL– shoot,R F1
and R F2 in Figure
The simple, basic design in 0.68 1 stabilize the control loop
Figure 1 for sequential po- V
at the unity-gain point.You
sition control exploits the can also improve response
LIGHT
quick response time of a time by applying a braking
power op amp, working in force, which you create by
tandem with a pair of pho- 32V
using R L and CL to form a
todiodes. The result is a lead network, which en-
low-component-count sys- –V ables the amplifier to mod-
tem that provides high reli- ify the motor drive based
ability, accuracy, and re- on a change in the sensor
PD1 PD2
peatability when you use it output. The motor in Fig-
in well-defined oper- ure 1 has EMF (electromo-
ating conditions. The Figure 1 tive force) of 14V and can
circuit in Figure 1 achieves apply a 46V stress across
sequential position control An optoelectronic circuit uses a power op amp to achieve sequential the conducting output
by using a power op amp to position control. transistor when you reverse
integrate the differential it. This power dissipation is
output of a pair of photodiodes to drive rent reverses the motor drive, causing the a worst-case scenario; you need to check
the motor in the proper direction until the system to lock to the index point. The use it against the SOA (safe operating area)
photodiode currents are equal.Movement of a differential configuration eliminates of the amplifier. Figure 2 shows optimum
between index points occurs when you errors from temperature and time insta-
momentartily switch a fixed input current bility in the optoelectronic devices. The
to the amplifier’s input, causing the am- entire system uses a simple switch, as
plifier to drive the motor in the desired di- Figure 1 illustrates, to generate both for-
rection. The charge on CF maintains mo- ward and backward motion. Because mo-
tor drive as the input current switches off tor response time and system inertia vary
before reaching the index point. greatly in different applications, you
To ensure continued motion in the de- achieve proper damping by select-
sired direction, the motor drive receives ing CF and R F based on the applica- Figure 2
reinforcement by the output from the tion. CF needs to be small enough to al- With optimum beam-sensor alignment, the
first photodiode as it illuminates. As the low drive reversal before the index point light beam illuminates half the photosensitive
second photodiode illuminates, its cur- passes the second photodiode; otherwise, area of each diode.

design
ideas
alignment for the beam sensor. D1 grate digital control. When
You achieve optimum alignment LINE 1 logic lines are low, the signal
by centering the light beam in re- diodes do not conduct. This
lationship to the active areas of condition allows the photodi-
each photodetector. The light PD1 PD2
R1 odes to control the circuit. A
beam needs to illuminate half 4.7k _ high level on Line 2 causes
the photosensitive area of each POWER current to flow to the sum-
OP AMP
diode. When sizing the “hole,” + ming junction and swing the
consider the distance be- amplifier negative.A high lev-
Figure 3
tween the location of the el on Line 1 raises the sum-
R2
light beam and the photodiodes. 4.7k
D2 R3
ming junction voltage above
If the beam is too large, the sen- LINE 2 4.7k ground and swings the ampli-
sors do not produce any change fier positive. By selecting a
for a range of positions. Too resistance value that allows
small a beam produces a nonlin- This circuit imparts digital-interface control to the circuit in Figure 1. a logic-level supply high
ear transfer function along the enough to provide at least
center line between the photosensitive light source with higher intensity. twice the maximum current from each
areas. This nonlinearity can create diffi- Figure 3 illustrates how you can use a photodiode,the circuit maintains system
culty in selecting the value of CF for nonbipolar signal without digital-to- control regardless of the photodiode
dampening the circuit and requires a analog conversion for systems that inte- signals.
Dual-polarity supply provides 12V from one IC

Keith Szolusha, Linear Technology Corp, Milpitas, CA
ell-regulated, dual-polarity possible, thus saving board space and
W
500
power supplies find wide use in cost. Some dual-polarity dc/dc-convert- 5VIN
400 8VIN
disk-drive, handheld-device, au- er topologies—for example, overwind-
12VIN
tomotive, and notebook-computer ap- ings and flyback converters with multi- 300 15VIN
MAXIMUM
plications. In these applications, board ple-winding transformers—require ex- VOUT2 LOAD
space and allowable component heights cessive board space, component height, CURRENT 200
(mA)
are continually shrinking. So, power- or both; offer poor load regulation; or 100
supply designers face the challenge of provide limited load current. Figure 1
providing split rails with as few parts as shows an alternative approach that uses 0
0 100 200 300 400 500
VOUT1 VOUT1 LOAD CURRENT (mA)
VIN 12V
D1
5 TO 15V L1
CDRH4D28-100 CCOUP1 B0530 Figure 2
This graph shows the maximum load current at
1 F
X5R the VOUT2 terminal versus the VOUT1 load current.
16V CERAMIC 90.9k
VIN VSW
IC1
LT1961EMS8E
a single boost regulator using a dual-po-
CIN 2.2 F FB COUT1 10 F larity SEPIC (single-ended, primary-in-
X5R SHDN X5R
25V CERAMIC 15 nF
16V CERAMIC ductance-converter) architecture. The
SYNC VC L2
CDRH4D28-330 10k circuit saves space and offers good regu-
GND GND
6.8k lation and current-handling capability.
100 pF
The boost regulator, IC1, usually figures
in step-up-converter configurations, but
D2
the low-side power switch in IC1 allows
1 F
X5R CCOUP2
B0530 COUT2
10 F the use of the IC in both SEPIC and neg-
25V CERAMIC X5R
Figure 1 16V CERAMIC ative-SEPIC circuits.
L3 The combination of the two topologies
CDRH4D28-330
creates a dual-polarity SEPIC, an excel-
VOUT2 lent source for multiple-rail bias power.
12V
This circuit uses a single boost-regulator in a dual-polarity SEPIC architecture. The circuit provides well-regulated

design
ideas
12.5 12.4
12V outputs at varying load currents 12.4 VOUT1 AT 50 mA
12.3
(5W power with 12V input and 3.6W 12.3 VOUT1 AT 100 mA
12.2 VOUT1 AT 210 mA
with 5V input). Figure 2 shows the max- 12.2
imum available current at VOUT2 as a VOUT2 12.1 VOUT2 12.1

(V) 12 (V)
function of the load current at VOUT1. Fig- 12
11.9
ure 3 shows the efficiency of the con-
11.8 VOUT2 AT 50 mA 11.9
verter as a function of the load current
11.7 VOUT2 AT 100 mA
at VOUT1. Although the positive feedback VOUT2 AT 210 mA
11.8
11.6
11.5 11.7
0 100 200 300 400 0 50 100 150 200 250 300 350 400
85
VOUT1 LOAD CURRENT (mA) VOUT2 LOAD CURRENT (mA)
80
Figure 5
75 Figure 4
EFFICIENCY Regulation of the VOUT2 voltage is within 200
(%) 70 Regulation of the V OUT2 voltage as a function of
mV over almost all of the range of V OUT2 load
65
5VIN VOUT2 AT 140 mA VOUT1 load current is reasonably tight.
5VIN VOUT2 AT 50 mA
currents.
60 5VIN VOUT2 AT 215 mA
55
comes from VOUT1, VOUT2 maintains ex-
5VIN VOUT2 AT 50 mA small power inductors as opposed to a
0 100 200 300 cellent regulation (figures 4 and 5). The
400 transformer keeps the component height
VOUT1 LOAD CURRENT (mA)
circuit maintains the regulation as long below 3 mm,reduces board space,and al-
as each load draws a minimum of 5-mA lows layout flexibility.The high-frequen-
Figure 3
current. The SEPIC topology accommo- cy,current-mode boost-regulator IC uses
Efficiency of the circuit in Figure 1 is more than dates input voltages both above and be- all ceramic capacitors, thus minimizing
70% for most of the range of load-current values. low the output voltage. The use of three ripple and overall cost.

design
ideas The best of
design ideas
www.edn.com
Circuit forms simple, low-cost, 1-kV driver

Tai-Shan Liao and Prasit Champa, National Science Council, Hsinchu, Taiwan
igh-voltage drivers have recent- age, which you derive from the output of
H ly received much attention,because

they play an important role in driv-
ing piezoelectric and electro-optical
the error amplifier, serves as the indica-
tor for load conditions. Once the feed-
back voltage becomes lower than the
Circuit forms simple, low-cost,
1-kV driver........................................................87
Make a printer-port EEPROM
components, for example. Figure 1 shows green-mode threshold voltage, the
programmer and dongle ............................88
a simple, low-cost, 1-kV driver. The cir- switching frequency starts to decrease.
cuit uses offline, current-mode-control All the power losses are in direct pro- Circuit controls ratiometric or simul-
techniques and a flyback switching-pow- portion to switching frequency. These taneous power-up of multiple rails............90
er-supply design. IC1, a UC3844, is the losses include the switching losses of the Scheme provides automatic
major control component, using a transistor, core losses in the transformer power-off for batteries ..................................92
switching frequency of 100 kHz. The IC and inductors, and the power loss of the
provides frequency modulation to reduce snubber. The frequency modulation in What ’s Up sect ion at w ww.ed n.com .
the switching frequency under light- and the PWM-controller IC reduces the pow-
no-load conditions. The feedback volt- er consumption in the supply under
EI-25-2E6
CORE 1000V
+ 47 F 470k
T2 450V 1W
T1
+ 100k 70 105
110V AC 0.1 F +
220 F 5W TURNS TURNS 47 F 470k
400V 30k D1 450V 1W
1W
BR1 FR137
+ 47 F 470k
T3 450V 1W
FR137
105
TURNS + 47 F 470k
450V 1W
+ T5
22 F 0.1 F FIVE
25V
TURNS
T4 22 F
25V 0.1 F
7 SIX
5 TURNS
Q1
IRF840 1M
130k
30
6
1 IC1 FR137 1k
10O pF
UC3844 1k
VREF 1M
3
FB 2 30O pF 5 PC817
33k
4 8 1W
VR1
200 500k
15k
R5 6.8 nF 10k
3k
Figure 1
0.1 F
2.2 nF
A PWM-controller IC IC2
VR2
TL431
forms the heart of a 10k 10k
low-cost, regulated,
1-kV-dc supply.
www.edn.com M ay 1 3 , 2 0 04 | e dn 87

design
ideas
light- and no-load conditions. But the open-loop error amplifier with a 2.5V prevent core saturation, the gap is ap-
frequency modulation has no effect on temperature-compensated reference. proximately 1 mm. The primary winding
the PWM operation under normal- and When the output voltage is lower than the has 70 turns of 28-gauge wire. Both the
high-load conditions. desired level, the feedback to the UC3844 secondary windings have 105 turns of 34-
Pin 2 (the feedback pin) of the UC3844 automatically compensates the pulse- gauge wire. The primary and secondary
sums the current-sense signal,the output- width modulation of the output trigger- auxiliary windings have five and six turns,
voltage feedback signal, and any added ing signal.Ceramic bypass capacitors (0.1 respectively, of 34-gauge wire.The dc out-
slope compensation. The feedback-con- F) from VCC and VREF to ground provide put voltage of the circuit in Figure 1 is 1
trol circuit uses a TL431 adjustable shunt low-impedance paths for high-frequen- kV (fixed).You can adjust the output volt-
regulator to detect the output signal. A cy transients. This design uses a Tomita age in a 50V range by adjusting VR 1.Both
PC817 passes the signal to the feedback (www.tomita-electric.com) EI25-2E6 load and line regulation are less than 1%,
pin of the UC3844. The TL431 acts as an core set to fabricate the transformer. To and power efficiency is 80% at full load.
Make a printer-port EEPROM programmer and dongle

GY Xu, XuMicro, Houston, TX
ou can easily use a PC’s print- Once you settle on the hardware
Y er port for serial-EEPROM pro-

gramming. You can use a de-
vice-programmer circuit used to
14
1 CO
2 DO
design, the main task is to write
software. This task is not difficult.
For many embedded-system-soft-
program the MicroWire serial EE- ware engineers, it’s routine and in-
PROM 93CXX (Figure 1). The cir- C3
17 teresting. A freeware executable
cuit is so simple that any further 18 8
program, Pseep2.exe, is available
simplification seems impossible. VCC for this purpose. A sample demo
This programmer circuit contains 1 program, secret.bin, allows you to
CS 7
PE
no microcontroller, as most device 2
practice the programming.You can
SK
programmers do. It needs neither a download the software from the
9 D7 93CXX
separate power supply, or “wall- Web version of this Design Idea at
3 6
wart,” nor a cable.When in use, it di- DI ORG www.edn.com.It handles only one
rectly plugs into the PC’s printer 4
DO MicroWire device—the popular
port. However, you still can use a ca- GND 93C46’s read/write operation as an
25
ble if convenient—for PC printer 13 5 example. Another important fea-
ports behind the PC, for example. GND ture of this circuit is that, once you
The circuit also requires neither a program the 93CXX device, the
DB-25M
resistor nor a decoupling capacitor. CONNECTOR
system becomes a primitive don-
These advantages come from the gle. You can then use it as a hard-
PC’s printer-port resources and ware-protection device for your
Figure 1 This printer-port serial EEPROM program-
the architectural simplicity of the valuable software. Only you know
MicroWire serial EEPROM. The mer can also act as a dongle once you program the device. whatever was programmed in the
printer port comprises the 8-bit device.
data, status, and control registers. Each read/write operations. This design uses the When the protected software runs, it
register has its unique address. On the chip-select signal from the reverse level of first checks whether the device is present
classic IBM PC, the data port serves sole- the control bit C3 (Pin 17). It also ties to- at the printer port and whether the code
ly for output, but the control port can gether pins DI and DO and connects them matches what you programmed. If a
serve as either input or output.The eight- to the Control bit C0 (Pin 1), which can match doesn’t exist, the software refuses
pin, tiny, serial EEPROM consumes less serve as input or output, thereby saving to continue and exits. The dongle is
than 1-mA current in the active state,and one pin. These selections caused no prob- primitive, but it does illustrate the basic
the printer port’s data pin can supply a lems in practice. Because control Pin 1’s principle of dongle-protection technolo-
few milliamps, so this design uses D7 (Pin logic is the reverse of the logic level on bit gy. You can build the circuit using wire-
9) as a power-supply pin. No decoupling C0, the software must take care of the in- wrapping or point-to-point soldering
capacitor is necessary in practice. version. The MicroWire interface nor- techniques on a solderless breadboard, in
The MicroWire chip uses the CS (chip- mally requires a pullup resistor on the DO which case you’ll need a cable, or with
select), SK (clock-signal),DI (data-input), pin, but such a resistor is already inside the your own pc board. It’s a one-evening
and DO (data-output) pins to control its PC, so it’s unnecessary. project.
88 e d n | M ay 1 3 , 2 0 04 www.edn.com

design
ideas
Circuit controls ratiometric or simultaneous
power-up of multiple rails
Dirk Gehrke, Texas Instruments, Freising, Germany
any applications use FPGAs, IC2 controllers share a soft-start capaci- 3
M ASICs, or DSP chips, which usual-

ly require multiple voltage rails,
typically two: the core voltage and the I/O
tor,C14. This example uses two buck con-
verters with integrated synchronous-
rectification FETs. From a 5V
0.2 mSEC
0.50V
2
0.2 mSEC
0.50V
voltage. The core voltage is usually lower input-voltage rail,IC1 generates the 3.3V
than the I/O voltage. Guidelines for de- I/O voltage. Buck converter IC2 gener-
termining how to power up two or more ates the 1.5V output voltage.
voltage rails depend on the part and the The soft-start pin, available on both
manufacturer you use. The first imple- controller ICs, serves two purposes. You
mentation in Figure 1 shows how to re- can use it to enable the controller cir- 0.2 mSEC
alize ratiometric sequencing, which cuitry if required—an implementation 1 10 mV 50
10 MSAMPLES/SEC
you could realize by tying an open-col- 23 50 mV DC x
means that both power-supply output 50 mV DC 2 DC 2.00V
10
x
10
x
rails simultaneously start and simultane- lector or open-drain gate to the SS Pin. 4 0.1V DC 10□ STOPPED
ously reach their final regulated output If the transistor or FET is active, it
Figure 2
voltage. This implementation uses resis- ties the SS Pin to ground potential,
tor R 15 connected to ground;the path and forcing both controllers to stay off. Once This graphic shows measurement results for
components in red are deleted. You can you release the SS Pin, both ICs start to the ratiometric implementation.
achieve the ratiometric function by stack- charge C14 with their internal 5-A cur-
ing together multiple converters that rent sources.In total,10-A current flows timeC14(1.2V/10 A).As the output ac-
share one soft-start capacitor. This con- into C14. Once C14 reaches the threshold tivates, a brief ramp-up at the internal
nection ensures that both controllers voltage of 1.2V, both controllers start to soft-start ramp may occur before the ex-
ramp up their output voltage at the same operate. You can easily calculate the de- ternal soft-start rate takes control. The
time during power-up. Both the IC1 and lay versus the capacitor’s value: Delay output then rises at a rate proportional
VIN 5V L1 I/O 3.3V, 3A

VIN PH
R1
+ C7 C8
C1 C2 76.8k C6
RT C12 47 F 47 F
470 F 10 F 47 nF R7
C5 BOOT
1.8 nF 105
100 nF TPS54310
C13 VBIAS R8
IC1
56 pF 27.4k
VSENSE
SYNC R2 C10
R9 3.83k 6.8 nF
D1 SS
1k COMP
GND R3 R6
40.2k 13.7k
C9 R15
470 pF 10.22k R5
Q1 330k
C11
47 F
L2 CORE 1.5V, 6A
VIN PH
R4
330k C19 C20 C21
PGOOD C18 47 F R 47 F
BOOT 47 nF 13
5.6 nF 33.2
TPS54610
Figure 1 RT IC2 SYNC R14
R10 10k
VBIAS VSENSE
71.5k C17
This circuit provides C15
SS R11 18 nF
ratiometric (delete red 100 nF
COMP
path and components) or GND R12
C14 14.7k
simultaneous power-up C16
39 nF
sequencing. 1.5 nF

design
ideas
to the soft-start capacitor. You can pro- start at the same time with the same parator output pin.This action forces the
gram the soft-start time via C14. The next ramp, reaching their final value at the pin to rise immediately to the output-
equation represents the soft-start time same time. Once both rails reach 1.5V, voltage level because of resistor R 4’s
calculation. The actual soft-start time is you must increase IC1’s output voltage to pullup action. A lowpass filter consisting
likely to be less than the calculated ap- 3.3V, its final value. To make that increase of R 5 and C11 forms a delay circuit, driv-
proximation because of the brief ramp- happen, Q1 places R 6 in parallel with R 3. ing MOSFET transistor Q1’s gate. This
up at the internal rate. Soft-start You can calculate the value of R 6 using the delay circuitry determines when Q1 be-
timeC14(0.7V/10 A).If you set IC1 for next three equations. The given parame- comes active. Q1 has a threshold voltage,
ters are: VOUTCORE1.5V; R 827.4 k ; VGSTH, of 1.6V. Once the gate voltage
2
5 mSEC
VREF0.891V, the internal bandgap-ref- reaches or exceeds the threshold voltage,
0.50V erence voltage of IC1; and R 340.2 k . VGSTH, Q1 starts to conduct, putting R 6 in
3 You can program VOUTI/O via R 8 and R X . parallel with R 3. Because of the resistor-
5 mSEC
0.50V
R X represents the value of R 3 and R 6 in a ratio change, IC1’s output voltage ramps
parallel connection. up to its final I/O-voltage value of 3.3V.
The MOSFET this design uses has an on-
resistance of roughly 10. This figure
might sound high, but, because of the
high-ohmic-resistive divider, this value
5ms does not affect performance. Figure 3
1 10 mV 50
500 kSAMPLES/SEC
shows the results of the described imple-
2 50 mV DC
3 50 mV DC 2 DC 1.02V
mentation during power-up.
4 0.1V DC □ STOPPED
Significantly, in this implementation
Figure 3 both converters run at the same switch-
ing frequency. IC2 is the master con-
These curves, distinctly different from those in R X must have a value of 10.22 k  to pro- troller, programmed to a 700-kHz
Figure 2, show simultaneous-sequencing duce VOUTI/O3.3V. switching frequency. IC1 starts at a lower
results. initial switching frequency of roughly
630 kHz, 10% below the switching fre-
3.3V and IC2 for 1.5V, they both reach quency of IC2. Once IC2 begins to oper-
their final voltage level at the same time. ate, it synchronizes IC1 via the Sync Pin.
Figure 2 shows measured results of the ra- Diode D1 limits negative voltage spikes at
tiometric sequencing. In this example, R 6 needs a value of the Sync input. Placing a well-chosen
In the simultaneous-sequencing sce- 13.7 k . Applying 5V to the input-volt- Schottky diode between both output
nario, IC2 acts as the master controller. age rail activates both controllers at once, voltage rails can ensure that, even during
You program its output voltage via R 14 allowing them to start at the same time. power-down, both rails have a voltage
and R 12 to a value of 1.5V. R 8 and R 3 pro- Once the master controller, IC2, reaches difference of 400 to 600 mV for safety
gram the slave controller IC1’s output an output voltage level equal to or greater reasons. The cathode connects to the I/O-
voltage to a value of 1.5V. As the ratio- than 90% of the initial value, the IC re- voltage rail, and the anode connects to
metric scenario describes, both voltages leases the power-good open-drain-com- the core rail.
Scheme provides automatic power-off for batteries

Miguel Gimenez, Altair-Equipos Europeos Electronicos, Madrid, Spain
he circuit in Figure 1 provides a circuit, the circuit incorporates an auto- is approximately six minutes. The timer’s
T simple and inexpensive way to pro-

tect one of the most valuable com-
ponents in portable applications:the bat-
power-off function with a time period
that is a function of preprogrammed
time constants.
output feeds the Q1 inverter that activates
medium-power, pass-through Q2 transis-
tor. This circuit is configured as a pnp
tery. Applications include all portable IC1 and related parts provide a bistable block to ensure low losses to the load. The
equipment that requires a limited time of toggle function and also ensure protection loss comes only from VCE(SAT)—approxi-
operation, such as test instruments, gui- against switch-contact bounce. IC1C mately 0.2V at 100 mA,or 20 mW. For ap-
tar tuners, and electronic toys. Pressing buffers the toggled signal and isolates the plications demanding more current, you
the on/off momentary switch starts the R 1-C1 charging current. This signal feeds can choose a more suitable transistor. A
cycle, and the circuit provides power to the IC2 timer, configured as a monostable MOSFET can be an efficient approach
the application circuit. If you again press multivibrator that remains activated un- when you need either lower standby loss-
the switch at any instant, the circuit til it times out, according to the expression es or a lower voltage drop between the bat-
switches off and “sleeps” until the next t1.1R TCT. This figure is the auto-pow- tery and the application circuit.
cycle. In case you forget to switch off the er-off time. In the example, this interval Standby losses in the switched-off state

design
ideas
Q2
BD140
+ VIN
VOUT
9V DC
– BATTERY R9 TO
C6
100k APPLICATION
R3 1 F
22k
R7
R2 2.2k
IC1A IC1B IC1C
CD4023A 2.2k CD4023A CD4023A
1 3 11 D1 LED
2 9 4 6 12 10
8 5 13 8
RT R4 R5 R6
R1 VCC
1M 100k 100k 10k
390k 2 3 Q1
S1 TRIGGER OUTPUT
4 BC337
1 2 RESET
5
CONTROL IC2
C1 6
THRESHOLD
ON/OFF 100 nF 7
DISCHARGE
MOMENTARY
CT C2 C3 C4
330 F 1 nF 10 nF 10 nF GND
C5
Figure 1 1 555
10 nF ON
OFF OFF
This battery-saving circuit is handy for applications requiring a limited operating time. T
are negligible, because the circuit draws LED, because it is connected in the cur- gles the bistable circuit to the off state,
power only from the CMOS gate in the rent-source leg of the driver transistor. performing the same role you might have
inactive off-state. LED D1 indicates the The output transition to 0V during time- forgotten with the on/off switch. This
on-off status of the circuit.No extra pow- out ensures the timed power-off by simple circuit is useful when the applica-
er comes from the battery to drive this means of the C5 feedback loop that tog- tion doesn’t require a microcontroller.

design
ideas The best of
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Circuit provides 4- to 20-mA loop

for microcontrollers
Robert Most, Dow Corning Corp, Auburn, MI
15V 15V
he 4- to 20-mA current loop is ubiq-
T uitous in the world of controls in

manufacturing plants. Discrete log-
ic, microprocessors, and micro-
15V
100
1%
controllers easily cover the digital Figure 1 6 _

100 1/2 7 680
Q3
portions of control schemes, such as lim- 1M 1%
5
TL032 2N3906
8.2k 8 +
it switches, pushbuttons, and signal FROM
3
+ 4
27k
lights. Interfacing a 4- to 20-mA output PROCESSOR 100k

1/2
TL032
1 IOUT
TIMER Q2
to a rudimentary microcontroller can be 4.7 F 2 _ Q1
2N3906
2N3904 56k
problematic. A built-in A/D converter RL
would be nice,but such a device is some- TO
PROCESSOR
140 27k
times unavailable in the “economy” line 1% INPUT PORT
of these processors. Serial 4- to 20-mA
chips exist but are relatively expensive
and require serial programming and in- This configuration provides both a 4- to 20-mA loop and an open-circuit indication.
volve microcontroller overhead. Most
lower end chips lack dedicated serial ditional voltage swing below ground po- back through its emitter-base junction
ports and require pin-programming. tential to keep it in its active region and and through the 680 resistor to the op
This circuit is a low-cost alternative does not cut off. The emitter resistor of amp. The voltage developed across the
that provides not only a 4- to 20-mA out- npn transistor Q1 sets the current span of 680  resistor turns on Q2, resulting in
put, but also a digital feedback signal that the circuit. With a 5V drive from the mi- a logic-one feedback to the microcon-
indicates an open wire in the current loop crocontroller, the output current is 20 troller. Note that the open loop requires
(Figure 1). One output-port pin sets the mA.A grounded input results in less than at least 1 mA of current for the open in-
current, and one input-port pin monitors 1 mA. A duty cycle of 12.5% drives the dication to function, which is below the
an open circuit in the loop wire. The cir- loop at 4 mA and exhibits linear control normal 4 mA—a “zero” output condi-
cuit does not require the open-loop feed- to full scale. Although it may not be
back portion of the circuit for the current mandatory, most current loops prefer a
loop to operate; you can omit it for fur- grounded return path. The purpose of Circuit provides 4- to 20-mA loop
for microcontrollers........................................89
ther cost savings. the second operational amplifier is to
The circuit derives its drive from a sim- provide a current source, rather than the Minimize the short-circuit current pulse
ple timer output in the microcontroller. current sink of the first stage, and the in a hot-swap controller ..............................90
The duty cycle of the timer determines grounded return path. Hence, pnp tran- Reduce EMI by sweeping
the output current of the circuit. The in- sistor Q3 provides this high-side drive. a power supply’s frequency ........................92
put RC network in front of the first op- Bipolar-junction transistors Q1 and Q3
erational-amplifier signal conditions the meet cost considerations, but you could Get just enough boost voltage ..................94
pulse train from the processor,so that the also use MOSFETs for slightly better per- Processor’s PWM output controls
op amp interprets it as a dc voltage. In ad- formance. LCD/LED driver ..............................................96
dition, the network ensures that the min- The open-loop feedback portion of
Method provides automatic
imum input voltage is close to 100 mV, this circuit lets the microcontroller
machine shutdown........................................98
even if the input is at ground potential. know that a fault condition exists on the
This minimum voltage ensures that the line. The processor can then execute Circuit makes simple high-voltage
feedback loop of the first op amp does alarm, shutdown, or other control func- inverter ..........................................................100
not fold back to the positive rail when tions to mitigate possible safety con- Publish your Design Idea in EDN . See the
you cut off npn transistor Q1. If you use cerns. When an open-loop condition oc- What ’s Up sect ion at w ww.ed n.com .
a dual supply, the transistor has the ad- curs, Q3 shunts the entire loop current
www.edn.com M ay 2 7, 2 0 0 4 | ed n 89

design
ideas
tion for this type of control system. microcontroller you select has a built- tion is important if you use a single-
Response time for a step change is ap- in A/D converter, response time can de- supply topology. An operational ampli-
proximately 500 msec, which is accept- crease by a couple of orders of magni- fier that can maintain stability close to
able for most current-loop control de- tude with the elimination of the in- its negative, or ground, rail is an im-
vices, such as control valves. If the put-filtering network. Op-amp selec- portant asset.
Minimize the short-circuit current pulse

in a hot-swap controller
Jim Sherwin and Thong Huynh, Maxim Integrated Products, Sunnyvale, CA
ecause of internal circuit- tor chip. The circuit of Figure 5
B
M1
RS
breaker delay and limited FDS7788 can limit short-circuit current to
0.006
MOS-gate pulldown current, 12VIN 12VOUT approximately 100A for less than
many hot-swap controllers do not 200 nsec. The pnp transistor, Q1A,
limit current during the first 10 to which triggers when the voltage
50 sec following a shorted out- across R S reaches approximately
put. The result can be a brief flow IN SENSE GATE 600 mV, drives the npn transistor,
of several hundred amperes. A ON MAX4272ESA STAT POR
Q1B,to quickly discharge M1’s gate
simple external circuit can count- capacitance. The steep voltage
CSPD GND CTIM
er this problem by minimizing the waveform aids quick triggering of
initial current spike and terminat- C1 the pnp transistor.
ing the short circuit 22 nF The oscilloscope’s ground lead
NC
within 200 to 500 nsec. A Figure 1 introduces an artifact, which ap-
typical 12V, 6A, hot-swap-con- A typical hot-swap controller circuit exhibits a 30- sec short- pears as the leading-edge oscilla-
troller circuit contains,as do many circuit current pulse of 400A peak. tion in Figure 6. Again, as in Fig-
others, slow and fast comparators ure 4, the apparent reverse-
with trip thresholds of 50 and 200 mV resistances. The waveform recorded dur- overshoot current and the steep rise in the
(Figure 1). The 6-m sense resistor, R S, ing a short circuit indicates a peak cur- waveform of Figure 6 arise from parasitic
allows a nominal slow-comparator trip at rent of 400 from the 2.4V peak across R S, series inductance in the sense-resistor
8.3A for overload conditions and a fast- decreasing to 100A in 28 sec (Figure 2). chip. C2 connects between the gate and
comparator trip at 33.3A for short cir- You can limit the short-circuit current source of M1 to reduce the positive-tran-
cuits. Only circuit resistances limit the duration to less than 0.5 sec by adding sient step voltage applied to the gate dur-
initial short-circuit current spike during a Darlington pnp transistor, Q1, to speed ing a short circuit.Zener diode D1 reduces
a period that includes the fast-compara- the gate discharge (Figure 3). D1 allows ID(ON) by limiting VGS to less than the 7V
tor delay and the 30 sec it takes to com- the gate to charge normally at turn-on, available from the MAX4272.Although D1
plete interruption of the short circuit by but, at turn-off,the con- M1
discharging M1’s gate capacitance. Vari- troller’s 3-mA gate-dis- RS FDS7788
ous elements, such as R S and the on-re- charge current is direct- 12VIN
0.006
12VOUT
sistance of M1, contribute to the circuit ed to the base of Q1. Q1
then acts quickly to dis- MMBTA64FSTR-ND
FLAG-COMPARATOR charge the gate, in less Q1
TRIGGER POINT
than 100 nsec. Thus, the D1
high-current portion of MMBD4148
the short circuit is limit-
ed to slightly more than
IN SENSE GATE
the fast comparator’s de-
VOLTAGE MEASURED ACROSS R S=6 m. lay time of 350 nsec. The ON MAX4272ESA STAT POR
apparent reverse over- CSPD GND CTIM
shoot current and the
C1
1V M5 SEC CH1 –200 mV steep rise in the wave- NC 22 nF
form of Figure
Figure 2 The short-circuit current 4 arise from Figure 3
in Figure 1 is 400A, decreasing to 100A in parasitic series induc- The addition of Q1 increases the gate-pulldown current, lim-
28 sec. tance in the sense-resis- iting the short-circuit-current duration to less than 0.5 sec.
90 e d n | M ay 2 7, 2 0 0 4 www.edn.com

design
ideas
M1
RS FDS7788
STEEP RISE AND
REVERSE OVERSHOOT 0.006
IN SENSE-RESISTOR 12VIN 12VOUT
VOLTAGE MEASUREMENT C2
IS AN ARTIFACT OF
SENSE-RESISTOR PARA- R1 D1 100 nF R3
SITIC INDUCTANCE.
100 5.1V 1k
Q1B
R2
100 FFB2227A
Q1A
M 250 nSEC CH1 –360 mV

IN SENSE GATE
Figure 5
ON MAX4272ESA STAT POR
Figure 4 The steep rise and reverse This hot-swap
overshoot in Figure 3’s circuit are artifacts of controller has CSPD GND CTIM
sense-resistor parasitic inductance. fast limiting of C1

short-circuit- NC 22 nF
is rated at 5.1V when biased at 5 mA, it current peaks.

limits VGS to approximately 3.4V in this
circuit because only 100 A of gate-charg- slightly more complex circuit (Figure 5)
ing current (zener-bias current) is avail- reduces the peak short-circuit current to
able from the IC. The limited VGS lowers 100A, as well as truncating the pulse width
ID(ON)—at some expense to on-resist- to less than 200 nsec. You can apply either
ance—and allows a quicker turn-off of technique to most hot-swap-controller
M1. You could also use D1 and C2 to some circuits. Individual results vary according
advantage in figures 1 and 3, to reduce to the impedance of the power source,the
ID(ON) during short circuits. impedance of the short circuit, and the
Either of the two circuits can protect a quality and attack time of the short circuit
backplane power source by minimizing itself. Note that it is inordinately difficult M 100 nSEC CH1 –520 mV
the energy dissipated when a hot-swap- to achieve a repeatable low-resistance short

controller circuit incurs a short circuit.The circuit by manual manipulation of a
Figure 6
simpler circuit (Figure 3) dramatically shorting bar. You require careful lay- This waveform depicts the
shortens the short-circuit-current interval out and low-ESR capacitors to create a short-circuit-current peaks for the circuit in
to somewhat less than 500 nsec, and the power source with very low ESR. Figure 4.
Reduce EMI by sweeping a power supply’s frequency

John Betten, Texas Instruments, Dallas, TX
witching power supplies can be but at diminished amplitudes. The sim- parator output trips to a low state. The
S notorious noise generators. You

should prevent this noise, which is
conducted, radiated, or both, from re-
ple circuit in Figure 1 makes the switch-
ing converter operate over multiple fre-
quencies rather than one, thereby
voltage on R 6 instantly drops to a lower
reference level because R 5 is now in par-
allel with R 6. C3 begins to discharge to-
turning to the input source, where it can reducing the time average at any one fre- ward this new reference level because R 3
potentially wreak havoc on other devices quency. This scheme effectively lowers is simultaneously in parallel with C3.The
operating from the same input power. the peak emissions. cycle repeats after C3 discharges to the
The goal of an EMI (electromagnetic-in- The circuit in Figure 1 is a self-starting voltage on R 6 when the comparator out-
terference) filter is to block this noise and oscillator with an oscillation frequency of put reopens.You must carefully select the
provide a low-impedance path back to approximately 500 Hz. When you apply components to ensure that the two volt-
the noise source. The larger the noise, the power, C3 begins to charge up from 0V, age-reference states of R 6 are lower than
greater the size,expense, and difficulty of and the output of the TL331 comparator the upper and lower possible charge
the filter design. Power supplies that op- is in a high-impedance state because its states of C3. The circuit uses C3 to adjust
erate at a fixed frequency have their noninverting input sees a higher voltage the oscillator frequency; you should se-
largest EMI emission at this fundamen- than that of the inverting input. As C3 lect C3 to have a lower value than C2.The
tal, fixed frequency. Emissions also occur charges, its voltage crosses the voltage ref- oscillator’s frequency is approximately
at multiples of the switching frequency erence of the R 1-R 6 divider,and the com- equal to

design
ideas 5V BIAS
C1 R1 R2
0.1 F 10k 49.9k
R3
10k
IC1
5 UCC3813
1 RT
4 1 8
IC1 13.7k COMP REF
3 C2 2 7
TL331DBV R4 FB VCC
1 F
Capacitor C2 ac-couples the ramp R5 2 24.9k 3
CS OUT
6
voltage of C3 into the UCC3813’s oscil- 6.04k 4

RC GND
5
lator pin. The injected signal adds to the R6 C3 CT

charging current of CT during its posi- 4.99k 0.1 F 330 pF
tive portion (ac signal), thus increasing

the controller’s operating frequency.
During the injected signal’s
negative portion, some of CT’s Figure 1 A low-frequency oscillator ramp, injected into the RC pin, modulates the supply’s switch-
charging current disappears, slowing ing frequency.
the controller’s operating frequency.
Figure 2 shows the effects of the inject- the frequency-sweep rate. the circuit below the power converter’s
ed signal on the charging of CT. R 4 con- The differential EMI-current measure- low-frequency limits, or saturation of
trols the magnitude of the current that ment of Figure 3 (1 dBV1 dBA) magnetics may occur. This circuit demon-
is injected. Reducing R 4’s value increas- shows the before-and-after effects of strates a low-cost, small-area approach to
es the range, or spread, of the operat- adding the frequency-shifting oscillator. reducing conducted-EMI emissions.
ing frequency around its nominal fixed This design easily achieves a 10-
frequency. The injected signal’s oscilla- dBA reduction with a 12-kHz
tion frequency, which C3 sets, controls sweep window. A wider win-
1
dow further reduces EMI, but
1 SEC the modulator frequency may
0.50V
be noticeable in the converter’s
10115 SWPS
output ripple voltage. It is also
desirable to make the injected
ramp voltage as linear in shape
as possible to prevent the
switching converter from
1 SEC BWL

1 50 mV DC
spending excess time at its
2 50 mV DC
200 mSAMPLES/SEC switching-frequency limits.The
3 0.1V DC
4 0.5V DC 1 DC 1.39V □ STOPPED nonlinearity can result in an
EMI response with two
Figure 2 The external oscillator varies distinct frequencies. You Figure 3 The EMI of the flyback converter
the charging of the timing capacitor. must take care not to operate differs with and without external modulation.
Get just enough boost voltage

Kieran O’Malley, On Semiconductor, East Greenwich, RI
VIN14V
dding a current-mirror circuit to
A a typical boost circuit allows you to

select the amount of boost voltage
and to ensure a constant difference be- SHUTDOWN
C1
22 F
+
5
L1
22 H
D1
VOUT24V
tween the input and the output voltages 4

SS
VOC
VSW
8
(Figure 1). This circuit is useful for high- 3 IC1
BC856BDWLT1 +
MBRS120T3 C3
side-drive applications, in which a sim- NC
CS5171 22 F
ple voltage doubler is unacceptable be- 1 2 Q1A Q1B
VC VFB
cause of the voltage range of the
C2 AGND PGND R2 R4
components involved or where the input 0.01 F 6 7 10k 8.2k
voltage can vary widely. You can also use R1
the circuit at the front end of a 4.7k R3
power supply to ensure that the F i g u r e 1 1.27k
PWM controller has enough voltage to

start correctly in low-input-voltage con- Adding a current-mirror circuit to a boost circuit allows you to get just enough boost voltage.

design
ideas
ditions. The circuit maintains a 10V dif- of 65V. In this case,VIN14V (nominal), you use a 10-k  resistor.
ference between VIN and VOUT, but you so you need VOUT to be 24V (nominal). Q1B mirrors the current and sets up the
can easily change it to provide other volt- First, calculate a value for R 2, thus estab- feedback voltage to the PWM circuit. The
ages. The PWM circuit in Figure 1 is the lishing the reference current. If you select CS5171 has an internal voltage of 1.28V
CS5171 from On Semiconductor (www. a reference current of 1 mA, you obtain (typical),so R 3 yields the correct feedback
onsemi.com), but you can use the idea voltage when the current flowing
with any boost circuit. The current-mir- through it is 1 mA. In this case, by select-
ror circuit, comprising the dual-pnp ing 1.27 k  for R 3, you obtain an output
transistor, Q1, and the associated resis- voltage of 24V. As VIN varies, VOUT tracks
tors, establishes a current that depends on it and maintains a 10V difference be-
the voltage difference between VIN and tween the input and the output. R 4 helps
VOUT. The dual-pnp transistor has a VCEO Because the output voltage is not critical, reduce the power dissipation in Q1B.
Processor’s PWM output controls LCD/LED driver

Joe Neubauer, Maxim Integrated Products, Sunnyvale, CA
he PWM (pulse-width-modulation) LED driver (Figure 3). The circuit com- voltage, VCONT:
T output available from many micro-

processors is based on an internal 8-
or 16-bit counter and features a pro-
prises simply the PWM source, capacitor
C, and resistors R D and R W. For CMOS
circuits, you calculate the open-circuit
grammable duty cycle. It is suitable for output voltage as VCONTDVDD, where
adjusting the output of an LCD driver VCONT is the control circuit’s output volt- where VREF is the reference voltage at the
(Figure 1), a negative-voltage LCD driv- age, D is the PWM duty cycle, and VDD is feedback input.
er (Figure 2), or a current-controlled the logic-supply voltage. The control cir- Bear in mind that the initial charge on
cuit’s output im- filter capacitor C produces a turn-on
VIN
IN MAIN 3.3V pedance is the sum transient. The capacitor forms a time
+
C1 SWIN C3
300 mA of the resistor values constant with R CONT, which causes the
R D and R W: R CONT output to initialize at a voltage higher
SDIG 3.3V R DR W. For the cir- than that intended. You can minimize
200 mA
REF C5 cuit of Figure 1, the this overshoot by scaling the value of R D
C8
MAX1552 output voltage, as high as possible with respect to R 1 and
1.5V
COR1
200 mA
V OUT
, is a function R 2. As an alternative, the microprocessor
C4 of the PWM average can disable the LCD until the PWM volt-
ON
SDIG ENSD 1.8V
OFF COR2 VIN
20 mA 5V
C6
ON
COR2 ENC2
OFF +
SW
RSENSE
ON C9
LCD ENLCD LCD
OFF L1 0.1 F 1 8
20V V CS
D1
1 mA
MAIN 2
LX 7
C2 ADJ DHI
R3 R4 C7 DIGITAL
R1 VOUT
ADJUST MAX749
RESET RS LFB 3 6
OUTPUT CTRL DLOW
R2
ON/OFF
LOW-BATTERY LBO GND 4 +
5
OUTPUT FB GND
Figure 2
CONNECTION FOR RFB
PWM-CONTROLLED
LCD BIAS
CCOMP
CONNECTION FOR
VDD RD
PWM-CONTROLLED
RW
FROM LCD BIAS
PROCESSOR
VDD RD
PWM OUTPUT RW
0 C FROM
PROCESSOR
PWM OUTPUT C
0
Figure 1
This simple circuit provides positive-output voltage LCD drive. This configuration provides negative-output-voltage LCD drive.

design
ideas VIN
1 F
C1F C1N
1 F
C2P C2N
2.7 TO 5.5V 1 /1.5 OUT
REGULATING CHARGE PUMP

age stabilizes. For Figure 2, the output + 4.7 F
1 F
voltage, VOUT, is a function of the PWM
MAXIM
average voltage, VCONT: MAX1570
LED1
EN1
ON/OFF
AND REFERENCE LED2
DIMMING EN2 AND LOW-DROPOUT
LED3
where VREF is the reference voltage at Figure 3
CONTROL CURRENT
REGULATORS
SET LED4
the feedback input. For Figure 3,the
LED5
output current is a function of the PWM RSET
average voltage, VCONT:

GND PGND
CONNECTION FOR
PWM-CONTROLLED
LCD BIAS
VDD RD
RW
FROM
PROCESSOR
PWM OUTPUT
C
where VREF is the reference voltage at the 0
Set output and K is the current-scaling PWM combines with current control in this LED-driver circuit.
factor.
R D isolates the capacitor from the feed- point, the following equation defines the mize ripple voltage at the output, you
back loop in the PWM-control methods. lowpass filter’s cutoff frequency: f C should set the cutoff frequency at least two
Assuming a stable voltage at the feedback 1/(2 RC), where R R D||R W. To mini- decades below the PWM frequency.
Method provides automatic machine shutdown

Jean-Bernard Guiot, Mulhouse, France
ome machines need to run for long 15 of relay K2T incurs a delay before open- tacts of K2T open,K1 turns off,and the ma-
S periods and therefore may finish ing, because K2T is a time-delay relay, the chine completely turns off. The varistors,
their work in the middle of the night machine stays on during the delay time. VR1,suppresses voltage spikes.You must se-
or during the weekend. For the time re- This delay allows a second contact of KSTOP lect VR1, K1, K2T, and H1 in accordance with
maining, until the operator returns, the to control an automatic telephone dialer the power-mains voltage and the power
machines stay idle, uselessly consuming (not shown) to inform the remotely locat- rating of the machine. You select KSTOP ac-
power. This Design Idea allows a machine ed operator and allows the process to fin- cording to the controller’s output (the re-
to completely shut itself down after finish supplementary tasks, such as cooling lay coil) and the power-mains voltage (the
ishing its work. In addition, the method down,removing chips,allowing coolant to relay contacts).The circuit has worked sat-
allows for informing the machine opera- flow back into the tanks, for example. isfactorily in hundreds of machines over
tor by phone. You insert the circuit into Once the delay time expires, the con- a five-year period.
the area that Figure 1 indicates as a
ADD CIRCUIT IN DASHED LINES TO EXISTING MACHINE
dashed line into the main supply line of
the machine. The relay, KSTOP,connects to FROM
1 2 TO
a free output of the programmable con- POWER
3 4 MACHINE
MAINS
troller of the machine.You must program 5 6
the controller in such a way that relay K1
FUSE 1A
KSTOP is energized as long as the process
is running. In normal operation, switch VCC
S1 stays in manual position; thus, the MANUAL AUTO 1 18 14
A1
power contactor, K1, is on, and the ma- K2T KSTOP KSTOP
2 15 11
chine receives power. When an operator S1 A2
starts the process, relay KSTOP energizes,
and the indicator,H1, lights, signaling the
operator that switch S1 is ready for
operation. The timer relay, K2T, is Figure 1 FROM
A1 A1 B1
1 CONTROLLER
also on,closing its contact 18-15. Switch- K1
VR1
K2T H1
ing S1 to automatic now has no effect. A2 A2
2
At the end of the process,relay KSTOP and

indicator H1 turn off. Because contact 18- This circuit allows a machine to completely shut itself off after doing its assigned task.

design
ideas
Circuit makes simple high-voltage inverter
Francesc Casanellas, Aiguafreda, Spain
1
simple high-voltage MOSFET in-
A
30 H
verter solves the problem of driving R1 D1
TO THE OTHER INVERTER
a high-side MOSFET, using a low- 340V
4.7 BYV26C
voltage transistor, Q1, and a special C1
+
C2
D2
arrangement involving D6 (Figure 1). 680 F 220 nF 12V

BYV26C R2 +
This inverter is much faster than those 22k
C3
D3 22 F D4
that optocouplers drive, so dead-time 1N4148 BYV28-50
problems are minimal. The inverter has Q1
D5
the usual blocking diodes D4 and D6,and C4
2N2907A
UF5406
the parallel diodes D5 and D8. Q3 provides 100 pF R3 R4
1M 22
the turn-off signal to Q2. When Q3 turns Q2
IRFP450
on, Q2’s gate short-circuits to ground
through R 4. R 4 limits current and damp- D6 OUTPUT
ens oscillations. Q2’s gate dis- BYV28-50
charges quickly; only the value Figure 1
D7
of R 4 limits discharge time. Q1 stays off, 1N4148
D8
thanks to R 2, and C3 charges to 12V This circuit is probably the Q3 UF5406
PWM
through D2. The gate pulse creates a cur- simplest high-voltage R5 IRFP450
rent through C4, and D3 protects the inverter you can build. 22
100 ed n | M ay 2 7, 2 0 0 4 www.edn.com

design
ideas
base-emitter junction of Q1. 12V inverter with 150% overload ca-
In the turn-on of Q2, the fol- pacity. If you change the MOS-
lowing scenario occurs: When FET, the value of C4 has to change
the control input, PWM, 1k
2N2222A according to the total gate charge
goes low, Q3 quickly turns Figure 2 plus the output capacitance of Q3,
off,thanks to D7. A displacement which is much lower and, in fact,
current, C4dV/dt, flows 2.2 nF 300
OUTPUT negligible. Q1 amplifies the ca-
through C4 to the base of Q1. Q1 1N4148 pacitor current, so C4 is propor-
charges the output capacitance tional to QG2hFE1. Make C4’s val-
INPUT
of Q3 and the gate capacitance of 2.2k ue no higher than necessary,
2N2222A
Q2, and Q2 turns on. C3 supplies 560 because the base current in Q1
the collector current. If the pe- would be too high. To obtain all
riod is long, Q1 keeps conduct- the speed advantages of the cir-
ing and compensating the leak- cuit, the PWM signal should be
age of Q3. If D6 were a Schottky This buffer enhances speed at the PWM input of Figure able to quickly drive Q3. If neces-
diode,which is leaky, you would 1’s circuit. sary, you can use a buffer circuit
have to reduce the value of R 1. A (Figure 2). You can drive the cir-
short cross-conduction period exists be- current spikes. The inductor needs a cuit with a single CMOS gate. The circuit
tween the two MOSFETs, a phenomenon snubber comprising D1, R 1, and C2. Note in Figure 1 is probably the simplest high-
that is more apparent when Q3 turns off that the inductor value is conservative voltage inverter you can design. It has
and Q2 turns on. A small inductor, L1, in and can be smaller. served in thousands of three-phase mo-
series with the main supply limits the The values are for a 370W, three-phase tor drives from 0.37 to 0.75 kW.
102 ed n | M ay 2 7, 2 0 0 4 www.edn.com

design
ideas The best of
design ideas
www.edn.com
Circuit provides ISFET-sensor bias

Brian Harrington, Analog Devices, Wilmington, MA
VCC
SFETs (ion-sensitive field-effect tran-
I sistors) are useful for measuring the

acidity of fluids. Accurate measure-
ments require that the ISFET’s bias con- + VA
3
1
8
+
RG1
7
V+
IC1 OUT
6
V01
2.5V RG2 5
ditions (ID and VDS) be held constant _
2 _ V– REF
VCC R1
4 20k
while the gate is exposed to the fluid un- AD8221 VD
V+ 3
der test. The acidity of the fluid changes VEE 7 +
the channel width, resulting in a gate- VDB 6

OUT IC3 Q1
source voltage, VGS, that is proportional AD8627 2
4 _ VG
to the fluid’s pH. A recently published V–
Design Idea shows a biasing circuit for VCC
VEE
FET + V5
the ISFET (Reference 1). The circuit in
3 7 1V
Figure 1 provides a simpler and more 1
+ V+ _
RG1
accurate implementation. Voltage VA IC2 OUT
6 VS
sets ID, the drain current, through ISFET 8 5

RG2
2 _ V– REF
Q1, while voltage VB sets VDS, the drain- 4
AD8221 VCC VEE
source voltage across Q1. Both AD8821 + VB
3V VEE
high-precision instrumentation ampli- _
+ V2 _ V3
fiers, IC1 and IC2, are configured for uni- 12V –12V
_
ty gain. IC3, the AD8627 precision JFET- +
input amplifier, buffers the drain

voltage, VD, ensuring that all of the
current flowing through R 1 flows Figure 1
through Q1. This circuit provides ideal bias for an ISFET, a sensor used to measure fluid acidity.
To control ID, amplifier IC1 forces the
differential voltage between its output to 20 k , ID scales to 50 A/V. Similarly, voltage within the common-mode range
and the reference input to equal its dif- amplifier IC2 forces the differential volt- of the circuit. For this circuit, the range
ferential input voltage, VA. Because the age between its output and the reference of VG is (VA2VEE)VG(V CC2
sensed differential voltage is equal to the input to equal its differential input volt- VA).
voltage across R 1, IDVA /R 1. With R 1 set age, VB, thus forcing VDS to equal VB. Figure 2 shows the advantage of the
(Note: If your design does
not require independent
Circuit provides adjustment of VDS and ID,
VREF
ISFET-sensor bias ..........................................95 the circuit can operate
from a single control volt-
Microprocessor supervisor and regulator
age. Tie VA and VB togeth-
form in-range voltage monitor ..................96
er and drive it with the de-
White-LED driver provides sired voltage VDS. R 1 is then VG +IN
REFIN
64-step logarithmic dimming......................98 equal to VDS/ID.) The volt-
Switcher improves age of interest, VGS, ap- VS ADC
IN
overvoltage-protection circuit ..................100 pears between the gate
voltage and the output of
Precision peak detector uses
IC2. A useful fea-
no precision components ..........................102 Figure 2
ture of this circuit
Publish your Design Idea in EDN . See the is that the current source
floats, enabling the gate This configuration shows the advantage of the floating gate
voltage to connect to any when the circuit of Figure 1 connects to an ADC.
www.edn.com J u ne 1 0, 2 0 04 | ed n 95

design
ideas
floating gate when the circuit is connect- sistor R 1 dominates the current-source than 450 V for drain-source voltage as
ed to the AD7790 differential-input sig- errors for currents higher than 1 A and, high as 2V.
ma-delta ADC.The gate voltage connects therefore, are less than 250 nA for drain
directly to the ADC’s reference. The only currents as high as 250 A. The VDS er- Reference
signal-conditioning circuitry required rors originate from the gain error of IC3 1. Casans, S, AE Navarro, and D Ra-
between VS or VG and the ADC’s input is and input offset voltages of IC2 and IC3. mirez,“Circuit forms novel floating cur-
a simple RC filter. The 0.1% error in re- The error in drain-source voltage is less rent source,” EDN , May 1, 2003, pg 92.
Microprocessor supervisor and regulator

form in-range voltage monitor
Ilie Poenaru and Sabin Eftimie, Catalyst Semiconductor, Bucharest, Romania
ow-cost microprocessor supervi- time to stabilize before you remove the VCC
L sors reset controllers when power-

supply voltages fall below given lev-
els. As added protection, you can also
reset. The threshold voltage of the
CAT811 microprocessor reset circuit,
IC 2, sets the lower limit of the voltage
VCC
R1 CAT811
reset the microcontroller when the pow- range, VLOW. This threshold can be 2.32 RST
M R R ST
er supply is too high by combining a to 4.63V using standard products. Cus- CAT431
low-cost shunt-voltage regulator with a tom threshold devices with thresholds as GND
supervisor that has a manual reset input. low as 1.8V are also available. The 1.24V IC2
A simple overvoltage/undervoltage-pro- CAT431L shunt regulator, IC1, and two R2
100k
IC1
tection circuit is easy to make (Figure 1). resistors, R 1 and R 2, set the upper limit,
The circuit’s output is active (low) when VHIGH: VHIGHVREF(1 R 1/R 2), where
the monitored supply voltage, VCC, is VREF is the internal reference voltage of GND
outside a predefined range. After the IC 1 (V REF1.24V). The maximum
Figure 1
supply voltage returns to within the VHIGH that you can set is 5.5V, and
functioning limits, the reset output, the maximum supply voltage is 9V. This simple circuit uses a microprocessor super-
RST, remains active for a minimum of This design uses the CAT811 supervisor and a shunt regulator to form an over-
140 msec. This interval gives the system visor with a threshold voltage of 4.63V voltage/undervoltage-protection circuit.
Figure 2 Figure 3
As the supply voltage rises into range, the reset pin in Figure 1 As the supply voltage falls into range, the reset pin in Figure 1
becomes active low. becomes active low.
96 e d n | J u ne 1 0 , 2 0 04 www.edn.com

design
ideas
for tests. The upper limit of the voltage tive (low) for a minimum of 140 msec serts when the supply voltage increases
range is 5.5V using a 10-k  poten- (Figure 2 ). When the supply voltage out of range (Figure 4 ). A reset signal
tiometer with R 17.75 k  and falls into range, the reset pin also be- also asserts when the supply voltage
R 22.25 k . As the supply voltage ris- comes active (low) for a minimum of falls out of range (Figure 5).
es into range, the reset pin becomes ac- 140 msec ( Figure 3). A reset signal as-
Figure 4 Figure 5
The reset signal in Figure 1 asserts when the supply voltage The reset signal in Figure 1 asserts when the supply voltage
increases out of range. falls out of range.
White-LED driver provides

64-step logarithmic dimming
William Hadden, Maxim Integrated Products, Sunnyvale, CA
he circuit of Figure 1 is designed wiper voltage of digital potentiometer sponds to minimum LED current and,
T for portable-power applications that IC 1. The op amp then multiplies that therefore, minimum brightness. Because
require white LEDs with adjustable, voltage by a gain to set the maximum the SET voltage is fixed at 0.6V, any volt-
logarithmic dimming levels. The circuit output current. Zero resistance at the age change at the left side of R 5 changes
drives as many as four white LEDs from potentiometer’s W1 terminal corre- ISET, and the resulting change in LED
a 3.3V source and adjusts C C
2 3
the total LED cur- 1 F 1 F
rent from 1 to 106 Figure 1

D A B B
mA in 64 steps of 1 dB 1 1 1 2
C 1N C 1P C 2N C 2P
each. The driver is a V IN
C
IN
1 OUT
3.3V C D D D D
charge pump that mirrors C 1 1 F
4 1 2 3 4
1 F
the current ISET (sourced IC
A 3
from IC3’s SET terminal) EN1
3 MAX1573
R A
to produce a current of 16
10k
1 EN2
4
LED1
D 4
1 5 R
(215 ISET3%) through
 3
RST
VCC
H1
11
+
IC 4 5k B
5
LED2
C 4
2 4
each LED. Internal cir- 14
R MAX4480
3 _
2
SET D 3
D IC 1.8k LED3
cuitry maintains the SET DS1801
1
2 C 3
15 LED4
terminal at 0.6V. To con- CLK
W1 9
GND
R R D
trol the LED brightness, 12
AGND 10k 1.8k
3 4 2
op amp IC2 monitors the GND L1

1 10
difference between the This circuit provides a logarithmic-function dimming
high-side voltage and the capability for white LEDs.
98 e d n | J u ne 1 0 , 2 0 04 www.edn.com

design
ideas
currents alters their brightness level. R 5 30 enters a bit into the register. The circuit
sets the maximum LED current: 25 uses only one potentiometer, so bits 0
R 5215 0.6/ILED(DESIRED), where ILED is 20
through 7 are “don’t-care” bits. Bits 8
the current through one LED. I
LED
through 14 determine the wiper position:
IC1 is a digital potentiometer with a log- (mA) 15 Bits 8 through 13 set the code, and bit 14
arithmic taper and an analog-voltage 10 is “mute.” (Logic one at bit 14 produces the
wiper.Each wiper tap corresponds to 1 dB 5
lowest possible output current by setting
of attenuation between H1 and W1 (pins the left side of R 5 at approximately 0.599V.)
0
11 and 9). The IC contains two poten- 64 48 32 16 0
After entering all 16 bits, enter the code
tiometers controlled by a 16-bit code via a CODE
and change the brightness level by driving
three-wire serial interface. To set the RST high. Figure 2 shows the logarithmic
Figure 2
LED current, drive RST high and relationship between an LED current and
clock 16 bits into the D terminal of IC1, LED current versus input code changes for the the potentiometer’s input code.
starting with the LSB. Each pulse at CLK circuit in Figure 1.
Switcher improves overvoltage-protection circuit

Jason Rubadue, National Semiconductor, Thornton, CO
vervoltage-protection typical propagation delays of
O
FDC5614P
VIN LOAD
circuits often protect elec- 500- to 6000-nsec turn-off
tronic devices from pow- 22 nF 1 nF 24k times and 1800- to 7000- sec
er-supply transients, such as a turn-on times. The improved
rise from plugging in batteries ADJ
PGATE propagation delay is a result of
ISENSE
or an external power adapter. VIN LM3485
the LM3485’s driver, which can
Although these devices tradi- R1 sink 320 mA and source 440
332k
tionally find use as hysteretic FB mA, as opposed to other over-
GND
switching controllers, you can voltage-protection circuits,
R2
reconfigure the LM3485 ( Fig- 33.2k
which sink only approximately
ure 1) to provide a robust 60 mA.
Figure 1
overvoltage-protection The LM3485 also has an ad-
circuit. A hysteretic switching controller can do double duty as an overvolt- justable overcurrent-protec-
By selecting the feedback re- age-protection circuit. tion feature. In the sample cir-
sistors using the formula VIN cuit, when the current exceeds
1.252(R 1R 2)/R 2, you can program the 1.1A, the LM3485 turns off the FET. Af-
IC to trip off at any level from 4.5 to 35V. ter 9 sec, the LM3485 turns back on
In Figure 1, R 1 and R 2 turn off the PFET the FET and begins sensing the current
when VIN exceeds 13.8V. You can calcu- again through the FET’s on-resistance.
late the hysteresis using the formula For more precise current sensing, add
VHYS0.01(R 1+R 2)/R 2. In this example, an external current-sense resistor be-
the expression calculates a hysteresis of tween the FET and VIN and then move
110 mV. The accompanying oscilloscope the ISENSE line of the LM3485 over to
plot of VOUT versus VIN shows the sam- the source of the FET. The sample cir-
ple circuit with a hysteresis of roughly cuit in Figure 1 is derived from the stan-
800 mV (2V/division, 0V level at lowest dard LM3485 evaluation board. You can
line, 500 nsec/division). Why isn’t it 110 easily modify this board to create an
mV as calculated? We measured This plot shows the hysteresis overvoltage-protection circuit by re-
Figure 2
the turn-off propagation delay of and the overvoltage trip point. moving a few components—the induc-
the sample circuit at approximately 450 tor, the diode, and the CFF capacitor—
nsec, almost one complete time division, delays into account, the scope plot ap- by moving the feedback line from VOUT
whereas the turn-on propagation delay proaches the calculated hysteresis and to VIN, and by selecting suitable resistor
was only 70 nsec (all measured using a 13.8V trip level. However, compare these values.
40 load). By taking these propagation times with competing ICs with larger
100 ed n | J u ne 1 0 , 2 0 04 www.edn.com

design
ideas
Precision peak detector uses no precision components
Jim McLucas, Longmont, CO
hen you need a precision peak The high-input-impedance FET improves its switching speed and pre-
W detector, you would usually im-

plement it with one or several op
amps and a few other associated compo-
source follower, Q1, and the associated
circuitry enclosed by the dotted line in
Figure 1 buffer the input to the com-
vents random oscillation when its input
voltage is in its linear range.
This circuit works by essentially creat-
nents. This technique usually works well parator. This buffer is essentially the de- ing its own reference for the negative in-
unless your design requires operation sign published in Reference 2. Op amp put of the comparator. If the voltage on
higher than a few kilohertz. In designs re- IC2D forces the dc voltage at the input to the positive input of the comparator is
quiring such operation, the accuracy of the comparator at the junction of D1 and greater than the voltage at the negative in-
the circuit severely deteriorates unless at R 3 to be equal within a few millivolts to put, the comparator’s output goes high
least one of the amplifiers has a high slew the dc voltage at the FET gate.If the peak and charges capacitor C3 until the voltage
rate and frequency response extending to detector has a driver with an impedance on the capacitor is a few millivolts greater
tens or even hundreds of megahertz. Per- of less than approximately 150, you can than the voltage on the positive input.
formance depends on the desired fre- eliminate the buffer in the dotted-line Then, the comparator stops charging C3
quency response and peak-to-peak in- box. However, as the source impedance until the cycle repeats. This action en-
put-voltage range of the peak detector increases, the accuracy of the peak detec- sures that the voltage on holding capaci-
(Reference 1). The circuit in Figure 1 tor decreases if you don’t use the buffer. tor C3 is nearly equal to the peak voltage
uses a moderately fast, inexpensive com- An LM306 comparator, IC1, provides suf- at the input to the comparator. Schottky
parator instead of a high-slew-rate op ficient speed and current to charge the diodes D2 and D3 couple the output to the
amp to implement the peak detector. holding capacitor,C3, over an input range holding capacitor,C3. The feedback from
This circuit provides wide bandwidth of 25 Hz to more than 1 MHz,with an in- the output of IC2A to the junction of D2
and high accuracy without the use of pre- put-voltage range of 500 mV peak to and D3 keeps D3 biased to 0V when it is
cision components, and it’s simple and more than 4V peak. The comparator ex- off, thereby preventing reverse leakage
inexpensive—about $3.50 (1000). hibits a few millivolts of hysteresis, which through D3 (Reference 2). The feedback
12V 12V 12V 12V

HIGH-IMPEDANCE C2
BUFFER 12V 0.1 F
R5 R6 R7
OFFSET C4
220k 1.2k 1.2k R9 ADJUST 0.1 F
Q1 R8 5k
R3
AC 2N5485 8 10k
560 R10
INPUT D 2
+ –12V 47k 4
R4 IC1 7 5 R13
S +
560 LM306 IC2A 7 10k
3 _ 1 R11 10
D2 D3 ¼TL084 +
R1 10M IC2B
R2 D1 SD101C SD101C 6 _ 8
10M R14 ¼TL084
1.2M 1N4148 C1 4 C3 R12 9 _
11 560k DC
0.1 F 0.1 F 150 OUTPUT
C6
R17
3.3 F
100
C5
–12V 0.1 F
3 R16
+
1 IC2C 2.7k
¼TL084
_ 2 –12V
R15
GAIN 50k
ADJUST
R21
Q2 1.2M
2N3904 R19 12
+
10k IC2D
14 C10
¼TL084
_
13 0.1 F
R18 C7
1.2k 0.01 F
Figure 1 –12V
C8 R20
2000 pF 1k
C9
0.1 F
This circuit provides precision peak detection,
using no precision components.

design
ideas
also provides reverse bias to D2 when the
TABLE 1—MEASURED RESULTS FOR PEAK-DETECTOR CIRCUIT
output of the comparator is pulled low.
Frequency (Hz) 25 50 100 1000 10K 100K 1M 2M 3M
The IC2A FET-input op amp has low in- % error (500 mV peak input) 2 0.6 0.2 0 1 0.8 0.5 3.2 5.4
put-bias current, so it does not discharge % error (1V peak input) 1.8 0.4 0 0.1 0.8 0.7 1.3 3 5.2
C3 between charging pulses. IC2C buffers % error (2V peak input) 2.1 0.4 0.1 0.3 1.0 1.4 0.6 2 3.8
the negative input of the comparator for % error (4V peak input) 2 0.8 0.5 0.5 0.8 0.8 0.5 1.8 3.5
the same reason.The 10-M resistor, R 11,
provides sufficient discharging of C3 so sary. If a precision ac source is not avail- voltage to exceed approximately 5V.
that the dc output from IC2B decay to a able, you can use an accurate dc source Table 1 shows measured results for the
negligible level in two to three seconds af- and a high-impedance voltmeter for cal- circuit. If desired, you can delete R 9, R 10,
ter removal of the ac-input signal. ibrating the circuit. Apply 500-mV dc to R 14, R 15, and R 16 from the circuit and still
R 13 and C6 filter the dc output to re- the input and adjust R 9 for 499 mV at Pin obtain good performance.
move most of the noise that the com- 10 of IC2. Then, apply 4V dc to the input
parator causes. R 14 provides a small and adjust R 15 for 3.980V output (Pin 8 References
amount of attenuation of the dc output, of IC2). The maximum peak input volt- 1. Simpson, Chester, “Fast amplifiers
so that R 15 can provide approximately age is approximately 5V, because the simplify ac measurement,” EDN , May 9,
2% adjustment of the dc output. For maximum input-voltage specification 1996, pg 100.
best precision, set R 15 for minimum gain for the LM306 is 7V. The accuracy of 2 Williams, Jim, A Designer’s Guide to
and apply a 500-mV, 10-kHz signal to the the circuit decreases when the input peak Innovative Linear Circuits, Volume II ,
input. Adjust R 9 for 500-mV dc output. is higher than 4V. Remember to use a Cahners Publishing, 1987.
Then, apply a 4V, 10-kHz signal and ad- blocking capacitor in series with the in- 3. Graeme, Jerald, “Peak detector ad-
just R 14 for 4.010V-dc output. Check and put if the signal to be measured includes vances increase measurement accuracy,
repeat these two adjustments if neces- a dc offset that can cause the peak input bandwidth,” EDN , Sept 5, 1974, pg 73.

design
ideas The best of
design ideas
! Check it out at:
www.edn.com
Circuit produces variable numbers of burst pulses

Michael Kornacker, Northrop Grumman Corp, Rolling Meadows, IL
he add-on circuit in Figure 1 can select the number of pulses and spaces.
T produce one to 15 burst pulses with

the same number of spaces between
the bursts at a pulse width (frequency)
Counter IC1 controls the number of
bursts,and counter IC2 controls the num-
ber of spaces. The two hexadecimal
Circuit produces variable numbers
of burst pulses ................................................79
Method provides fast, glitch-free isolation
that an external square-wave generator thumbwheel switches,S1 and S2, select the
of I 2C and SMBus signals ............................80
at the input sets. The add-on circuit count value. Each switch position is num-
produces a variable number of bursts bered zero to 15. S1 controls the number Simulate input-offset current
and a variable number of spaces be- of burst pulses, zero to 15,and S2 controls for current mirrors..........................................84
tween the bursts by using an external the number of spaces, zero to 15. For ei- Designing high current chokes
square-wave generator as a source. The ther the IC1 or the IC2 counter to count, is easy ..............................................................84
project in this design required a TTL Pin 7 must be high.If Pin 7 is low,then the
burst signal, but resources did not allow counter remains disabled. For a counter to What’ s Up sect ion a t w ww.edn .com.
for the expense of a burst generator. The be loaded with a desired count,Pin 9 must
circuit basically comprises two hexa- be low and then high. The carry output at
decimal, divide-by-16 counters set up Pin 15 is normally low until the counter to the zero state upon power-up. After
so that the counter on the left produces reaches a count of 15, and then it goes that, the thumbwheel switches set the
a user-selectable zero to 15 pulses and high. When the circuit is powered on, re- count value.
the counter on the right produces a sistor R 1 and capacitor C1 form an RC- When a clock signal arrives at the
user-selectable zero to 15 spaces. The time-constant power-on-reset circuit at counters’ Pin 2 with the desired fre-
two hexadecimal thumbwheel switches Pin 1. This feature initializes the counters quency, counter IC1 starts counting up,
and counter IC2 re-
S1 S2 mains in the off-state
0-FH SPACES
because the low signal
0-FH PULSES
at IC1’s Pin 15 carry
5V
output applied to IC2’s
4.7k 4.7k
R2 R6 Pin 7 disables counter
4.7k 4.7k
R3 R7 IC2. When IC1’s count
4.7k 4.7k reaches the end (15), it
R4 R8
4.7k 4.7k goes high and enables
R5 R9
IC2 to count. IC1’s car-
R2
ry output also goes
4.7k through inverter gate
IC 3A and then to the
16 10 6 5 4 3 1 6 5 1 C1
16 10 4 3 OR gate IC4’s Pin 1.
VCC T D8 D4
D2 D1 CLR VCC T D8 D4 D2 D1 CLR 10 F
FREQUENCY IC3A
The low signal on one
IC2
INPUT
2 IC1 15 2 15
input of IC4—and the
CLK CAR 7404 CLK 74161
74161 CAR
1 2 fact that,because IC2 is
P GND LD P GND LD now counting, its car-
7 8 9 7 8 9 ry output at Pin 15 is
IC3B
4 3 also low at IC4’s Pin
7404
2—means that a low
1
3
7432
signal appears at IC1’s
Figure 1
2 Pin 7, and thus IC1
IC4
GATE 2 now becomes dis-
3 BURST OUTPUT
7400 abled. Both IC1 and
1 IC 2 counters’ Enable
IC5
This circuit produces a variable number of burst pulses and spaces. pins are cross-con-
www.edn.com J u ne 2 4 , 2 0 0 4 | ed n 79

design
ideas
nected, so that when one counter is switches for the next count. this circuit to produce even more puls-
counting,the other counter becomes dis- When IC 1 is counting, the output of es or spaces by simply cascading more
abled. The two counters work in this IC 3A (the gate signal), assumes a high counter chips where needed. Also, you
way, back and forth, counting up to 15 level at AND gate IC5’s Pin 2. This state can replace switches S1 and S2 by an 8-
and enabling and disabling each other. allows the clock signal to pass through bit write-output register, making the
And finally for the two counters, when IC5 unimpeded to the output. The out- pulse and space counts software-con-
the carry output on IC2 goes high, the put of IC5 is the burst output.When IC1 trolled, or you could apply the gate sig-
circuit then, after it reaches a count of 15 is disabled and IC2 is counting, the gate nal to the control input of a CMOS
through the inverter IC 3B, loads a new signal from IC3A asserts a low signal at switch to burst analog signals, such as
count or reloads the old count into the IC 5’s Pin 2. The output is also low and sine waves at its input.
counters as set by the thumbwheel produces no bursts. You can configure
Method provides fast, glitch-free

isolation of I2C and SMBus signals
Mark Thoren, Linear Technology Corp, Milpitas, CA
2C is a popular serial protocol for V
I
V
power controllers, ADCs and DACs, 2k
EEPROMs, and other devices. In cer-

tain data-acquisition and power-control
situations, you must isolate the I2C BAT85
Figure 1
master from one or more slave de- ISOLATED SDA
V
vices for noise, grounding, or safety is-
sues. Also, although 128 peripherals may HCPL2300#300
connect to the bus,at some point,differ- 2k V
ences in ground potential and excessive 74HC125
bus capacitance begin to erode noise and
ISOLATED
timing margins. This Design Idea shows GROUND
how to provide fast, glitch-free optical BAT85
isolation of I2C or SMBus signals by us- SDA
ing a method that meets the require-

ments for the 400-kHz enhanced-I 2C- HCPL2300#300
2
bus specification. The I C bus consists of 74HC125 ISOLATED
bidirectional clock and data lines (SCL GROUND
and SDA) that are pulled up with resis-

tors or current sources. Devices connect
to the bus with open-collector I/O pins. This circuit represents a simple I 2C isolator.
One way to isolate I2C signals is with a
variation of the circuit shown in Figure leases its SDA line, the voltage on the line logic high puts the output in a high-im-
1, which shows only SDA; SCL operation rises until the isolated side’s LED can turn pedance state. Traces 1 and 2 show the
is identical. fully on. Only then will the nonisolated inputs to the enable lines of the SDA and
The circuit in Figure 1 works on the SDA line go low again. This situation oc- isolated-SDA buffers. Traces 3 and 4 show
principle that a device pulling the non- curs at various times during I2C com- the outputs, respectively.
isolated SDA line low turns on an opto- munications, including clock synchro- This type of circuit has been pub-
coupler LED, pulling the isolated SDA nization (on the SCL line), multimaster lished in a number of forms, often with
line low and disabling the isolated side’s arbitration, and SMBus interrupt arbi- slow optocouplers that require 5 to 10
optocoupler LED and vice versa.Howev- tration (on the SDA line). Figure 2 shows mA of LED drive. These circuits may
er, if devices on both sides of the isolation details of the operation of the circuit in work in a limited set of applications, but
barrier are pulling their respective SDA Figure 1. The 74HC125 tristate nonin- they are slow and still produce glitches,
lines low, the optocouplers are in an inverting buffers simulate the open-drain and trying to overcome speed and drive
determinate state, with both LEDs par- outputs of two I2C devices.A logic low on issues with high-speed components
tially on. When the nonisolated device re- the EN line forces the output low, and a makes the circuits almost unusable. The
80 ed n | J un e 2 4, 2 0 0 4 www.edn.com

design
ideas
circuit in Figure 1 uses fast HCPL2300 When both sides are idling high, both
optocouplers that require only 500 A optocouplers are off. When one side
of LED drive. If both SDA lines are held pulls its line below 0.4V (a safe assump-
low and then released at the same time, tion for both open-collector and open-
the optocouplers fight each other and drain outputs), the comparator turns on
form an oscillator (Figure 3). The char- its LED. The other side’s line pulls down
acteristics of this oscillation depend on to approximately 0.6V, which is still in-
terpreted as a logic low but does not re-
sult in that side’s LED turning on. When
both sides are pulling their lines low,
both LEDs are on. In this state, if one side
releases its line, it rises cleanly from the
low level of the I2C device’s output to ap-
proximately 0.6V. This scope photo shows the
Figure 5
Figure 5 shows details of the op- operation of the improved
eration of the circuit in Figure 4. The I2C isolator.
combination of the LT1719 compara-
tor and Agilent (www.agilent.com)
HCPL2300 optoisolator meets the tim-
ing requirements of the 400-kHz en-
The simple I2C isolator pro-
hanced I2C-bus specification. Total
Figure 2 propagation delay is approximately 100
duces large glitches under
some circumstances.
nsec, and you can adjust the logic
thresholds to suit other requirements.
pullup resistance, supply voltage, and Although you can use this circuit for
capacitance on the data lines. (Remov- both SDA and SCL lines to support full
ing one of the 9-pF scope probes stops clock synchronization, the extra cir-
the oscillation, and replacing it with a cuitry is unnecessary as long as the
10-pF capacitor starts it up again.) master never tries to communicate
The circuit shown in Figure 4 solves faster than the slowest slave device. If
these problems by setting up three Using high-speed components you don’t need clock synchronization,
logic levels:“high”(pulled up to 5V), Figure 3 you can use a single optocoupler for
in Figure 1’s circuit causes
“pulling low,” and “being pulled low.” unpredictable behavior. SCL.
5V
ISOLATED 5V
2k
SDA
LT1719
74HC125 169
V+ +
7.5k 11.5k
_ (0.4V)
V
HCPL2300 SHDN
1k
ISOLATED 5V
5V
5V
ISOLATED ISOLATED
GROUND GROUND
2k
ISOLATED SDA
LT1719
V+
+ 74HC125
11.5k 7.5k
Figure 4 169
(0.4V) _
V
The improved I2C SHDN HCPL2300
isolator is fast 1k
ISOLATED
and produces no GROUND
glitches.

design
ideas
Simulate input-offset current for current mirrors
Johan Bauwelinck, Gent University, Gent, Belgium
140
imulating the output-offset cur- matches, and so on, the in-
S rent of a current mirror is straight- put offset current is not

forward. You simply have to apply an equal to zero. The design in
input current, measure the output cur- Figure 1 provides high ac- S
120
E100
C
rent, and calculate the difference. This curacy and a low simulation N E
R
output-offset current, however, is not time. R
U 80
equal to the input-offset current, espe- You use feedback to force C C
O
cially when the circuit is not a 1-to-1 mir- the current of a CCCS (cur- F O 60
ror. Simulating the input-offset current rent-controlled current R E

B
with high accuracy is more complicated. source) to equal the input- M U 40
N
Suppose you’re dealing with a 1-to-1 mir- offset current. The current
ror and you want to know what input that flows into voltage 20
current is needed to obtain an output source VOUT is the difference

0
current of 10 A. Ideally, the input cur- between the output current –300 –200 –100 0 100 200 300 400 500 600 700
rent would be 10 A, assuming that the of the mirror and the INPUT-OFFSET CURRENT (nA)
input offset current is zero. However, be- ideal output current. Figure 2
cause of the finite beta of bipolar tran- This current is the “error This bar graph shows the input offset-current distribution.
sistors, finite output impedances, mis- current” (IERROR ). When the
CCCS equals the input- current).And, because you obtain the re-
offset current, then the sult by calculating the dc operating
CCCS error current is zero. The point, the simulation time is small.
G*IERROR IIDEAL IIDEAL high-gain CCCS ampli- Figure 2 shows simulation results of
fies the error current, and 500 Monte Carlo runs for IIDEAL10 A,
the CCCS adds to the in- gain G1000, and VOUT1V. The npn
put current. In this way, transistors have an emitter length of 40
IERROR you create a feedback microns and use a 0.35-micron silicon-
loop, and the current that germanium BiCMOS process, but you
you measure through the can use the simulation method for all
VOUT CCCS is the input-offset current mirrors and all types of transis-
current. The feedback tors. The average of the distribution in
Figure 1
loop implements a high Figure 2 is 194 nA, and the standard de-
gain that ensures a high viation is 131 nA. The average is not zero
Use this circuit for simulation of current-mirror input-offset currents. accuracy (negligible error because of the base-current error.
Designing high-current chokes is easy

Louis Vlemincq, Belgacom, Evere, Belgium
omewhat unusually, this Design many inductive components subjected more problematic to determine.
S Idea deals with a formula rather

than a circuit. You might think that
all the basic formulas of magnetic phe-
to high peak currents, such as dc filter
chokes, ac reactors for resonant con-
verters, and flyback transformers. In
The traditional methods of selecting a
suitable core size and air gap are gener-
ally based on tables or graphical infor-
nomena were discovered more than a such cases, you have to consider two mation. Examples of such methods in-
century ago. In fact, they probably were, main aspects: One is the current-carry- clude Hannah curves and energy-
but, at the time, some were of little prac- ing capacity of the wire, and the other is storage-capacity graphs. I found these
tical interest and were essentially disre- the peak induction that the core mate- methods cumbersome,inflexible,and al-
garded and never included in books or rial supports. The first point is well- most impossible to automate; hence, I
formula tables. I developed the formu- known and relatively easy to deal with, looked for a better approach. I wanted a
la describe here because I had to design but the magnetic induction is much formula as compact and elegant as the

design
ideas
one that is at the base of a symmetrical 1. Select a core size that seems likely to where 0 is the permeability of a vacu-
converter’s design: NV/(4BFA), where suit your application (The selection in- um (410 7), and k is a factor that
N is the number of turns required to formation that the manufacturer pro- depends on the implementation of the
achieve the target induction,V is the volt- vides can be useful.) air gap. For a single air gap, as in a po-
age applied to the winding in volts, B is 2. Use the formula and the core’s data tentiometer core in which the center
the peak magnetic induction in the core sheet to compute the number of turns re- pillar is machined, k 2. If,instead, you
material in tesla, F is the frequency of op- quired for the worst-case situation—in use spacers such as in a U-core, the air
eration in hertz, and A is the effective other words,the maximum peak current gap is split in two, and the factor k 1.
core area in square meters. and magnetic induction below the satu- If you need high accuracy for the in-
This formula is attractive because you ration limit for the whole temperature ductance value, you should build a sam-
need only essential parameters; you need range. ple to optimize the gap. Also, for small
not mess around with the permeability 3. Check that the resulting winding or large gaps, the formula loses its ac-
or the length of the magnetic path,for ex- does not exceed the capacity of the coil curacy because it assumes that the mag-
ample. By combining and algebraically former; if it does, select the next-higher netic material has a negligible reluc-
manipulating the fundamental equations size. tance compared with the air gap. If the
of the magnetic formula, I arrived at a 4. Compute the air gap required to gap is small or if the core material has
similarly simple equality applicable to achieve the target inductance using the a low permeability, the assumption
inductors: N(LI)/(BA), where L is the manufacturer’s data or the following for- about negligible reluctance is no longer
inductance in henries, and I is the in- mula (approximate): true. At the other extreme, the first-or-
stantaneous peak current in amperes. der term of the formula does not suffi-
Here again, you need no more parame- ciently compensate for the apparent in-
ters than the bare minimum. Using this crease in the core area that fringe fields
formula, a typical design procedure is: cause. Thus, discrepancies can exist be-

design
ideas
tween the calculated and the measured also increase the number of turns. How comes almost as large as the core, yield-
values. can this situation be? ing two implications: Because the sur-
The relationship N(LI)/(BA) can Increasing the current or the number rounding vacuum or air contributes as
also be useful in a different manner.You of turns results in an increase in ampere- much as the core itself to the inductance,
may want to reverse-engineer off-the- turns that the core sees, which should you can double the core area the formu-
shelf components to check that they do also increase the induction. The key to la uses with respect to the physical val-
not risk saturation at the intended peak understanding this apparent paradox is ue, and, even when saturation does oc-
current. (In converter circuits, the peak to take into account what the formula cur, the effect is much less brutal than in
current can be much higher than the implies: If L has to remain constant with a closed magnetic circuit. Second, the
rms current.) To do this reverse-engi- more turns, the air gap must be wider to simplified inductance formula is no
neering, you can use the form B(LI)/ reduce the apparent permeability () of longer valid.
(NA). For most general-purpose fer- the core,resulting in a greater current ca- To conclude, the user-friendly versions
rites, a peak induction of 0.2 to 0.25 tes- pacity, although the air gap appears of the formulas, expressed in more con-
la is acceptable, whereas materials for nowhere in the formula. The paradox venient units are:N0.01(LI)/(BA), with
power applications can tolerate more may explain why hardly anyone ever L in microhenries, I in amperes, B in tes-
than 0.4 tesla. Metal-powder cores ac- mentions this family of formulas. If you la, and A in square centimeters.
cept inductions as high as 1 tesla. If you try to superficially make sense of the im- And the user-friendly expression for
want to know what maximum current is plications of the formulas, you have to the air gap is
acceptable for a component, then the conclude that there must be a mistake
following form is convenient: I(BNA)/ somewhere.
L. At first sight, this formula looks coun- You can also apply the results to open-
terintuitive or even erroneous, because circuit magnetic components, such as
it seems to imply that you can increase cylindrical coils wound on a rod of mag- where  is in millimeters, A is in square
the current for a given induction if you netic material. In this case, the air gap be- centimeters, and L is in microhenries.

design
ideas The best of
design ideas
www.edn.com
Build a transformerless
12V-to-180V dc/dc converter
Francis Rodes, ENSEIRB/IXL, Talence, France
ome transducers for portable or
S automotive applications need accu-

rately regulated, high-voltage bias
and draw little current. To produce such
CD40106B
OUTPUT STAGE
D1 D2
high voltages from a low battery voltage,

designers typically use switch-mode Q2 C1
VC1
dc/dc converters—generally, flyback con-
VDD
verters. These converters exhibit high ef- 12V
ficiency at medium or high output pow- COUT VOUT
er. However, for the low output power for
biasing some transducers, the fixed VIN Q1 VOUT1
amount of power the power-switch
Figure 1
driver and the regulator circuitry re-
quire can have a detrimental effect on ef-
ficiency. Furthermore, the associated
transformer is rarely available off the
shelf, so it requires a custom-design ef- This four-IC circuit uses no transformers and converts 12V to 180V, using off-the-shelf components.
fort. This effort can account for 70% of
the entire design time. The two complementary MOSFETs, circuit in Figure 2 acts as a voltage-dou-
The circuit in Figure 1 overcomes the Q1 and Q2, mounted in a push-pull con- bler cell.
transformer-related problem,thanks to a figuration, represent the output stage of If you cascade N voltage-doubler cells
transformerless, switched-capacitor top- one CD40106 Schmitt-trigger inverter. in the chainlike structure of Figure 1, an
ology that requires only off-the-shelf The input signal,VIN, drives the push-pull extension of the voltage-doubler princi-
components. You can describe the oper- stage, producing a 0 to 12V square wave ple yields VOUT(N1)(VDDVD).From
ating principles of the circuit by first con- at 150 kHz. If you assume that VIN is 12V this equation, you can determine the
sidering the behavior of a single during the first half-period, then Q1 is on, number, N, of inverters you need to pro-
switched-capacitor cell and then extend- and Q2 is off. Consequently, D1 is for- duce a given high output voltage:
ing the concept to an N-cell voltage mul- ward-biased, and C1 charges positively to
tiplier. Figure 2 represents the equivalent VC1VDDVD, where VD is D1’s forward-
circuit of the first switched-capacitor cell. voltage drop (0.7V). Meanwhile, D2 is
forward-biased, and COUT charges to To produce 180V output voltage from
VOUTVDD2VD. During the second a 12V lead-acid battery, which can fluc-
Build a transformerless 12V-to-180V
half-period, the states reverse: VIN is 0V, tuate from 11 to 13.5V, an application of
dc/dc converter ..............................................83
Q1 is off,and Q2 is on, thus connecting the the equation with worst-case VDD of 11V
Build a simple one-chip negative terminal of C1 to the supply volt- yields
phototimer ......................................................86 age. This action forces the positive ter-
Solenoid trip circuit works minal of C1 to elevate itself to a voltage
at battery’s end of life ..................................88 higher than the supply voltage, VDD. D1
Servo loop improves now becomes reverse-biased and allows So, your design requires three
linear-regulator efficiency ............................90 C2 to charge up again through D2. If you CD40106 hex Schmitt-trigger inverters,
Boole helps simplify wiring assume that COUT’s value is considerably as Figure 1 shows. An inspection of the
and save money ............................................92 lower than the value of C1, then you can equation VOUT(N1)(VDDVD) re-
Publish your Design Idea in EDN . See the calculate that VOUT attains the value veals that the 11 to 13.5V fluctuation of
What’ s Up sect ion a t ww w.edn. com. VOUTVOUT1VC12(V DDVD). Thus, the lead-acid battery produces a propor-
assuming VDDVD, you can see that the tional 195 to 243V output-voltage fluc-
www.edn.com J u ly 8 , 2 0 04 | ed n 83

design
ideas
VBAT IBAT
12V
IC4 LP2951 8 1
+ C21
INPUT OUTPUT
1 µF
2
FEEDBACK + +
SENSE C22
NC
_ ERROR 3.3 µF
AMPLIFIER
8
VTAP NC
NC SHUTDOWN ERROR-DETECTION
COMPARATOR
60 mV
5
+
ERROR NC
_
1.23V REFERENCE
4
GND
D1 D2 D3 D4 D5 D6
C1 C2 C3 C4 C5 C6
IC1A IC1B IC1C IC1D IC1E IC1F

R1
33k
C20
100 pF
D7 D8 D9 D10 D11 D12
C7 C8 C9 C10 C11 C12
IC2A IC2B IC2C IC2D IC2E IC2F
VOUT
D13 D14 D15 D16 D17 D18 D19
180V
C13 C14 C15 C16 C17 C18 R2 IOUT
C19 10M
39 nF RL
H3 (LOAD)
250V
10k
Figure 2 IC3A IC3B IC3C IC3D IC3E IC3F
P3
100k
NOTES:
C1 TO C18: 33 TO 100 nF (63V).
D1 TO D19: 1N4148 OR EQUIVALENT.
IC1 TO IC3: CD 40106B.
IC4: LP2951 (NATIONAL SEMICONDUCTOR).
This circuit illustrates the operating principle of the basic voltage-doubler cell.
tuation. This variation is unacceptable tion techniques: Connect a high-voltage cause of the high cost and low efficiency
for biasing applications requiring accu- regulator directly to the output terminal, of linear high-voltage regulators, the cir-
racy. The obvious solution to this prob- VOUT, or control the low-supply voltage, cuit in Figure 1 uses the second regula-
lem is to regulate the output voltage, VDD, of the CMOS inverters to indirectly tion technique.
VOUT. You could use either of two regula- regulate the output voltage, VOUT. Be- The key element of the feedback loop
84 e d n | J u ly 8 , 2 0 0 4 www.edn.com

design
ideas
TABLE 2—OUTPUT REGULATION AND EFFICIENCY AT V BAT12V
is the low-cost, low-dropout regulator, IOUT (mA) VOUT (V) Ripple p-p (V) IBAT (mA) Efficiency (%)
IC4, the LP2951 from National Semicon- 0 180.3 0.08 3.4 NA
ductor (www.national.com).The output 200 180.6 0.1 7.6 40
of this regulator produces the variable- 400 180.7 0.1 11.7 52
supply voltage, VDD, to the 16 Schmitt- 800 180.2 0.15 19.8 61
1000 179 0.2 25 60
trigger inverters (IC1 to IC3). With this
arrangement, IC4 has to deal with input IC4’s error amplifier via the resistive di- converter. The input-regulation charac-
voltages ranging from only 11 to 13.5V. vider, R 2, R 3, and P3. IC1A, the first multi- teristic in Table 1 proves that the output
The output voltage, VOUT, feeds back to plier cell, produces the square waveform voltage does not fluctuate significantly
that the 18-cell,switched-capacitor volt- for battery voltages ranging from 11 to
TABLE 1—INPUT REGULATION age multiplier needs. Using the feedback 14V. From the output-regulation charac-
AT IOUT20 A network (R 1, C1), this Schmitt-trigger in- teristic in Table 2, you can see that the
VBAT (V) VOUT (V) verter constitutes a free-running oscilla- overall power efficiency attains 61%, the
11 180.3 tor that produces a 150-kHz square maximum output current reaches 1 mA,
12 180.3 waveform at its output. Tables 1 and 2 and the peak-to-peak output ripple volt-
13 180.3 show the measured electrical character- age does not exceed 0.2V.
14 180.3 istics of the regulated 12-to-180V dc/dc
Build a simple one-chip phototimer

Abel Raynus, Armatron International, Malden, MA
ecently, I needed to automatical-
R
MODE LED1 LED0 TIME (HOURS)
ly switch on a lamp when it became 0 OFF OFF ONE
dark and keep it on for a given time. R2 1 OFF ON TWO
Trying not to reinvent the wheel, I looked 100k 1 MC68HC908QT2 2 ON OFF FOUR
3 ON ON SIX
through what was available on the mar- S2
+ 3V MODE 7
ket, but I could not find an inexpensive PA0 LED0
5 IRQ
device that satisfied the requirement. PA2 6
Some products worked like a photo- PA1 LED1 L2004F31
switch, lighting a lamp when it becomes
VT80N1 2
dark and keeping it on while it is dark— R1
2 ADC 430 LAMP
in other words, the whole night. Others PA4
3 3 1
PA5
were designed as timers to turn a load on
and off at a given time and had no cor- 8
relation with darkness. These AUTO MANUAL ACTIVE
devices had more functions Figure 1 120V AC
than I needed, and they were rather ex- S1

pensive. As a result, I had to design the NEUTRAL
phototimer from scratch, and it turned This simple phototimer allows you to program the switch-on time after darkness falls.
out to be simple and inexpensive. The
phototimer (Figure 1) is based on the er delays by the pushbutton mode,switch photocell. The LTL-4231T-R1 LEDs from
low-end, eight-pin flash microcontroller S2.LED0 and LED1 indicate the prevailing LiteOn (www.liteon.com) come with
MC68HC908QT2 from Motorola (www. mode. After the delay time, the micro- built-in in resistors. You could also elim-
motorola.com). controller switches the lamp off and waits inate resistor R 2, but, in this case, Mode1
When switch S1 is in the Manual posi- for the next night to automatically repeat would be the start-up default mode. The
tion, the microcontroller disconnects the process. Teccor (www.teccor.com) L2004F31 log-
from the battery, and the lamp immedi- An advantage of the MC68HC908QT2 ic triac needs 3-mA gate current from the
ately switches on. When this switch is in is that it generates the time delay with its microcontroller, and it can deliver 4A
the Auto position, the microcontroller internal oscillator (12.8 MHz with 5% load current. Listing 1 is the C program
waits until it becomes dark and, after tolerance), meaning that you need not for controlling the phototimer. You can
that, switches the lamp on for a prede- use RC timing circuitry and struggle with download the routine from the Web ver-
termined time that the designer choos- component tolerances. I took some ad- sion of this Design Idea at www.edn.com.
es. This project has time settings for one ditional steps to simplify the design. The You can also modify the timer.You can
hour and two, four, and six hours. Dur- microcontroller’s PA5 input has an in- easily add time-delay modes making soft-
ing initialization, the timer sets the one- ternal, 30-k  pullup resistor, so there is ware changes plus adding indicating
hour delay as the default.You set the oth- no need for an external resistor for the LEDs; available microcontroller pins lim-

design
ideas
it the number of LEDs you can add. For example, as a continuous mode to light torola family allows you to increase the
more advanced projects, you can even the lamp just after power-up, without number of bidirectional I/O lines to 13.
use a seven-segment display, either di- waiting for night. You can use any type Also, instead of the photocell, you could
rectly or via a decoder, for time indica- of microcontroller in the project.For ex- use a different kind of sensor— temper-
tion. You can eliminate the Auto/Manu- ample, using the 16-pin microcontroller ature, pressure, or motion, for exam-
al switch by modifying Mode 0, for, MC68HC908QY2 from the same Mo- ple—to activate the time delay.
Solenoid trip circuit works at battery’s end of life

Brad Peeters, Theta Engineering, Costa Mesa, CA
his Design Idea involves a low- prevented the supply voltage from sag- the base of Q1, sufficient for Q1 to supply
T power motion-detector circuit that

operates from battery power for ex-
tended times. Part of the design includes
ging so dramatically, allowing the device
to continue functioning much further
into the battery’s life. However, the elec-
2A to the solenoid and remain well-sat-
urated. The design requires no current-
limiting resistor in series with the base of
a solenoid-operated trip mechanism that trolytic was bulky and expensive, and pre- Q1 because the outputs of the LP339 are
triggers whenever it detects motion. The sented an awkward packaging problem. naturally current-limited to approxi-
drive circuit for the solenoid in the orig- The circuit in Figure1 solves the prob- mately 60 or 70 mA each.
inal design worked fine as long as the bat- lem by incorporating feedback in such a Once the trip mechanism triggers, S1
tery was fresh but failed as the battery got way that any drop in supply voltage only opens, removing all power from the cir-
into the middle of its life, even though turns on the drive circuit harder. In test- cuit. The device remains in this state un-
sufficient energy remained in the battery ing, this circuit functioned even when the til you manually reset the trip mecha-
to operate the solenoid. The culprit was nominally 6V battery sags as low as 2V. nism. An entire trip event takes only
the battery’s internal resistance. The in- Q1 is a 3A, high-beta, low-saturation- about 10 msec, thus conserving the bat-
ternal resistance of a standard alkaline voltage pnp transistor that drives the so- tery and preventing excessive power dis-
cell increases as the cell’s life accumulates, lenoid. To energize the solenoid, Q1 has sipation in Q1 and the LP339. The re-
whereas the cell’s open-circuit voltage to turn on hard to minimize voltage drop maining section of the LP339 imple-
hardly changes.This increased resistance and get the most from the battery’s life. ments a single-section window com-
causes a sharp drop in supply voltage The circuit achieves the full turn-on by parator. A window comparator is neces-
whenever the drive circuit attempts to using three sections of an LP339 quad sary because motion detectors are com-
energize the solenoid. This drop upsets comparator in parallel. The LP339 is sim- monly ac-coupled circuits. You must
the drive circuit, preventing reliable op- ilar to the venerable LM339 but with low- apply the detection threshold equally to
eration. er power consumption, making it more positive or negative excursions. In other
The original design solved this prob- suitable for battery-powered applica- words,any excursion outside the window
lem by using a large electrolytic capacitor tions. Interestingly enough, it also has should trigger detection. In a quiescent
across the battery supply. This capacitor higher output drive. The three parallel state with no input signal, the network
functioned as an energy reservoir and devices provide approximately 200 mA to comprising R 3, R 5, and dual-diode D2
V
R1 + R2 V
C1
4.7M 270k Q1
R3 1 F S1
R4
220k FZT788
100k
+ C
IC2 2
3 10 F
V+ V+
7 + 1
2 OUT
1 V–
D2 12 6 + C
INPUT 4 – 3
D1 BAV99 – IC1B TLE2426
FROM 2 D4 6V 10 F
BAV99 5 LP339
MOTION + 1N4935 SOLENOID
DETECTOR IC1A 9
3 LP339 +
14
8 V–
–
V– IC1C
LP3 +
11 6V
+ BATTERY
13
R5 10
Figure 1 220k
–
IC1D
D3 R6 LP3
This motion-detector circuit BAV99 680k
works with 6V battery volt-

ages that sag as low as 2V. V–

design
ideas
keeps the negative input of IC1A one til it is higher than the negative input. Ei- A beneficial side effect of the time con-
diode drop above ground and the posi- ther case results in the output of IC1A’s stant formed by C1 and R 6 is to prevent
tive input one diode drop below ground. going high. This action in turn causes the false triggers on start-up by holding off
This level keeps IC1A’s output and, hence, IC1B, IC1C, and IC1D outputs to turn on, the IC1B, IC1C, and IC1D stage until the
the negative inputs of IC1B, IC1C, and turning on Q1 and energizing the sole- motion detector has had time to stabilize.
IC1D, low. Because R 1 and R 6 bias the pos- noid. R 4 provides positive feedback. If Q1 IC2 is a “ground-generator” chip, used to
itive input of IC1B, IC1C, and IC1D at ap- even starts to turn on, the partial turn-on create a circuit ground midway between
proximately 0.75V, the comparators’out- causes IC1B, IC1C, and IC1D to turn on the supply rails. In contrast to the origi-
puts remain off. more, precipitating a latch-up to ensure nal circuit,everything in this circuit is go-
The circuit trips if the input goes more that Q1 turns on all the way.Thus, all pos- ing in the proper direction to ensure pos-
than two diode drops above or below sible battery energy is delivered to the so- itive actuation of the solenoid once it
ground. For example, if the circuit’s in- lenoid. C1 provides further positive feed- reaches a trip threshold. The circuit uses
put goes below ground, the negative in- back when the supply sags. D3 protects only common, low-cost, and small com-
put of IC1A pulls down until it is lower the LP339’s inputs from being driven ponents. The circuit offers full usage of
than the positive input. If the input goes more than a diode drop below ground battery life and needs no bulky energy-
up,the positive input of IC1A pulls up un- when the power-supply sag is severe. reservoir capacitor.
Servo loop improves linear-regulator efficiency

Aurel Gontean, Technical University, Timisoara, Romania
inear regulators are easy to im- kHz fixed frequency. The LT1085, IC2, is an LT1085, maximum VDROPOUT is 1.5V;
L plement and have better noise and

drift characteristics than switching
approaches.Their largest disadvantage is
a good choice for the linear regulator. The
preregulator feedback loop uses an op-
erational amplifier, IC3.
for the LM2576T, VFB1.23V and if
k 1.5, VDROPOUT1.89V, slightly higher
than the value in the data sheet. The
inefficiency: excess energy dissipated as When the servo loop is closed, the dropout voltage is the same regardless of
heat. Several well-known techniques are feedback voltage for IC1 is: the output voltage and thus ensures rea-
(1)
available to minimize the input-to-out- sonable efficiency. (The overall efficien-
put voltage across a linear regulator.I had cy is greater than 56% for VOUT5V at 3A
been looking for an inexpensive, easy-to- and at least 72% for VOUT30V at 3A.)
implement, and efficient preregulator to The output voltage, VOUT, ranges from 0
reduce the dropout voltage of a linear If R 3R 5 and R 4R 6kR 3, Equation 1 to 30V, and VIN must be at least 5V greater
regulator. Closed-loop, self-oscillating becomes: than the maximum VOUT. IC3 has no spe-
preregulators built around a switching cial requirements, and IC2 may be any
transistor, a comparator, and a filter are kind of linear regulator. C6 reduces the
difficult to predict in terms of frequen- output ripple, and C2 filters some of the
cy. Thus, the power-mains input filter is 52-kHz noise on the control line coming
also difficult to implement. The best op- (2) from IC3. The result is a simple, robust,
tion is a fixed-frequency preregulator and high-performance laboratory pow-
combined with a linear, low-dropout Equation 2 yields the relationship er supply that can supply 3A in a 0 to 30V
regulator. The arrangement shown in VAVOUTVDROPOUTkVFB. You can set output-voltage range, using only a small
Figure 1 fulfills all the requirements. The the dropout voltage according to the lin- heat sink.
LM2576T-ADJ, IC1, switcher uses a 52- ear-regulator requirements. If you select
IC1
LM2576T-ADJ IC2
L1
1 4 LT1085
VIN IN FB 220 H
VA 3 IN
5
ON/OFF OUT
2 OUT 2 VOUT
3 ADJ
GND + + +
C1 D1 C3 C4 C5 R4 1 R1 C7 C8
+ D2 C6 R6
100 F C2 2200 F 100 F 100 nF 100 150 F 100 nF
R8 SR508 15k 15k
100 pF 3.3V 50V 50V 50V
50V 1% +
1%
6.8k
50V
25 F R2
–5V 2.5k
4 3
+
6 D3
2 R3 R7
IC3 – 12V
Figure 1 NE5534 7
10k 510
1%
R5 33V –5V
This inexpensive power supply uses a
preregulator to boost efficiency. 10k
1%

design
ideas
Boole helps simplify wiring and save money
Jean-Bernard Guiot, Mulhouse, France
o safely observe the positions of switches in series, Figure 1). cannot configure the circuit of Figure 1.
T two cylinders, you need two signals:

one circuit, X, which is open only
when both cylinders are in a safe posi-
This redundancy enables the detection
of errors, such as a short circuit within a
cable. The Boolean-logic equations of
Using Boolean arithmetic, you can derive
X ABAAB, which corresponds to
the schematic in Figure 2. You can easily
tion (two normally closed switches in these two circuits are X AB, and make a circuit equivalent to that of Fig-
parallel), and one circuit, Y, which is YA•B. The problem is that most small ure 2 using two ordinary SPDT limit
closed only when both cylinders are in limit switches are SPDT (single-pole, switches (Figure 3).
a safe position (two normally open double-throw) switches, with which you
A B A B
Y=AB B Y=AB •
• Y=AB •
A
B B
A A
X = A+B X = A+AB
X = A+AB
X = A+B
X = A+B
Figure 1 Figure 2 Figure 3
This circuit offers Boolean arithmetic proves Further simplification yields
redundancy in machine-control applications. that this circuit is equivalent to that of Figure 1. this circuit, which uses only two SPDT switches.

design
ideas The best of
design ideas
www.edn.com
High-side current monitor operates at high voltage

Greg Sutterlin and Brian Whitaker, Maxim Integrated Products, Sunnyvale, CA
he simplest technique R3 bias current is 500 A,but
T for measuring current in

an actuator or a motor is
to monitor the ground cur-
100m
FROM SUPPLY
(100 TO 250V)
the zener diode’s di/dt
slope goes negative below
300 A, a condition that
rent with a resistive element can introduce noise or
1 RS+ V+ 8
between the load and the IC1
even oscillation. The min-
2 RS– PG 7
ground. Because the device MAX4172 D1
imum specified bias—300
and its associated electronics 3 NC OUT 6
24V ZENER to 500 A—sets the max-
share a ground potential, 4 NC GND 5
Q1
imum value of R 1, and the
you need to amplify only the 300V PNP maximum allowed power
ZETEX
ground-current signal. This dissipation for R 1 and D1
FMMT597
approach,however, does not Q2 combined sets the mini-
300V PNP
detect device short circuits ZETEX mum value for R 1. Thus,
to ground, which can over- FMMT597 for supply rails of 100 to
load the high-side drive cir- OUTPUT
250V, a reasonable R 1 val-
R1
cuitry. To avoid such poten- (10 mV/mA) 150k ue is 150 to 225 k —150
tial fault conditions, you 17.5V FULL-SCALE R2 k  in this case.
10k
should use a high-side cur- Q1 and R 1 form a shunt
rent monitor to de- regulator. The design uses
Figure 1
tect short circuits Q1 because of its maxi-
and similar faults that can This circuit enables a 36V current-monitoring IC to operate at mum VCE rating of
occur following the current common-mode voltages as high as 130V. 300V, high gain of
monitor. High-side current 100V/V at 1 mA, and its
monitoring has advantages, but it finds voltage level, subject to limitations of the ability to handle 500 mW of power.Out-
limited use because of the dearth of de- external components. (The components put current is proportional to the voltage
vices able to handle the high voltage lev- in Figure 1 can accommodate 130V.) difference, VSENSE, between RS and
els—24V to many hundreds of volts— The accuracy of the circuit is better RS: IOUTgmVSENSE, where VSENSE
prevalent in the industry. Off-the-shelf than 1% for load currents greater than R SENSEILOAD. Transconductance for IC1 is
devices can operate to 32 and 76V, but 30 mA. IC1’s current-output stage allows 10 mA/V. If the maximum monitored
even 76V is insufficient for many appli- easy implementation of the current mir- load current, ILOAD, is 4A, and R SENSE is10
cations. Figure 1 shows a simple way to ror needed for level-shifting the output m, then the maximum IOUT is 10
adapt a standard 32V device for use at any signal to ground. Thus, you can easily mA/V10 m4A400 A.Thus,IOUT
monitor the ground-referenced signal by is proportional to ILOAD, and the maxi-
using an A/D converter or a comparator. mum expected output is 400 A. For ap-
High-side current monitor operates The circuit monitors load current in the plications of wide dynamic range in
at high voltage................................................65 presence of a 130V-dc common-mode which VSENSE can approach the absolute
level.You must ensure that you do not vi- maximum rating of the differential pair,
Digital potentiometers enable
olate IC1’s absolute maximum rating— 700 mV, you should protect the sense
programmable biquadratic filter................66
36V with respect to the ground pin—for pins by adding series resistors between
High-current supply uses the RS, RS, and V pins. For that R SENSE and RS and between R SENSE and
standard three-terminal regulator ............68 purpose, zener diode D1 limits the volt- RS. You should select the resistor val-
Synchronous flyback circuit provides ages between the V, RS, and GND ues to limit input currents to within 10
high-efficiency conversion............................70 pins to 24V. Thus, the typical voltage be- mA when the RS to RS difference is
tween these pins is 24V minus the VBE of 700 mV.
Q1, or 23.3V. The zener-diode current for IOUT is now proportional to ILOAD, but,
this circuit is approximately 700 A. for easy monitoring, you must level-
Note that the manufacturer’s suggested shift it to ground by using the Q1-Q 2
www.edn.com J ul y 2 2, 2 0 04 | ed n 65

design
ideas
current mirror. Q2’s high gain forces the maximum VCE rating of 240V. The de- I LOAD4A, VOUT400 A10 k 4V.
collector current to closely approximate vice in Figure 1 is rated at 300V. VOUT You can accommodate designs with
the emitter current which, when you now equals IOUTR 2. (The actual output lower or higher operating voltages by
apply it to R 2, produces a measurable current at Q2’s collector is slightly less, properly selecting Q 1, Q2, and the base
voltage at VOUT. As with Q1, Q2 needs a because of Q 2’s base current.) At resistor, R 1.
Digital potentiometers enable

programmable biquadratic filter
Deborah Mancuso and Donald Schelle, Maxim Integrated Products, Sunnyvale, CA
f the many types of analog filters
O
100 0
available to designers, few allow easy 90
SWITCHED-
SWITCHED- CAPACITOR-
adjustments of the filter parameters. CAPACITOR- –20 FILTER IC
80
The biquadratic, or biquad,filter is an ex- FILTER IC
70
ception,however.You can change that fil- –40
60
ter’s corner frequency (0), Q, and gain
(H) by adjusting the values of three resis- 50 –60
THD+N GAIN
tors.For that purpose, the lowpass biquad (%) 40 (dB)
–80
circuit of Figure 1 includes three digital 30 BIQUAD
potentiometers configured as variable re- 20
BIQUAD
–100
sistors in the feedback loops. Altering the 10
settings of these potentiometers changes 0 –120
the filter characteristics. The circuit pro- 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
1 0 1 0 0
, 0 0 0 0 1 0 1 0 0 0 0 0 0
duces corner frequencies of 5.5 to 55 kHz; 1 0 0,
0 0,
0 1 0
, 0,
0 0,
0
1 0 1 0
1, 1,
Q values of 0.055 to 5.5,depending on the FREQUENCY (Hz) FREQUENCY (Hz)
selected corner frequency; and gain of 1 (a) (b)
to 100, also depending on the selected

corner frequency. To tune the bi- Noise (a) and low bandwidth (b) plague switched-capacitor filters. The biquad filter
Figure 2
quad filter, you set a corner fre- of Figure 1 maintains less than 1% THD N over the range 20 Hz to 200 kHz.
15V 5V
C3 C4
1 F 1 F
Figure 1
6 10
R2 VDD VCC
7
H 1
SCLK SCLK
1k
C7 15V 5V C8
15V 5V
8
W IC2 CS
3
CSF
1 F 1 F 2
C5 5V 15V 9 DIN DIN
C6 L
1 F 1 F + C18 + C19 GND VSS MAX5438
47 F 47 F 4 C10
6 10 5
16V 16V 1 F
VDD VCC
10 6 7
R1 H 1
VCC VDD 1k SCLK SCLK + C20
7 8 W 3
1 H IC1 CS CSO 47 F –15V
SCLK SCLK 2 16V
3 8 C1 9 DIN DIN C2
CSH CS IC W L
2 3 1000 pF 1000 pF
9 GND VSS MAX5438 –15V R6
DIN DIN L 10k
4 5 C9
C11 VSS GND 15V C12 1 F
15V
1 F 5 4 MAX5438 1 F C14 15V
1 F C16
1 F
7 –15V R
4
–15V 2 7 R5
R3 – 330k
IC4 6 2 – 10k 7
1k 3 + 8 6 2
VIN IC5 –
3 8 IC6 6 VOUT
MAX437 +
1 4 3 + 8
MAX437
1 4 MAX437
1 4
C13 C15
1 F 1 F C17
–15V –15V 1 F
–15V
Digital potentiometers adjust the corner frequency, Q, and gain for this biquad analog filter.
66 ed n | J ul y 2 2, 2 0 04 www.edn.com

design
ideas C1
R2
R1
quency 0 in radians per second by ad- C2
justing digital potentiometer IC2 via the INPUT R3 R6

_
SPI interface. In the same fashion, set Q R4
_ R5
by adjusting IC1 and gain by adjusting IC3. +
_
Note that adjusting Q does not affect +

BP +
the corner-frequency setting, and a gain LP
R10
adjustment does not affect the settings of
Q or the corner frequency. The three R7 R9
equations below demonstrate this or-
thogonal tuning for the biquad filter: R8 BS AP HP
_
NOTES:
AP=ALLPASS. +
BP=BANDPASS.
BS=BANDSTOP.
HP=HIGHPASS.
LP=LOWPASS.
Figure 3 The standard biquad filter circuit produces lowpass and bandpass responses,
and the addition of a fourth op amp produces a highpass response. Removing R 10 and adjusting
various component values produce a notch or bandstop response or an allpass response.
where R IC1, R IC2, and R IC3 are the input re-
sistances of IC1, IC2, and IC3, respective- change for more pc-board real estate. en application.You can implement 15V
ly. The circuit in Figure 1 is substantially And, because monolithic switched-ca- voltage rails using digital potentiometers
more complex than the switched-capaci- pacitor filters are usually expensive, the and high-voltage op amps, such as the
tor approach usually integrated into an biquad circuit of Figure 1 may be a cost- MAX5438 and MAX437. The biquad fil-
IC, but the switching noise and low band- competitive solution. Many filter applica- ter is not limited to the lowpass response.
width of a switched-capacitor filter are tions require higher supply voltages,bipo- You can implement highpass, bandpass,
unacceptable in many applications (Fig- lar operation, or both, so the single 5V bandstop, and allpass filters by adding a
ure 2). A biquad filter offers better fre- supply associated with most switched-ca- fourth op amp to selected terminals of the
quency and noise performance in ex- pacitor filters may be inadequate for a giv- original lowpass design (Figure 3).
High-current supply uses

standard three-terminal regulator
I Hakki Cavdar, Karadeniz Technical University, Trabzon, Turkey
oltage-regulator design three-terminal regulators. These
V
VOUT
for high output currents 78xx regulators each handle 1A and

IC1 D1 IC2 D2
can be a critical and diffi- 78L12 78L12 are available in 5, 6, 8, 9, 10,12, 15,
VOUT  VOUT 
cult task. Although voltage reg- VIN IN OUT IN OUT 18, and 24V versions. In Figure 1,
ulators with 1A maximum out- COM
C1
COM
RL
two 7812 regulators are connected
C2
put current are simple to design, in parallel.
+
thanks to 78xx three-terminal C The two 7812s operate inde-
voltage regulators, at output VCOM pendently, and each delivers a
currents higher than 1A output, maximum of 1A. D1 and D2 sepa-
problems arise. For high D rate and isolate the two regulators.
output currents, voltage Figure 1 The output voltage is the regula-
regulators usually use parallel- tor’s nominal output minus a
Two 7812s connect in parallel to double the available output
connected power transistors. diode drop: VOUTVREGVD. The
current to 2A.
The design of the operating output voltage of the regulators is
points of these power transistors is a dif- power resistors dissipate high power, so the specified value if the COM pin con-
ficult task, because the transistors need the design needs heat-sinking.This Design nects to ground (0V). To increase the
critical power resistances at the collector Idea implements a simple voltage regula- output voltage of the circuit in Figure 1
and the emitter to set the dc operating tor that delivers high output current. The to the desired value, the COM pin must
point. Both the power transistors and the basic idea is to parallel-connect multiple connect to a voltage point one diode drop
68 ed n | J ul y 2 2, 2 0 04 www.edn.com

design
ideas VOUT
IC1 D1 IC 2 D2 IC20 D20

78L12 78L12 78L12
above ground. C, C1, and C2 are filter ca- VOUT VOUT 

VOUT 
VIN IN OUT I N O UT IN OUT
pacitors. Figure 2 shows a voltage regu-
COM COM C2 COM
C1
lator that uses 20 7812s and delivers 20A. C20
RL
All the diodes are 1N4007 types. C

+
C47,000 F, and all the numbered ca-

VCOM
pacitors have a value of 4700 F. The
7812s all connect to a heat sink
that a small fan ventilates.You can Figure 2 D
expand the concept of this Design Idea

to hundreds of amperes. A total of 20 7812 regulators extend the capability of Figure 1’s circuit to 20A.
Synchronous flyback circuit provides

high-efficiency conversion
Wayne Rewinkel, National Semiconductor, Phoenix, AZ
uck regulators are usually the cuit that looks a little like a buck regula- transistor and 6.2V zener diode and from
B first choice when you design non-

isolated step-down regulators un-
less the ratio of VIN to VOUT is greater than
tor and uses a buck controller but is ac-
tually a voltage-mode, synchronous fly-
back circuit. The application it targets
a bootstrap winding. Its EN (enable) in-
put is a comparator for UVL (under-
voltage lockout) to prevent start-up be-
10, the input voltage is high,or both. Low needs 3.3V at 2A with an efficiency re- low 28V. The controller drives a
duty cycle can be problematic for FET quirement of greater than 85% and an synchronous switch that provides lower
drivers and cause current-mode control input-voltage range of 36 to 60V. This loss than a Schottky diode and uses the
loops to lose control. Efficiency can fall one appeared the most promising of sev- lower FET’s on-resistance as the sense re-
dramatically to 60 to 70% at low VOUT eral evaluated technologies because of ef- sistor for current limiting. The 150-k 
and current of only a few amps. The efficiency and cost advantages over buck resistor at Pin 11 produces a switching
ficiency loss arises from switching loss- and asynchronous-flyback approaches. frequency of 250 kHz. The flyback trans-
es, because the upper switch always sees The LM2743 controller derives its former, designed by Pulse Engineering
full load current. Figure 1 presents a cir- power after start-up from the MMBTA06 (www.pulseengineering.com), is a low-
VIN
36 TO 80V
Figure 1
1N4148 10
4 1 µF
MMBTA06 1k
1k
1N4148 NS=1
3
1 F
5
100 nF 49.9k PA0791
LP 9 10
100k
6.2V NP=3
3010 50 µH NS=1
V PGD 2
6 7
7 6 5 4 3 2 1
ISEN PWGD V5 SGND PGND LG BOOT
RSNP 10 µF
LM2743MTC 100 6V
ON=1.08V
Si4850 CSNP RSNS
100 pF 20
EAO SS FB FREQ EN PGND HG LOUT
8 9 10 11 12 13 14 CSNS 330 nH
1813
470 pF
0.1 µF Si4848 VOUT
150k 300k 3.3V, 2A
470 µF
120 pF 10k 1k 4V
0.1 µF
3k 4.53k
This synchronous flyback circuit provides high efficiency with wide input/output ratios.
70 ed n | J u ly 2 2 , 2 0 04 www.edn.com

design
ideas
0.90 5
cost unit that provides 50 H of primary
inductance and a 3-to-1 turns ratio in a
13L15W11H-mm footprint. Its 3- 0.80 4
to-1 turns ratio prevents the primary
switch from seeing full output current,
0.70 3
resulting in less switching loss than that v60
v48 x x
of a buck regulator. The small LC filter at EFFICIENCY v30
x
WATTS
x LOSS60 x
the output allows a single 10-F ceram- 0.60 x LOSS48
x
2
LOSS30 x
ic capacitor to handle the high rms rip- x
ple current, and a low-cost aluminum x

0.50 x 1
capacitor also removes ripple and buffers
x
load transients. x
x
x
x
Figure 2 plots measured data at three 0.40 0

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
input voltages and several output cur-
I (A)
rents for the circuit in Figure 1. Ef- OUT
ficiency is displayed on the left for Figure 2

The circuit in Figure 1 provides more than 85% efficiency
the three uppermost curves,and the three over a wide range of output currents.
lower curves show total loss in watts
measured by the scale on the right. VOUT is important. You obtain best perform- nous flyback circuit applies to a wider
ripple measured 6 mV p-p at no load, ris- ance with four or more layers, separate power range; you can easily extend it to
ing to 20 mV p-p at 4A. The rapid fall in power and ground planes, and short and multiple outputs by adding secondary
efficiency at 3.5A comes from current wide gate-drive connections. Although windings. The additional outputs can use
limiting. As with any switcher and espe- the circuit of Figure 1 targets use in a 7W, either diode rectifiers or additional FETs
cially for flyback designs, pc-board layout single-output requirement, this synchro- driven from the low-gate driver.
72 ed n | J u ly 2 2 , 2 0 0 4 www.edn.com

design
ideas
LED driver doubles as fault monitor
Anthony Smith, Scitech, Biddenham, Berdfordshire, England
EDs find wide use as indicators and and pulls high, thus indicating a healthy diately turns off and deprives Q2 of col-
L as light emitters in devices such as LED.

optocouplers. In some applications,
lector current. Q2’s base-emitter junc-
Because Q2 and Q4 are both now on, tion now behaves like a diode, clamping
the LED or the emitter may be located re- the base potential of Q1 sits at roughly Q1’s base to a potential dictated mainly
motely at some distance from the main two VBE drops below the positive-supply by Q 2’s VBE drop and by the ratio of R 3
unit. Typical examples are dashboard- rail, VS , thereby placing one VBE drop to R 4. Because R 4’s value is smaller than
mounted automotive indi- that of R 3, Q2’s emitter po-
cators and industrial op- VS (5V NOMINAL) tential now rises toward VS.
tosensors. In critical ap- Once again, Q4 turns off and
R4
plications, you may require R1
2k goes low to indicate the fault
some means of monitoring 68 condition. With the resistor
Q4
the integrity of the LED. Us- values shown in Figure 1,
ing just four transistors and Q1 Q2 Q1’s base now sits at approx-
six resistors, this circuit pro- OFF 5V R3
FAULT imately 4V, leaving only 200
vides switchable, constant- 39k R5 to 300 mV across R 1. There-
VCONT
current drive for an 0V
ON 10k fore, the short-circuit cur-
LED and indicates Figure 1 R2 rent is effectively “choked
22k R6
both open- and short-cir- Q3 back” to less than a third of
100k
cuit fault conditions (Figure the normal value, thereby
1). And there’s a bonus, too. saving power—the bonus.
LED
Control signal VCONT Under normal conditions,
switches the LED on and with the LED on, Q1 con-
off. When VCONT is high, Q1 ducts more current than Q2,
and the LED are off. When 0V
causing its VBE drop to be
VCONT is as low as 0V, Q1 slightly larger than that of
turns on and sources a con- This LED driver doubles as a fault monitor and limits short-circuit current Q2. Consequently, the poten-
stant current to the LED. to boot. tial across R 1 is slightly less
Because most LEDs have a than a diode drop, and you
forward-voltage drop of at least 1.2V, ad- across R 1. Consequently, with R 168, may need to experiment with the value
equate base-bias voltage exists for Q3, Q1 sources a steady current of approxi- of R 1 to set the desired LED current.
which turns on,thereby providing a con- mately 10 mA to the LED. Provided that You must select R 3 to satisfy the base-
duction path for Q2. This conduction, in the value of R 2 is large enough,little of the current requirements of Q1 and Q2 when
turn, provides bias for Q4, which turns on LED’s forward current diverts into Q3’s VCONT is low. Tests on the prototype cir-
base. As long as the LED remains un- cuit produced good results with R 339
damaged, FAULT stays high, signaling k , although a smaller value may be re-
LED driver doubles as fault monitor ........83 normal drive conditions. Should the LED quired, depending on the LED current
go open-circuit, Q1’s collector load be- and the current gain of Q1 and Q2. When
Current source enables
comes just R 2 in series with Q3’s base. Be- the LED is on, both Q2 and Q3 are fully
op amp’s output to go to ground..............84
cause R 2 is much larger than R 1, Q1 satu- on, so a reasonably large value of R 5 is re-
Circuit distorts duty cycle rates, the voltage across R 1 falls to around quired to limit their joint collector cur-
for CML inputs ................................................86 20 mV or so, and the emitter potentials rent to an acceptable level. However, R 5
Build a charge pump of Q1 and Q2 rise toward VS. With insuf- must not be too large, or Q2 will be un-
with ultralow quiescent current ..................88 ficient base drive, Q4 now turns off, and able to furnish the current that R 4 and
the output falls to 0V to signal the fault Q4’s base require. Making R 5 approxi-
What’ s Up sect ion at w ww.edn .com. condition. mately four or five times larger than R 4
On the other hand, if a fault puts a is a good starting point.
short circuit across the LED, Q3 imme- Although the circuit in Figure 1 has a
www.edn.com A u gu s t 5 , 2 0 04 | ed n 83

design
ideas
5V supply, you could use other voltages, saturation, but beware of problems if devices with high current gain should be
provided that you scale the resistor val- you use a blue or a white LED, because adequate, although Q1 may need to be a
ues accordingly. Operation at lower volt- these devices tend to have relatively high power device if your design requires a
ages is possible as long as Q1 has ade- forward-voltage drops. The transistor high LED current,a high supply voltage,
quate “headroom” to stay out of types are not critical; most small-signal or both.
Current source enables

op amp’s output to go to ground
Frank Chan, Vancouver, BC, Canada
he LM324 is a cost-effective choice voltage down to the 120
T for an op amp, especially when you

need to apply ground-level inputs.
Although its output purportedly includes
millivolt level. In
Figure 1, Q1, Q2,and
R 3 form a 4-mA cur-
100
80
ground, its poor current-sinking capa- rent source that
VOUT (mV)
bility limits the applications. At output drains the output of 60
voltages lower than 0.5V, the op amp’s the LM324. R 4 is the R4=3.9k.
40
sinking current ranges only from 2 to 100 load, demanding a R4=30k.
A. You can add an external current- sink current of 4 20
sinking circuit to bring the usable output mA. This design
uses a 2N2222 0
15V 15V 15V 0 20 40 60 80 100 120
transistor for its
Figure 1 R1 VIN (mV)
10k R4
low saturation
3.9k R3 voltage. The out- With 0.5-mA load current, the output volt-
3.6k put characteris- Figure 3
LM324 age is linear down to 4 mV.
VOUT
+ tic becomes the
–
saturation characteristic of the added voltage is linear down to 4 mV. Figure 4
VIN + – transistors, Q1 and Q2. Using this cur- is the original output characteristic of the
R2 Q1 Q2 rent source, the output voltage is lin- LM324 driving R 4 (3.9 k ) without the
10k ear down to 22 mV above ground. added sinking current source. The cur-
Figures 2 and 3 show the output rent source presents a constant load to
characteristics. The lowest usable the LM324. You can configure a leftover
An external current source can bring the output voltage depends on the load op amp as a voltage comparator to cut off
usable output level of an LM324 down to (sink) current. When the load current the current source when the output volt-
the millivolt level. is 0.5 mA (R 430 k ), the output age is higher than 1V.
1600 1600
1400 1400
1200 1200
1000 1000
VOUT (mV)
800 VOUT (mV)
800
600 600
400 400
200 200
0 0
0 200 400 600 800 1000 1200 1 400 1600 0 500 1000 1500 2000
VIN (mV) VIN (mV)
Figure 2 Figure 4
The transfer function of Figure 1’s circuit is linear down to the This graphic shows the LM324 transfer function without the
low-millivolt level. added current source.
84 e d n | A ug u s t 5 , 2 0 0 4 www.edn.com

design
ideas
Circuit distorts duty cycle for CML inputs
Dieter Verhulst and Xin Yin, Ghent University, Belgium
o test a gigabit-speed data-re- 3.3V 1.5V 1.8V
T covery chip, you need a clock with a

controllable duty cycle. Because
most pattern and clock generators have
3.3V
130 130
C1
VP
50 50
a fixed duty-cycle output of 50%, the de-

PECL 10 nF CML
sign may require a small circuit to dis- VN
tort the duty cycle. The signal with con-
trollable duty cycle drives a standard MC100EP16 82 82 C2 C3
10 pF 10 pF
CML (current-mode-logic) input with 3.3V
on-chip termination resistors. One side,
VP, of the differential CML input takes VIN
single-ended drive from a PECL (posi-
VREF
tive-emitter-coupled-logic) circuit (Fig- VOUT
ure 1). The other input, VN, connects to

a controllable dc voltage. If this dc volt-
ADJUST
age is equal to the average voltage of the 1k
NCP565-D VREF
single-ended signal, the duty cycle stays
50%. If the signal has nonzero rise and 100
fall times (TRF), you can distort

Figure 1
the duty cycle by lowering the dc
voltage (Figure 2). The distortion gen- This circuit can make slight adjustments to the duty cycle you apply to a CML input.
erated is equal to the time difference be-
tween the crossing of the single-ended TRF /2
VP
signal and its average and the crossing
between the single-ended signal and the
set dc voltage (DT). Thus, the theoreti-
cal maximum distortion that you VN
can generate is TRF. Figure 2
DT
You can control TRF by selecting a
buffer with the desired TRF value, the By exploiting the rise and fall time of a signal and manipulating a dc bias voltage, you can
MC00EP16 buffer in this design, and by control the duty cycle of a CML signal.
changing the output capacitance for this
buffer (C2). To set the voltage at node VN, source instead of applying a dc voltage Because the single-ended signal is ac-
the design uses the internal termination source. This procedure makes the circuit coupled, the average voltage of this sig-
resistors and a controllable current more immune to power-supply changes. nal at node VP is equal to the internal ter-
Figure 3
(a) (b)
This photo shows duty cycles of 55.1% (a) and 65.3% (b).

design
ideas
mination voltage of the CML input. If no creates a stable, controllable current therefore, the duty cycle for the signal
current enters the VN input, this node source. The buffer inside the reference that the CML input sees. The circuit was
also assumes the internal termination drives the bias voltage of an npn tran- tested with a 1.25-GHz clock. Figure 3
voltage, and the duty cycle is 50%. This sistor and changes it until the voltage at shows the waveforms of the differential
voltage is independent of the average Adjust is equal to VREF . The current signal (VPVN) at the CML input set at
voltage of the single-ended signal at the pulled through the transistor and the VN 55% (Figure 3a) and 65% ( Figure 3b).
buffer’s output and the internal termi- input is equal to VREF/R. R is the resist- The described circuit increases the duty
nation voltage. ance between the emitter of the transis- cycle; if the duty cycle needs to decrease,
The NCP565-D voltage reference, us- tor and ground. Changing R changes you’d connect the single-ended signal to
ing a reference voltage, VREF , of 0.9V, this current, the voltage at VN, and, VN and the current source to V P.
Build a charge pump

with ultralow quiescent current
Greg Sutterlin, Maxim Integrated Products, Sunnyvale, CA
ortable battery -powered de- VOUT
P vices often spend most of their life

in standby mode,in which the qui-
escent current of an internal boost con-
R1
301k R2
2.2M
verter continuously bleeds the battery.

C3
The quiescent current during standby 410 pF
can be larger than the actual load cur-
rent. Though several inductor-based VBATT
converters offer maximum quiescent
V+ VBATT
current of less than 10 A, designers R3 –
OUT
1M IN– NO1 NC1
usually prefer or require a regulated +
IN+
charge pump for cost-sensitive designs IC1
that must be intrinsically safe. Off-the- REFERENCE MAX981
GND COM1
shelf regulated charge pumps with out- C1
V– IN1
put-current capabilities of at least 10 +
10 F
R5 IN2
mA have typical minimum quiescent R4 1M
COM2
currents of 50 to 100 A. If that level 1M VBATT VOUT
of quiescent current is unacceptable,

you can reduce the overall average by NC2 N02
adding circuitry that remotely moni- + C
2
IC2
tors the regulated voltage and toggles 12 F
MAX4685
the charge pump into and out of
shutdown. That approach,how- F i g u r e 1
ever, may not achieve the desirable qui- This charge-pump circuit uses analog switches to achieve ultralow quiescent current.
escent-current level of less than 10 A.
The advent of low-on-resistance analog
switches and ultralow-current com- energy to a storage capacitor tied to age reference, and a comparator. The
parators and references makes possible VOUT. The transfer capacitor then comparator serves as a voltage monitor
a charge-pump circuit whose maximum charges again, and the cycle repeats. and an oscillator. When the circuit is in
quiescent current is approximately 7 A With ideal analog switches exhibiting regulation, the comparator output is
(Figure 1). zero loss, the VOUT level equals two times low, which closes the NC (normally
Charge pumps use an ac-coupling VBATT. As expected, however, the analog closed) switches and allows C1 to charge
technique to transfer energy from a switches’ finite on-resistance produces to VBATT. When the voltage at VOUT dips
transfer capacitor to a storage capacitor. an output level that drops in proportion below the output-regulation thresh-
The transfer capacitor first charges via to the load current. The basic regulated old—3.3V in this case—the comparator
analog switches to the level of VBATT,and charge pump in Figure 1 includes an os- output goes high. The NO (normally
then other analog switches transfer the cillator, several analog switches, a volt- open) switches close, transferring C1’s

design
ideas
charge to C2. This cycle repeats until VINVOUT[R 2/(R 1+ R 2)]. The resist- ple. For this application (ILOAD10 mA),
VOUT regains regulation. ance of R 1R 2 should be greater than 1 C110 F. To calculate the value of C2,
Resistors R 3 to R 5 provide the hys- M to minimize VBATT loading. If make an approximation based on the
teresis necessary for oscillation. Their VOUT3.3V and R 2 is 2.2 M, R 1 calcu- desired ripple voltage:C2(ILOADtLOW)/
value, 1 M, creates a notable level of lates to 301 k . Capacitor C3 connects VRIPPLE . With ILOAD10 mA and V RIP-
hysteresis and minimizes VBATT loading. to the comparator’s VIN input. Along PLE
150 mV, C212 F.
As the comparator output changes state, with R 1 and R 2, C3 sets the oscillation With these component values, the
feedback resistor R 5 creates hysteresis by frequency according to the following circuit draws a maximum quiescent
moving the threshold you apply to the simplified relationships: tDISCHARGE  current of 6.9 A and offers a consid-
comparator’s positive input. For the re- tLOW(R 2C3)ln[(V IN(LOW))/(VIN+ erable improvement over off-the-shelf
sistor values shown, reference value HIGH))]; tCHARGEtHIGH(R 2C3)ln charge pumps. You can further lower
nominal for IC1 (1.182V), and [1  ( V IN  (HIGH)  V IN +(LOW))/ the quiescent current by increasing the
VBATT3V, the VINthreshold swings (VBATTVIN(LOW)]; and f OSC1/tPERIOD, resistor values, but that effect is mini-
between approximate values of where tPERIOD  tLOWtHIGH. mal because IC2’s maximum quiescent
VIN(low)0.39V and V IN(high)  To maximize efficiency and reduce current of 3.8 A dominates the total.
1.39V. When the circuit is in regulation, the effects of comparator slew rate, you This circuit lets you implement an ul-
VIN slightly exceeds VIN, the com- should set a relatively low frequency. tralow-quiescent-current-regulated
parator output is low, the R 1-R 2 divider Choosing C3470 pF yields the follow- charge pump. Until off-the-shelf op-
senses the voltage at VOUT, and the ing: tLOW178 sec, and tHIGH68 sec; tions are available, it provides an alter-
threshold at VIN is low (0.39V). With thus, f OSC4 kHz. native for designers seeking to imple-
VIN at 0.39V, you can calculate the R 1 Select the values of C1 and C2 to ment a low-cost design without the use
and R 2 values from the equation achieve the desired load current and rip- of inductors.

design
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Dual-voltage regulator meets USB-power needs

his Design Idea stems from the
T limited availability of IC voltage reg-

ulators that can meet key USB-pow-
er specs, coupled with the need for turn-
200k
24 µA
MAXIMUM
100 nF
39 12 µA 27 12 µA
on sequencing and rise-time control at

100k 8
each output. As always, for PC-related 18 µA +
2N3904 100 nF 100 nF
designs, minimum cost is a primary mo- 1/2
100 nF LPV358
tivation. USB specs require
Figure 1
all loads to limit inrush cur-
100k 169k
rent to less than 100 mA plus 50 C of 3.3V
charge when powered on. If permission 1 µF

10 µF
CLOAD
is granted to increase the load to 500 mA,
inrush limiting may be required again to 10 nF
prevent excursions over the 500-mA lim- 2N3904 0520
+
it. The other troublesome USB-power re- 1/2
LPV358
quirement is the “suspend”-current LM385
10 nF
1.235V
maximum of 500 A, of which you may 4 100 pF
use only 250 A; a termination resistor 100k 45.3k V1.814
requires the rest. Suspend requires the 1 µF 33 µF

CLOAD
load to power down but keep alive just
enough to listen for permission to pow-
er up again.So,the sum of the regulators’ This circuit meets USB specs for controlled power-up sequence and slew rate.
operating currents plus load current
must be less than 250 A. The dual-reg- 4.5 TO 5.25V
ulator circuit meets the USB

Figure 2 100 nF
spec and powers an ASIC 3.9 12 µA
3.9
12 µA
200k
that requires a core voltage of 1.8V and 24 µA 2N3906 2N3906
MAXIMUM
I/O voltage of 3.3V to rise with a con-
100k
trolled sequence and slew rate (Figure 1). + 8 100 nF
18 µA
1/2
Specifically, the core and I/O voltages 100 nF LPV358 13.3
3.3V
track within 0.5V until the core voltage 2N4401 150 mA
reaches 1.8V. The controlled slew rate 100k 169k
1 µF
limits inrush current to less than 100 100 nF
2N4401 0520
+ 10 nF
Dual-voltage regulator meets 1/2
LM385 10 nF LPV358
USB-power needs ..........................................69 1.235V
4 100 pF 1.8V
Scalable latch requires 100k 45.3k 150 mA
no capacitors or clock ..................................70

1 µF
Phone-line-voltage monitor meets
FCC specs ........................................................72
This configuration boosts the output current of Figure 1’s circuit to more than 200 mA.
Instrumentation amp has
differential outputs ........................................78 mA. Two micropower linear regulators drive, and not reverse polarity as you ap-
use a very-low-power bandgap voltage ply power. Each op amp has an npn tran-
What’ s Up sect ion a t ww w.edn. com. reference and a dual op amp.The dual op sistor buffering its output to provide
amp must draw low power, have inputs greater than 100 mA.The regulator loops
active to ground, provide rail-to-rail are stable with these components and
www.edn.com A ug u s t 1 9, 2 0 04 | ed n 69

design
ideas
194 A available for the
USB
POWER 51.1 load during suspend
mode. Figure 1’s appli-
5V 0.1 µF 0.1 µF >100 µF 5V
INPUT 24 µA
cation requires regula-
200k 12 µA
MAXIMUM tor current of less than
Si2335 8
100k 150 mA from each out-
+
2N3906 18 µA 1/2 put.You can easily mod-
475k 100 nF LPV358
ify the circuit to provide
2N3904 more than 200 mA per
169k 3.3V
channel by substituting
0.01 µF
10 nF 1 µF a 2N4401 for the 2N-
475k 100k
0520 3904 and adding active
current limit with a
2N3904
2N3906 (Figure 2).
+
Many USB-powered
1/2
10 nF LPV358 supplies also require a
LM385
1.235V 2N3904
5V output.The circuit of
4 100 pF
Figure 3 provides precise
100k 45.3k
inrush limiting for 5V
1 µF 1.8V and a signal to enable
Figure 3 other supplies or loads.
The portion of the cir-
For USB applications requiring 5V, this circuit provides precise inrush limiting. cuit in broken lines lim-
its inrush current to less
values. Simple current limiting accrues ter.A small Schottky diode connected be- than 100 mA at power-on. The 51.1 re-
from a resistor in series with each tween 1.8V and 3.3V guarantees the 3.3V sistor charges the 5V load capacitance to
2N3904 collector lead. to be within 0.5V of the 1.8V during approximately 4.5V, and the 2N3906 then
A 200-k  resistor that connects to the start-up. Inrush current of approximate- releases the PFET’s gate, allowing it to
10-nF bypass capacitor at the voltage ref- ly 38 mA is IINRUSHCLOAD(dV/dt), where short-circuit the resistor. Finally, the
erence controls the 1.8V power-up rise CLOAD is the total load capacitance, 2N3904 turns off,enabling the linear reg-
time. The resulting rise time is approxi- dV1.8V, and dttRISE. The total oper- ulators to start. This inrush circuit pre-
mately tRISE20 A1.235V/10 nF 2.5 ating quiescent current of this dual reg- cisely limits peak inrush current inde-
msec. The 3.3V supply follows the 1.8V ulator measures just 56 A, and the pendently of capacitive load.Use of a large
supply, according to the 10-msec time worst-case maximum spec for the circuit load capacitance prevents load-current
constant of its 100-k , 100-nF input fil- in Figure 1 is 64 A. This figure leaves spikes from reaching the USB input line.
Scalable latch requires no capacitors or clock

Robert Most, Dow Corning S&T Electronics, Midland, MI
5V
ircuits that latch one-of-N
C switches usually use a digital ap-

proach. Such circuits are
often useful in human-inter-
Figure 1
SEL 1
TCR-22
SEL 2
TCR-22
SEL 3
TCR-22
TO NEXT
SECTION
R1
face situations, such as audio-mixing
470
consoles, video-feed selection, or cur-
rent-loop-control redundancy systems. 1.5k CHANNEL 1 1.5k CHANNEL 2 1.5k CHANNEL 3
RESET
In high-precision analog systems,such as ALL
high-fidelity audio or video,elimination TO NEXT
of clocking circuits, whenever possible, SECTION
reduces the chances of coupling noise

back into the signals of interest. The cir-
cuit in Figure 1 is a scalable one-of-N BF256C
latch that has the advantages of no clock
and no capacitors, and it has an intrin- This one-of-N latching circuit uses no clock or capacitors. The LEDs double as channel indicators.
70 e dn | A u gu s t 1 9, 2 0 04 www.edn.com

design
ideas
sic “active-channel” indication. 5V sections can be across control rooms.
The operating principle of this circuit Upon initial power-up,all channels are in
is based on current steering. A current the off-state. In addition, Figure 1 shows
sink comprising an n-channel JFET, the an optional reset-all pushbutton. De-
DUAL SINGLE
BF256C, provides approximately 5-mA TO CHANNEL
SECTIONS
pressing the reset-all switch steers the en-
current draw, which is approximately the tire current sink’s capacity through this
hold current of any one of the small-sig- 470 1k switch, thus delatching any SCR that was
nal SCRs (silicon-controlled rectifiers). active.
When you select a channel by momen- You can substitute other n-channel
tarily depressing the corresponding JFETs, but you must accordingly scale the
switch, the associated SCR turns on, drain current of the chosen JFET by vary-
2N3904 OR
lighting the LED connected to EQUIVALENT
ing the value of R 1. You can easily modi-
Figure 2
its cathode and providing a fy this circuit to allow more than one SCR
logic one on the CHANx line. The SCR to be active at a given time. For a multi-
automatically latches the selected line un- ple-active-channel system, you must set
til you depress another channel switch. A current mirror replaces the JFET in Figure 1 the current level to activate only the
When you actuate any other channel and allows the choice of single or dual channels. number of SCRs desired and no more.
switch, the corresponding SCR latches, For example, a system with two active
releasing the previous channel. This latch the use the CHANx line to select an ana- channels would require a current level of
behavior is the result of the inability of log switch, a mechanical relay, or anoth- 8 to 10 mA in the current sink. Figure 2
the current sink to draw enough current er device. Scalability is straightforward: shows a possible alternative current sink,
to sustain more than one SCR at a time. Additional channel sections require only replacing the JFET and R 1, for this
The circuit needs blocking diodes to the momentary switch, a 1.5-k  resistor, arrangement. If you use indicating LEDs
isolate the cathodes of the SCRs. If you an SCR, and a diode. Because this in a multiple-channel arrangement, you
use an LED, as in Figure 1, it also doubles method uses a current-based scheme, the should take proper precautions with
as an “active-channel” indicator. You can use of long lines is not an issue. Channel maximum LED current.
Phone-line-voltage monitor meets FCC specs

Brad Peeters, Theta Engineering, Costa Mesa, CA
hen you design equipment that
W
5V
interfaces to a phone line, it is of- R2
IC1 47k
ten desirable to be able to moni-
PS2701
tor the dc voltage on the line. This abil- 3 4
ity can be useful, for example, to LINEV
determine whether a line is in use before

R1 R4
attempting to go off-hook and possibly 10M
1 2 10
interrupting somebody’s phone call. TIP
FCC regulations place strict lim- D1 D2
its on the amount of leakage cur- Figure 1 IN4148 IN4148
rent an on-hook device can draw from R5

a phone line. The specifications work 3.3M Q2
2N3906
out to approximately the equivalent of C1
5 M  as the minimum leakage resist- 22 nF
Q1
FILM
ance. So, you have the challenge of mon- This circuit moni- 2N3906
C2
itoring the line voltage without exceed- tors dc voltage on 1 nF
ing the regulatory limits and also a phone line and
maintaining the galvanic isolation represents 10-M R6
Q3
quired between the phone line and your leakage resistance 10M
2N3904
equipment. The circuit in Figure 1 across the line. R7 R8
shows a method of meeting this chal- 10M 10M
lenge with 100% margin. In other
RING
(continued on pg 76)
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design
ideas
5V
words, it presents approximately 10- R2
IC1 47k
M leakage resistance across the line. PS2701
The basic relaxation oscillator has the 3 4
LINEVP
LED of an optoisolator in the discharge
path of the main capacitor. It delivers a R1
pulse train,the frequency of which varies 10M 5V
1 2
TIP R3
with the voltage on the phone line. By 47k
IC2
measuring the period between pulses, PS2701
the equipment’s microcontroller can 3 4
LINEVM
easily determine the approximate line
voltage. C1 is the timing capacitor. It R4
should be a film-type capacitor rather 1 2
10
than ceramic for good results. It slowly

D1 D2
charges through R 1, a 10-M re- IN4148 IN4148
sistor.When the voltage across C1 F i g u r e 2
C1 R5
reaches approximately 3V, the remainder 22 F Q2
3.3M
of the circuit turns on, causing C1 to rap- FILM 2N3906
idly discharge through R 4 and the op- Q4

NDS331N Q1
toisolator’s LED. This action causes the 2N3906
C2
optoisolator’s output transistor to briefly 1 nF
turn on, creating a low-going pulse ap-
proximately 200 sec wide (the signal la- R6
Q3
beled LINEV). This width is sufficient 10M
2N3904
for even a slow microcontroller to cap- R7 R8
ture an interrupt.When C1 discharges to 10M 10M
approximately 1.5V, the circuit turns off,
RING
and the cycle repeats.
Q5
Q2 and Q3 form an SCR (silicon-con-
NDS331N
trolled-rectifier)-like regenerative pair.
D2 and Q2 function basically as a current This circuit works with either the Tip or the Ring polarity and reports the polarity of the line
mirror. Normally, you construct a cur- to the host microcontroller.
rent mirror using two or more identical
transistors. By using a 1N4148 diode proves the operating characteristics of larity and reports the polarity of the line
rather than another 2N3906, you reduce the circuit. to the host microcontroller. This circuit
the gain of the current mirror to well be- This circuit assumes that Tip and Ring is suitable when you need to know not
low unity. The 1N4148 functions as have protection against polarity reversal only the magnitude, but also the polari-
though it has many times the base-emit- such that Tip is always more positive.The ty of the line voltage. As you can see, it has
ter diode area of the 2N3906. Reducing circuit of Figure 2 works with either po- two outputs, one for each polarity. Q4
the gain in this fashion and Q5 are low-threshold n-
helps the regenerative pair channel MOSFETs, con-
to turn off at the appropri- nected in such a way as to
ate point, keeping the oscil- always connect the bottom
lator from “sticking” on. Q1 rail of the relaxation circuit
and the diode-resistor net- to the most negative side
work driving its base func- FREQUENCY of the timing capacitor.
(Hz)
tion as the trigger circuit. The positive rail of the re-
When the voltage across C1 laxation circuit connects to
gets high enough, Q1 starts the most positive side of
to turn on and inject cur- the timing capacitor using
rent into Q3. Once Q3 starts diode isolation, taking ad-
to turn on, regeneration vantage of the fact that
kicks in, and Q3 and Q2 turn the optoisolator LEDs are
on hard and stay turned on diodes.
VOLTS
until the capacitor dis- Figure 3 shows a plot of
charges sufficiently. C2 Figure 3 the frequency-versus-volt-
provides additional positive The frequency-versus-voltage response for the circuit of Figure 2 shows the age response of the circuit
feedback through Q1; it im- spread across a sampling of five units for both polarities of line voltage. of Figure 2. It shows the
76 e dn | A u gu s t 1 9, 2 0 04 www.edn.com

design
ideas
spread across a sampling of five units for er and in production are mostly attrib- ditions. You can also use it to detect the
both polarities of line voltage. General- utable to variations in C1. Although not small voltage changes that might be of
ly, the responses for the positive and highly precise, the circuit is more than interest in detecting barging in—when
negative voltages in a given unit are so adequate for distinguishing between on- another device on the line goes off-hook
close that the plot lines overlay each oth- hook (typically, greater than 18V) and while this device is using the line.
er. The unit-to-unit variations are larg- off-hook (typically, less than 12V) con-
Instrumentation amp has differential outputs

Moshe Gerstenhaber and Stephen Lee, Analog Devices, Wilmington, MA
tate-of-the-art ADCs accept dif- 12V
S ferential inputs, allowing you to dif-

ferentially implement the entire sig-
nal path from sensor to converter. This 
+
1V
+

AD8221
V0UT
VREF 12V
3V
0V
structure provides significant perform- _
10k R1 R2
ance advantages, because differential sig- +
1k 1k OUTPUT
nals increase the dynamic range, reduce 12V OP27 VOLTAGE
_ 12V
hum, and eliminate ground noise. Fig-
_
ures 1a and 1b show two common dif- (a) 10k 12V
ferential-output instrumentation-ampli- OP27
+
2V
fier circuits.The first provides unity gain,
and the second implements a gain of two. 2.5V 12V
Both circuits, however, suffer from in-
creased noise, offset error, offset drift,
gain error, and gain drift as compared 12V
with an instrumentation amplifier with a
1V
single-ended output. Figure 2 shows a (b)
+
+ V0UT 3.5V
differential-output instrumentation am-  AD8221
VREF
plifier that has none of these deficiencies. 0V
_ R3 R4
The design exploits the fact that the out- 1k 1k OUTPUT
put of an instrumentation am- 12V 12V VOLTAGE
Figure 1
plifier is the difference between _
the output pin, VOUT, and the reference The differential-output cir-
OP27
pin, VREF. This application adds an in- cuits having unity gain (a) and 1.5V
+
verter with a gain of 1 between the two a gain of two (b) suffer from
pins. high noise level, excessive off- 2.5V 12V
With an input voltage, V, the output set error and drift, and signif-
voltage (VOUTVREF) must also be equal icant gain error and drift.
to V. The reference pin’s voltage is oppo-
site in polarity to the output pin’s volt-
age. Therefore, the output must produce 12V
VOUTVIN/2 and VREFVIN/2 to satis- 1V
fy (VOUTVREF)V. Applying a 2.5V sig- +
+ VOUT
nal to the noninverting terminal of the AD8221
A
3V
op amp sets the common-mode output  0V _ VREF
R5
level. The op amp establishes 2.5V at
10k
Node B. Accordingly, if you apply 1V to B
12V
the input, 3V appears at Node A, OUTPUT
Figure 2 _ 2.5V
and 2V appears at Node C. R6
+
VOLTAGE
Thus, the output is 0.5V higher than and This differential-output 10k OP27
0.5V lower than 2.5V. Errors from instrumentation amplifier
VOUTVREF are a function only of the in- preserves the gain and adds 12V 12V
C
strumentation amplifier. Errors such as no offset, drift, or noise to 2V
offset, noise, and gain error that stem the output signal.
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design
ideas
Figure 3 A 2V p-p, 1-kHz input signal (top), and 1V p-p Figure 4 The spectral analysis of the differential-out-
differential-output signals (bottom) have an output common- put signal shows that input to the instrumentation amplifier
mode voltage of 2.5V. is 2V p-p, 1 kHz.
from the inverter amplifier and resistors waveform in a performance photo shows Another performance photo shows the
equally affect both outputs. Thus, they the 2V p-p, 1-kHz input (Figure 3). The spectral density of the differential out-
contribute only to the common-mode two outputs appear at the bottom. The put (Figure 4).
output, which the ADC rejects. The top output common-mode voltage is 2.5V.
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Buffer adapts single-ended signals

for differential inputs
Randall Carver, Analog Devices Inc, Greensboro, NC
DC
C coupling of single-ended signals
D into differential-input, single-sup-

ply ADCs can be challenging. The
input signal requires level shifting from
220
240
DC
220
RF
240
ground to VS/2 as well as single-ended- VIN 3 + 25 11
5 VIN+
to-differential conversion. In addition, 64.9 IC1 8
IC3
you must balance the differential inputs R AD8351
G
25 AD6645
28 2 VOCM 7 12
of the ADC to cancel even-order har- 240 VIN CML
4 _
monics and common-mode noise. Sys- 10 3
10k 10k
tems often require this signal translation 240 0.01 F
220
to take place without injecting dc bias
currents back into the signal source. Pro- 220 10M
DC
cessing wideband signals with large dy-
namic range (12- to 14-bit ADCs) can 0.01 F
also add to the circuit complexity.Wide- _ 6
band amplifiers address nearly all these 10k 10k 7 IC2B
DC OP262
issues, but their standard implementa- 5k
5
tion requires the use of ac coupling. _ 2 +
This Design Idea describes a new cir- 1 IC2A
OP262
cuit that eliminates this requirement 5k
Figure 2 + 3
through the use of an external dc feed-
back loop. It also allows the lower end of
the passband to extend to dc. The basis This circuit is a wideband, dc-coupled, single-ended-to-differential buffer.
of the circuit is a simple level-shifting cir-
cuit (Figure 1). Tying two series resistors connected between the source and a neg- reference (CML) signal. The addition of
between VS and a signal source attenuates ative supply of equal value remove dc bias this external dc feedback path allows you
the signal by a factor of two and biases it currents from the source. to open the VOCM pin of IC1 and de-
to VS/2. The center tap is buffered; single- The circuit of Figure 2 expands upon
sided supply circuits can then process the this simple concept by replacing the sup-
Buffer adapts single-ended signals
signal. Two additional series resistors ply voltages VS with precise VDC lev-
for differential inputs ....................................85
els that track one another. In addition,
VS
this design implements differential sig- Triac lighting and heating controller
naling by doubling the number of level- uses few parts ................................................86
R Constant-current, constant-voltage
shifting resistors. You produce the VDC
levels by subtracting the 2.4V ADC ref- converter drives white LEDs ........................88
erence signal (CML pin) from the com- Sequential state machine aids
AC R
RS mon-mode level of the amplifier, which in automatic control......................................90
you form by summing the two amplifier Hysteretic regulators provide
R
outputs through equal-value resistors. high performance at low cost ....................92
The circuit amplifies, filters, and inverts Power-supply IC drives multiple LEDs ......94
R
the difference to create the VDC levels. Supercapacitor boosts current
The dc feedback-loop gain of approxi- from small battery ........................................99
Figure 1 VS mately 1040 allows the amplifier to track
This simple circuit level-shifts ac signals to the output common-mode level to with- What’ s Up sect ion a t ww w.edn. com.
accommodate the  V supplies. in (2.4V/1040) 2.3 mV of the ADC’s
S
www.edn.com S e p t em b e r 2 , 2 0 0 4 | ed n 85

design
ideas
FRONT-END HARMONIC
GAIN DISTORTION THIRD HARMONIC AT 6 dB
(dB) (dBFS) THIRD HARMONIC AT 12 dB
SECOND HARMONIC AT 6 dB
SECOND HARMONIC AT 12 dB
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 3 Figure 4
This graphic shows the frequency response of the circuit in Figure 2 for This plot shows harmonic distortion versus frequency for a 1-dB
various values of gain. (referred to full-scale) input to the ADC at 80 MHz.
couple it to ground, disabling the the bandwidth extends beyond 1 GHz pedance. The 28 resistor provides for a
AD8351’s internal dc feedback path. (Figure 3). After you determine the re- balanced input that the amplifier sees.
The level-shifting resistors have a ratio quired gain, you adjust resistor R F to bal- You can accommodate a differential-in-
of 1.09-to-1 to reduce the required swing ance the two differential signals into the put signal structure by replacing the 28
of the VDC levels to 2.4 [(1.09 ADC. Table 1 shows typical values of R G resistor with a 64.9 resistor and tying
1)/1.09]4.6V. The design uses accu- and R F for various gain levels. The 64.9 the additional negative input signal to the
rate networks with excellent tracking to resistor provides for a 50 source im- junction of the new 64.9 resistor and
ensure good CMRR (common-mode-re- the two 240 level-shifting resistors. This
jection ratio) and minimize the injection TABLE 1—RESISTOR VALUES differential-input structure allows you to
of dc bias currents into the source. IC2 FOR VARIOUS FRONT-END GAINS remove R F. The circuit maintains the ex-
uses a rail-to-rail feedback amplifier to al- RG RF Front-end gain cellent distortion performance of the
low the use of 5V supplies. The re- () () (dB) AD8351 amplifier,allowing the circuit to
maining circuits are powered from 5V. 56.2 1540 12 drive 12- and 14-bit ADCs with minimal
Resistor R G varies the overall gain of the 154 698 6 degradation of the ADC’s dynamic range
front end. For a front-end gain of 0 dB, 1000 316 0 (Figure 4).
Triac lighting and heating controller uses few parts

David Caldwell, Flextek Electronics, Carlsbad, CA
he triac lighting-control circuit in
T
C1 F S1 P1
LINE (120V/60 Hz) 1
Figure 1 is small and inexpensive be- PLUG
1
SPST
cause load and housekeeping power 0.47 F 2
10A
come directly from the line voltage, R1
120V AC R3 3
thereby eliminating bulky, expensive sup- 820 10M

120V INCANDESCENT
0.5W
plies. The CLZD010 closed-loop con- PHASE LP1
D1
troller maintains constant light intensity 5V DC 300W LAMP
by automatically adjusting the timing of
FEEDBACK
the triac’s firing until the feedback signal 1N4148
VSET IC1
and setpoint command are equal.The 5V 1 18
FBK HEN IR
supply is a charge pump that energizes C1 D 2 R2 2
REF LEN
17
SENSOR
Q2
3 16 QSE113
on the negative swing of the line voltage 4
SPT STA
15
1N5232B 10k BIP TIM
and then transfers charge to C2 on the 5.6V
5
GND VDD
14
6 13
positive swing. Zener diode D2, minus the C2 C3
7
PS0 CS3
12
220 F 0.1 F PS1 CS2
forward drop of rectifier D1, sets the 5V. 8
PS2 CS1
11
R5
9 10
Triac Q1 is a latching switch that PWM CS0
4.99k
conducts in either direction un- Figure 1 CLZD010 Q1
R4
C4
til you remove gate drive and load cur- 200
56 F
L4008L6
rent drops below its holding threshold,
CLOSED-LOOP LOGIC
which occurs at the zero-crossing point NEUTRAL CONTROLLER TRIAC
of the line voltage.
The circuit pulses the triac gate for 100 This closed-loop lighting-control system uses a few inexpensive parts.
86 ed n | S e p t em b e r 2 , 2 0 0 4 www.edn.com

design
ideas C1
LINE (120V/60 Hz) F1 S1 P1
PLUG
1
SPST
0.47 F 2
10A
sec to turn on the load for the remain- 120V AC R3 3
R1
der of each 60-Hz half-cycle, so higher 10M
820
0.5W
power accrues by turning on earlier in the PHASE
D1 IC2
half-cycle. R 3, at the timing pin of the con- 5V DC 1 2
troller chip, detects line phase. Controller VS OUT
FEEDBACK LM34
pins CS3 to CS0 set the closed-loop con- 1N4148
VSET IC1
figuration for an application. You can eas- 1
FBK HEN
18 GND
D2 2 17 3
ily modify the lighting-control circuit for R2
3
REF LEN
16
SPT STA TEMPERATURE
R5
thermal control (Figure 2). Closed-loop 1N5232B 10k
4
BIP TIM
15 SENSOR
5 14 50
timing is 134 sec for optimized tempera- 5.6V
6
GND VDD
13 300W
PS0 CS3
HEATER
ture response, using controller pins CS3 C2 C3 7
8
PS1 CS2
12
11
220 F 0.1 F PS2 CS1
to CS0. The circuit initially drives the 9
PWM CS0
10
heater at high power levels until CLZD010 Q1
Figure 2 R4
the temperature nears its final 200
value and then reduces the power to avoid L4008L6
overshoot. The CLZD010 controller is NEUTRAL

CLOSED-LOOP
CONTROLLER
LOGIC
TRIAC
available from Flextek Electronics (www.
flex-tek.com). A slight modification adapts Figure 1’s circuit to for heating control.
Constant-current, constant-voltage
converter drives white LEDs
Keith Szolusha, Linear Technology Corp, Milpitas, CA
VIN
EDs usually take their drive from a R3
L
3.3 TO 4.2V
0.1
constant dc-current source to main- D2 1%
tain constant luminescence. Most
dc/dc converters, however, deliver a con- LXHL-BW02
L1
stant voltage by comparing a feedback SD25-100 D1 PMEG2010EA
10 H
voltage to an internal reference via an in-
ternal error amplifier. The easiest way to
turn a simple dc/dc converter into a con- ON/OFF
8 7 6
stant-current source is to use a sense re- VIN SW SW
sistor to convert the output current to a C1 9
ISP
3
1  F SHDN
voltage and use that voltage as the feed- 6.3V IC1 2
ISN R2
back. The problem is that 500 mA of out- CERAMIC LT1618 866k
4
put current with a 1.2V drop—the typi- IADJ FB 1
R5 C2
cal reference voltage—in the sense 1M
250/
GND VC 4.7 F
500 mA*
resistor incurs relatively high power loss- 5 10 R1
10V
R4 CERAMIC
es and, thus, a drop in efficiency. C3 124k
Figure 1 2.2M 0.1  F
One approach is to use an ex-
ternal op amp to amplify the voltage drop
across a low-value resistor to the given * 500-mA FLASH ONLY.
reference voltage. This method saves con- The LT1618 white-LED driver supplies 250-mA constant current and 500-mA flash from a
verter efficiency but significantly in- lithium-ion battery.
creases the cost and complexity of a sim-
ple converter by using additional Figure 1 shows the LT1618 driving a 1W, can pulse it up to 500 mA for a camera
components and board space. A better white Lumileds (www.lumileds.com) flash.R 4 is set for a 250-mA torch or dim-
approach is to use the LT1618 constant- LXHL-BW02 Luxeon LED. ming operation. The IADJ (current-ad-
current, constant-voltage converter, You need no external op amps for this justment) pin provides the ability to dim
which combines a traditional voltage- compact approach. The LXHL-BW02 the LED during normal operation by
feedback loop and a unique current-feed- has a forward voltage of 3.1 to 3.5V for varying the resistor setting or injecting a
back loop to operate as a constant-volt- 250 mA of current. Although the maxi- PWM signal. Access to both the positive
age, constant-current dc/dc converter. mum dc rating of the LED is 350 mA,you and the negative inputs of the special in-

design
ideas
ternal constant-current amplifier allows the negative input pins of the LT1618. avoids the need for an additional induc-
you to place the sense resistor anywhere Although the LT1618 conventionally tor. This design uses one small, low-cost
in the converter’s output or input path serves as a high-frequency boost con- inductor, matching the all-ceramic ca-
and provide constant output or input verter with the load connected between pacitors and low-profile IC. Tying the
current. Without access to both inputs, VOUT and ground, this method of tying load back to VIN increases the inductor
you would need a ground-referenced the load from VOUT back to VIN allows the current by summing both the input and
sense resistor, some additional level-shift- IC to drive the LXHL-BW02 from a lithi- the output currents. The internal switch
ing transistors, or an op amp. In this case, um-ion battery input. Tying the load losses double, and the overall efficiency
the floating sense resistor’s value is only back to VIN allows the forward voltage of of the approach is approximately 70%
100 m; at 500 mA, it consumes an av- the LED (the load voltage) to be either over the input-voltage range.Even at this
erage of 50 mW of power. The sense re- above or below the input voltage as the efficiency, it is difficult to match the com-
sistor connects directly to the positive and battery voltage changes. This topology pactness and low cost of this approach.
Sequential state machine aids in automatic control

Abel Raynus, Armatron International, Malden, MA
reating a sequential state ma-
C
5V
chine is a common approach for au-
tomatic-control design. The meth- ACTIVE
1 120V AC
od finds wide use for controlling
sequential processes in industry, robot- MC68HC908QT2
ics, and measuring.The concept of a state 7
R2 PA0 LED0
machine is simple: A number of states de- 20k LAMP
scribe a process under control; each state
produces some output signals and ad- PA1 6 LED1
vances to the next state according to re- Q1
2 ADC
2 L2004F31
ceived input signal. PA5
R1
Two kinds of state machines exist. In a 430
3 3 1
Moore machine, only the current state PA4
determines an output. A Mealy machine’s NEUTRAL
VT80N1
output depends on both the current state 8
and the inputs. A state diagram unique-
ly and completely specifies a Moore
Figure 2 This simple circuit uses a Moore state machine to control a phototimer.
machine (Figure 1). Based on this di-
agram, you can create a microcontroller
program that assigns five assembler di- (delay value), the next state to go to for cor (www.teccor.com) activates the lamp.
rectives to each state: an address offset, an input of zero, and the next state to go The triac needs a gate current of 3 mA
the outputs, a time to remain in this state to for an input of one. from the microcontroller can drive load
As an example of a Moore machine, current as high as 4A rms at a maximum
STATE 1
consider a phototimer, which automati- voltage of 200V. The two LEDs with
PORT A=$01 DARK=0 cally lights a lamp for a given time when built-in resistor, LTL-4231T-R1s from
DELAY=2 SEC it becomes dark. After that time expires, LiteOn (www.liteon.com), indicate a cur-
it switches off the lamp and waits for the rent state in binary code. Thus,the Moore
DARK=1 next night to repeat the process (Figure machine has two outputs—the lamp and
DARK=1 DARK=0
2). The design uses an eight-pin Mo- the state indicator—both of which the
torola (www.motorola.com) MC68HC- Port A setting determines. The delays oc-
STATE 3 DARK=1 STATE 2 908QT2 microcontroller; Listing 1 at cur at 2 sec for states 1 and 3, and 4 min-
PORT A=$03 PORT A=$12 www.edn.com shows the program code. utes for state 2. In a real project, you can
DELAY=2 SEC DELAY=4
DARK=0 MINUTES The photocell determines the Moore ma- set any delay, even several hours or days.
chine’s input signal. The threshold of The delay affects only the complexity of
darkness is equal to 1.6V, which corre- the timer-interrupt routine. You can
Figure 1 This state diagram uniquely sponds to a value of 52H after built-in download the program code in Listing 1
and completely specifies the analog-to-digital conversion. The sensi- from the Web version of this Design Idea
workings of a Moore state machine. tive triac, Q1, model L2004F31 from Tec- at www.edn.com.

design
ideas
Hysteretic regulators provide
high performance at low cost
ysteretic voltage regulators offer itors (Figure 2). It is almost identical to
H
VIN
the potential advantages of sim- RBIAS CIN Figure 1’s circuit except for the added re-
plicity, fast response, 100%-duty- sistor, R SERIES, and the new connection
cycle operation, high efficiency at light point for CFF. The inductor’s ripple cur-
loading, and low cost. They need no VREF rent induces the ac voltage present across
+ Q1
loop-compensation components to add R SERIES and connects to comparator by
delays; thus, response time to a load CFF. This controlled ac voltage eliminates
change is less than one switching cycle. D1
the need for any COUT ESR. The feedback
What’s the catch? You must be able to ac- loop eliminates the dc voltage drop that
cept a switching frequency that is not R SERIES creates. This new configuration
Figure 2
precisely controlled and a sensitivity L produces predictable switching frequen-
to noise that requires layout skill. CFF cy with even zero-ESR capacitors and of-
Figure 1 shows a simple hysteretic fers the potential of nearly zero VOUT rip-
switching regulator made from a com- RFB2 RFB1
ple at the cost of a resistor and the small
parator with a fixed hysteresis and a RSERIES added dissipation of R SERIES carrying full
PFET. The comparator switches on the load current.
COUT
PFET whenever VOUT falls to its low ESR The following equation approximates
threshold and off again when VOUT rises VOUT the switching frequency for either circuit,
to its high threshold. The time VOUT provided that COUT’s reactance at the
lingers between the thresholds deter- switching frequency is lower than the
mines the on-time and, hence, the An added series resistor makes this circuit’s ESR and CFF’s reactance is much lower
switching frequency. The inductor’s rip- switching frequency more predictable. than R FB1: FS(VOUT/VIN)(V INVOUT)
ple current flowing through the ESR of ESR/(VHYSTL2ESR TPD(VINVOUT)),
COUT provides a triangular voltage-ripple Herein lies a potential problem with where ESR is the sum of COUT’s ESR and
waveform, which produces predictable simple circuits of this type. ESR is a ma- R SERIES, VHYST is the comparator’s hystere-
operation. jor factor in determining switching fre- sis voltage, and TPD is the average propa-
quency, and ESR can vary over a wide gation delay of the comparator plus the
VIN range for any given capacitor type. This PFET.
RBIAS CIN
variance is seldom a good thing and can You can build the circuits of figures 1
lead to inductor saturation if the fre- and 2 as drawn,using a comparator, such
quency falls too low or
VREF FET overheating aris- VIN
+ 5 TO 15V
Q1 ing from switching
losses if the frequency 30.1k
10 nF 8
rises too high. A simple 5 VIN SI3457
D1 ADJ 7
2.2 F P
solution to the ESR- GATE
Figure 1 variance problem is to 16V

LM3485
use a ceramic COUT ca- ISEN 1
CFF pacitor in series with a MBRS2040
resistor. Although this GND FB
L 2, 6 4
technique works nicely
RFB2 RFB1 MOS6020-472
in the lab, it often pos-
es problems in the real 330 pF 330 pF
ESR
COUT world, in which several
VOUT ceramic capacitors
Figure 3 0.1
bypass loads. 10k 4.42k
Another approach VOUT
1.8V, 1A
This hysteretic regulator suffers from unpre- to predictable frequen- 10 F
dictability of the switching frequency because cy control allows the 6V
of COUT ESR variance. use of low-ESR capac- This circuit occupies an area smaller than a postage stamp.

design
ideas
as the LMV7219, which claims 7.5-mV use, because any induced voltages from kHz over a VIN range of 5 to 15V for
built-in hysteresis, or by using a con- stray magnetic fields can produce unpre- VOUT1.8V and VOUT ripple less than 5
troller, such as the LM3485, which pro- dictable switching frequencies and ripple. mV p-p. The 30.1-k  resistor and the
vides a current-limiting feature, wider You can build the circuit in Figure 3 PFET’s on-resistance of 0.1 set the cur-
VIN range, and lower cost. You cannot in an area smaller than a postage stamp. rent limit to trigger at 1.5A. The no-load
overemphasize the layout sensitivity for This circuit produces output current of bias current is lower than 500 A. Most
hysteretic regulators. You cannot allow at least 1A, using small ceramic capaci- impressive is the dynamic VOUT change of
the feedback connection to pick up any tors, a SOT-6 PFET, a 67-mm inductor, only 10 mV for a load transient greater
stray signals. Open-core inductors are at- and an SMB-package, surface-mount than 0.5A.
tractive for cost reasons but difficult to Schottky diode.FS varies from 600 to 700
Power-supply IC drives multiple LEDs

John Lo Giudice and Vee Shing Wong, STMicroelectronics, Schaumburg, IL
right LEDs are becoming promi- The circuit in Figure 1 uses IC1, the in- drop across the sense resistor. The output
B nent sources of light. They often have

better efficiency and reliability than
do conventional light sources. Although
tegrated offline Viper22A switching reg-
ulator in a constant-current configuration
to drive two to eight 1W LEDs. The cir-
of the TSM103 drives the optocoupler,
IC3, which transfers the feedback to the
Viper22A on the primary side. Figures 2a,
LEDs can operate from an energy source cuit operates by monitoring the voltage 2b,and 2c show the completed board and
as simple as a battery and a resistor, driv- drop across the sense resistor,R 6, and uses the top and bottom layouts.
ing a string of LEDs in constant-current this voltage as feedback to regulate the The LED’s drive current is IOUTV5/R 6,
mode can better match the luminance be- current through R 6 and the LEDs. An op- where V5 is the voltage at Pin 5 of IC2.You
tween the devices without needing to erational amplifier in the TSM103, IC2, could easily modify the circuit to drive 3
match LEDs for their forward-voltage monitors the voltage drop across R SENSE or 5W LEDs, as long as you respect the
drop.A switching supply also gives better and compares it with the 0.175V refer- maximum power rating, by simply
efficiency than methods using a linear bal- ence, which resistor divider R 5-R 7 sets, changing the sense resistor to set a high-
last resistor to limit the current. and closes the loop to maintain a 0.175V er current value. When you design a con-
R1
68
5%
F1 1W D1
4 600V, 1A
FUSE D3
J1 400V CRAMER
STTH102 J2
2 1 1 CVP11-046 0.35A (7V-27.5V)
C11 2
DF06MGI
1 38T 1
1 0.047 F 10
D4 2
C1 C2 180T 2
+ 3 2 + PKC-136 + C7
3 10 F 10 F 220 F
2 8
400V 4 1 400V 50V R6
R2 5 0.5
C3 100 R8 1/2W
56T
L1 47 pF 5% 10
COMP0STAR 1 kV 5% 6 W1
1/2W 1 2
45 mH 1/4W
C5
1
D2 4.7 nF R4
2 STTH102 100
IC1
VIPER22A 5%
8 1/4W
DRAIN VDD 4
7 R3 4 1
DRAIN IC3
6 6.2k
DRAIN H11A817A
5 5% 2
DRAIN
1/4W 3
1 F 3 R9
SOURCE B 2.2k
2 C6
SOURCE 1/2W R10
0.33 F 1 2 2 1k
+
C4 50V IC2 R11
1/4W
22 F TSM103 1k
50V 1
1 VCC 8
OUT1
2 7 C8
VE1 OUT2 0.1 F
3 6
VREF VE2
4
GND VE2+
5
Figure 1
This constant-current LED driver can R7

10k R5
drive two to eight LEDs. 750

design
ideas
(a) (b) 93 mm (c)
46 mm
Figure 2 These photos show the completed board (a) and the top (b) and bottom (c) layouts.
stant-current power supply,the design of factors: the allowable VDD for the Viper22, uses a turns ratio of primary to second-
the transformer and the operating limi- which has a range of 9 to 38V for the un- ary output voltage for the maximum
tations of the circuit directly determine dervoltage and overvoltage thresholds, re- number of LEDs. Using these criteria, as
the output-voltage compliance of the spectively; the maximum wattage of 12W the number of LEDs decreases, so does
constant-current source. For a design for the Viper22A; and the fact that the re- the reflected voltage. If you base the
that can drive two to eight LEDs in series, flected voltage across the drain of the transformer on two LEDs, then the re-
the voltage drop across the LEDs can vary MOSFET, which takes account of the flected voltage quadruples with eight
from approximately 7V for two LEDs to turns ratio [(NP/NS)VOUT], added to the LEDs and may exceed the rating of the
28V for eight LEDs. This output voltage input voltage, must be less than 730V. Viper. The turns ratio between second-
reflects back across the transformer and For a design that can drive two to eight ary to the VDD winding is set for an out-
in turn changes the VDD voltage to the LEDs, you must design the system taking put voltage of two LEDs to the minimum
control circuit and the peak VDS across into account the fact that the reflected VDD voltage of 9V. As you add LEDs, VDD
the power MOSFET. voltage on VDD is proportional to the out- increases proportionally until it reaches
The designers of the transformer in put voltage. To keep the reflected voltage the overvoltage-shutdown point of 42V
this application considered three limiting manageable, the transformer’s design nominal.

design
ideas
Supercapacitor boosts current
from small battery
Yongping Xia, Navcom Technology, Torrance, CA
ome battery-powered devices re- ence, senses the voltage on the superca-
S quire large amounts of current in a

short period of time but spend most
of the time in sleep (power-down) mode.
pacitor. R 3 provides 0.5V hysteresis to the
comparator. When the voltage is lower
than 1.7V, the comparator’s output is low
The momentary large-load current de- and thus turns on the p-channel MOS-
mands large batteries to meet the time re- FET, Q1. The battery charges the super-
quirement, even though the average cur- capacitor. Once the voltage on the super-
rent consumption is low. For instance, a capacitor reaches 2.2V, the comparator
system operates for 1.5 sec every 10 hours switches high to shut off Q1. You could
and needs 500 mA at 3.3V during the op- use this low-to-high transition at Point A
eration. Although the average current is as a battery-charge-complete indicator or
only 21 A, small,“coin” batteries cannot to trigger another device, such as a mi-
drive such a heavy load. crocontroller’s interrupt line.
1/2 FDC6312P 1/2 FDC6312P
Q1 Q2
R1
R4
10M
10M
R3
60M
1 5 C2
+ OUTIC1 VCC 1.5F
BT1 LOAD
3V 2 MAX917 2.5V
C1 VEE
0.1 F 3 4
IN+ REF
R2
15M
A B
Figure 1 A supercapacitor helps a small battery to deliver large pulses of energy.
To eliminate the need for larger bat- Q2, another p-channel MOSFET, con-
teries, the circuit in Figure 1 solves the trols the discharge of the supercapacitor.
problem by gradually building up energy When Point B is floating, the switch is off.
in a supercapacitor. The device releases When an open-drain or open-collector de-
the energy when it is needed. Because the vice pulls down Point B, the switch is on.
supercapacitor has low internal imped- Because the voltage on the supercapacitor
ance, the momentary current can easily continuously drops when the switch is on,
exceed several amperes. you can use a boost dc/dc converter to gen-
Because a coin-type lithium battery erate a constant output voltage. Select a
delivers 3V and the supercapacitor’s rat- boost converter with the lowest possible
ed voltage is 2.5V, the circuit uses a volt- working input voltage to obtain the max-
age-controlled switch to cut off the bat- imum energy from the supercapacitor. For
tery once the voltage on the super- example, you can use an LTC3402 to gen-
capacitor reaches 2.2V. This design uses erate a stable 3.3V output. Once it starts,
a 1.5F, 2.5V supercapacitor from Power- the LTC3402 can work with input voltages
Stor (www.powerstor.com), model A10- as low as 0.5V. The energy from the super-
30-2R5155. IC1, a micropower voltage capacitor is 1/2V2C, or 1/2[(2.2V)2
comparator with built-in 1.245V refer- 1.5F(0.5V)21.5F]3.4J.
www.edn.com S e p t em b e r 2 , 2 0 0 4 | ed n 99

design
ideas The best of
design ideas
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Slow diodes or handy timing devices?

Louis Vlemincq, Belgacom, Evere, Belgium
ost designers consider slowness ased. When the control signal reverses its
M in diodes to be an imperfection or
a limitation. Why not take a more
positive view of the situation? After all, a
polarity,a negative bias appears immedi-
ately on Q1, but D2 cannot instantly cease
conducting and short-circuits the base
R1 C1
zener or an avalanche diode is no more drive to Q2 during all of its reverse recov-
than a diode with a limited breakdown ery time. The advantage of generating a D1 LF
voltage, and you can view a varactor as a dead time in this way lies in the fact that
diode with a large and nonlinear parasitic you need include only a small safety mar-
capacitance. Similarly,could you view the gin: The phenomena governing the re-
slowness of a diode as a property or even covery time of a diode are similar to those
a feature? For example, consider a PIN resulting in storage times in power de-
diode. Few people are aware that the key vices. In particular, they both display
a strong positive-temperature co-
efficient, for which this In this circuit, a slow diode pro-
Figure 2
Q 1 scheme compensates. The tects the switching transistor from
D 1 ability to operate at duty cycles destructive voltage transients.
close to 100% allows a better us-
age of the power components, gy from C1 to the transformer and ulti-
PWM DRIVE translating into savings and high- mately to the load. The overall efficiency
er performance:A universal-input is therefore better, and R 1 can have high-
supply,for instance, can operate at er resistance and can be smaller. Added to
Q 2
lower supply voltages. the lower cost of a standard diode versus
D 2 Figure 2 shows another exam- a fast one, the method provides non-neg-
Figure 1
ple. This standard clamping cir- ligible benefits.
You can use slow diodes to generate dead time in a cuit protects the switching tran- It is preferable to select a diode with a
half-bridge configuration. sistor of a flyback converter recovery time as long as possible. Popu-
against the voltage spike generat- lar types, such as the 1N400X series, have
property of a PIN diode is indeed its ed by the imperfect coupling between the recovery times of approximately 2.5 sec,
slowness; without it, it would generate primary and the secondary windings but some models reach more than 5 sec.
large amounts of distortion and require of the transformer. In an equivalent Ideally, C1 and LF should resonate at a pe-
a larger control current to function prop- schematic, this scenario translates into a riod equal to twice the diode’s recovery
erly. You can put this ability of slow leakage inductance, LF, in series with the
diodes to store large amounts of electri- primary winding. The circuit works in
Slow diodes or handy
cal charge to good use in a variety of oth- the following way: Each time the transis-
timing devices? ..............................................83
er circuits. Figure 1 shows how to gener- tor turns off, the current in the leakage
ate dead time using such diodes. A PWM inductance continues to flow, but D1 in- Diode compensates distortion
sandcastle (stepped) waveform feeds a tercepts it and “redirects” it to C1. C1 has in amplifier stage ..........................................84
half-bridge. a large enough capacitance that cycle-to- Transistors offer overload delay ................86
In a classical implementation, you must cycle variations do not influence it. The
Inertial-navigation system
insert dead time in the control circuitry to average voltage on C1 results from a bal-
uses silicon sensors........................................88
avoid the simultaneous conduction of the ance between the charging input from the
two transistors when the duty cycle ap- leakage inductance and the current that LED driver provides oscillator
proaches 100%. This dead time is a stan- bleeds from R 1. Usually, D1 is a fast diode, for microcontroller ........................................90
dard feature of PWM-control ICs. If you but, if you substitute it with a slow one, Use op-amp injection
use slow diodes for D1 and D2, you need interesting things happen: Instead of for Bode analysis............................................90
no dead time. If, for example, Q1 receives switching off when the voltage on C1 Publish your Design Idea in EDN . See the
a positive base, or gate, drive and is there- reaches its peak,D1 continues to conduct, What’ s Up sect ion a t w ww.edn .com.
fore conducting,D2 becomes forward-bi- thus transferring back charge and ener-
www.edn.com S e p t em b e r 1 6 , 2 0 0 4 | ed n 83

design
ideas
time. When the component values are itive cycle of the resonance to the aver- Normally, these small snags should
nearly optimum, R 1 can have a large val- age clamping voltage and because slow pose no problem; you can substitute the
ue, its only role being to provide a “seed” diodes often exhibit a slightly poorer for- new components in a design without any
current to prime the circuit. You pay a ward-recovery characteristic than do other change. The circuits in figures 1
small penalty for these advantages: The their fast counterparts. This characteris- and 2 are only two examples, but you can
peak clamping voltage increases by sev- tic results in a step of several volts at the apply the same useful principles to a va-
eral volts, because you must add the pos- beginning of the conduction. riety of other circuits.
Diode compensates distortion in amplifier stage

S Chekcheyev, Pridnestrovye State University, Moldova
he voltage amplifier in Figure 1
T exhibits smaller nonlinear distortion

than does the conventional amplifier
in Figure 2. Diode D1 compensates for
the distortion inherent in the npn tran-
sistor. The voltage gain of a common-
emitter amplifier depends on the
transconductance of the transistor. The
transconductance of the bipolar transis-
tor is as follows:
Nonlinearity of the The diode in the circuit of
Figure 3 Figure 4
transconductance of Q1 Figure 1 produces varying,
results in this distorted waveform. beneficial, negative feedback.
where e is the charge of an electron, k is
Boltzmann’s constant (approximately tive half-cycle (Figure 3). 20
1.381023J/K), TC is temperature in The dynamic resistance of diode D1 in CONVENTIONAL

AMPLIFIER
degrees Celsius, I is the emitter current, Figure 1 is inversely proportional to the 15 LINEARIZED
AMPLIFIER
and ne/[k(273 TC)]. So, the trans- instantaneous current. That dynamic re-
THD
conductance is proportional to the emit- sistance forms part of the negative-feed- (%) 10
back circuit of the amplifier. The average
current of diode D1 is equal to the aver- 5
12V
R3
age emitter current of transistor Q1.
R1 2k OUTPUT However, the instantaneous current of D1 0
C1 100k
10 F becomes smaller, and the instantaneous 0 1 2 3 4 5
INPUT VOUT P-P
Q1
dynamic resistance of D1 becomes
BC847C Figure 5
larger when the instantaneous emit- The linearized amplifier pro-
R2 R4 C2 ter current of Q1 becomes larger, and vice duces less than one-third the harmonic distor-
36k 510 1000 F
versa. Therefore, the negative feedback tion of the conventional amplifier.
D1 becomes stronger during the negative
D1N4148
half-cycle of the output signal. As a result, comes more symmetric (Figure 4). The
R5 C3 the output signal of the amplifier be- circuits in figures 1 and 2 have the same
510 1000 F
average collector current and the same
Figure 1 12V
load resistance. Figures 3 and 4 show the
R1 R3 results of their PSpice simulation. The
The addition of a simple diode in the emitter cir- 100k 2k OUTPUT amplitude of the output signal is 5V p-p
C1
cuit yields the symmetric waveform of Figure 4. 10 F in both cases with a 1-kHz sinusoidal sig-
INPUT
Q1
BC847C nal applied to the input. You can see that
ter current. Consequently, the instanta- R2
the linearized amplifier yields a more
neous voltage-gain coefficient of the con- 36k R4 C2 symmetrical output signal. Figure 5 gives
1.5k 1000 F
ventional common-emitter amplifier is the quantitative results of the simula-
proportional to the instantaneous tions. The improvement in harmonic dis-
emitter current. As a result, the neg- Figure 2 tortion accrues because of the suppres-
ative half-cycle of the output signal gets This amplifier circuit produces the distorted sion of the even harmonics in the output
more amplification than does the posi- waveform of Figure 3. of the linearized amplifier.
84 ed n | S e p t em b e r 1 6 , 2 0 0 4 www.edn.com

design
ideas
Transistors offer overload delay
Christophe Basso, On Semiconductor, Toulouse, France
lthough an SMPS VOUT trigger the protection. This
A (switch-mode power
supply) can protect itself
against permanent short cir-
circuit does not delay the
rise of the feedback voltage
but momentarily increases
cuits, it sometimes has prob- IOUT the output-power level by a
lems when dealing with tran- given percentage. When
sient overloads. Transient I
I
3
2
IOUT is within regulation,
overloads are not short cir- I 1
Pin 2 is below 3V and D1 is
cuits but can push the power MAXIMUM not biased. As a result,Q2 is
FEEDBACK
supply above its nominal FB EXCURSION blocked and Q1 pulls R 3’s
load value. This scenario oc- lower terminal to ground.
REGULATION
curs with typical loads such IS LOST The current-sense pin
as printer heads and small REGULATION OVERLOAD 1 OVERLOAD 2 SHORT CIRCUIT therefore sees a current im-
motors. When facing such a START-UP
age, which the voltage-di-
load profile, the power vider ratio of R 2 and R 3 af-
Figure 1
supply can easily trigger Overloads and short circuits can be similar in this typical fects.
its protection circuit, espe- power profile for a printer. In this example, VPIN4
cially if the open-loop gain is VSENSER 3/(R 3R 2)0.82
high.You will see any decrease in the out- its internal pullup voltage and triggers a VSENSE, where VSENSE is the voltage across
put voltage on the primary side as a loss protective burst mode. Note that this R SENSE. If the NCP1200 imposes a maxi-
of feedback current, because the con- protection acts independently of any mum-current setpoint of 1V, the IC au-
troller cannot keep the voltage constant. badly coupled auxiliary level, because the thorizes 1.2V over R SENSE as long as Q1 is
Figure 1 shows a typical power profile high-voltage source (Pin 8) directly pow- biased (instead of 1V in a regular config-
for a printer. You can clearly see the powers the controller. In the presence of uration). As soon as Pin 2 jumps to a
er variations and the corresponding overloads 1 and 2, Pin 2 would jump to higher value, such as 4V, indicating a loss
feedback-voltage swings that occur. The the maximum of its capability and would of regulation or a severe overload, D1
start-up sequence is a short circuit be-
cause, with VOUT far from its target, the HIGH VOLTAGE
feedback current is not yet established.

The nominal output current, I1, corre-
sponds to the regulation zone, in which
the load is constant.When a first overload 1 8
occurs (I2 in Figure 1), the feedback pin

pushes the primary-current setpoint (in 2 7
a current-mode controller), but the NCP1200
waveform’s excursion starts to diminish, 3 6
because it is approaching its maximum Q3
Q4
level. In I3, the power supply has difficul- 4 5
ty remaining in regulation and, in short-
circuit condition, VOUT collapses to
ground. If the primary PWM controller R4
R2
R3 1k
has a simple short-circuit-protection Q5 D1
10k
4.7k +
scheme, the protection mechanism can CVCC

3.3V
RSENSE
trigger in the overload zones 1 and 2, R5 Q1
whereas it should trigger only in the fi- 22k
Q2
nal one. Figure 2 portrays an approach +
R6 C3
based on the NCP1200 from On Semi- 10 F
1k
conductor (www.onsemi.com).
This circuit permanently monitors the
feedback line (Pin 2) to detect
Figure 2
whether a short circuit is present on A transistor network increases the peak current for a moment until the power sup-
the secondary side. If so, Pin 2 jumps to ply gives up by reducing the peak setpoint.

design
ideas
starts to conduct via Q4.This transistor opens. The divider goes away, the power sult, by dimensioning the R 5 and C3 ele-
buffers the feedback-pin impedance: C3 supply no longer ensures a large peak ments, you can insert a delay to enable
starts to charge up via R 5, and, when it current, and VOUT goes down, thereby the supply to cope with transient loads.
reaches approximately 0.7V at 25C, Q1 properly triggering the protection. As re-
Inertial-navigation system uses silicon sensors

Tom Niemi, Rockwell Collins, Cedar Rapids, IA
strap-down inertial-navigation 1 2 T 6 7 0 1 2
2 3 4 5 P 1 2 2 0
0 1 3
A
D S X X E
4 4 4 4 4 4 P T T D S 4 4 0 0 0
0
P P P P P P V X X V V S P P P P P P
E
1 VDD1 P50
system uses silicon sensors to meas- 1 5V 2 BIAS
R
P51
3 VLCD0 P52
ure displacement without entailing 4 VLCD1 P53
2 GROUND 5 VLCD2 P20

the bulk and expense of moving parts or 6
7
VSS1
COM0
P21
P22
GPS receivers. For example, a three-axis CXL04M3 X AXIS 8 COM1 P23

AN10 9 COM2 P24
THREE-AXIS 3
accelerometer and three angular-rate ACCELEROMETER 11
COM3
S0
PD78F9418A P25
P26
sensors can determine the position and Y AXIS 12 S1 P27

48
4 AN11 13 S2 AVSS
47
14 S3 AN10
velocity of a vehicle such as a robot or ra- 15
16
S4
S5
AN11
AN12
46
45
Z AXIS
dio-controlled aircraft. This hardware 5 AN12 17
18
S6
S7
AN13
AN14
44
43
configuration requires that you read and 19

20
S8
S9
AN15
FAN16
E
42
0 1 2
3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 D R
integrate the sensor outputs and then 1 1 1

1 1 1 1
S S S
1 1 1 2 2
S S S S
2 2 2 2
S S S S S
2 2 D V
S S S S
S S V A
V
combine and process them to obtain sta- (a) 1 2 3 4 5 6 7 8

2 2 2 2
9 0 1 2 3 4 5 6 7
2 2 2 2
2 3 3 3 3
8
3 3 3 3
3
5
0
4
R5
bilized location values. Figure 1 shows 2.7k (c)
one such complete system. An inexpen-
sive 8-bit microcontroller can handle the
R6
sensor reading and integration tasks, and 1 8 2.7k
perform simple lowpass filtering of the VIN V+
2 7
accelerometer’s output to remove con- VIN+ INA118 VOUT
R7
version noise. The microcontroller can 3 6 AN13 1 8 2.7k
V V
even run a basic position and velocity al- 4 5
REF VIN
2 7
V+
gorithm; alternatively, you can pass the VIN+ INA118 VOUT

3 6 AN14
preprocessed data to a DSP system. The VREF
1 8
V
NEC (www.necelam.com) PD78- 4 5 VIN V+
2 7
F9418A microcontroller has seven ADC VIN+ INA118 VOUT
X AXIS VOUT 3 6 AN15
inputs, so it can handle the six inputs 5V
1 2 VREF
V
from the sensors. VREF VGND
4 5
CG-16D
Because a Crossbow (www.cross 3 4
Y AXIS
5V VOUT
bow.com) CXL04M3 accelerometer de- ANGULAR RATE 1 2
livers 0.5V/g (9.8m/sec2), it can directly SENSOR
VREF CG-16D VGND
3 4
feed three of the microcontroller’s ADC Z AXIS
5V VOUT
inputs. Each NEC/Tokin CG-16D angu- ANGULAR RATE 1 2
(b) SENSOR
lar-rate sensor generates only 1.1 VREF CG-16D VGND
3 4
mV//sec, so it requires the aid of an in-
strumentation amplifier. The Burr- An accelerometer (a), three silicon sensors (b), and ANGULAR RATE
Figure 1 SENSOR
Brown (www.ti.com) INA118 fills a microcontroller (c) fit together to form a complete
the bill. The microcontroller has enough inertial-navigation system.
I/O lines to drive three Varitronix
(www.varitronix.com) VIM-503 41/2- culates the average value of the ac- the time squared, halve that quantity,and
digit LCDs that display the x, y, and z lo- celerometer’s outputs over 1000 samples then add the result and the bias value to
cation relative to the starting point. One and uses this information to calculate the previous x position. You find veloci-
of the fundamental tasks in this applica- bias-error adjustments for each axis. You ty by multiplying the bias-corrected x-
tion is to initialize the sensors and A/D apply each bias value by adding it to the axis reading by the time and then adding
converters to minimize bias error. Listing readings for that axis. Using the x axis as it to the previous x velocity. You can
1 at the Web version of this Design Idea an example, you determine the vehicle’s download the microcontroller code from
at www.edn.com shows the code to cali- movement from its starting point by in- the Web version of this Design Idea at
brate the accelerometer. The routine cal- tegrating: Multiply the x-axis reading by www.edn.com. 

design
ideas
LED driver provides oscillator for microcontroller
Wallace Ly, National Semiconductor, Santa Clara, CA
he major building blocks for a LM2791/2 to provide a clock source. You inverter (Figure 1). The net signal is a
T white-LED driver are an oscillator, a

charge pump, and a regulated cur-
rent source. National Semiconductor
can realize a simple yet useful circuit by
accounting for the fact that a pseudo
square wave is present across the flying
clean, 2-MHz clock source. The oscillo-
scope graph depicts the pseudo square
wave and the resultant square wave at the
(www.national.com) produces a device capacitor’s (C1) pins. You can take this output of the inverters (Figure 2). You
that contains all these building blocks in pseudo square wave from these pins and can use this signal as a simple clock
the highly integrated LM2791/2 IC. You clean it up. source for a baseband controller or mi-
usually use white-LED drivers in tandem To accomplish this task, you inject the crocontroller to perform simple tasks
with cellular baseband controllers or mi- signal, via a 330 resistor, R 1, into a sim- such as keypad decoding or battery-iden-
crocontrollers. You can easily adapt the ple inverter gate, such as a DM7404 hex tification detection.
1G SAMPLE/SEC
VIN
POUT
CIN 1 F FLYING
CHOLD
CAPACITOR
2V P–P
X(2)
C1 CURRENT
R1 CHARGE
SOURCES
LED1
330 PUMP
IS LED2
SD
R3 MICRO-
BRIGHT CONTROLLER
INPUT
5.36V P–P
Figure 1
PB1
CK0 PORT11
1V BW M 500 nSEC 2.12 V
COP8SBR PB2
CK1 PORT12
Figure 2
DM7404 INVERTERS A logic inverter cleans up the pseudo square wave
(top) from the flying capacitor; the result (bottom) is a stable clock
A white-LED driver doubles as a clocking source for a microcontroller. source for the microcontroller.
Use op-amp injection for Bode analysis

Martin Galinski, Micrel Semiconductor, San Jose, CA
ode analysis is an excellent way to mon method of injection is the use of
B
POWER-SUPPLY
measure small-signal stability and OUTPUT NETWORK- transformer. Figure 1 demonstrates how
ANALYZER
loop response in power-supply de- "A" INPUT a transformer injects a signal into the
signs. Bode analysis monitors gain and feedback network. A 50 resistor affords
NETWORK-
phase of a control loop. It performs this 50
impedance matching to the network-an-
ANALYZER
monitoring by breaking the feedback SOURCE alyzer source. This method allows the dc
loop and injecting a signal into the feed- loop to maintain regulation and allows
back node and then comparing the in- FEEDBACK NETWORK- the network analyzer to insert an ac sig-
jected signal with the output signal of the ANALYZER nal on the dc voltage. The network ana-
"R" INPUT
control loop.The method requires a lyzer then sweeps the source while mon-
Figure 1
network analyzer to sweep the fre- itoring A (voltage channel) and R
quency and compare the injected signal Bode analysis using transformer injection yields (reference channel) for an A/R-ratio
with the output signal. The most com- gain and phase information in a control loop. measurement. Although this method is

design
ideas
NETWORK-ANALYZER
the most common for meas- NETWORK-ANALYZER "A" INPUT by a factor of two by R 3
"R" INPUT
uring the gain and phase of a and R 4 and goes to the
power supply, it has signifi- 8V feedback output. (The
R1
cant limitations. First, to 1k POWER- 50 resistor balances the
measure low-frequency gain MIC922BC5 + SUPPLY network analyzer’s source
OUTPUT
and phase, the transformer FEEDBACK impedance.) This action
needs high inductance. Fre- _
R2 essentially breaks the loop
quencies lower than 100 Hz, 1k and injects the ac signal
R3
therefore, require a large and 1k 8V on top of the dc output
expensive transformer. R4 voltage and sends it to the
Figure 2
Also, the transformer 1k feedback terminal. By
must be able to inject high Op-amp injection is a NETWORK-ANALYZER monitoring the feedback
50 SOURCE
frequencies. Transformers good alternative to trans- terminal (R) and output
with these wide frequency former-based injection terminal (A),the analyzer
ranges generally are custom- and has no minimum-fre- measures gain and phase.
made and usually cost sever- quency limitation. This method has no min-
al hundred dollars. By using imum frequency. Make
an op amp, you can avoid the cost and output to the noninverting input by half. sure that the bandwidth of the op amp
frequency limitations of an injection The network analyzer is generally a 50 is much greater than the expected band-
transformer. Figure 2 demonstrates the source.R 1 and R 2 also divide the ac signal width of the power supply’s control loop.
use of an op amp in a summing- ampli- from the network analyzer by half. These An op amp with at least 100-MHz band-
fier configuration for signal injection.R 1 two signals “sum” together at half their width is more than adequate for most
and R 2 reduce the dc voltage from the original input. The output then gains up linear and switching power supplies.

design
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Combine two 8-bit outputs to make one 16-bit DAC

Steve Woodward, Chapel Hill, NC
nexpensive, 16-bit, monolithic DACs tion posed a challenge, because, at design
I can serve almost all applications.

However, some applications require
unconventional approaches. This Design
finalization, the NPSL included no ap-
propriate, flight-qualified, 16-bit DACs,
and the budget included no funds for cer-
Combine two 8-bit outputs
to make one 16-bit DAC ..................................85
LED driver provides
Idea design concerns circuitry I recently tification of new devices. I escaped from software-controlled intensity ..........................86
designed for a tunable-diode laser spec- this impasse by exploiting two fortuitous
trometer for a Mars-exploration applica- facts: The update rate of the two DACs Improve roll-off of Sallen-Key filter ................88
tion. The control circuitry included two was only tens of hertz, and the 69RH- AC-coupling instrumentation amplifier
16-bit DACs that interface to the radia- 051A had a number of uncommitted, 8- improves rejection range of differential
tion-hardened, 8051-variant 69RH051A bit, 14.5-kHz PWM outputs. These out- dc input voltage..................................................88
microcontroller. Because of the intend- puts made one 16-bit DAC; a second pair
Simplify computer-aided engineering
ed space-flight-qualified specification, of PWM bits and an identical circuit
with scientific-to-engineering conversion ....94
everything in the design had to consist made the other (Figure 1).
solely of components from the NPSL Hex inverter IC1’s VCC rail connects to 1.5V battery powers white-LED driver ..........96
(NASA parts-selection list). This restric- a precision 5V reference. The inverter’s Simple V COM adjustment uses
any logic-supply voltage ..................................96
IC2 5V
C4 69RH051 A Publish your Design Idea in EDN . See the
27 pF 40 What’ s Up sect ion at w ww.edn .com.
18 VDD2
XTAL1
0.1 F
14.756 MHz Y1 20
VSS
19
XTAL2 EA
31 outputs are accurate analog square waves.
C5 9
RST The low-order PWM-signal output,
27 pF 28
VDAC
A15
27
PWM0, of the 8051 controls the V3
A14
0 TO 5V R3 R2 R1
A13
26 square wave, and the high-order PWM
(REFERENCE) 200k V4 3.92k V1 1M 25
11
TX0
A12
A11 24 output, PWM1, controls the V1 square
10 23
RX0 A10
22
wave. R 2 and R 6 passively sum the two
4 3 A9
IC1
A8 21 square waves in the ratio R 2/R 63290/1
HC04
16
million1/255 to produce V4, duplicat-
WR
10
IC1
11 17 ing the 28 ratio of the 16-bit sum.This ac-
R0
HC04
ALE 30
tion makes the dc component of V4 equal
12 13 32
to 5V(REF)(PWM0255PWM1)/256.
IC1 AD7
8
CEX4 AD6 33 Thus, if you write the 0 to 255, high-or-
C8 HC04 34
7 AD5 der byte of a 0 to 65,535, 16-bit DAC set-
R5 0.0056 R4 CEX3 35
F V 6 AD4
CEX2
200k 2 3.92k 2
IC1 1 PWM1 5 AD3 36
37
ting to the CEX1 register of the 8051 and
CEX1 AD2
HC04
PWM0 4
CEX0 AD1 38 write the 0 to 255, low-order byte to
C9 39
0.01 F
8 IC1
9 AD0 CEX0, a corresponding 16-bit analog
R6 V3 HC04 12 29 representation appears in the dc compo-
INTO PSEN
1M
R7
nent of V4. The accuracy of the R 2-to-R 6
1M 6
IC1 5 ratio is the only limit on the monotonic-
HC04
ity and accuracy of this circuit. For ex-
5V (REFERENCE) ample, one part in 25,50014.5 bits for
14
1%-tolerance R 2 and R 6 and a full 16 bits
Figure 1 VCC for 0.3% tolerance or better. But the sto-
IC1
C1B HCO4 ry doesn’t end there. Two problems re-
0.1 F GND
Two PWM outputs from a 7 main.
microcontroller combine to The first problem is the extraction of
form a monotonic 16-bit DAC. V4’s desired dc component from all—or
www.edn.com S e p t em b e r 3 0 , 2 0 0 4 | ed n 85

design
ideas
at least 15 or 16 bits99.995%—of the tively nulls out approximately 99% of the ance ratio is approximately 300-to-1,
undesired square-wave ac ripple. The R 3- ripple. This nullifying action leaves such which is small enough to merit attention.
C9 lowpass filter does some of this work. a small residue that an approximately 2- Load-cancellation resistor R 1 provides
If you make C9 large enough, in princi- msec and, therefore, approximately 25- such attention.R 1 sums a current into the
ple, the filter could do the whole job. The msec-settling-time R 3C9 product easily R 2 driving node that, because it is equal in
reason this simple approach wouldn’t erases it. magnitude but opposite in phase to the
work is that, to get such a large ripple at- The other problem is compensation for current through R 6, effectively cancels the
tenuation of approximately 90 dB with a the low,but still nonzero, on-resistance of load on the R 2 drivers. This process makes
single-stage RC filter would require an the HC14 internal CMOS switches, so the combined on-resistance approxi-
approximately 300-msec time constant that the resistance doesn’t perturb the mately 100 times less important than it
and a resultant 3-sec,16-bit settling time. critical R 2-to-R 6 ratio. This issue is of no otherwise would be. The result is a sim-
This glacial response time would be too particular concern for R 6, because the R 6- ple, highly linear and accurate voltage-
slow even for this undemanding applica- to-on-resistance ratio is greater than output DAC with a respectable, if not
tion. To speed things, the R 4, R 5, R 7, C8 10,000-to-1, making any associated error blazingly fast, settling time of approxi-
network synthesizes and then sums V2: an negligible. This situation is not the case mately 25 msec.And the most important
inverse-polarity duplicate of V4’s 14.5- for R 2, however, in which, despite the result, in this case, was a parts list with an
kHz ac component. This summation ac- triple-parallel gates, the R 2-to-on-resist- impeccable NPSL-compliant pedigree.
LED driver provides software-controlled intensity

Neda Shahi and Bjorn Starmark, Maxim Integrated Products, Sunnyvale, CA
ecent advances in VIN
R
D1 SMB R1
operating efficiency 1
L1
2
CMSH1-100 51
VCC
have expanded the use C1 22 H C2 C3
of LEDs from one of mere 3.3 F ELL6RH 0.47 F R2 0.1 F LED1
1206 Q 1210 16k 1206
indicators to becoming 10V
1
IRLL110 100V 100V
GND
driving forces in electronic SOT223
lighting. Increased reliabili- LED2
ty and ruggedness (versus VIN

C4 11 10
other lighting technologies) 0.1 F VIN GATE
R3
gives the LED a bright fu- 4 56k
CA
ture indeed. Vendors in re- 5 Q2 MMBT5551
CS SOT23
cent years have introduced IC1
12 LED(N-1)
many ICs for driving LEDs, TO CS DACOUT
6
Q3 MMBT3906 10k
R 4
1 7
but the problem of driving CONTROLLER
2
SCLK FB SOT23
DIN R5
serial chains of LEDs has re- COMP
8 510k
3 9
ceived less attention. One CL GND R6 LED(N)
12k
approach to that problem MAX1932
C5 R7
adapts a bias-supply IC 12QFN
0.33 F 10k
Figure 1
for APDs (avalanche
photodiodes) to provide
adjustable-current, soft- The APD driver, IC1, provides high-voltage LED modules with software-adjustable intensity control.
ware shutdown, and logic
indication of open-circuit faults (Figure sheet help you select components for the these conditions correspond to a full-
1). This design reconfigures the APD-bias step-up dc/dc converter. The current-ad- scale output of 39 mA and a resolution of
IC,IC1, to allow its low-voltage DAC out- justment transfer function is: 150 A. The three-wire serial interface
put to modulate the high-voltage, cur- that controls IC1 allows you to shut down
rent-sense feedback via a high-voltage- IC1 by writing code 00hex to the DAC.
output transconductance stage com- The circuit also provides an output-volt-
prising Q2 and Q3. These two comple- age limit. If an LED fails open, the R 5-R 7
mentary transistors provide first-order where VCL is the current-limit threshold divider limits the output voltage, in this
temperature-compensation sufficient for (2V), CODE is the digital code to the case, to 50V. Simultaneously, the CL pin
the application. DAC in decimal format, and IOUT is the goes high to indicate the open-fault con-
Equations from the MAX1932 data desired output current. For this circuit, dition.

design
ideas
Improve roll-off of Sallen-Key filter
Doug Glenn, Teledyne, Lewisburg, TN
he well-documented Sallen- mately one-third to one-fourth
T
10
Key active filter is a staple of 0 the value of R 1, and then adjust
BREADBOARD
analog design.This Design Idea –10 R 4 as needed to allow use of
shows a way to obtain better roll-off –20 SIMULATED standard capacitor values. The
THREE POLE
by adding just a few common pas- –30 graph in Figure 2 shows the im-
SIMULATED
sive components. Figure 1a shows –40 provement in the cutoff rate of
a typical implementation of a –50 the filter; the result is a quasi-el-
three-pole, lowpass version. In op- –60 liptic response. A breadboard of
eration, you adjust the ratio of ca- 100 1000 10,000 100,000 the circuit in Figure 1b uses 5%
pacitors C1 and C2 to give a parts. The measured results
Figure 2 The improved cutoff rate of the filter results
peaked response for the two show good agreement with the
poles within the feedback loop.The in a quasi-elliptical response. Spice simulation. To take ad-
peaked response compensates for vantage of the faster roll-off,
the initial roll-off in the third pole formed quency, F1/(2R 4C4), is equal to ap- just scale the frequency and impedance
by the R 3-C3 section at the input. In Fig- proximately twice the desired cutoff fre- to your application. The highpass dual of
ure 1b, a twin-tee notch filter replaces the quency. this circuit works as well as the lowpass
R 3-C3 section at the input. The notch fre- Select a value for R 4 that’s approxi- version.
C1 R4 R5 C1
0.1 F 3600 3600 0.1 F _
_
R3 R1 R2 R1 R2
10k 10k 10k C6 10k 10k
+ 0.02 F +
C3 C2 C2
0.015 F 470 pF C4 R6 C5 470 pF
0.01 F 1800 0.01 F
(a)
(b)
Figure 1 The addition of a twin-tee network (b) considerably improves the roll-off rate of the circuit (a).
AC-coupling instrumentation amplifier improves

rejection range of differential dc input voltage
Francis Rodes, Olivier Chevalieras, and Eliane Garnier, ENSEIRB, Talence, France
he need for conditioning low- proach to removing the differential dc strumentation amplifier is to maintain
T level ac signals in the presence of

both common-mode noise and dif-
ferential dc voltage prevails in many ap-
content. But this technique requires the mean output voltage at 0V. To do so,
adding a pair of capacitors and resistors you insert an autozero feedback loop,
to ac-couple the inputs of the difference comprising IC4, R FB, and CFB, in a classic
plications. In such situations,ac-coupling amplifier. The manufacturing tolerances three-op-amp instrumentation amplifi-
to instrumentation and difference am- of these components severely degrade the er. This feedback loop produces a fre-
plifiers is mandatory to extract the ac sig- CMRR (common-mode-rejection ratio) quency-dependent transfer function:
nal and reject common-mode noise and of the amplifier. If cost is not an issue, you
differential dc voltage. This situation typ- could perform an initial trim, but this op-
ically occurs in bioelectric-signal acqui- eration is useless for biological applica-
sition, in which metallic-electrode polar- tions plagued by wide variations in elec-
ization produces a large random dif- trodes and tissue impedances. The Consequently, the ac-coupled instru-
ferential dc voltage, ranging from differential topology in Figure 1 ad- mentation amplifier behaves as a high-
0.15V, which adds to low-level biolog- dresses these problems (Reference 1). pass filter with a 3-dB cutoff frequen-
ical signals. Input ac-coupling is one ap- The principle of this ac-coupled in- (continued on pg 92)

design
ideas
VIN1 +
cy from the equation f 1/2R FBCFB. At R R
IC1
first glance,you might think that the out- _
put-autozeroing behavior of the ac-cou-
pled instrumentation amplifier is per- R2
fect. Unfortunately, the output _

R1
autozeroing capability of this circuit is IC3 VOUT
R2
strongly limited. You can determine this + CFB
limitation by expressing the output volt-
RFB
age as a function of the input signals and _ _
the integrator’s output voltage, VZ: IC2
R

R
IC4
VOUT(12R 2/R 1)(VIN1VIN2)VZAD VIN2 + +
VZ
(VIN1VIN2)VZ, where VOUT is the out-
put voltage. In this expression, AD
12R 2/R 1 is the differential gain in Figure 1
the passband. At dc,the output voltage is This ac-coupled instrumentation amplifier accommodates only 5-mV maximum input.
0V as long as the integrator’s output does
not reach its saturation voltage, VZ(MAX) . as a function of the input signal and the
Therefore, setting the output voltage at integrator’s output voltage,VZ, becomes:
0V in the above expression yields the
maximum differential-input dc voltage
that this circuit can handle:
In the above equations, the additional

term, 1R 4/R 3, is the gain of the active-
feedback stage.
Consider, for instance, the typical per- In this expression, AD(12R 2/R 1) The new expressions for VIN(MAX) and
formance and constraints of a portable (1R 4/R 3) is the new differential gain in AD(MAX) clearly show the advantages of
biotelemetry system: differential gain of the passband. Figure 2’s ac-coupled instrumentation
1000, 5V split power supplies, and op At dc, the output voltage remains 0V as amplifier with active feedback: For an
amps with rail-to-rail output-voltage long as the integrator’s output does not identical differential gain, you can extend
swing. In this system, the application of reach its saturation voltage, VZ(MAX). the polarization-voltage range, VIN(MAX),
the formula for VIN yields a maximum Therefore, setting the output voltage at by a factor equal to the gain of the active-
differential-input dc voltage of only 5 0V in the new expression for output volt- feedback stage. Conversely, for a given
mV. This limited performance is unac- age yields the new maximum differential- polarization-voltage range, VIN (MAX),
ceptable for biological applications, in input dc voltage and differential gain. you can increase the differential gain by
which you encounter differential-input They are, respectively: the gain of the active-feedback stage.
dc voltages of 0.15V. The ac-coupled
instrumentation amplifier in Figure 2 R4
1/2 LT1464
R R 1/2 LMC662 100k
overcomes this limitation, thanks to the VIN1 +
100k 100k
+
addition of “active feedback,” which in- IC1 IC5
R3
cludes voltage divider R 3-R 4 and the as- _ _
1.5k
sociated buffer amplifier, IC5. With this R2
3.3k
arrangement, the following equations 1/2 LMC662
_
give the new transfer function and high- R1
R2 IC3 VOUT
pass cutoff frequency, respectively. 470
3.3k CFB
+
CMRR 1 F
TRIM T RFB
4.7M
_ R RF _
100k 95k
IC2 IC4
VIN2 + 10k +
VZ
1/2 LT1464 1/2 LMC662
NOTE: R AND R F ARE 1%; OTHERS ARE 5%
Figure 2
This instrumentation amplifier can accommodate a differential-input
The expression for the output voltage range of 0.34V.

design
ideas
The only drawback of this topology is and it can handle a differential-input dc- rent and current drain. (Respectively:
apparent in the expression for f C, the voltage range of 0.34V. VNOISE26 nV/Hz, f C9 Hz, IBIAS0.4
highpass cutoff frequency.You multiply To obtain this performance, you set the pA, and ICC230 A.)
this frequency by the gain of the active- active-feedback stage gain and the differ- A theoretical analysis using the LT
feedback stage. Therefore, to maintain a ential-amplifier gain, respectively, to 67.6 1464’s noise parameters shows that un-
given cutoff frequency, you must multi- and 15. With these gain values, the noise der worst-case conditions, the input-
ply the time constant by a factor equal to performance of the ac-coupled instru- noise voltage should not exceed 11 V
the active-feedback stage gain. This fac- mentation amplifier of Figure 2 is simi- rms. Tests on prototypes confirm this
tor can be an issue in processing signals lar to that of a classic instrumentation prediction; the tests effectively measure
whose spectrum includes low-frequency amplifier. This situation occurs because input-noise voltages of 3 to 6 V rms. To
components. In such applications, R FB the autozeroing and active-feedback sum up, an ac-coupled instrumentation
and CFB can reach prohibitive values. stages, IC4 and IC5, are after the input dif- amplifier with active feedback is well-
Consequently, you must make a trade-off ferential stage, IC1 and IC2. Consequent- suited for applications requiring high dif-
between the time constant and the active- ly, the gain of the differential stage rough- ferential gain, a capability for handling
feedback stage gain. The component val- ly divides their respective noise con- large differential-input dc voltages, and
ues in Figure 2 are a typical example of tributions,which are therefore negligible. low-noise performance.
such a trade-off: The values are for an You can use several low-noise op-amps
EEG (electroencephalogram) amplifier for IC1 and IC2. For portable bioteleme- Reference
with 5V split power supplies. The am- try applications, the LT1464 is a good 1. Stitt, Mark, “AC-Coupled Instru-
plifier has a differential gain of 1000 and compromise for input-noise density, mentation and Difference Amplifier,”
a highpass cutoff frequency of 2.3 Hz, noise-corner frequency, input-bias cur- Burr-Brown, AB-008, May 1990.
Simplify computer-aided engineering

with scientific-to-engineering conversion
Alexander Bell, Infosoft International, Rego Park, NY
he simple yet useful The formula is in VB; you
T formula in this Design

Idea enables conver-
sion from scientific format
could use it in any VB/VBA-
backed software applications.
In this example, the function
(for example, 2.29), which is in a code module of an MS
is typical for CAE (com- Excel file (Figure 1). You
puter-aided-engineering), could also use it as an Excel
double-precision output Add-In (.xla) or a “pure-VB,”
values, into “human- compiled-DLL component.
friendly” engineering for- You can download Listing 1
mat (for example, 2.2 nF). and the Excel file from the
The engineering format is Web version of this Design
more suitable for bills of Idea at www.edn.com. The
material and other electri- input numerical value in this
cal and electronic-engi- formula has double-preci-
neering documents The formula appears in the formula bar, taking the first sion accuracy, and its range
and specifications. Figure 1 spans from approximately
numeric parameter from the column to the left. The unit of
The formula is rather electrical resistance, “ohm,” is a second parameter. 1.79308 to 1.79308, which is
straightforward. It takes sufficient for any practical
two parameters. The first is the numerical-engineering practice. Listing 1, avail- engineering calculations. Note that the
cal value,and the second one specifies the able at www.edn.com, shows details of the maximum value is even bigger than the
unit of measurement—ohms, farads, or formula. The tricky part of the formula famous “googol,” which is represented by
henries, for example. Alternatively, it is the conversion to a decimal type after 100 digits.
could be of any random text,including an the formula calculates the ratio of two log
empty string, “.” The formula calculates values (Reference 1). This step ensures the Reference
the mantissa/order of magnitude and re- correct order-of-magnitude calculations 1. Bell, Alexander, “What’s wrong with
turns the text string, formatted in com- in cases in which the mantissa of the in- INT(LOG) in VBA?” Access-VB-SQL Ad-
pliance with commonly accepted electri- put value is close or equal to one. visor , October 2002, pg 65.

design
ideas
1.5V battery powers white-LED driver
Steve Caldwell, Maxim Integrated Products, Chandler, AZ
lthough white LEDs are common L1
A in a variety of lighting applications,

their 3 to 4V forward-voltage drop
makes low-voltage applications challeng- 1.5V
+
C1
10 H
10 F R1
ing. Charge pumps and other ICs are 5
1
62 mA
available for driving white LEDs, but they LX 4
OUT
generally don’t work with the low supply 1
BATT C2 4 5
voltage of 1.5V in single-cell-battery ap- 10 F RS+ RS D2
IC1 3
D1 VCC
plications. The low-voltage circuit of Fig- MAX1722
3.9V IC2
ure 1 provides a current-regulated output 2 GND MAX4073T
suitable for driving white LEDs. 3 1
The boost converter,IC , can sup- Figure 1 FB OUT
GND
1
ply load currents to 62 mA with input 2
voltages as low as 1.2V, making it suitable
for use with a 1.5V, single-cell battery. Be- Powered from a single-cell battery, this circuit provides a regulated output current suitable for
cause a white LED draws negligible load driving a white LED.
current until the output voltage rises
above 3V, the boost converter can start across R 1 with a gain of 20.This high gain provides overvoltage protection at the
with input voltages as low as 0.8V. boosts efficiency by enabling use of a output. When the output voltage rises
By deriving feedback from a high-side small-valued current-sensing resistor. above the sum of the zener voltage (VZ)
current-sense amplifier, IC2, the circuit You can calculate the value of R 1 from the and IC1’s 1.235V feedback voltage (VFB),
allows current regulation without sacri- desired output current: R 11.235V/ the feedback voltage (Pin 3) rises and
ficing efficiency. IC2’s 1.8-MHz band- (20IOUT). For 1.5V input and 62-mA causes IC1 to stop switching.Thus, for an
width also eliminates instability in the output, the circuit efficiency of Figure 1 open-circuit output, the output voltage is
feedback loop. IC2 amplifies the voltage is approximately 80%. Zener diode D1 regulated at VZVFB.
Simple VCOM adjustment uses

any logic-supply voltage
Peter Khairolomour and Alan Li, Analog Devices, San Jose, CA
ll TFT (thin-film-transistor) LCD
A
TABLE 1—OUTPUT-VOLTAGE RANGE
panels require at least one appropri-
R2 tolerance (%), scale R2 (k) VCOM (V) Step size (mV)
ately tuned VCOM signal to provide a 30, zero 0 3.5 3.9
reference point for the panel’s backplane. 30 mid 3.5 4.0
The exact value of VCOM varies from pan- 30, full 7 4.5
el to panel, so the manufacturer must pro- 30, zero 0 3.3 6.8
gram the voltage at the factory to match 30, mid 6.5 4.2
the characteristics of each screen. An ap- 30, full 13 5.1
propriately tuned VCOM reduces flicker
and other undesirable effects. Tradition- the assembly line usually perform. This VCOM-adjustment process, resulting in
ally, the VCOM adjustment used mechani- adjustment is not only time-consuming, lower manufacturing cost and higher
cal potentiometers or trimmers in the but also prone to field failures arising from product quality. Unfortunately, many
voltage-divider mode. In recent years, human error or mechanical vibration. panels operate at higher voltages, and the
however, panel makers have begun look- A simple alternative to achieving the choice of available supply voltages is lim-
ing at alternative approaches because me- increasing adjustment resolution for op- ited. The system implementation for a 5V
chanical trimmers can’t provide the nec- timal panel-image fidelity is to replace supply is straightforward (Figure 1).
essary resolution for optimal image the mechanical potentiometer with a dig- Without a 5V supply, the circuit can be-
fidelity on large panels. They also require ital potentiometer. Using digital poten- come more complex.
a physical adjustment that technicians on tiometers, panel makers can automate the This Design Idea shows a simple way

design
ideas
that you can use any available logic sup- stores the desired potentiometer setting plications. For systems that have no 5V
ply to power the potentiometer provid- into the EEPROM. The AD5259 uses a supply, many designers would be tempt-
ing the VCOM adjustment. The 6- or 8-bit 5V, submicron CMOS process for low ed to simply tap off the potentiometer’s
AD5258/59 nonvolatile digital poten- power dissipation. It comes in a space- series-resistor string at the 5V location.
tiometer demonstrates this approach.An saving 10-pin MSOP, an important fea- This approach is not viable,because, dur-
I2C serial interface provides control and ture in low-cost, space-constrained ap- ing programming (writing to the
VCC SUPPLIES POWER 14.4V
3.3V 14.4V TO BOTH THE
3.3V MICROCONTROLLER
5V AND THE LOGIC R1
R1 SUPPLIES OF THE
DIGITAL POTENTIOMETER 70k
C1 70k
C1 5V
1 F AD5259 1 F AD5259
R6 R5 VDD R6 R5
10k 10k VDD
_ 10k 10k _
VLOGIC IC1 VLOGIC IC1
AD8565 AD8565
SCL R2 R2
+ 3.5V<VCOM<4.5V SCL 3.5V<VCOM<4.5V
CONTROLLER 10k CONTROLLER +
10k
SDA SDA
GND GND
R3 R3
25k 25k
Figure 1 Figure 2
A digital potentiometer makes it easy to adjust V COM to the A separate VLOGIC pin makes it possible to derive the V DD supply from
desired value. the potentiometer’s resistor string.

design
ideas
VDD
EEPROM), the AD5259’s VLOGIC pin typ- RDAC1
RDAC1
VLOGIC A1
ically draws 35 mA. It cannot draw this RDAC EEPROM REGISTER
current level through R 1 because the volt- DGND
W1
age drop would be too large. For this rea- B1
son, the AD5259 has a separate VLOGIC pin

that can connect to any available logic SCL
8 DATA
supply. In Figure 2, VLOGIC uses the sup- SDA 2
I C
8
SERIAL
ply voltage from the microcontroller that INTERFACE CONTROL
is controlling the digital potentiometer. AD0
Now, VLOGIC draws the 35-mA program-
AD1
ming current, and VDD draws only mi- COMMAND-DECODE LOGIC
croamps of supply current to bias the in-
ternal switches in the digital potentio- POWER- ADDRESS-DECODE LOGIC
ON
meter’s internal resistor string. If the pan- RESET
el requires a higher VCOM voltage,you can CONTROL LOGIC
add two resistors to place the op amp in
a noninverting gain configuration. Figure 3 This block diagram shows the digital potentiometer’s inner workings.
The digital potentiometer has 30%
end-to-end resistance tolerance. Assum- 4V0.5V, with a maximum step size of target specification. Also, because the
ing that the tolerances of R 1, R 3, and VDD 10 mV. As Table 1 shows, the circuit in digital potentiometer’s logic supply
are negligible compared with those of the Figure 2 guarantees an output range of matches the microcontroller’s logic lev-
potentiometer,you can achieve the range 3.5 to 5.4V with a step size within 10 els, the microcontroller can read data
of output values that Table 1 shows. As- mV. And, despite the 30% tolerance of back if desired. Figure 3 shows a block di-
sume that the desired value of VCOM is R 2, the midscale VCOM output meets the agram of the digital potentiometer.

design
ideas The best of
design ideas
www.edn.com
Build a negative-voltage power-side switch

Michael English, Micrel Semiconductor, San Jose, CA
hen you need to quickly connect
W
TTL-LEVEL INPUT R1
a negative power supply under VIN=0.8 TO 2.4V 5.1k
logic control, the negative power- +

side switch in Figure 1 can help. Al-
though originally intended for driving
the gates of high-current MOSFETs, the
Q1 C2 C1
MIC4451 can assume a different role. It 2N3905 10 F, 15V
10 F, 15V
provides complementary, low-on- MIC4451
Figure 1
resistance MOSFET switches to R2
OUTPUT
TO LOAD
connect a system power-supply rail to a A power-MOSFET gate driver 7.5k
negative input voltage or to ground, en- does double duty as negative-
abled by a digital signal. The MIC4451 supply power switch. –12V
comprises an input buffer with a small
amount of hysteresis and several logic in- nel devices at the output is approximate- plifies inversion of logic control as need-
verter/buffers that ultimately drive a ly 1. So, the output can connect a 100- ed. Figure 1 shows details of the interface
high-current output stage. Figure 2 mA load to the negative input voltage of the MIC4451 to TTL levels, using a
shows a block diagram of the MIC4451. with less than 100-mV voltage drop. A common-base pnp transistor for level
The on-resistance of the n- and p-chan- noninverting version,the MIC4452, sim- translation. The emitter current of Q1 is
approximately: IE(VTTLHVBE)/R 1
VS (2.40.65)/R 1, where VTTLH is the TTL-
8 high level, 2.4V. IE should be 400 A in
0.3 mA
MIC4451
accordance with TTL specs, so
INVERTING IE(2.40.65)/R 1400 A.
0.1 mA
Solving for R 1, you obtain R 1
6, 7
1.8V/400 A4.5 k . The VIH (lowest
OUT permissible high input) logic-level
2k specification of the MIC4451 is 2.4V.
IN
2 MIC4452 Ignoring base-current errors, ICIE,
NONINVERTING
so R 2IC2.4V. Note that the MIC-
4 4451’s input voltage, VIH, is specified
GND with respect to the ground pin of
Figure 2 The MIC445x FET driver includes low-on-resistance complementary FETs.
the part. To determine R 2:R 22.4V/
Build a negative-voltage
power-side switch ........................................105
Circuit offers series protection
against power-line transients....................106
Build a simple, soft-action
muting switch ..............................................108
High-voltage amplifier
uses simplified circuit ..................................110
Simple circuit provides
power sequencing........................................112
(a) (b) Publish your Design Idea in EDN . See the
Turn-on (a) and turn-off (b) characteristics of the circuit in Figure 1 are for a
Figure 3
12V supply.
www.edn.com O c to b er 1 4 , 2 0 04 | ed n 105

design
ideas : 4 mV
AT: –1 mV
: 3.18 mSEC
AT: 1.62 mSEC
V+
D1
times when driven from
5.6V TTL. The output bypass
IA
RA
capacitor and on-resist-
1.8k ance of the MIC4451 de-
IB termine the rise and fall
RB
3k times. Figure 4 shows a
simple circuit for sensing
Q1 C2 C1 the level of a positive sup-
2N3905
10 F, 15V 10 F, 15V ply. The detection
IC MIC4451 threshold, V, is a Figure 5 The circuit in Figure 4 turns on
OUTPUT
RC TO LOAD function of the break- the negative supply when the positive supply
7.5k
down voltage of zener exceeds 1.5V.
diode D1, VBE of Q1, resis-
–12V tor values, and the input tector trips when R CIC 1.5V, so re-
threshold of the MIC4451. arranging: R C1.5V/0.2 mA7.5 k .
Figure 4 This circuit senses the magnitude of a Referring to Figure 4 and Figure 5 shows details of the operation
positive supply and turns on a negative supply when the ignoring base-current er- of the negative power switch with posi-
positive supply exceeds a threshold. rors, the collector current tive-supply sensing. To sum up, a circuit
of Q1 is approximately: IC intended for driving high-speed-MOS-
IE2.4V/0.4 mA6 k  minimum. IAIB; IC(VVZVBE)/R AVBE/R B. FET gates finds new use as a negative-
You can comfortably choose real val- Choosing V7V and using a 5.6V power-supply switch. You can easily in-
ues for R 1 and R 2 somewhat higher than zener diode with component values from terface the MIC445x to logic-level
the worst-case limits calculated above,so Figure 4 allows you to solve for IC: control signals. You can use a simple cir-
choose R 15.1 k  and R 27.5 k . Use IC(75.60.65)V/1.8 k 0.65V/3 cuit to detect the level of a positive sup-
1% resistors to ensure worst-case logic k (0.416 0.216) mA0.200 mA. Be- ply voltage and connect a negative sup-
levels are satisfied over temperature. Fig- cause the input threshold of the ply when the positive voltage has risen
ures 3a and 3b show power-switching MIC4451 is typically 1.5V, this level de- above a certain threshold level.
Circuit offers series protection

against power-line transients
Alfredo Saab and Travis Eichhorn, Maxim Integrated Products, Sunnyvale, CA
oltage transients on low-voltage
V 1 Q
power lines can sometimes attain D1
IXFH26N50
1N4007
amplitudes many times the nominal
voltage level. That behavior often calls Q3
for protection against the ap- 2N3906 10k
Figure 1 10k
plication of improper power 25W 1k
levels. The usual way to protect sensitive
circuitry against overvoltage is to add 6
1k 1k
parallel clamps. Fuses or other current- 8 GATE Q4
BATT SRC 7
limiting devices precede these clamps’ 2N2222 2.2 nF + 100 F
high energy-absorption capability. Oth- 3.3M IC1 35V
er cases require the use of high-voltage 4 MAX1614
0.01 D2 LBI 1k
2
series protection (instead of parallel F 18V
470k
OFF
ZENER
clamps) because of the difficulty in re- 1 3
10k
Q2
ON LBO
setting or replacing fuses,an inaccessible GND 2N3904
operating environment, or the need for 5
uninterrupted operation. The series-

2.2k D3
protection circuit of Figure 1 turns off 1N4148
the power switch using a series-connect-
ed, high-voltage, n-channel MOSFET This circuit protects a load, connected to the right pair of terminals, from undervoltage and high-
power switch, Q1, and a fast overvoltage voltage transients in the supply voltage, connected to the left pair of terminals.
106 ed n | O c to b er 1 4 , 2 0 04 www.edn.com

design
ideas
V
detector. The power switch and OUT
2V/DIV
tiates a rapid sequence: Q3 turns
series-connected power rectifier, on, which turns on Q4, which
D1, protect the load turns off Q1 by quickly discharg-
against high-voltage Figure 2 VIN ing its gate capacitance.
transients and continuous over- 50V/DIV You can demonstrate the cir-
voltage as high as 500V of either cuit’s performance by applying a
polarity. 150V transient to the supply volt-
In the circuit, which powers age while the circuit output is de-
VGATE
loads as heavy as 1A from a nom- livering 1A at 12V (Figure 2).The
20V/DIV
inal 12V power line, a high-side- internal impedance of the tran-
switch driver,IC1, biases the pow- sient source is 1, and the rise
er switch fully on. You can time of the applied voltage is 1
increase the maximum load cur- sec. The circuit draws 20 A
rent by changing D1 and Q1. To during normal operation, includ-
guard against low supply voltage, A 150V transient applied to V IN of the Figure 1 circuit has little ing 3 A by the undervoltage-
IC1 includes an undervoltage- effect on VOUT. lockout, voltage-sensing divider
lockout feature that allows oper- and 17 A by IC1. If your design
ation only when the line voltage is greater power switch to ground, turning it off needs high-temperature operation, note
than 10V. To protect against overvoltage, hard. Rising overvoltage first turns on that the gate-current output of IC1 is rel-
the circuit includes a three-transistor,no- zener diode D2, which protects the IC by atively limited. Your design calculations
bias-current, 50-nsec-operation over- clamping the voltage across it to approx- for high temperature should also pay
voltage detector that triggers when the imately 18V. Zener current flows through close attention to leakage currents that
input voltage reaches approximately 20V. the 2.2-k  resistor, producing a base the other circuit components con-
At that time,Q4 “crowbars”the gate of the voltage that turns on Q2. That action ini- tribute.
Build a simple, soft-action muting switch

John Firestone, Bremerhaven, Germany
he circuit in Figure 1 adds a soft off voltage, makes the on/off transition ample. Q1 can then finish muting. Mak-
T muting switch with power-up/pow-

er-down muting to a line-level audio
circuit. R 4, C1, and JFET Q1 quietly
times roughly equal. R 2 and D3 quickly
discharge C1 and mute the signal during
power-down. For this process to work,
ing Q1 a more tightly defined PN4392 can
soften this requirement and allow mut-
ing of lower impedance signals. R 3 un-
ground a signal in 100 to 200 msec when the signal path should remain stable to loads S1 from R 2, so that D3 does not
you close S1 or release it when you open below roughly one-third the normal shorten the earlier transition times. S1’s
S1. Potentiometer R 2, set to twice Q1’s cut- supply voltages—below 4V in this ex- normally closed contact, resistor R 1, and
dual-LED D2 add an indicator light. D1
raises the red LED’s on-state threshold to
R1
D1 RED
3.9k indicate green when muting is off. Re-
D2
1N4148 –12V placing D1 with a short circuit causes the
MUTE 1
GREEN red LED to light. This scheme makes a
2 more expensive DPDT (double-pole,
3
S1
double-throw) switch unnecessary, pro-
Q1 vides uninterrupted light as S1 switches,
–12V
TP1 2N3819 and reduces the LED-current change for
R3 R4 D SIGNAL TO BE MUTED less noise (references 1 and 2).
R2 82k 2.2M (10- TO 100-k  IMPEDANCE)
20k G S
C1
References
100 nF 1. Linkwitz, SJ, “Loudspeaker System
D3
1N4148
Design,” Wireless World , Volume 84, June
NOTE: 1978, pg 67.
SET VOLTAGE AT TP 1 TO TWICE Q 1's VGS(OFF), 2. Self, D, “Inside Mixers,” Wireless
SO THAT 0.50V GS(OFF) = 0.7RC=150 mSEC.
Figure 1 World , Volume 97, April 1991, pg 280,
www.dself.dsl.pipex.com/ampins/mixer/
This simple circuit provides soft muting for line-level audio circuits. mixerdes.htm.

design
ideas
High-voltage amplifier uses simplified circuit
Jui-I Tsai, Jun-Ming Shieh, Tai-Shan Liao, and
Ching-Cheng Teng, National Chiao Tung Unversity, Taiwan
any scientific instruments and
M sensors need ac high-voltage drive.

High-voltage drive is useful for
driving electrodes in many applications.
The challenge is to boost the output of a
conventional op amp to high voltages.
Available ac high-voltage amplifier mod-
ules are limited to approximately 1200V
p-p. This Design Idea presents a simpli-
fied ac high-voltage amplifier that uses
complementary, cascaded NMOS and
PMOS transistors (Figure 1). The OP07
op amp has low input-offset voltage, low
input-bias current, and high open-loop
gain.These attributes make this op amp Figure 2 Figure 3 The input is 750
The sinusoidal
useful for high-gain instrumentation ap- input is 8V p-p (top trace), and output mV (top trace), and the output is 200V
plications.In addition, the OP07 features is 1800V p-p (bottom trace). p-p (bottom trace).
1000V excellent stability of offsets and

gain over time and temperature.
R25 R26 Q1
The ac gain of the LM356 stage,
R15
10k 3M which R 3, R 4, R 7, and R 9 determine,
3M is approximately 100.
R24
Q11 82k
R27
Q2
The high-voltage MTP2P50E p-
R14 3M
3M
channel MOSFET has maximum
drain-to-source- and gate-to-
R28
drain-voltage ratings of 500V. The
Q3
12V
R23
3M high-voltage BUK456800B n-
R2
C2
Q12
82k channel MOSFET has maximum
0.1 F R10
R5
20k 10k
R29
drain-to-source- and gate-to-
3M R6 Q4
7.5k 3M drain-voltage ratings of 800V. Q1
R1 12V R11 through Q6 are PMOS transistors,
R4 12V 10k
10k
2 – 7 2M R22 R37 R30
R40
and Q7 through Q12 are NMOS de-
6 3 7
3
CP07 +
6
10k 3M 3M
1k vices. These FETs are well-suited
+ R3 LF356
4
20k
2
– R21 R38 OUTPUT
for high-voltage cascade circuits.
4 12V R31 R36
–12V 10k 3M 4M 10M
They connect symmetrically in se-
FUNCTION R7 R9
–12V
R12 Q5 ries to increase their overall break-
10k
GENERATOR 510k 510k
R32 Q7 MONITOR down voltage for power applica-
R13
4M R39 tions. The bias-voltage circuits
10k
R8
10k
R20
comprise separate biasing-resistor
C1 D1
5k 0.022 F
1N961 82k
R33 Q8
pairs R 10 to R 13 and R 14 to R 17; the
R16
4M result is a symmetrical output of
3M the high-voltage amplifier. Figure
2 shows a sinusoidal input of 8V
R34 Q9
Figure 1 Q6
R18 4M
p-p at 100 Hz and an output of
R17 82k 1800V p-p. Figure 3 shows a sinu-
This ac high-voltage 3M
soidal input of 750 mV p-p at 2
amplifier can deliver R19 R35 Q
10k 10 kHz and an output of 200V p-p.
more than 1800V p-p. 4M
The total power bandwidth of the
circuit is approximately 200
1000V
kHz.

design
ideas
Simple circuit provides power sequencing
John Betten, Texas Instruments, Dallas, TX
SICs, FPGAs, and DSPs can require ure 1 shows a simple op-amp circuit that figuration with the next-higher output
A multiple supply voltages with re-

strictions on their start-up sequenc-
ing. Often, I/O voltages, which usually
integrates a dual switching power supply
to provide simultaneous output-voltage
sequencing.
voltage as its input or “sense” voltage.
Thus, at power-on, when the 3.3V output
is 0V, amplifier IC1’s output voltage is
have the highest voltage, must come up In this power-sequencing circuit, three high, also forcing the TPS5120 controller
first, followed by all other voltage rails in output voltages sequence at start-up, dur- to regulate its output voltage to 0V. The
a high-to-low order, with the core voltage ing which each output voltage tracks the output voltage of amplifier IC3 is also
last. This scenario may also require that next-higher voltage rail until it reaches its high, because the 2.5V output, which is
one supply rail not exceed another by fixed regulation voltage. Assume that a also 0V, controls input voltage. As the
more than a diode drop; otherwise, ex- 3.3V “master”-I/O voltage (not shown) 3.3V output rises linearly, the amplifier’s
cessive current may flow backward from powers up normally. The controller for output voltage decreases linearly to 0V.
the I/O voltage through the IC into a low- this voltage uses its soft-start function to The 2.5V output voltage thus increases
er voltage, possibly damaging the expen- provide a smooth linear ramping of its from 0V to its maximum setpoint of
sive IC. Often, you can control this se- voltage.The TPS5120 dual switching reg- 2.5V. The 1.8V output voltage tracks the
quence by placing external diodes ulator generates two additional voltages, 2.5V output in a similar manner. Set the
between successive voltage rails to clamp 2.5 and 1.8V. In most standard switching- amplifier’s component values such that
a higher voltage to within a diode drop of regulator circuits, the bottom sides of R 4 when the sensing voltage, such as the
a lower voltage, thus preventing possible and R 10 would be grounded, thus fixing 3.3V, reaches the tracking-voltage level—
latch-up in the IC. The diode conducts the output-voltage setpoints. In this cir- here, 2.5V—the amplifier’s output volt-
only when a lower voltage rises above a cuit, the output of an amplifier controls age just attains 0V. Therefore, increases in
higher one at turn-on, but not if a high- the voltage at the bottom of each of these the sense voltage higher than 2.5V can-
er voltage were to increase above any low- resistors. An amplifier output voltage of not further raise the tracking output volt-
er voltage, because the diode is reverse- zero sets the output voltage to its prede- age, because the amplifier’s output volt-
biased. A preferred method would be to termined fixed voltage, but any voltage age has already saturated to ground level.
use the power-supply controller to pre- greater than zero forces the output volt- Simultaneous tracking requires sever-
cisely control the start-up-voltage se- age to be lower than its setpoint. al important design criteria. The ampli-
quencing of the power-supply rails. Fig- The amplifiers are in an inverting con- fier’s feedback ratio,R 5-R 6, must be equal
TYPICAL SYNCHRONOUS BUCK CONVERTER

SEQUENCING CIRCUIT
5V BIAS 2.5V VIN

C2
0.1 F R1
Figure 1 IC1 100k
5
3 + OPA336N IC2
1 TPS5120DBT
4 – OUT 2.5V
1 30
INV1 LH1
2 R4 2 29 +
FB1 OUT1_U
R5 R6 3 28
J1 51.1k 0.85V C7 SOFTSTART1 LL1
100k 51.1k 4 27
1 REFERENCE 1000 pF PWM/SKIP OUT1_D
3.3V 5 26
VOLTAGE CT OUTGND1
SENSE 2 6 25
GND 5V_STBY TRIP1
7 24 VIN
GND VCC
8 23
C8 1.8V REF TRIP2
5V BIAS 9 22
0.1 F STBY1 VREF5
C11 C12 10 21
R7 STBY2 REG5V_IN
0.1 F 1000 pF 11 20
FLT OUTGND2
IC3 100k 12 19
5 POWERGOOD OUT2_D
3 + OPA336N 13 18
SOFTSTART2 LL2
1 14 17
FB2 OUT2_U
4 – OUT 15 16
INV2 LH2 +
2
R11 R12 R10 1.8V
J2 88.7k
100k 88.7k
2.5V 1
SENSE 2
GND
VIN
An amplifier circuit forces the converter’s output voltages to track during start-up.

design
ideas
to the feedback-resistor divider herently faster at start-up than
ratio set by R 1 and R 4. In addi- the 3.3V sense voltage. A large
tion, you must use the TPS5120 soft-start capacitor value does
controller’s reference voltage, not allow for fast tracking on
0.85V in this exam- the outputs. Too small a value
ple, as an input to the Figure 2 may cause output-voltage
amplifier’s noninverting termi- overshoot when you initialize
nal. Any reference-voltage val- power. Figure 2 shows the
ue other than this one forces the start-up voltages for three syn-
tracking-voltage output to a chronous buck converters. The
voltage different from the sense 3.3V acts as a master, and 2.5
voltage. The amplifier you se- and 1.8V track their respective
lect should have a low input- higher voltages.You can set the
offset voltage and be capable of sense voltage for the 1.8V out-
an output voltage at least as put to track the 3.3V output
great as the controller’s refer- rather than the 2.5V with
ence voltage. equally good linear tracking
A rail-to-rail amplifier works The 2.5 and 1.8V outputs track the 3.3V output at start-up. during start-up. You can add
well in this application. Indi- this sequencing circuit to any
vidual amplifiers to allow localized com- amplifier’s noninverting input for the power-supply controller that provides
ponent placement,avoiding routing near reference voltage. It uses a small, soft- access to its reference voltage, soft-start
any noise sources.This design uses an ad- start capacitor value for the TPS5120 capacitors, and output-voltage resistor-
ditional decoupling capacitor near the controller so that the controller was in- divider network.

design
ideas The best of
design ideas
www.edn.com
Latching power switch uses

momentary-action pushbutton
Anthony Smith, Scitech, Biddenham, Bedfordshire, UK
LOAD VOLTAGE,
ost inexpensive pushbutton
M
VS VL
switches, particularly pc-board- Q4
mounting and membrane types,
R1
have momentary action. Latching types 470k
R7
1M
are often larger and relatively expensive,
Q2 R9
and they frequently are unavailable in the
DC SUPPLY R3 1k
style you’d like to use. You can thus have + R8
 VOLTAGE, VS 470k
Q1 100k
a problem if you need a small, inexpen-
sive on/off switch for latching power to R5
R2 LOAD
10k
a load. The circuit in Figure 1 shows how 470k
S1 R4
you can use a simple,momentary-action, 1k Q3
SPNO (single-pole, normally open)
pushbutton switch to latch power to a VC1
C1 R6
load. Requiring just a handful of com- 1 F 470k
mon, garden-variety components, the
0V
circuit works over a wide voltage range
and is ideal for single-cell applica-
tions, because it can operate at volt- Figure 1 The momentary-action pushbutton switch, S1, provides positive latching action
ages as low as 1V or less. Transistors Q2 in this circuit.
and Q3 form an SCR-like structure that
functions as a simple latch, Q4 switches for Q2 and Q4, which both turn on. Q2 the circuit would “chatter” on and off
power to the load, and S1 is the momen- now provides base bias for Q3 via R 5,and each time you pressed the pushbutton
tary pushbutton switch. also for Q1 via R 3. The circuit is now in switch and would end up in an indeter-
When you first apply the supply volt- its on, or latched, state and remains that minate state. Although Figure 1 shows a
age,VS, all four transistors are off,and ca- way even though S1 is open. The load is value of 1 F, other values may be more
pacitor C1 charges via R 1 and R 2 until its now energized, and VL is roughly equal to suitable for a particular application, so
voltage, VC1, is equal to VS. The circuit is VS. Transistor Q1 is now saturated, caus- prepare to experiment. None of the re-
now in its off,or unlatched, state,and the ing C1 to discharge via R 2 such that VC1 sistor values is particularly critical, and
load voltage, VL, is 0V. A momentary clo- falls to a few tens of millivolts (Q1’s col- the values shown in Figure 1 are fairly
sure of the pushbutton switch, however, lector-emitter saturation voltage). An- optimal for a supply voltage of approxi-
causes C1 to dump its charge into the base other momentary closure of the push- mately 1 to 1.5V—in other words, a sin-
of Q3, which conducts and furnishes bias button switch couples this low voltage to gle cell. At higher voltages, the resistor
Q3’s base, turning it off. As a result, all values should increase proportionally, al-
four transistors turn off, and the circuit though you should hold R 2 and R 4 con-
Latching power switch uses
momentary-action pushbutton ................101 reverts to its off, or unlatched, state. The stant at approximately 470 and 1 k , re-
load is now de-energized, and VL falls to spectively. Keeping the R 2-C1 time
Method provides overpower protection
0V. Because Q1 is now off, C1 begins to constant fixed at a few hundred millisec-
for quasiresonant supplies ........................102
charge again via R 1 and R 2, such that an- onds ensures that the time taken to dis-
Circuit delivers dimming control other momentary closure of S1 latches the charge the capacitor is not excessive; oth-
for white-LED driver ....................................106 circuit on again. erwise, once the circuit has been latched,
System implements digital-clock Timing capacitor C1, acting with R 1 there may follow an unacceptable delay
modulation....................................................108 and R 2, provides debouncing for the before it can be unlatched. Resistor R 4
Publish your Design Idea in EDN . See the pushbutton switch, such that contact limits the current flowing from C1 into
What’ s Up sect ion a t ww w.edn. com. bounce has no effect on the desired latch- Q3’s base to a safe level; its value should
ing function. Without the RC time delay, be fairly small to ensure that R 5 and R 6 do
www.edn.com O c to b er 2 8 , 2 0 0 4 | ed n 101

design
ideas
not distort the voltage appearing at Q3’s current drain on VS when the circuit is signal types with good current gain
base when the switch closes. latched on. Furthermore, for a particu- (moderate to high forward current gain).
You should size resistor R 1 according to lar value of VS, R 1 should be large enough Power switch Q4 should have low VCE(SAT)
the supply voltage you use. For a given to ensure that VC1 does not rise too quick- to ensure most of the supply voltage is de-
value of R 2, R 1 determines the time it ly after the circuit has been unlatched, or livered to the load when the circuit is
takes VC1 to rise toward VS immediately it could turn the latch back on again be- latched. You should select resistor R 9 to
after the circuit has been unlatched. In fore the switch has opened. You may need furnish plenty of base drive for Q4; the
other words, R 1’s value determines the some experimentation to determine the value depends mainly on VS, on the load
time needed to “prime” the circuit to optimum value for R 1, but with C11 F current, and on Q4’s saturated current
make it ready to be latched on again. If R 1 and R 2470 k , the test circuit per- gain. The circuit provides an inexpensive
is too large, it becomes impossible to formed well with a value of approxi- way of deriving a latching function from
latch the circuit on soon after it has been mately 470 to 680 k  at VS1V and ap- a momentary pushbutton, and, like a me-
unlatched. On the other hand, if R 1 is too proximately 4.7 M at VS10V. chanical latching switch, the quiescent
small, it may impose an unacceptable Transistors Q1 to Q3 can be any small- (unlatched) current drain is zero.
Method provides overpower protection

for quasiresonant supplies
Nicolas Cyr, On Semiconductor, Toulouse, France
he main characteristic of qua- livered to the output obeys the following ciency. Because L P and  are fixed with a
T siresonant switch-mode power sup-

plies is that they exhibit a varying fre-
quency when the input voltage changes.
equation: POUT1/2(LPIP2FSW),
where LP is the primary inductance, IP is
the peak primary current, FSW is the
moving switching frequency FSW, IP has to
move in the opposite direction to main-
tain a constant output power. So, when
For a flyback power supply, the power de- switching frequency, and  is the effi- input voltage VIN rises, FSW increases; as
VIN
+
CBULK
VIN
LPRIM
LPRIM
VAUX VOUT VOUT
+
CBULK RVCC
LAUX LOUT RFWD LAUX LOUT
D2
+
CVCC D1
RDMG
CRES
CRES
8 7 6 5
RCOMP NCP1207
CS 1 2 3 4 RCOMP
RCS
RSENSE
(a)
CDMG RCS
Figure 1 RSENSE
The standard approach (a) for overpower protection is unac-

ceptable when you need low standby power; an approach
(b)
using a fraction of the input voltage (b) comes to the rescue.

design
ideas
a result, IP needs to decrease in ing to supply the controller and
response to the feedback-loop to detect the core-reset event.
requirements. For a widely By modifying the arrangement
varying line-voltage applica- of the winding, you can gener-
tion, the peak current almost ate the flyback information for
doubles between high and low the demagnetization detection
input voltages for a constant PMAX during off-time and combine,
output power. But quasireso- (W) on the same winding, the for-
nant controllers feature only ward information for the over-
overcurrent protection. This power compensation during
limitation is part of a structur- on-time. By adding a diode in
al problem. The controller series with the auxiliary wind-
monitors the peak current, ing, you can access the forward
and, when they reach the max- VIN (V) voltage (Figure 1b). This for-
imum allowed value, the ward voltage is proportional to
controller circuitry detects Figure 2 The output power rises to 165W without compen- NVIN, where N is the turns
an overload. Unfortunately, if sation but remains within 70W using the compensation scheme. ratio between the primary and
the power supply delivers its the auxiliary windings. You
nominal power at the lowest worst-case or you need to keep the pin impedance add R FWD to supply the reverse current
input voltage, it delivers more power for low for noise purposes, it forces you to during the forward activity.
a higher input voltage. For a widely vary- adopt a low value for resistor R CS in se- Knowing the value of the forward volt-
ing line-voltage application, this power ries with the current-sense information. age and the series resistor, R CS, you can
could be more than three times higher. It then requires a low-value compensa- then easily calculate the value of com-
This fact is the consequence of the flyback tion resistor, R COMP, wasting a lot of pow- pensation resistor R COMP to create the de-
equation. er. When you need low standby power, sired offset on the current-sense signal at
A classic way to compensate this vari- this approach is unacceptable. To over- high input voltage. On a demonstration
able-power effect is to create an offset on come the problem, it might be useful to board built on the NCP1207 from On
the current-sense pin that compensates use a fraction of the input voltage to low- Semiconductor (www.onsemi.com), D1
for the peak-current variations as a func- er the voltage drop on R COMP. The power is a 1N4448 diode,R CS680, R COMP18
tion of the input voltage, VIN. You obtain the resistor wastes would then become k , and R FWD4.7 k , the protection
this effect using an overpower-protection negligible. toggles at 60W at 100V dc and 70W at
scheme—wiring a compensation resistor You achieve this method by using the 365V dc, instead of 55W at 100V dc and
from the high-voltage rail to the current- forward voltage of an auxiliary winding. 165W at 365V dc without compensation
sense information (Figure 1a). Unfor- On a forward winding, a voltage propor- (Figure 2). Figure 3 shows circuit wave-
tunately, you cannot always implement tional to VIN occurs during the on-time, forms of the line compensation at
this scheme. Whether you use the CS which is the scenario you are looking for. VIN365V, and Figure 4 shows the wave-
(current-sense) pin for another function Usually, you use a flyback auxiliary wind- forms at VIN100V. 
: 400 mV COMPENSATION
COMPENSATION OFFSET=OV
OFFSET
1 CURRENT=
1 CURRENT= SENSE PIN VOLTAGE
SENSE PIN VOLTAGE
2 SENSE=
2 SENSE= RESISTOR VOLTAGE
RESISTOR VOLTAGE
3 COMPENSATION
3 COMPENSATION
VOLTAGE
VOLTAGE
4 DRAIN 4 DRAIN
VOLTAGE VOLTAGE
Figure 3 These waveforms represent line compensation Figure 4 A set of waveforms accompanies line compensation
at input voltage of 365V. at input voltage of 100V.

design
ideas
Circuit delivers dimming control
for white-LED driver
Wallace Ly, National Semiconductor, Santa Clara, CA
VDD
he demand for power in color cell-
T phone handsets is constantly increas-

ing. New applications steadily emerge,
making it imperative to reduce power
VDD
CS
1 F
+
consumption in the design. Exami- VIN1

nation of usage data shows that more Figure 3
VDD
than 50% of the power consumed is in VDD
providing backlighting for the color RPU BIAS – VOUT1
100k
screen. People use the phones for playing 50k +
TO LM2794/95
20k
games and MP-3s and a multitude of oth- SHUTDOWN BRGT PIN
er heavy-duty, multimedia functions. Fig- BYPASS
CB +
+ VOUT2
ure 1 shows the classic way to use a back- 50k
1 F
–
light-driver IC to provide dimming. By 20k
modulating an external PWM signal, the
VIN2
circuit controls the white-LED current.By VIH
VDD
adjusting the on/off-time ratio, or duty VIL

UP/DOWN
DIGITAL VOLUME
cycle, the circuit can provide drive rang- BASEBAND/
CLOCK
CONTROL
ing anywhere from full-on to full-off.This APPLICATION
PROCESSOR
circuit relies on the fact that the baseband
VIH
or application processor has a PWM
VIL
timer available. A second method of ob-
CLOCK
taining dimming is to use an adjustable
analog-input interface (Figure 2). The A headphone amplifier finds dual use in a white-LED dimming circuit.
drawback of this approach is that it re-
quires a DAC block in the digital-base- ward. The output of the LM4811 attach- the white-LED driver. The resultant ap-
band or application processor. es to the BRGT pin of the LM2794. The proach requires only two general-pur-
This Design Idea presents a more output current from the LM4811 is di- pose input/output lines, which are avail-
widely adaptable approach to the dim- rectly proportional to the digital value able in all modern baseband and
ming challenge. Although the LM4811 stored in the digital-volume-control application processors. Moreover, this
headphone amplifier is not designed to block. The rising edge of the clock, along method requires zero processor cycles
operate as a DAC, you can tweak it to do with the polarity of the Up/Down pin, once the LED current is set. The ap-
so. Figure 3 shows the dimming applica- sets the appropriate output current of the proach is therefore optimal for both soft-
tion. The implementation is straightfor- LM4811 and, thus, the output current of ware and hardware.
VIN POUT VIN POUT

CHOLD CHOLD
CIN 1 F CIN 1 F
D1 D1
1 F 1 F
C1+ C1+
C1 C1
1 F D2 1 F D2
LED1 LED1
C1– C1–
C2+ C2+
C2 D3 C2 D3
1 F LED2 1 F LED2
C2– C2–
3V
SD D4 0V BRGT D4
LED3 LED3
BRGT SD
LED4 LED4
GND ISET GND ISET
LM2794/95 RSET LM2794/95 RSET
Figure 1 In this classic LED-dimming configuration, an

Figure 2 This dimming circuit requires the existence of
external PWM signal varies the duty cycle of the driver. a DAC in the application processor.

design
ideas
System implements digital-clock modulation
Dan Doberstein, DKD Instruments, Nipomo, CA
n spread-spectrum and direct-se-
I quence receivers,it’s often necessary to

change the frequency of the clock os-
cillator, and thus the spreading-code
/20
ADVANCE
/19 /20 /21 /20
clock, to lock the receiver’s reference

pseudorandom-noise code to the incom-
RETARD
ing code. The original design used a
VCXO (voltage-controlled crystal oscil- NOTE: ADVANCE/RETARD PULSES TAKE EFFECT ON THE NEXT CYCLE, NOT THE CURRENT CYCLE.
lator) for this function, but this revised
design implements an all-digital method FCLK 23-BIT SHIFT REGISTER
1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 (RESET)
CLOCK
that provided additional functions, using 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
LOAD WITH
SINGLE ONE,
a midlevel CPLD from Altera (www.al- IN ALL OTHERS
ZEROS
tera.com). A commercially available part,
/19
SINGLE ONE
the 74HC297, provides the function.This ROTATES FOREVER /20
part is an all-digital PLL chip that most /21
DIVIDE-
engineers have never heard of. The MODULATED
SELECT
SWITCH
74HC297 can digitally modulate an ap- CLOCK OUTPUT
FOUT
plied clock. It performs this task by ADVANCE SWITCH-
CONTROL
adding or subtracting a pulse to or from RETARD LOGIC
a divided-down clock.
Upon examining the functions of this This scheme allows you to change the rate of the spreading-code clock
Figure 1
part, two issues emerge. First, it divides in spread-spectrum applications.
the input clock by two before modulat-
ing it. Second, the modulation method 19, 20, or 21. The choice of the tap points and FM on the applied clock, FCLK. The
inserts and subtracts pulses.Although the is a function of the target application’s tap numbers this design uses reflect those
pulse-addition/subtraction issue is ac- needs,although you can choose other tap that fit the target application. The target
ceptable, the divide-by-two function re- points. In operation,if the system detects application needs approximately 1-MHz
duces the phase/frequency-control reso- an Advance pulse, the switch selects the final output frequency with a phase res-
lution. With the inspiration of the divide-by-19 for one FOUT cycle.If the sys- olution of one-twentieth of a cycle, or the
74HC297 in mind, we sought a method tem detects a Retard pulse, the switch se- equivalent of 50 sec in the time domain.
that had finer resolution in phase and fre- lects divide-by-21 for one FOUT cycle. Af- If you need more phase resolution, in-
quency for the same applied clock fre- ter every Retard or Advance pulse, the crease the shift register’s length. For ex-
quency. At first, we tried discrete coun- system returns the selection switch to the ample, a 101-stage shift register with tap
ters using a digital switch to select divide-by-20 position. The single one, as points at 99,100, and 101 has a phase res-
different divide ratios. This approach it shifts through the register, effects the olution of approximately 3.6. The ad-
worked at low clock frequencies but setting and resetting of the switch. At vantages of the shift-register approach
failed as clock speed increased because of first, it appears that this system will mod- are speed and scalability. You can clock
propagation-delay effects at the switch. ulate the FCLK input in an FM-like fash- shift registers at extremely high speed.
Eventually, we devised a method that ion. But, on second thought, it also acts Additionally, the shift-register approach
used a long shift register and a tap-selec- as a phase modulator. On a single Ad- automatically provides you with clock
tion switch to implement a variable clock vance pulse, approximately one-twenti- signals that are exact advanced or delayed
divider/phase modulator. Figure 1 shows eth of an output cycle is subtracted, and versions of the primary tap used for FOUT.
the block diagram of the system. a single Retard pulse adds approximate- This feature is useful in creating precise
You load the 21-bit shift register with ly one-twentieth of an output cycle. If the phase-related signals. The feature also
a single one and the rest zeros. A switch- Advance or Retard pulses are continuous provides an advantage in the control of
selectable tap point feeds back to the shift streams at frequency FMOD, the output the switch function, so that you can man-
register’s input. In effect,a single one now frequency is FOUT(FCLKFMOD)/N, age propagation-delay issues.
goes around and around at a frequency, where N20 in this case, and the sign is Figure 2 shows the schematic in Al-
FOUT, determined by the tap point and the positive for Advance pulses and negative tera’s Max Plus II design software. This
applied clock, FCLK. The switch function for Retard pulses. software allows the use of standard logic-
allows selecting one of three divide ratios: So, this modulator can do both PM gate symbols in schematic format to cre-

design
ideas
INPUT
SYS_CLK
VCC VCC
CLRN
A B CLRN CLK CLK CLKIH STLD H G F E D C B A SER A B CLRN CLK
RESET_ INPUT
MODULATOR D Q SHIFT FIVE-CELL
74164 SHIFT 74165
REGISTER 74164
PRN QA QB QC QD QE QF QG QH REGISTER QHN QH QA QB QC QD QE
DFF
VCC
VCC VCC VCC
7474 7474 7474

AND2 1PRN 1PRN 1PRN INPUT
1D 1D 1D ADV_IN
1Q 1CLRN 1Q 1CLRN 1Q 1CLRN
1QN 1CLK 1QN 1CLK 1QN 1CLK NAND2
OR3 AND2 2Q 2PRN 2Q 2PRN 2Q 2PRN INPUT
AND2 2QN 2D 2QN 2D 2QN 2D RET_IN
OUTPUT
CLK_OUT 2CLRN 2CLRN 2CLRN
2CLK 2CLK 2CLK
AND2 D FLIP-FLOPS D FLIP-FLOPS D FLIP-FLOPS
7404
Figure 2
Altera’s software allows you to enter standard logic-gate symbols to create a programmed CPLD. (continued on pg 112)

design
ideas
ate a programming file for FOUT these flip-flops clear if Ad-
PHASE
the device. Although this de- vance/Retard pulses arrive si-
sign uses a CPLD, a discrete multaneously, an illegal input
version using digital-logic condition.
ICs, as the schematic shows, The second set of flip-flops
should also work. The FCLK captures the rising edges of the
input connects to all the shift Advance/Retard inputs. Subse-
register’s clock inputs. A Re- STEP=2/N quent rising edges are ignored
set function initializes the for a complete cycle of FOUT.
registers with a single one This set of flip-flops holds the
SLOPE=0
and the rest zeros. Using a state of the selection switch for
single flip-flop, FCLK samples SLOPE=0 2 NT MOD the next cycle of FOUT. After
the asynchronous reset signal SLOPE 2 NT MOD every cycle of FOUT, these flip-
to ensure synchronous oper- .......
TMOD 2TMOD 3TMOD 4TMOD
TIME flops reset to the divide-by-20
ation. Three sets of flip- state. The output of the third
flops prepare the Ad- set of flip-flops controls the
vance/Retard signal for Figure 3 The stair-step portions of this graphic show where AND/OR switch logic, which
use by the selection switch. phase is added to or subtracted from F OUT. selects the divide ratio for the
From the right-hand side of current cycle. As the single log-
Figure 2, the first set of flip-flops on the them for the next cycle of FOUT. We ic one shifts to the right,it first latches the
Advance and Retard inputs ensures that assumed that these signals would be selected switch position into the last set
these signals are synchronous with the fi- asynchronous with the input clock, FCLK. of flip-flops. This selection could be di-
nal output frequency, FOUT, and stores The NAND gate ensures that both of (continued on pg 116)

design
ideas
vide-by-19, -20,or -21, depending on the flip-flops, thus returning to the divide- point until the next cycle of FOUT. We pro-
Advance/Retard inputs. The AND/OR by-20 state. grammed the modulator into an Altera
gates now can select which tap point con- A propagation delay is inherent in the EPM7128-10 (10-nsec) device, and used
nects to the shift register’s input for that Advance/Retard control inputs. If you an input-clock frequency, FCLK, of 20
cycle of FOUT. After one more shift, the apply an Advance/Retard pulse, it will not MHz. When the divide-select switch is in
single logic one clears the second set of be applied to the selection of the tap the divide-by-20 state, it is easy to com-
pute the frequency output; it’s just the in-
put clock divided by 20.For an N-bit sys-
tem, it would be the input clock divided
by N. But how do you derive a general
formula for FOUT if Advance/Retard puls-
es arrive at a rate of FMOD? Whenever an
Advance or Return pulse is processed, a
fixed amount of time is added or sub-
tracted to the time between FOUT pulses.
You need an expression for the equiva-
lent amount of added or subtracted
phase—in other words, the phase step.
One complete cycle of FOUT with no
Advance/Retard modulation takes
N/FCLK seconds. This interval is just the
period of the output with no modula-
tion.If you add or subtract one clock pe-
riod, how much phase does this represent
with respect to FOUTN/FCLK? In terms of
the fraction of time that adding or sub-
tracting one clock period from the nom-
inal output cycle,you can write: Fraction
of one output cycle per Advance/Retard
pulse(clock period)/(nominal-output
period)(1/FCLK)(FCLK/N) cycles1/N
cycles.
Converting to radians and defining
this step as the phase step or STEP, 
STEP
2/N radians. Therefore, every
time an Advance or Retard pulse is
processed, the phase of the output
changes by 2/N radians. You can now
use the fact that frequency is the time de-
rivative of phase to derive the formula for
FOUT. Figure 3 shows a time plot of phase
of the output FOUT for the three possible
commands: Advance, Static (divide-by-
N), and Retard. In Figure 3, at first phase
is added, no change occurs in phase, and
then phase is subtracted. The frequency
is not changed where the slope is zero,
and is equal to FCLK/N. At the stair-step
portions of the plot, you can approxi-
mate the slope as  2/NTMOD. You can
interpret this figure as the change in the
output frequency (in radians). To convert
to cycles, divide by 2, which gives the
change in output frequency as FMOD/N
for Advance or Retard pulses arriving at
a rate of FMOD.

design
Edited by Bill Schweber
ideas The best of
design ideas
www.edn.com
Digitally control room light intensity

Donal McNamara, Analog Devices, Limerick, Ireland and
Kieran Kelly, Analog Devices, Limerick, Ireland.
any people favor different light which indicates the temperature of the
M and temperature settings for dif-

ferent rooms depending upon their
mood or whether they are working or re-
two zones.
On power-up, the PIC16C67 config-
ures its ports to control the LCD and the
Digitally control room light intensity ......103
Circuit tests V COM drivers ............................104
laxing. The circuit in Figure 1 controls ADT7516. The ADT7516 has a dual in- Use two picogate devices
the intensity of the artificial light in a terface, comprising I 2C and SPI, so the for bidirectional level-shifting....................106
room and monitors the temperature of master communicates in SPI mode. The Simple nanosecond-width pulse
two zones. The two main circuit blocks ADT7516 operates in SPI mode, once the generator provides high performance ..108
are the PIC16C67 master controller and controller initializes the LCD.
the ADT7516 temperature-sensor inter- The ADT7516 senses both its internal Accurately measure resistance with
face, which includes a four-channel ADC temperature and the temperature of a re- less-than-perfect components ..................110
and a quad voltage-output DAC. Other mote thermal diode (Q1 configured as a Publish your Design Idea in EDN . See the
components include a photodiode and diode), and the PIC16C67 displays these What’ s Up sect ion a t ww w.edn. com.
an op amp that monitor the ambient temperatures on the LCD. One of the
light; a rotary potentiometer that sets the ADT7516’s analog inputs monitors a po-
light intensity; an LED bar array and dis- tentiometer that you adjust to set the re- DAC value. The DAC controls an
play driver, which indicate the light-in- quired light intensity.The PIC controller LM3914 LED-bar-array controller that
tensity setting; a light-dimmer-control reads the potentiometer value from the shows the potentiometer setting on the
circuit; and a 16two-character LCD, ADT7516 and outputs a corresponding array. If you set the potentiometer half-
VDD
LED BAR
ARRAY
LM3914
20 1
LED1
Figure 1 VDD 19 2
LED2
18 3
LED3
A microcontroller, a temperature LED4
17 4
sensor with an A/D converter, and a 16 5

LED5
15 6
few other components form a smart GND LED6 14 7
LED7
room-light-intensity controller. LED8
13 8
VDD
12 9
LED9
11 10
LED10
6
VDD IC1 VOUTA 2 INPUT
DIMMER CIRCUITRY LAMP
ADT7516
VOUTB 1
5 MAINS SUPPLY
GND 400V
MOC3020
VOUTC 16 TR1AC
VDD 7
E D+/AIN1 /AIN1+ VOUTD 15
2N3908 B
Q1 8 PIC16C67 LCD
R2 EXTERNAL D–/AIN2 /AIN2–
13k TEMPERATURE 4
C CS PORT B6 PORT D
SENSOR
9
LDAC /AIN3 10
INTERRUPT
R1
R3 16TWO-
DIAL 1M 14 11 CHARACTER
10k AIN4 DOUT /ADD PORT B4
LCD
15V 12
SOA/DIN PORT B8 PORT B2
3
3 VREFIN 13 PORT B1
+ 7 PORT B7
SCL/SCLK PORT B0
IC2 5
2 _ OP07
4
D1
PHOTODIODE –15V
www.edn.com N o ve m b e r 1 1 , 2 0 0 4 | ed n 103

design
ideas
way, for example, then half of the LEDs troller uses the potentiometer and pho- any conversions during its operation; all
turn on, indicating that you want an in- todiode values, which the ADT7516 digit has to do is read back from four value
tensity that is half of what the light source itizes, to maintain equilibrium between registers and act according to its pro-
can deliver. the light intensity and the required light gram. This circuit ensures a constant light
A second DAC output controls a setting. If the photodiode reading is less intensity within a room, saving power
DIAC-based (X1) light-dimmer circuit. than the potentiometer setting, the con- when daylight takes over as the main light
This dimmer circuit operates like any troller increases the dimmer DAC value; source. It also extends the lifetime of a
other light dimmer, except that the DAC it decreases the dimmer DAC value if the light bulb, thus saving on maintenance
controls it instead of a potentiometer. A reading is greater. bills in a large office environment. You
photodiode monitors the intensity from One of the features of the ADT7516 is can also extend the application to include
the light bulb.An OP07 amplifies its out- its round-robin mode, in which it con- control of air conditioning and to mem-
put and feeds it into one of the stantly monitors all of its measurement orize heat and light settings that suit in-
ADT7516’s analog inputs. The PIC con- channels. The master need not initialize dividuals tastes.
Circuit tests VCOM drivers

Soufiane Bendaoud, Analog Devices, San Jose, CA
lat-panel LCD mon- use,such as NTSC, PAL, or
F
300
itors offer excellent SECAM. Computers, on
3k
image quality and the other hand, typically
8V
more compact form factor refresh the screen at a 75-
than CRTs—hence, their 2 _
Hz rate.A single picture el-
V
steadily increasing popu- 1k 10 10 10 10 ement, or pixel, on an LCD
AD8665
larity. Unfortunately, the 3
+ V+
screen comprises three
10 nF 10 nF 10 nF 10 nF
complexity of their manu- subpixels, one each of red,
facturing process makes 1k green, and blue.
LCD monitors consider- 0 TO 8V Electrically, the subpix-
SQUARE WAVE
ably more expensive than els behave like capacitors,
CRTs. The amplifier In this typical VCOM driver, an array of capacitors simulates the storing a certain voltage
Figure 1
that drives VCOM, the subpixel load. until the next voltage ar-
voltage on the backplane of rives. Changing the volt-
the LCD panel,must be able to drive large an amplifier used as a V COM driver. First, ages on the subpixels, one row at a time,
capacitive loads, deliver high peak output consider some video theory. Flat-panel refreshes the screen. These voltages use
currents,and maintain a constant output television screens differ in the rate at VCOM as a reference. The absolute value of
voltage. This Design Idea describes a which the screen refreshes. The refresh the voltage differences, VCOM, represents
simple test to measure the usefulness of rate for TVs depends on the standard you the brightness of the subpixels.The video
signal undergoes inversion
8V
on a frame-by-frame basis
8V
to ensure that the time av-
VOUT2 erage of the pixel voltages
R1
1 1 is zero, thus preventing
3 200 3 1 1
V1
2 2 2
3
2
3 IRF9521 screen burnout. The cir-
74HC00 C1
74HC00 74HC00 74HC00
cuit of Figure 1 tests the
100 pF
IRF4905 VCOM driver by applying a
square wave to a capacitor
8V IRF730 array representing the sub-
pixels in the panel. This
Figure 2 circuit simulates the worst-
VOUT1
1 case condition, in which all
1 3 1 the subpixels switch on or
3 2 3 IRF9521
2 2
74HC00
off simultaneously. A pair
74HC00
74HC00
MTP3055 of high-power, low-on-
resistance MOSFETs gen-
IRF730 erates the square wave.
An array of NAND gates drives power MOSFETs in this VCOM test circuit. A nonoverlapping drive
104 ed n | N o ve m b e r 1 1 , 2 0 0 4 www.edn.com

design
ideas
scheme ensures that both MOSFETs do uses high-speed NAND gates. An RC stage. Figure 3 shows the nonoverlap-
not turn on at the same time. Otherwise, network at the input of the second ping drive to the gates of the output
simultaneous conduction would give rise NAND gate controls the nonoverlap de- stage. Figure 4 shows the instantaneous
to high shoot-through currents. Figure lay. The first pair of MOSFETs acts as peak output current of the AD8565 in
2 shows the MOSFETs and the nonover- predrivers to provide the current needed Figure 1 in response to a pulse from the
lapping drive scheme. The drive scheme to drive the power-MOSFET output test circuit.
10V
VOUT2
5V
CH 2=100 nA/DIV
SEL>>
0V
V(R36:1)
10V
VOUT1
5V CH 1=5V/DIV
0V
0s 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
V(R37:1)
TIME (SEC)
TIME (2 SEC/DIV)
Figure 3 Figure 4
Nonoverlapping gate drive prevents large shoot-through The AD8565 exhibits peak currents greater
currents in the output stage of Figure 2’s circuit. than 250 mA in response to a test-circuit pulse.
Use two picogate devices

for bidirectional level-shifting
Bob Marshall, Philips Semiconductors
n new mixed-voltage systems, it is
I
VCC LOW
often necessary to level-shift a control
DIR
signal from a high level to a low level.
An open-drain device, such as the 1 7
74LVC1G07, easily performs this shift.
5
However, when a bidirectional signal re- I/O A 2 6 1 6 I/O B
quires level-shifting, it takes a bit more
LVC2G07
circuitry,because simply tying two open- LVC2G241
drain devices pins together generates just 3 5 4 3
a latch function. 2
The circuit in Figure 1 shows how to
4 8
connect the 74LVC2G241 and 74LVC-
2G07 devices together to shift the signal
at A from a high level to a low
Figure 1 VCC HIGH
voltage at B and to shift a low lev-
el at B to a higher level at A. The DIR sig- A two-IC circuit allows signal level-shifting in both directions; signal-flow direction is under circuit
nal controls the direction of the transfer. control.
When DIR is low, the A side is the input,
and the B side is output. When DIR is becomes the input to Pin 1 of the the 74LVC2G241, and the lowest voltage
high, B becomes the input, and A be- 74LVC2G07 and Pin 4 of the 74LVC2G07 level supply necessary should supply the
comes the output. To have B behave as an becomes the input to Pin 2 of the 74LVC2G07. For example, to shift a sig-
input when the DIR signal is low, redo the 74LVC2G241. nal from 3.3 to 1.8V, the 1.8VCC should
circuit so that Pin 3 of the 74LVC2G241 The highest voltage VCC should supply supply the 74LVC2G07 device. The size

design
ideas
of the pullup resistor is unimportant, tor could be as low as 150. It should be lower when driving a 4-mA load. The
but, for best speed, it should be as small as large as possible to reduce power con- 74LVC2G07 and 74LVC2G241 provide a
as practical to reduce the RC change time sumption. quick and easy way to obtain a bidirec-
of the output signal of the 74LVC2G07. The 74LVC2G07 supply level deter- tional level translation and take up little
The current output of the74LVC07A is 24 mines VOL and VOH at B. At 1.8V, the VOH board space. 
mA at 3.3V; at that VCC, the pullup resis- would be near V CC, and VOL is 0.45V or
Simple nanosecond-width pulse generator

provides high performance
Jim Williams, Linear Technology Corp
f you need to produce extremely fast Comparators IC2 and IC3, arranged as
I pulses in response to an input and trig-

ger,such as for sampling applications,
the predictably programmable short-
A=5V/01V
complementary-output-level detectors,
represent the networks’delay difference as
edge-timing skew. Trace B is IC3’s fixed-
time-interval generator has broad uses. B=5V/01V path output, and Trace C is IC2’s variable
The circuit of Figure 1, built around a output.Gate G1’s output (Trace D), which
C=5V/01V
quad high-speed comparator and a high- is high during IC2-IC3 positive overlap,
speed gate, has settable 0- to 10-nsec out- D=5V/01V presents the circuit output pulse. Figure 2
put width with 520-psec, 5V transitions. shows a 5V, 5-nsec width, measured at
Pulse width varies less than 100 psec with 50% amplitude, output pulse with
5V supply variations of 65%. The mini- 10nSEC/DIV R 390. The pulse is clean and has well-
mum input-trigger width is 30 nsec, and defined transitions. Post-transition aber-
input-output delay is 18 nsec. Pulse-generator wave- rations, within 8%, derive from G1’s
Figure 2
Comparator IC1 inverts the input forms, viewed in 400-MHz bond-wire inductance and an imperfect
pulse (Figure 2, Trace A) and isolates the real-time bandwidth, include input (Trace A),
50 termination.IC1’s output drives fixed IC3 (Trace B) fixed and IC2 (Trace C) variable
and variable RC networks. Programming outputs and output pulse (Trace D). RC net-
resistor R G primarily determines the networks differential delay manifests as IC2-IC3
1V/DIV
works’charge-time difference and, hence, positive overlap. G1 extracts this interval and
delay at a scale factor of approx 80/nsec. presents circuit output.
1/4 LT1721 2nSEC/DIV

INPUT 510
_
R0.8 /nSEC 1/4 LT1721 The 5-nsec-wide output with
IC1 + Figure 3
50 +
COMPARATOR R390 is clean with well-
VARIABLE 8 pF IC2
DELAY _
G1 defined transitions. Post-transition aberrations
74AHCO8
are within 8% and derive from G1 bond-wire
TO 2.5V 0.1 F AND
2.5V GATE inductance and an imperfect coaxial probe path.
DIFFERENTIAL OUTPUT
1k 1k
DELAY 5V
GENERATOR
+ 1/4 LT1721
IC3 1V/DIV
620
_
FIXED 8 pF
Figure 1 DELAY
200pSEC/DIV
This pulse generator has 0- to 10-nsec width and 520-psec transitions. IC 1 unloads termina- The narrowest amplitude
Figure 4
tion and drives the differential delay network. The IC 2-IC3 complementary outputs represent pulse width is 1 nsec, and
delay difference as edge timing skew. G 1, which is high during IC2-IC3’s positive overlap, the base width measures 1.7 nsec.
presents circuit output. Measurement bandwidth is 3.9 GHz.

design
ideas
coaxial probing path. Figure 3 shows the
narrowest full amplitude, 5V pulse avail-
able. Width measures 1 nsec at the 50%
amplitude point and 1.7 nsec at the base
in a 3.9-GHz bandwidth. Shorter widths 1V/DIV 1V/DIV
are available if partial amplitude pulses
are acceptable. Figure 4 shows a 3.3V,
700-psec width (50%) with a 1.25-nsec
base. G1’s rise time limits minimum
achievable pulse width. The partial-am- 500 pSEC/DIV 200 pSEC/DIV
plitude pulse, 3.3V high, measures 700
psec with a 1.25-nsec base (Figure 5). Fig- The partial-amplitude A transition detail in
Figure 5 Figure 6
ure 6, taken in a 3.9-GHz sampled band- pulse, 3.3V high, meas- the 3.9-GHz bandpass
pass, measures 520-psec rise time. Fall ures 700 psec wide with a 1.25-nsec base. The with rise time of 90 psec shows 520-psec rise
time is similar.The transition of the probe trace granularity is an artifact of the 3.9-GHz- time; fall time is similar. The granularity
edge is well-defined and free of artifacts. sampling-oscilloscope operation. derives from sampling-oscilloscope operation.
Accurately measure resistance

with less-than-perfect components
Dave Van Ess, Cypress Semiconductor
or transducers, such as current, you need do no math, so
F strain gauges or thermistors,

you must accurately and in-
expensively measure resistance us-
VREF
RREF
VRESPONSE
BUFFER ADC
this method was popular when the
cost of computation was more than
the cost of building an accurate
ing circuitry built with imperfect RT current source. However, the accu-
components and in which racy of the current source directly
Figure 1
gain and offset errors can limits the accuracy of the reading
significantly limit the accuracy of The resistive-divider topology provides a lower cost alterna- and any gain or offset errors from
ohmic measurements. The right tive to a current source and a precision resistor for calibration. measuring the response voltage off-
circuit topology makes it possible sets the accuracy, as well.Addition-
to eliminate most error terms while sistance, requires a stimulus.One method ally, the range of measurement is limited
measuring ohms, leaving the accuracy to of measuring resistance is to force a to the ADC’s signal range, as the follow-
be determined by just a single reference known current through a resistor and ing equation shows:
resistor. measure the voltage across the resistor.
Unlike measuring voltage or current, Measuring ohms in this way means that,
measuring a passive attribute, such as re- with the correct selection of stimulus
V0
VREF+
V0 VREF+
.... RREF3 RREF2 RREF1

RREF
V1 BUFFER
12-BIT ADC
G=0.94
RT
.... RT3 R T2 RT1
V2 VREF
VREF
V2
Figure 2 Figure 3
Remove most gain and offset errors using two measurements Extend the idea to handle multiple sensors and signal paths, using
and a ratio calculation. multiplexing through a single buffer and A/D converter.

design
ideas
With the development of more pow- offset error, which can be the largest con- plex to a single buffer and A/D convert-
erful microcontrollers and on-chip ra- tributor of error to the overall accuracy. er, and the eight analog pins let you
tiometric ADCs, a resistor-divider block Using more expensive and precise com- measure as many as six transducers (Fig-
architecture (Figure 2) provides a less ex- ponents reduces the offset error of any op ure 3). Alternatively, you could connect
pensive approach: amps in the measurement path. each of four sense paths to its own buffer
Figure 2 shows how to significantly re- and converter.
move gain and offset errors, in which Listing 1 at the Web version of this De-
subtracting two measured voltages re- sign Idea at www.edn.com shows how
This architecture has a theoretical moves any offset errors in the measure- you implement the circuit of Figure 2 us-
range of measurement from short circuit ment system: ing a programmable analog system-on-
to open circuit, but any offset error from chip controller. It uses the ADCINC12
measuring the response voltage limits the user module, programmable-gain-ad-
actual range; the reference resistance lim- justment user module, and two analog
its overall accuracy and any gain and off- The ratio of these two difference val- output buffers. Placing the analog block
set errors from measuring the response ues removes any measurement-path gain of the ADCINC12 just below the buffer
voltage. error, leaving the reference resistance to and setting the clock for the ADCINC12
The cost of the reference resistor de- determine the measurement error. This to 167 kHz for a sample rate of 10 sam-
termines the error that the reference re- result is valid as long as the measured sig- ples/sec remove any 50- or 60-Hz inter-
sistor introduces, and you derive the sup- nal is never outside the range of the A/D ference from the signal. Increase the sam-
ply voltage, VCC, from the reference converter. To guarantee this condition, ple rate if the application requires a faster
voltage, VREF. The gain error of a ratio- set the sense buffer gain to slightly less conversion. The control software is in C;
metric ADC is generally small and does than unity. the program calculates the resistance
not contribute much to the overall error, You can also measure multiple resis- reading and leaves it in a global memory
but this situation is not the case for the tors, in which all the sense paths multi- location.

design
Edited by Brad Thompson
ideas The best of
design ideas
www.edn.com
Quickly find pc-board shorts

with low-cost tracer technique
Teno P Cipri, Engineering Expressions Consulting
predominant failure mechanism
A
CURRENT PATH
for production pc boards is shorted
traces. Finding hidden shorts is of-
ten time-consuming and frustrating.
Typical techniques of cutting traces, lift-
ing pads, and “blowing” shorts are, at NO VOLTAGE DROP
best, questionable because they may af- TRACE A
fect the reliability of the circuit, and the
ever-decreasing geometries and lower NODE 1 NODE 2
SHORT
NODE 3 NODE 4
voltage ICs make these practices tricky
and risky. High-end, four-wire DMMs TRACE B NODE 7 NODE 6 NODE 5
(digital multimeters) or ohmmeters,
which can accurately measure the small
NO VOLTAGE DROP LOWEST VOLTAGE DROP
resistance values, are expensive
Figure 1
and sometimes not available on a
designer’s bench. By applying a fixed current to various nodes and looking at the resultant voltage drops, you can
An inexpensive alternative approach home in on the likely location of a pc-board short circuit.
for finding short circuits, using the con-
cepts of four-wire DMMs and ohmme- Most digital buses have at least 1 over keep the battery from depleting when the
ters is simple and requires only the tools the length of the run, but a trace imped- circuit is not in use.
you already have on your bench and a ba- ance of only 200 m still has a 2-mV A node can be any accessible part of the
sic understanding of Ohm’s Law. This ap- drop with 10-mA current applied. Most circuit path under test, such as a via, a
proach uses the principal that all con- lab-grade handheld DMMs can easily re- pad, or a test point (Figure 1). Note the
ductors have resistance properties, and a solve to 1 mV. Because you are looking for current path: When current is flowing be-
distinct voltage drop exists between the relative values, the absolute accuracy of tween two nodes, a minute voltage drop
various nodes in the shorted circuit.This the instrument isn’t critical. However, the occurs across the two nodes. When the
approach systematically locates the nodes current must be constant to achieve re- current doesn’t flow between two nodes,
with lowest impendence between them peatable results, and you must isolate its there is no voltage drop across those
and isolates the fault to two nodes. current source from the ground of the nodes.
circuit under test. To find the short in this example, put
A 1.5V battery in series with a 1.5-k  one DMM probe on any node on Trace
Quickly find pc-board shorts
resistor is an adequate current source for A and the other on any node on Trace B,
with low-cost tracer technique....................97
this purpose. The battery provides the and note the voltage drop. In this exam-
Read isolated digital signals isolation and relatively constant voltage; ple, if you had started with the positive
without power drain......................................98 select the resistor to source around 10 probe on Node 1 and the negative probe
MOSFET shunt regulator mA. (For lower impedance traces, such as on Node 5 and moved the negative probe
substitutes for series regulator ................100 power-supply lines, or in situations in to Node 6, you would note a slight volt-
which the DMM lacks millivolt resolu- age drop. Next, you move the probe to
Zener test circuit serves
tion, use a higher current.) An optional Node 7 and note that the voltage drop is
as dc source..................................................104
clamping diode, with a cathode connect- equivalent to the voltage drop at Node 6.
Gain-programmable circuit ed to the battery’s negative terminal and From this test, you can deduce that the
offers performance and flexibility............106 an anode connected to the resistor’s free short must exist between nodes 5 and 6
Publish your Design Idea in EDN . See the end, provides protection for low-voltage because no current flows from Node 6 to
What’ s Up sect ion a t ww w.edn. com. logic circuits. If you use the diode, you Node 7.Then, move the positive probe to
may also need to add a power switch to Node 2 and note a small voltage drop.
www.edn.com N o ve m b e r 25 , 2 0 0 4 | ed n 97

design
ideas
Continue down the line to Node NODE 5 NODE 6 NODE 7
source is connected to any node on
3 and note another small drop. Trace A and the other side of the
TRACE A
Next, probe Node 4 and note current source is connected to any
there is no voltage node on Trace B.
drop. You can now Figure 2 SHORT In this example, the short is be-
deduce that the short must be between two node pairs,and you can
tween nodes 2 and 3 and nodes isolate the short only to those
TRACE B
5 and 6. pairs. A little knowledge of the
Redrawing Figure 1 with the NODE 1 NODE 2 NODE 3 NODE 4 board layout and common sense
equivalent circuit in Figure 2 now come into play. You need to
makes clear how this technique The equivalent circuit of the pc-board layout shows the principal know only where the two traces
works. You are now looking at a of the source-and-probe technique. are adjacent between nodes 5 and
simple series network of resistors 6 and nodes 2 and 3,and you have
and looking for voltage drops across any not flowing). When current is flowing, found the most likely place for the short.
resistor that has current flowing through the short is farther from the current If it is underneath a component,you have
it. When a node is outside the current source. If no current is flowing, then the to remove the component; removing the
path, no voltage drop occurs. By under- short is closer to the current source. This component often removes the short. If
standing the relationship of each of the two-valued logic makes it simple to iso- the short is on an internal layer, you may
vias and their position in the current late the problem.The beauty of this tech- have to do some selective cutting and
path, you can systematically isolate the nique is that it doesn’t matter to which jumping to isolate the short from the
short by looking for lower voltage (cur- two nodes the current source is connect- traces, but at least you minimize the
rent flowing) or higher voltage (current ed, as long as one side of the current number of cuts on the board.
Read isolated digital signals without power drain

Alfredo H Saab and Joseph Neubauer, Maxim Integrated Products Inc, Sunnyvale, CA
lthough optocouplers offer de-
A
ISOLATION
signers a straightforward method of SENSE_CLK MAX5048 BARRIER
T1
establishing galvanic isolation be- IC1
R1
tween circuits that operate at different W1 W3
1k
ONE ONE
ground potentials, they do not provide an TURN TURN
1/4 74HC132
ideal approach. An optocoupler draws C1 Q1
power from the isolated circuit, switches 50 pF IC2 W2 W4 2N7000
R2 ONE
relatively slowly, and loses current-trans- 1k TURN
ONE
TURN DATA_IN
fer ratio as its light emitter ages.
20 pF
The circuit in Figure 1 overcomes T2
IC2
these limitations by replicating a digital C2 ISO_COMMON
signal’s state, drawing no power from the 1/4 74HC132
isolated input, and consuming only
modest power on the nonisolated side.
_
As Figure 2 shows, the circuit imposes DATA_OUT C3
LE IC 0.1 F
only a 20-nsec input-to-output delay 3
+
from the positive edge of SENSE_CLK to MAX913
DATA_OUT. R4
Figure 1 R3
MOSFET transistor Q1 oper- 3.3k 1.5k
5V
ates in either of two states—high resist-
ance between source and drain (R DS/OFF),
or low resistance (R DS(ON)) when a control
signal drives Q1 into conduction. When You can use a simple ferrite-bead transformer to isolate logic-level signals.
conducting, Q1 imposes a low resistance
across T1’s secondary winding, W3. The puts of MOSFET-driver IC1 differentiate end of winding W1. Figure 2 shows the
remainder of the circuit senses the state the SENSE_CLK signal’s positive-going relationship among the circuit’s signals.
of T1’s secondary resistance. Resistor R 1, input edge, producing a positive-going Connected in series-aiding mode, the
capacitor C1, and the complementary in- 5V pulse at IC1’s output and driving one two primary windings W1 and W2 of T1
98 ed n | N o ve m b e r 25 , 2 0 0 4 www.edn.com

design
ideas
form a 2-to-1 inductive volt- 1V/DIV
and R 4 set IC3’s trigger-volt-
age divider whose center tap age threshold. Transformer
drives the inverting input of SENSE_CLK T1 provides a 1-to-1-to-1
IC3, a high-speed compara- 0 turns ratio and comprises a
tor. With Q1 off and thus pre- MAX5048
single-hole ferrite bead
senting an open circuit OUTPUT (Fair-Rite part number
0
across the secondary of T1, 2673000101) with three
the junction of windings W1 identical single-turn wind-
MAX913- INPUT
and W2 applies a pulse of ap- ings. To minimize stray in-
0
proximately 2.5V to com- ductance, keep the connec-
parator IC3’s inverting input tion to the junction of
and drives IC3’s internal state MAX913 LE windings W1, W2, and IC1 as
low. Meanwhile, IC2’s two 0 short as possible. Also, the
gates, resistor R 2 and capaci- grounded end of W2 should
DATA_IN
tor C2 generate a short strobe return to IC1’s ground con-
pulse in the middle of IC1’s 0 nection.
output pulse and applied to The circuit’s isolation ca-
DATA_OUT
IC3’s LE (latch-enable) input. pabilities depend on its pc-
0
Latching IC3’s internal board layout and the prop-
50 nSEC/DIV
state to its external output erties of transformer T1,
(DATA_OUT) produces whose type 73 ferrite core is
Figure 2 Each positive-going transition of SENSE_CLK transfers the
a logic-low output that moderately conductive.
follows DATA_IN. If DATA_ state of the galvanically isolated digital signal at DATA_IN to DATA_OUT. Thus, T1’s isolation proper-
IN goes sufficiently positive ties depend on its windings’
to bias Q1 on, Q1’s low resistance across ing pulse at LE forces IC3’s DATA_OUT insulation. For example, Teflon or Kap-
W3 reflects a low impedance to windings high, again following the state of ton-insulated wire can withstand sever-
W1 and W2 of T1. The reduced pulse am- DATA_IN. al kilovolts. If you carefully construct T1
plitude at the junction of W1 and W2 and IC1, IC2, and IC3 operate from a single using the specified core and Teflon-in-
IC3’s inverting input of approximately 5V power supply. Separate bypass capac- sulated AWG #24 wire, the transformer
0.5V is insufficient to trigger IC3,, and itors placed adjacent to each device’s can exhibit interwinding capacitances of
IC3’s internal state goes high. The latch- power pins minimize noise. Resistors R 3 0.2 pF or less.
MOSFET shunt regulator substitutes

for series regulator
Stuart R Michaels, SRM Consulting
ou would normally use a series lin- has a threshold voltage of 2 to 4V at 250 at 50 mA. Because you operate the MOS-
Y ear regulator or a dc/dc converter to

obtain 3V dc from a higher supply.
However, when breadboarding a concept,
A. The upper curve of Figure 2 shows FET at or near threshold, its on-resistance
that the IRF521 achieves a gate-to-source spec doesn’t apply, and the output im-
voltage of 3V at a current of about 200 pedance of this circuit is far higher than
you may be able to use a shunt regulator, A. MOSFETs can vary from device to you would expect from the on-resistance.
especially if a series regulator of the cor- device, but the typical MOSFET has a However, in general, the lower the on-re-
rect voltage is unavailable. The MOSFET threshold at approximately the mean be- sistance, the lower the output impedance
in Figure 1 can replace a zener diode in a tween the maximum and the minimum at a specific current near threshold.
shunt regulator and provide lower output limits. This circuit may require that R 2 and C1
impedance than a zener diode. The lower curve in Figure 2 is the out- stop the oscillation in the MOSFET. Add
The MOSFET is self-biased by con- put impedance, which you obtain from a filter capacitor to the output to mini-
necting its drain to its source. The differ- the upper curve by differentiating the mize the effect of load transients. Con-
ence between the input voltage and the upper curve. Although the output im- necting a large filter capacitor from the
gate-to-source threshold voltage,VGS,sets pedance, R OUT, is near 800 at a current gate to the source with short leads elim-
the current. The IRF521 in this example of 100 A, it rapidly drops to less than 6 inates the need for R 2. You can use other

design
ideas
VIN
R1
GATE-TO-SOURCE THRESHOLD VOLTAGE
VOUT VGS (V)

ROUT (k)
S
R2
100
G
IRF521
C1
0.1 F
OUTPUT IMPEDANCE
ID (A)
A MOSFET configured to
Figure 1 Figure 2
replace a zener diode of a
shunt regulator provides lower impedance
edn041111di35301 DIANE A plot of key parameters—gate-to-source voltage and output impedance—versus drain current
than a diode-based implementation. shows smoothness of variation over two and one-half decades.
MOSFET families and other voltages if wide variations in operating voltage. For ative-temperature coefficient of the gate-
necessary. instance,many 3.3V-dc microcontrollers to-source voltage. This circuit has signif-
Although you may be unable to get the can operate as low as 2.5V dc and as high icant change in output voltage over a
exact output voltage you need at the cur- as 3.6V dc. Note that operating a MOS- wide temperature range; it is suitable for
rent you prefer, many devices tolerate FET near its threshold causes a large neg- only limited temperature ranges.
Zener test circuit serves as dc source

John Jardine, JJ Designs, West Yorkshire, UK
his Design Idea describes a versa-
T tile test circuit for zener diodes after

yet another misread zener diode had
infiltrated the ranks of 1N4148 diodes 2.1V
FULL LOAD
100V 5V
B
100V
A
AT IDC 2A

assembled on a pc board.As a bonus, the L1 330 F

0V D3 OUTPUT
circuit can serve as a moderate-voltage, 10 TO 110 kHz
BA157 NOMINAL
E1 100V AT 10 mA
power-limited adjustable dc source. Al-
E2
though conventional multimeters’resist- 4.7V
2.7V R6
ance ranges typically apply enough volt- R1 R2 C1 2.2
47k 47k IN5617GP 1W
age to forward-bias most diodes, few can 47 pF
Q1 C3 MAXIMUM
IC1 FET (LOGIC) LOAD
drive a zener diode into reverse conduc- 74HC132 (1/4) R5 0.3, 200V 1 F
1 100k 2SK2350 150V
tion. Figure 1a shows a simple variable- 3
2
frequency dc/dc step-up converter whose D2
R3
output voltage depends on the device 10k IN4148
A
under test’s breakdown voltage. D1 5V 15V
R4 0V B 50k
Upon power application, Pin 3 of IC1 4.7V
100k
IN750
(one section of a 74HC132 quad dual-in- C2
put Schmitt-trigger NAND gate) goes to 10 nF LOGIC ONE WHEN VARIABLE
22 TO 110V
UNIT IS RUNNING
logic one and switches on Q1, an N-chan- OUTPUT
nel logic-level power MOSFET. Current

(b)
flows through Q1 and R 6 and stores en- (a)
ergy in inductor L1’s magnetic field. The output voltage of a simple variable-frequency dc/dc step-up converter depends
Figure 1
Zener diode D1 limits the voltage at on the device under test’s breakdown voltage (a). To use the circuit as a variable
IC1’s Pin 1 to 4.7V. Simultaneously, diode medium-voltage power supply, replace the device under test with a network (b).

design
ideas
D2 and resistor R 3 charge C2 and establish 4.7V—plus the forward voltage across power supply and 430 mA of input cur-
a logic one at IC1’s Pin 2. When the volt- D3—0.7V. Thus, for a 100V zener as the rent, the circuit delivers 10 mA at 100V
age at point E1 reaches approximately device under test, the voltage at E2 meas- for a 100V output, yielding an efficiency
2.7V, IC1’s input-voltage threshold, IC1’s ures approximately 105.4V. of approximately 50%. Feeding L1 from a
output goes to logic zero, switching off At start-up and under fault conditions, separate 12V power supply improves ef-
Q 1. resistor R 4, diode D2, and resistor R 3 pro- ficiency.
Energy stored in L1’s magnetic field duce an asymmetrical oscillation at ap- If you design your own inductor for L1,
discharges through fast-recovery diode proximately 2 kHz, which reduces the av- aim for a nominal inductance of 330 H
D3 and charges C3. Capacitor C1 helps re- erage current through L1 and Q1 to a safe at 2A and a dc winding resistance of less
move diode D1’s stored charge and helps level. than 0.5. For optimum operation, use
restart the charging cycle. To use the circuit as a variable medi- a fast-recovery diode for D3 and a logic-
After several cycles, the voltage at E2 um-voltage power supply, replace the de- level N-channel MOSFET with a break-
reaches the device under test’s reverse- vice under test with the network in Fig- down voltage of 200V or greater and an
breakdown voltage and feeds current via ure 1b. Adjusting the potentiometer on-resistance of less than 0.3 for Q1,.
R 1 to IC1’s Pin 1. As a result, the voltage varies the voltage at point E2 from 22 to Note that zener-diode manufacturers
at E 2 stabilizes at the sum of the device 120V. Maximum current available from specify breakdown voltages at specific
under test’s reverse-breakdown voltage the circuit depends on the dc resistance, test currents. Also, when you subject
and a constant offset voltage of 5.4V L1’s magnetic-saturation characteristics, them to high reverse voltages, signal
comprising the voltage across D1— and Q1’s on-resistance. For a nominal 5V diodes exhibit zener behavior.
Gain-programmable circuit
offers performance and flexibility
Luo Bencheng, Key Laboratory of Mental Health, Institute of Psychology,
Chinese Academy of Sciences
ou can use a standard precision in- pins Z0 to Z2 of IC2 R1
Y strumentation amplifier, such as the with a microcontroller

INA118 or AD623, as a gain-pro- to provide self-ad-
grammable amplifier with high accura- justable gain according
GAIN
SELECT
(VIA MICRO-
CONTROLLER)
B
A
C
R2
R3
cy and wide gain range. However, the gain to the selected weight- R4
range of such parts is fixed at certain val- ing resistor. Unfortu- K
R5
ues, limiting their flexibility. To solve the nately, the perform- IC2
problem, a usual way is to use a gain-ad- ance and quality of the R6
justable circuit controlled by a micro- circuit cannot provide R7

computer (Figure 1). good performance and
R8
IC2 is a programmable 1-of-8 analogy high quality due to the V
multiplexer that connects to eight on-resistance of IC2,
R0
weighting resistors, R 1 to R 8, to improve which you also cannot VIN _
the gain range of the circuit based on IC2, control, especially as IC1
VOUT
OP27
a general-purpose precision amplifier. the tempera- +
Figure 1
The overall gain of the circuit depends on ture changes.
R
the value of the selected weighting resis- The modified gain-
V
tor, as follows: adjustable amplifier
circuit in Figure 2 uses
the same IC1 but A basic gain-programmable amplifier circuit uses digital outputs
changes IC2 to a pro- from a microcontroller to set gain.
grammable 2-of-8 dif-
where R ON is the on-resistance of IC2,and ference-input analog multiplexer, which to R G8, to improve the gain range of the
R X is one of the selected weighting resis- connects to four balancing resistors, R 01 circuit. By controlling the port-select pins
tors, R 1 to R 8. You control the port-select to R 04, and eight weighting resistors, R G1 Z0 to Z1 ofIC2 with a microcontroller,the

design
ideas
circuit provides self-adjustable gain V
R01
with high quality. The overall gain of the K1
circuit is: R02
VIN +
IC01 R03
_ V
R04
V +
where R GA is one of the selected weight-
VOUT
ing resistors, R G1 to R G4, and R GB is one _
of the selected weighting resistors, R G6 RG1
to R G8. V
Analog multiplexer IC2 is on the in- RG2 V
K2
put side of amplifier IC1. Resistors R 01 to _ RG3
R 04 balance the signal-input channel to IC02 RG4
decrease the level-shifting because of
+
the on-resistance of multiplexer IC2 and C A
minimize the effect of that resistance. GAIN
RG5 RG6 RG7 RG8
Additionally, two operational ampli- V SELECT
fiers, IC01 and IC02, act as follow-
ers to improve the overall driver Figure 2
performance and common-mode-re-
jection capacity of the circuit. The modified circuit provides more flexibility, along with high performance.

design
ideas The best of
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Dual-output nonisolated SMPS powers appliances

Fabio Cacciotto, STMicroelectronics, Catania, Italy
odern appliances offer a range of chip SMPS controller, such as STMicro-
M features that rely heavily on mi-

crocontrollers and auxiliary cir-
cuits. Although conventional iron-core
electronics’ Viper22A, IC1, to derive as
much as 3.3W of regulated dual-voltage
power over an ac line-voltage range of 88
Dual-output nonisolated SMPS
powers appliances ........................................99
High-voltage amplifier
drives piezo tubes........................................100
transformers can provide ac line-isolat- to 265V ac (Figure 1). For the values in
ed, low-voltage power for a microproces- the figure, this circuit delivers 5V5% Phone wire, RJ-11 jacks and
optocouplers build a bus ..........................101
sor, coupling the processor’s control sig- at currents as high as 300 mA and
nals to line-side power switches requires 12V 10% at currents as high as 150 Use a PC’s parallel port
to program a clock source ........................102
yet another layer of electrical isolation, mA.
such as optocouplers or pulse trans- The Viper22A’s internal circuitry in- Constant-on-time buck-boost regulator
converts a positive input
formers. cludes a 60-kHz clock oscillator, a voltage
to a negative output ..................................104
Designers can avoid the complexity reference, overtemperature protection,
Rainbow LED indicates
and expense of adding isolation compo- and a high-voltage power MOSFET that
voltage with color........................................106
nents by powering the microcontroller can provide several watts of power. Al-
and its auxiliary circuits from the non- though the Viper22A occupies an eight- Publish your Design Idea in EDN . See the
isolated ac line. An offline SMPS lead package, operating requires only
(switched-mode power supply) can eas- four connections: operating power, VDD;
ily produce a single low voltage, but ob- feedback, FB; and the MOSFET’s source and doubles as a protective fuse.Diode D1
taining multiple voltages can prove more and drain. The remainder of the pins, re- rectifies the ac line voltage, providing ap-
challenging and require a relatively com- dundant source and drain connections, proximately 160V dc to a filter compris-
plicated design. help dissipate heat into the pc board. ing C1, R 1, L1, and C2. In addition to
As an alternative, you can use a single- Resistor R 4 limits input surge current smoothing dc ripple, the filter reduces
C9
R1
100 nF 1.2k
R4 IC1
AC IN 22 VIPER22A
L1
D1
470 H
1N4007 D3
STTH106
D2
D7
VDD DRAIN STTH106
6.8V
+ + C5
C3 FB
CONTROL 0.47 F
10 F
C4
D4
Figure 1 22 nF SOURCE VOUT1
STTH106 –12V DC
1 C7
This offline
56 TURNS 220 F
C1 D5 +
SMPS controller +
VOUT2
100 nF C2 STTH102
–5V DC
delivers dual 22 F L2
2
output voltages. 420 H TOTAL PINS 1 TO 3 D6

4.3V
49 TURNS
3 Q1 R5
C6 C8 4.7k
+ 4.7 F + 470 F
R2 R3
22 68
AC IN
COMMON
www.edn.com D e c em b e r 7, 2 0 0 4 | ed n 99

design
ideas
electromagnetic interference to help magnitude of the maximum regulated dc To avoid high-frequency instability in the
achieve compliance with EU standard output voltage, so use a fast-recovery compensation loop, keep connections to
55014 CISPR14. Snubber capacitor C9 diode rated for 600V peak-inverse volt- ceramic capacitor C4 as short as possible.
across D1 helps further reduce conduct- age for D3. Inductor L2 comprises a TDK SRW0913
ed emissions. The voltage at VOUT2 provides feedback ferrite drum core with two windings
Reservoir capacitor C3 acquires a pos- to close the regulation loop. The sum of whose turns ratio sets the output voltage
itive charge via diode D3 during the general-purpose PNP transistor Q1’s at V OUT1 . To maintain regulation when
MOSFET’s off-time and supplies VDD to base-emitter voltage plus D6’s reverse VOUT1 is unloaded and VOUT2 is fully
IC1 during the MOSFET’s on-time. Re- voltage sets VOUT2 at 5V. Zener diode D7 loaded, add bleeder resistor R 5 from
verse voltage across D3 can reach the sum shifts the voltage at IC1’s feedback input VOUT1 to common ground.
of the peak rectified line voltage plus the terminal into its linear range (0 to 1V).
High-voltage amplifier drives piezo tubes

Bipin Duggal, Netaji Subhas Institute of Technology, New Delhi, India
R9
iezoelectric tubular positioners
P
20k
that drive manipulators in scanning D2 VCC
tunneling microscopes require 1N4148
high-voltage, low-current drive circuits.

The circuit in Figure 1 can drive high-re-
Q4 MJE340
Q3
sistance, low-capacitance piezo- D1
electric loads at a 3-dB band- F i g u r e 1 1N4148 MJE350 MJE350 Q1
12V
width of 6 kHz. It offers a low-cost R4
R8 R3
alternative to commercial drivers. Tran- 1k 4 1M
10k
VIN 2 _ MJE350 OUTPUT
sistors Q3 and Q4 form a current mirror, 1
IC1 6 R5
with R 3 setting Q4’s collector current as LF411 OUT Q5
10k MJE350
3 R6
the following equation determines: + 5
10k
7 Q2
IC3IC4 [ VCC(VCC)VBE(Q4)]/R 3. Q6
R7 VCC
Operational amplifier IC1 provides base 12V 40k
MJE340
VCC
drive to Q5, which in turn drives Q6.With RETURNS
no signal applied to IC1’s input, the col- This complementary-symmetry
VCC
lector currents of Q6 and Q3 balance, and amplifier features low component count.
the output taken from the junction of
emitter followers Q1 and Q2 rests at 0V.
Applying an input signal to IC1 drives
its output toward the positive or the neg-
ative 12V supply rail. Allowing IC1’s out-
put to saturate would introduce sufficient
slew-rate delay to cause oscillations. Al-
though specifying a relatively fast opera-
tional amplifier, an LF411, improves the
(a)
amplifier’s bandwidth and slew rate, an- TIME (nSEC)
tiparallel diodes D1 and D2 improve sta-

bility by restricting IC1’s output excur-
sion to one diode forward-voltage drop.
You can adjust R 7 to minimize output
dc offset voltage and slew rate. As a rule
of thumb, select resistor R 7 to be twice the
value of R 9. The ratio of R 9 to R 8 sets the
amplifier’s gain. Figure 2 shows the input
and output waveforms using optimal val- (b) TIME (nSEC)
ues for R 7 and R 9. Note that the
VCEO ratings for Q1 and Q2 limit VCC Figure 2 The input waveform show input voltage applied as a pulse of 2 to 2V (a). The
and VCC to 300V or less. output waveform shows an amplifier gain of 20 and minimized output offset (b).
100 ed n | D e c em b e r 7, 2 0 0 4 www.edn.com

Phone wire, RJ-11 jacks and

optocouplers build a bus
Ernie Deel, EFD Systems, Marietta, GA
lthough cutting-edge technolo- communications range, and adds a meas- nicating with isolated-side devices. You
A gy reaps publicity, the real world of-

ten runs on modest hardware that’s
just “good enough” for home automa-
ure of protection for attached hardware.
However, inexpensive optocouplers in-
troduce delays that can cause communi-
can implement RS-232, TTL, or invert-
ed-TTL interfaces by configuring a single
jumper and altering connections as ap-
tion, alarm systems, and equipment- cations timing errors. Faster optocouplers propriate. Figure 1 illustrates representa-
monitoring applications. Figure 1 shows can minimize errors at the expense of com- tive examples of each interface.
a low-speed, multidrop digital data net- ponent cost and overall complexity, but us- When adding an RS-232 device, you
work that uses inexpensive optoisolators, ing conservatively sized data packets at can ensure compliance with the RS-232
telephone jacks, and two-pair wiring. rates of 4.8 kbps or less allows the use of standard by using a control line, such as
This version of the familiar current less expensive components. The H11A- DTR or RTS, to provide pull-up power,
loop offers a simplified and somewhat 817D optocouplers provide 5-kV isolation and negative voltage from the TX (trans-
novel implementation in which opto- and current-transfer ratios of 300 to 600%. mit) line to passively pull the RX (receive)
couplers serve triple duty as level con- A wall transformer/rectifier provides line low. You can devise a suitable mas-
verters, isolation/protection devices, and 12V-dc power for the isolated bus, and ter/slave-communication and error-de-
bus interfaces. Galvanic isolation avoids devices attached to the bus provide a few tection protocol to meet your require-
ground loops, increases the effective milliamperes of 5V power for commu- ments. Using separate transmitter and
www.edn.com D e c e mb e r 7, 2 0 0 4 | ed n 101

design
ideas
TWISTED PAIRS
22 TO 24 AWG UNSHIELDED
470 Y TWISTED PAIRS
4.7k G
12V +
DC 4.7k R
_
4.7k 4.7k 4.7k 4.7k
H11A8170
(TYPICAL)
470 470 470 470

4.7k 4.7k 4.7k 4.7k
4.7k 1N4148 4.7k 1N4148 4.7k 1N4148 4.7k 1N4148
47 F 47 F 47 F 47 F
J1 J1 J1 J1
+ 16V + 16V + 16V + 16V
RX RX RX GND
DTR DTR +5V RX
Figure 1 (+) GND TX (+) GND TX GND TX 5V
A low-cost RJ-11 RJ-11 RJ-11 RJ-11

4 0 0 1 4 0 0 1 4 0 0 1 4 0 0 1
master/slave 5 0 0 2 5 0 0 2 5 0 0 2 5 0 0 2
bus provides 6 0 0 3 6 0 0 3 6 0 0 3 6 0 0 3
BRGY BRGY BRGY BRGY
as many as
RS-232 JUMPERS 2 TO 5 RS-232 JUMPERS 3 TO 6 INVERTED JUMPERS 1 TO 4 TTL
six isolated MASTER FOR RS-232 SLAVE FOR INVERTED SLAVE FOR TTL AND SLAVE
SLAVE ALTERNATIVE WIRING
nodes.
NOTE: JUMPERS 5 AND 6 ARE PERMANENTLY CONNECTED.
receiver lines helps simplify the required telephone jack, thus facilitating quick rate, the bus can extend as far as 500 ft.
software. The node-point hardware eas- and easy RJ-11 hookups to master and Inexpensive dual twisted-pair telephone
ily fits inside an ordinary surface-mount slave devices.At a 4.8-kbps or lower data wire forms the bus.
PIN IC1
NUMBERS LM4040-4.1
Use a PC’s parallel port to DB3 5

R1
150
1
3
2
C1
10 nF
program a clock source DB4 6

R2
150 C2
2.2 F
By William Grill, Honeywell BRGA, Lenexa, KS R3

150
8
DB0 2 2 7
his Design Idea shows how you can provides 4.096V of
T
R 4
150 IC 1
use Linear Technology’s LTC6903 stable power to IC1 FROM PC'S
DB
3 3
LTC6903
2
PRINTER 1
R
programmable oscillator as a clock and IC2. For optimal PORT 5
4 150 4 6
source for direct-digital synthesis, data performance, mini- DB 2
conversion, switched-capacitor filtering, mize the lead lengths

5
clock, and voltage-controlled oscillator of bypass capacitors
IC CLOCK
circuits. The LTC6903 operates from 2.7 C1 and C2 with respect NC7SZ125 CONNECTOR
3
to 5.5V with modest power consumption to IC2’s power 2 4

and can produce clock signals at fre- and ground con- Figure 1
1
quencies of 1 kHz to 68 MHz.Typical fre- nections. High-speed
3
25
quency error and resolution over the buffer IC3 isolates IC2’s
range are 1.1 and 0.1%, respectively. output and prevents
You can control the programmable os- frequency pulling due PC-programmable wide-range clock source features minimal
cillator circuit in Figure 1 via an IBM- to load variations. component count.
compatible PC’s parallel port, which also Listing 1 on the Web
provides power to the circuit.Resistors R 1 version of this Design Idea at OCT and DAC. The program derives
and R 2 limit power-supply current drawn www.edn.com translates a user-supplied the closest values for OCT and
from parallel-port data bits DB3 and DB4, input into a 16 bit, SPI-compatible data DAC by solving the equation:
and resistors R 3 through R 5 isolate pro- stream that programs IC1’s output fre- f (2OCT)2078/(2 (DAC)/1024). At
gramming bits DB0 through DB2. A pre- quency. The LTC6903’s output frequen- initial application of power, IC2’s output
cision micropower voltage reference, IC1, cy depends on two control coefficients, frequency defaults to 1.039 kHz.

design
ideas
Constant-on-time buck-boost regulator converts
a positive input to a negative output
Robert Bell, National Semiconductor Inc, Chandler, AZ
uck regulators find wide appli-
B cation as step-down regulators for

converting large positive input volt-
ages into a smaller positive output volt-
10 TO 50V
 VIN
BST
C4
0.022 F
47 H
C1 R3
ages. Figure 1 shows a simplified buck VIN 22 F IC1
SW
249k
regulator that operates in continuous- LM5010 D1 R1
 R IS 3.8k
conduction mode—that is, the inductor ON C5
FB 22 F
current always remains positive.The out- VOUT
put voltage, VOUT, is equal to DVIN, VCC SS PGND AGND R2
R4
where D is the duty-cycle ratio of the C2 C3 1k
0.5
buck switch,Q1, and VIN is the input volt- 1 F 0.01 F
12V
age. The duty cycle, D, is equal to
TON/TS, where TON is the on-time F i g u r e 3
of Q1 and TS is the switching-frequency Based on National Semiconductor’s LM5010, this buck-boost regulator operates over a wide input-
period. voltage range.
You can reconfigure a buck regulator
into a buck-boost circuit to convert a regulator IC that converts a 10 to 50V where K represents a constant,R 3 sets the
positive voltage into a negative voltage positive supply voltage into 12V. Al- buck switch’s on-time interval, VIN is the
(Figure 2). The basic component config- though many applications use a fixed input voltage, and VOUT is the magnitude
urations of both circuits are similar, and switching frequency and modulate the of the output voltage. Substitute
the inductor and the rectifier diode are output pulse width, this design features TON1/FS and then solve for FS to yield:
transposed. Because the main switch, Q1, a constant-on-time approach in which
remains in the same location for both the IC’s internal output transistor turns
configurations, you can use an IC buck on for an intervalthat’s inversely propor-
regulator for either topology. Switching tional to the difference between the cir-
on Q1 applies input voltage VIN across cuit’s input and output voltage. Providing that current through L1 re-
power inductor L1, and current inthe in- Inside IC1, a regulation comparator mains continuous, VOUT remains regulat-
ductor ramps up while Q1 remains on. monitors the output voltage from voltage ed.Because R 3 and K are constants,switch-
When Q1 switches off, inductor current divider R 1 and R 2 and a 2.5V internal ref- ing frequency FS remains constant. This
continues to flow through C1, the load re- erence, and,if the output voltage falls be- relationship holds true provided that the
sistance and D1, producing a negative low the desired value, the comparator current through the inductor remains
output voltage. During Q1’s next on-time switches on IC1’s output transistor for an continuous.At lighter loading,the current
interval, the output capacitor supplies interval that an on-timer determines: in the inductor becomes discontinuous—
current to the load. that is, the inductor current drops to zero
Figure 3 shows a low-cost buck-boost for a portion of the switching cycle.At the
converter based on the LM5010 buck- onset of discontinuous operation, the
VIN
VIN
IL
D*TS
D*TS
Q1
Q1 TS
TS
IQ1
IQ1 D1
VOUT
VOUT
L1
L1 C1
D1 C1 IL
ID1
ID1
Figure 1
In the basic buck-regulator circuit, current flows continuously Figure 2
through inductor L 1. The buck-boost regulator circuit produces a negative output voltage.

design
ideas
switching frequency begins to drop and 400 kHz, delivering 12V at approximate- sation or stability issues to worry about.
thus brings VOUT back into regulation. ly 0.5A for 10V input and approximate- The transient response is fast, because
Operating a buck-boost regulator in ly 1A of output current for 50V input. there are no bandwidth-limiting feed-
fixed-frequency mode without an oscil- Resistor R 4 ensures that the minimum back components.The regulator operates
lator eliminates loop compensation and amount of output-ripple voltage neces- at approximately 400 kHz. The output-
stabilization components and, as a sary for regulation—approximately 25 current capability varies with the input
bonus, offers fast transient response un- mV—is available. voltage. When you apply 10V input volt-
limited by feedback-network lag time. Fixed-frequency operation without an age, the output-current capability is ap-
With the component values in Figure 3, oscillator offers a low-cost, easily imple- proximately 0.5A, and, at 50V input, the
the regulator operates at approximately mented regulator with no loop-compen- output current is approximately 1A.
Rainbow LED indicates voltage with color

David Prutchi, Impulse Dynamics, Haifa, Israel IC2
KINGBRIGHT
eters that indicate analog lev-
M
AAF5060PBESEEVG
els via a moving-pointer meter, a R1
D1
numeric display, or a column of 56 4 3
LEDs typically occupy considerable pan- GREEN LED
el area and require more than a casual R2
D2
glance to read.An indicator lamp or LED 7 6
150
5 2
ANALOG GP0/AN0 GP1/AN1/VREF
takes little space but indicates only an on INPUT 5
4 GP2/TOCKI/AN2/INT RED LED
or off condition. However, an unobtru- GP3/MCLR/VPP
3
R3
D3
GP4/OSC2/AN3/CLKOUT 68 6
sive LED that changes color as a 1 2
1
Figure 1 VCC GP5/OSC1/CIN
function of a measured value BLUE LED
would enable an observer to easily assess IC1
5V PIC12F675
the measurement.
The circuit in Figure 1 comprises IC1, Using a minimal number of components, this voltage-to-color converter uses a single rainbow LED
a Microchip PIC12F675 microcontroller to monitor an analog voltage level.
driving IC2, a Kingbright AAF5060PBE-
SEEVG “rainbow” indicator that con-
tains three ultrabright LED chips (red,
green, and blue) within one package.
Modulating each LED’s duty cycle pro-
duces all of the perceivable colors of the
visible spectrum, including white light.
Listing 1 at the Web version of this De- STEPS
PER
sign Idea at www.edn.com contains a PIC 14-STEP
program for the PicBasic Pro compiler, FRAME
which is available from MicroEngineer-

ing Labs Inc (www.melabs.com). This
program converts a 0 to 5V input applied
to Pin 3 of IC1 to an 8-bit digital value
that corresponds to a perceived color
containing certain amounts of
Figure 2
red, blue, and green.
A/D COUNTS
Under control of a PWM routine,each
LED flashes for an interval proportional You can alter the color versus input-voltage palette by modifying the firmware.
to its corresponding content of red,green,
or blue. During each PWM frame, an ed, the eye’s slow response integrates their (shades of blue, purple, and aqua) denote
LED die receives power for as many as 14 output to create the illusion of a change an input in the 0 to 2.5V range, and “hot”
steps per frame as the color map of Fig- in intensity proportional to the duty cy- colors (shades of red, orange, yellow, and
ure 2 shows.(You can view the color map cle. The RGB-encoding function in List- white) denote an input in the 2.5 to 5V
at the Web version of this Design Idea at ing 1 assumes that the analog input to IC1 range. You can create different palettes by
www.edn.com.) Although not all LEDs has a zero-signal offset of 2.5V, which changing the primary-color proportions
are necessarily simultaneously illuminat- switches all LEDs off. “Cool” colors stored in the RGB encoding table.

design
ideas The best of
design ideas
www.edn.com
Impedance transformer flags failed fuse

Kevin Ackerley, Future Electronics, Vancouver, BC, Canada
C2
depicts a circuit that detects
F
igure 1 VCC 5-TO-1 TOROIDAL
10 nF CONNECTOR TRANSFORMER
the opening of a miniature circuit
R1 TO LOAD
breaker or high-rupture-capability CIRCUIT
100k
fuse in a high-reliability telecommunica- R5
+ L2
tions power supply. The circuit generates IC1 3.3k L1
AD8606
an alarm when a failure changes the im- _ C4 T1
pedance of an electromagnetic sensor. R2
R4 470 nF
10k
Traditional fault-detection circuits sense 100k
the voltage difference developed across VCC

LOGIC
an open fuse, leakage current flowing D1
C3
OUT
100 nF
through a fused circuit, or closure of an R3
1N4148
D3 R9
auxiliary (volts-free) contact by an actu- 470 +
IC2 1N4148 47k
D2
ator fuse. All three methods suffer from 1N4148 R6
AD8606 Q1
_
disadvantages: Voltage-difference circuits C1
100k R7 R8 C5 2N3904
100 nF 100 nF
can introduce unacceptable delays as long 4.7k 10k
as 30 minutes because the system’s bat-

teries sustain the bus voltage. Leakage-
current sensors rely on the presence
of a load that may not be present un- Figure 1 This sensor circuit operates from a single 5V power supply.
der certain conditions. Adding auxiliary
miniature-circuit-breaker support cir- Under normal operation, an intact fuse which in turn drives a peak detector
cuits or special high-rupture-capability or closed circuit breaker completes a low- formed by D3 and C5. Transistor Q1 satu-
indicator fuses and their connectors can impedance path through T1’s single-turn rates and provides a logic-low signal to an
significantly increase system cost. primary (sense) winding. Transformer external alarm. Figure 2 shows a typical
Capacitor C4 and the secondary in- action presents a low impedance at the application for sensing backup-battery-
ductance, L2, of transformer T1 resonate junction of C2, C4, and R 5 and reduces the circuit failure.
at approximately 42 kHz,a frequency that loop gain around IC1 to an amount To design transformer T1, you calcu-
minimizes noise production in the audio, insufficient to sustain
RF, and psophometric noise bands. Op- oscillation.
erational amplifier IC1 and associated When a fault occurs
TOROIDAL
components form an ac-coupled posi- and interrupts current TRANSFORMER
SYSTEM EARTH
tive-feedback amplifier with a gain of 20. through T1’s primary
winding, its secondary +
BATTERY CUSTOMER'S
STRING 1 + L0AD
impedance increases,
Impedance transformer flags allowing full loop gain – RECTIFIER 1
failed fuse ........................................................67 and permitting IC1 to
Digital waveform generator provides oscillate at 42 kHz, LVD1
flexible frequency tuning for which L2 and C4 deter- BACKPLANE FUSE LOAD FUSE
sensor measurement ....................................68 mine. Under fault con-
Battery-operated remote-temperature ditions, T1’s turns ratio BATTERY SHUNT
injects less than 10 mV LOAD SHUNT LVD2
sensor drives 4- to 20-mA current loop....70
of wideband conduct-
Precision current source
is software-programmable ..........................72
ed noise into the dc
bus. Capacitor C3 The system wiring diagram shows transformer
couples the oscil- Figure 2
What ’s Up sect ion at w ww.ed n.co m.
T1’s primary winding. Low-voltage-disconnect
lating signal to IC2, a units LVD1 and LVD2 isolate the 48V battery or the customer’s
gain-of-3 amplifier, load for maintenance.
www.edn.com D e c em b e r 1 7, 2 0 0 4 | ed n 67

design
ideas
TOROIDAL CORE
late the required impedance and turns PLAN CONNECTOR

ratio. Equation 1 describes the basic
transformer relationship:
(1)
ELEVATION
where Z1 is the impedance of the primary
winding, Z2 is the impedance of the sec-
ondary winding N1 is the number of pri-
mary turns, and N2 is the number of sec-
ondary turns.
Figure 3
Under normal operation with
current flowing in the primary winding, The primary winding (battery cable) passes through transformer T 1’s center.
the secondary impedance comprises the
low primary-side impedance plus T 1’s teration of T1’s design, but if that data is Also, select a core material that doesn’t
leakage reactance. When no current unavailable, you can use Equation 3 to saturate at full primary current.
flows in the primary winding, the num- calculate the inductance. Note that the core’s central area must
ber of turns in the secondary and the provide clearance for the battery cable
toroidal core AL (inductance per turn) (3) (primary winding) and secondary wind-
determine the secondary winding L2’s ing. This application uses a Philips 3C85
inductance and number of turns per where e, the effective permeability, equals toroidal ferrite core (part no. TN 16/9.6/
Equation 2: the magnetic constant, 4107Hm1, I 6.3-3C85) with a secondary winding com-
is the path length, and A is the cross-sec- prising five turns of 0.2-mm2 insulated
(2) tional area in millimeters squared. copper wire. (Philips, however, has dis-
Select a core that presents a high val- continued the 3C85 ferrite core. Ferrox-
where N2 is the number of turns around ue of inductance to ensure that the dif- cube’s type 3C90 ferrite may serve as a re-
the toroidal core. ference between an open and a closed placement. Specifications are available at
Ferrite-core manufacturers publish in- primary circuit causes a large change in www.ferroxcube.com.) Figure 3 shows the
ductance-per-turndata that simplifies al- relative secondary-winding impedance. completed transformer.
Digital waveform generator provides flexible

frequency tuning for sensor measurement
Colm Slattery, Analog Devices, Limerick, Ireland
ariable-resistance sen- frequency and measuring
V
SENSOR ASSEMBLY MOVING OBJECT
sors convert a fixed dc ex- changes in the phase or ampli-

citation voltage or current tude of output voltage V2 with
into a current or voltage that’s a respect to excitation voltage
straightforward func- C L V1. However, this approach
Figure 1
tion of the quantity un- limits the sensor’s dynamic
V1 REFERENCE
dergoing measurement. In an- VOLTAGE range and resolution.
EXCITATION
other class of sensors, moving VOLTAGE
As an alternative, you can
objects or fluids produce a sen- drive the sensor with a swept-
R V2 SENSOR
sor signal by altering an LC cir- OUTPUT frequency ac source that tracks
cuit’s inductance or capacitance. the sensor’s resonant-frequen-
Figure 1 shows a basic ac-driven cy variation. Figure 2 shows
tuned-circuit proximity sensor, The amplitude and phase of the resonant-circuit sensor’s output one approach in which IC1, a
L and C, and sampling resistor, voltage, V2, vary with moving object’s position. DDS (direct-digital synthesis)
R. Under static conditions,L and device, produces a sine-wave
C resonate and provide maximum im- C varies and alters the circuit’s resonant excitation voltage. Lowpass filter IC2 re-
pedance at one frequency. As an object frequency.You can derive the object’s po- moves clock artifacts and harmonics, and
approaches the sensor, the value of L or sition by exciting the sensor with a fixed amplifier IC3 drives the sensor. Amplifi-
68 ed n | D e c em b e r 1 7, 2 0 0 4 www.edn.com

design
ideas
er IC4 boosts the sensor’s output voltage,
VDD
V2, and drives IC5, a dual-channel, 12-bit
AMPLIFIER
ADC,which simultaneously samples and
CLOCK IC
digitizes reference voltage V1 and IC4’s IC1 VOUT 2 IC3
AD9833 LOWPASS AD8XX
output. IC5, a DSP-capable microcon- FILTER
SCLK FSYNC SDI
troller, analyzes the sensor output’s am-
plitude and phase, setting the frequency VDD V1 REFERENCE
VDD VOLTAGE
of IC1 via alternate programming of ei-
ther of IC1’s dual frequency-control reg- VDRIVE SENSOR
isters. One of IC6’s serial ports delivers IC5
SPI
position data to an external controller. DR0 DOA VA1
IC6 DR1 DOB
Using a DDS/DSP combination offers ADSP-218X VA2 IC4 V2
SCLKO SCLK
SERIAL
considerable flexibility when using var- DATA SERIAL PORT 0
TFSO CS AD8XX
SIGNAL
ious types of sensors. For example, cer- OUT AD7866 VOLTAGE
tain sensors require a relatively narrow AMPLIFIER
but high-resolution range of

Figure 2
excitation frequencies, and
others may work best with broadly swept A swept-frequency source and a DSP controller combine to offer a versatile sensor-
excitation. excitation system.
Battery-operated remote-temperature sensor

drives 4- to 20-mA current loop
Scot Lester, Texas Instruments, Dallas, TX
ou can remotely measure temper- TPS62300 series of ICs, for example,con- In the sample circuit, which occupies
Y ature using a 4- to 20-mA current

loop as long as 4000 feet and a bat-
tery-powered, white-light LED driver.
verts a battery voltage of 2.7 to 6.5V into
a constant current, which you program
using an external resistor and voltage on
50 mm2, the LED driver drives the 4- to
20-mA current loop proportionate to a
sensed temperature of 10C at 4 mA
You usually configure this equipment to its ISET pin. The current that normally and 50C at 20 mA. The driver applies
provide a programmable, constant cur- drives the LED instead powers the loop 0.6V to the ISET pin and monitors current
rent to an LED from a battery source. The (Figure 1). flow from the pin. This current is multi-
V+ V+
R1
2 3 VREF 51.1k V+
IC2
IN OUT
0.1 F
R2 0.1 F
29.4k IC4
1 F
3 RISET TPS60230RGT
+ 5
1 6.49k
1
IC3 ISET
4 _ VISET 2 16
EN2
V+ 2 3 15
EN1
4 14
GND
5 13
4 2 VIN
R3 R4
IC1 150k 100k
5 1 6 12
D1 C2
11
C8 C1
7
0.015 F PGND 0.47 F 0.47 F
10
C1+
8 V 9
OUT C2+
GND
17
1 F
Figure 1 TWISTED PAIR
RECEIVER
In this circuit, the LED driver drives the 4- to 20-mA current loop propor-
100
tionate to a sensed temperature of 10C at 4 mA and 50C at 20 mA.
70 ed n | D e c e mb e r 1 7, 2 0 0 4 www.edn.com

design
ideas
plied by 260 and mirrored to the LED REF2912 voltage reference, IC2, with the loops with as much as 180 of resistance
drive output: OPA374 op amp to scale the output of with battery voltages as low as 2.7V.
the TMP36 to the required voltage for the Therefore, the LED driver can drive more
LED driver, IC4. In general terms, the cur- than 1500 feet of 24 AWG or 4000 feet of
rent in the current loop for the circuit is: 20 AWG twisted-pair wire with a 100
load resistor at the receiver. You can
Because resistor R ISET, which is tied to achieve much longer distances with high-
the ISET pin, is fixed in the example, the er battery voltages. Because this circuit
output current is proportional to the powers the current loop, the battery life
voltage, VISET, which the output of op for these circuits depends on the meas-
amp IC3 determines. Using a 6.49-k  re- ured temperature. For the circuit shown,
sistor for R ISET means that VISET needs to a loop current of 13.3 mA corresponds
be 0.1V to provide 20 mA of loop current to a measured temperature of 25C.
and 0.5V to provide 4 mA. Therefore, using two AA alkaline batter-
The TMP36 temperature sensor, IC1, ies in series should provide more than 120
provides 750 mV of output at 25C and Substituting for the component values hours of remote-temperature monitoring
varies its output voltage by 10 mV/C. shown in the figure yields: at room temperature. The accuracy for
The output of the TMP36 is 0.4V at the circuit is about 2.5% of full scale with-
10C and 1V at 50C. Because these out any calibration. For tighter accuracy,
voltages do not directly match the volt- reduce the range of the measured tem-
age requirements of VISET, you use a The output of the LED driver can drive perature or calibrate the output. 
Precision current source is

software-programmable
Joe Neubauer, Maxim Integrated Products Inc, Sunnyvale, CA
ith the addition of a few inex- to these devices, besides the hard-wired resistor. The voltage across R SENSE deter-
W pensive miniature components, type, can be one, two, or three wires. IC1, mines current through the pass transis-
the hard-wired, voltage-controlled for example, has a three-wire SPI inter- tor, ISET: ISET(VCC - VIN)/R SENSE.
current source of yesterday becomes a face, and provides an end-to-end resist- The circuit can provide any current lev-
software-programmable voltage-con- ance of 50 k  with 256 incremental set- el for which the external components,
trolled current source (Figure 1). A digi- tings.Thus,each increment of the digital R SENSE and the pass transistor, can handle
tal potentiometer, IC1 in conjunction potentiometer changes VIN by: the associated power dissipation (PIV).
with a precision op amp, IC2, sets current Because the ratio setting of digital poten-
through a pass transistor, ISET, and a shunt tiometers is good, with a typical ratio-
regulator, IC3, provides a constant refer- metric resistor temperature coefficient of
ence voltage across the digital poten- 5 ppm/C), precision and stability for the
tiometer. By operating in its linear region, Op amp IC2 regulates current through current source depend primarily on the
the transistor controls load current in re- the pass transistor, and the digital poten- precision and stability of IC3 and R SENSE
sponse to the applied gate voltage. Each tiometer sets current through the R SENSE combined. 
incremental step of the digital poten-
VCC
tiometer increases or decreases the wiper
RSENSE
voltage, VIN, at the op amp’s
Figure 1 SHUNT
ISET
noninverting input. Thus, VIN MAX6138
varies with respect to the reference volt- IC3
GND
age, which in turn remains stable with re- _
IC2
spect to the supply rail: MAX5400 MAX4165 P
IC1 VIN+
This software- DIGITAL
+
programmable POTENTIOMETER
current source LOAD

applies current to
RS ISHUNT
Many types of digital potentiometer the load in 256
are currently available, and the interface equal increments.
72 ed n | D e c em b e r 1 7, 2 0 0 4 www.edn.com

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5V power supply teams

A the 5V auxiliary power that “silver

ten command a premium price. You can

Four-quadrant power supply provides

cannot transition 2 µF 0.1 µF

nections that allow you

2). The de-

ate signals with 0.1-Hz

AGND DGND VDD CAP/2.5V

FREQUENCY 0 REGISTER 10-BIT

F SYN C S CLK SDATA

The AD9833 DDS IC generates frequencies with 0.1-Hz resolution.

reduce the supply current. The AD9833

Simple dc/dc converter increases

T way to increase the power available

voltage. You calculate the feedback-re- 300-mA

Force/sense connection eliminates

D everyday analog-design element.

Analog multiplexer uses flying capacitors

T way to increase the number of

adding an analog-multiplexer chip 0.33 F

FPGA-configuration scheme is flexible

Add fault protection to a 4- to 20-mA loop supply

A of a power source and a current-

way-Addressable Q1 2.2k 102k

the modulat- Q3 PB1

from IC1 is capac-

Double DAC rate by using mixers as switches

Y sample rate of a DAC by interleaving

DDS IC plus frequency-to-voltage converter

thereby generating an 18-

FREQUENCY0 REGISTER 10-BIT

VDD square wave that serves as the clock

Low-noise ac amplifier has

I gain amplifier serves at the input to

GN2 GN1 GN0 BW2 BW1 BW0

amplifier with control of 10 to provide high SNR. For ex-

D ing power supply that can produce

WARNING: LETHAL VOLTAGE POTENTIALS!

NOTES: D1, D2, D3, D4, D5: MURS160.

Solid-state relays simplify

Table 1 shows the alternat- HSR412 CELL

the cells are measured. To +

measure the voltage of an in- 2V + MEMORY

SSR(N1) are energized and SSR(N+1)

tage isolation between the

Simple technique makes low-cost pc-board shields

M shields to reduce susceptibility to

Lowpass filter has improved step response

A you design lowpass filters for signal

pushing the cutoff frequency lower slows VDD OUT

sonable amount of time.The circuit in Fig- Q 4

C1 and C2 set the cutoff frequency at 0.1

window comparator. Transistor

Fault-latch circuit protects switchers

Circuit provides efficient fan-speed control

Simple circuit forms

standard 2N3906 pnp transistors to

flatness of this resistance normally results A2 A1 A0

Circuit forms satellite-dish command decoder