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LM5109B
SNVS477C – FEBRUARY 2007 – REVISED JANUARY 2016

LM5109B High Voltage 1-A Peak Half-Bridge Gate Driver

1 Features 3 Description
1• Drives Both a High-Side and Low-Side N-Channel The LM5109B device is a cost-effective, high-voltage
MOSFET gate driver designed to drive both the high-side and
the low-side N-channel MOSFETs in a synchronous
• 1-A Peak Output Current (1.0-A Sink and 1.0-A buck or a half-bridge configuration. The floating
Source) high-side driver is capable of working with rail
• Inputs Compatible With Independent TTL and voltages up to 90 V. The outputs are independently
CMOS controlled with cost-effective TTL and
• Bootstrap Supply Voltage to 108-V DC CMOS-compatible input thresholds. The robust level
shift technology operates at high speed while
• Fast Propagation Times (30 ns Typical) consuming low power and providing clean level
• Drives 1000-pF Load With 15-ns Rise and Fall transitions from the control input logic to the high-side
Times gate driver. Undervoltage lockout is provided on both
• Excellent Propagation Delay Matching (2 ns the low-side and the high-side power rails. The
device is available in the 8-pin SOIC and thermally-
Typical)
enhanced 8-pin WSON packages.
• Supply Rail Undervoltage Lockout
• Low Power Consumption Device Information(1)
• 8-Pin SOIC and Thermally-Enhanced 8-Pin PART NUMBER PACKAGE BODY SIZE (NOM)
WSON Package SOIC (8) 4.90 mm × 3.91 mm
LM5109B
WSON (8) 4.00 mm × 4.00 mm
2 Applications (1) For all available packages, see the orderable addendum at
• Current-Fed, Push-Pull Converters the end of the data sheet.

• Half- and Full-Bridge Power Converters

• Solid-State Motor Drives
• Two-Switch Forward Power Converters
Simplified Application Diagram
RBoot DBoot
VIN
VCC

HB
VDD HO

HI HS LOAD
LM5109

LI LO

VSS

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5109B
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Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 10
2 Applications ........................................................... 1 7.5 HS Transient Voltages Below Ground .................... 10
3 Description ............................................................. 1 8 Application and Implementation ........................ 11
4 Revision History..................................................... 2 8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 15
6.1 Absolute Maximum Ratings ...................................... 4 10 Layout................................................................... 16
6.2 ESD Ratings.............................................................. 4 10.1 Layout Guidelines ................................................. 16
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 16
6.4 Thermal Information .................................................. 5 11 Device and Documentation Support ................. 17
6.5 Electrical Characteristics........................................... 5 11.1 Documentation Support ........................................ 17
6.6 Switching Characteristics .......................................... 6 11.2 Community Resources.......................................... 17
6.7 Typical Characteristics .............................................. 7 11.3 Trademarks ........................................................... 17
7 Detailed Description .............................................. 9 11.4 Electrostatic Discharge Caution ............................ 17
7.1 Overview ................................................................... 9 11.5 Glossary ................................................................ 17
7.2 Functional Block Diagram ......................................... 9 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................... 9 Information ........................................................... 17

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (March 2013) to Revision C Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1

Changes from Revision A (March 2013) to Revision B Page

• Changed layout of National Data Sheet to TI format ............................................................................................................. 1

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5 Pin Configuration and Functions

D Package
8-Pin SOIC
Top View

VDD 1 8 HB

HI 2 7 HO
SOIC-8
LI 3 6 HS

VSS 4 5 LO

NGT Package
8-Pin WSON
Top View

VDD 1 8 HB

HI 2 7 HO
WSON-8
LI 3 6 HS

VSS 4 5 LO

Pin Functions
PIN
DESCRIPTION
NO. (1) NAME TYPE (2)
Positive gate drive supply – Locally decouple to VSS using low ESR and ESL capacitor located
1 VDD P
as close to IC as possible.
High-side control input – The HI input is compatible with TTL and CMOS input thresholds.
2 HI I
Unused HI input must be tied to ground and not left open.
Low-side control input – The LI input is compatible with TTL and CMOS input thresholds.
3 LI I
Unused LI input must be tied to ground and not left open.
4 VSS G Ground – All signals are referenced to this ground.
5 LO O Low-side gate driver output – Connect to the gate of the low-side N-MOS device.
High-side source connection – Connect to the negative terminal of the bootstrap capacitor and
6 HS P
to the source of the high-side N-MOS device.
7 HO O High-side gate driver output – Connect to the gate of the high-side N-MOS device.
High-side gate driver positive supply rail – Connect the positive terminal of the bootstrap
8 HB P capacitor to HB and the negative terminal of the bootstrap capacitor to HS. The bootstrap
capacitor must be placed as close to IC as possible.

(1) For 8-pin WSON package, TI recommends that the exposed pad on the bottom of the package be soldered to ground plane on the PCB
and the ground plane must extend out from underneath the package to improve heat dissipation.
(2) G = Ground, I = Input, O = Output, and P = Power

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VDD to VSS –0.3 18 V
HB to HS –0.3 18 V
LI or HI to VSS –0.3 VDD + 0.3 V
LO to VSS –0.3 VDD + 0.3 V
HO to VSS VHS – 0.3 VHB + 0.3 V
HS to VSS (2) –5 90 V
HB to VSS 108 V
Junction temperature –40 150 °C
Storage temperature, Tstg –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed –1 V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD – 15 V. For example, if
VDD = 10 V, the negative transients at HS must not exceed –5 V.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1500
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD 8 14 V
HS (1) –1 90 V
HB VHS + 8 VHS + 14 V
HS slew rate 50 V/ns
Junction temperature –40 125 °C

(1) In the application, the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed –1 V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD – 15 V. For example, if
VDD = 10 V, the negative transients at HS must not exceed –5 V.

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6.4 Thermal Information

LM5109B
THERMAL METRIC (1) D (SOIC) NGT (WSON) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 117.6 42.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 64.9 34.0 °C/W
RθJB Junction-to-board thermal resistance 58.1 19.3 °C/W
ψJT Junction-to-top characterization parameter 17.4 0.4 °C/W
ψJB Junction-to-board characterization parameter 57.6 19.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance – 8.1 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

6.5 Electrical Characteristics

TJ = 25°C (unless otherwise specified), VDD = VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
TJ = 25°C 0.3
IDD VDD quiescent current LI = HI = 0 V mA
TJ = –40°C to 125°C 0.6
TJ = 25°C 1.8
IDDO VDD operating current f = 500 kHz mA
TJ = –40°C to 125°C 2.9
TJ = 25°C 0.06
IHB Total HB quiescent current LI = HI = 0 V mA
TJ = –40°C to 125°C 0.2
TJ = 25°C 1.4
IHBO Total HB operating current f = 500 kHz mA
TJ = –40°C to 125°C 2.8
TJ = 25°C 0.1
IHBS HB to VSS current, quiescent VHS = VHB = 90 V µA
TJ = –40°C to 125°C 10
IHBSO HB to VSS current, operating f = 500 kHz 0.5 mA
INPUT PINS LI AND HI
TJ = 25°C 1.8
VIL Low level input voltage threshold V
TJ = –40°C to 125°C 0.8
TJ = 25°C 1.8
VIH High level input voltage threshold V
TJ = –40°C to 125°C 2.2
TJ = 25°C 200
RI Input pulldown resistance kΩ
TJ = –40°C to 125°C 100 500
UNDERVOLTAGE PROTECTION
TJ = 25°C 6.7
VDDR VDD rising threshold VDDR = VDD – VSS V
TJ = –40°C to 125°C 6.0 7.4
VDDH VDD threshold hysteresis 0.5 V
TJ = 25°C 6.6
VHBR HB rising threshold VHBR = VHB – VHS V
TJ = –40°C to 125°C 5.7 7.1
VHBH HB threshold hysteresis 0.4 V
LO GATE DRIVER
TJ = 25°C 0.38
VOLL Low-level output voltage ILO = 100 mA, VOHL = VLO – VSS V
TJ = –40°C to 125°C 0.65
TJ = 25°C 0.72
VOHL High-level output voltage ILO = −100 mA, VOHL = VDD – VLO V
TJ = –40°C to 125°C 1.2
IOHL Peak pullup current VLO = 0 V 1 A
IOLL Peak pulldown current VLO = 12 V 1 A

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Electrical Characteristics (continued)

TJ = 25°C (unless otherwise specified), VDD = VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HO GATE DRIVER
TJ = 25°C 0.38
VOLH Low-level output voltage IHO = 100 mA, VOLH = VHO – VHS V
TJ = –40°C to 125°C 0.65
TJ = 25°C 0.72
VOHH High-level output voltage IHO = −100 mA, VOHH = VHB – VHO V
TJ = –40°C to 125°C 1.2
IOHH Peak pullup current VHO = 0 V 1 A
IOLH Peak pulldown current VHO = 12 V 1 A

6.6 Switching Characteristics

TJ = 25°C (unless otherwise specified), VDD = VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Lower turnoff propagation delay TJ = 25°C 30
tLPHL ns
(LI falling to LO falling) TJ = –40°C to 125°C 56
Upper turnoff propagation delay TJ = 25°C 30
tHPHL ns
(HI falling to HO falling) TJ = –40°C to 125°C 56
Lower turnon propagation delay TJ = 25°C 32
tLPLH ns
(LI rising to LO rising) TJ = –40°C to 125°C 56
Upper turnon propagation delay TJ = 25°C 32
tHPLH ns
(HI rising to HO rising) TJ = –40°C to 125°C 56
Delay matching: Lower turnon and upper TJ = 25°C 2
tMON ns
turnoff TJ = –40°C to 125°C 15
Delay matching: Lower turnoff and upper TJ = 25°C 2
tMOFF ns
turnon TJ = –40°C to 125°C 15
tRC, tFC Either output rise and fall time CL = 1000 pF 15 ns
Minimum input pulse width that changes
tPW 50 ns
the output

LI
LI
HI
HI

tHPLH tHPHL
tLPLH tHPLH

LO

LO
HO
HO

tMON tMOFF

Figure 1. Typical Test Timing Diagram

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6.7 Typical Characteristics

100
100
VDD = VHB = 12V
CL = 1000 pF
VSS = VHS = 0V
CL = 1000 pF
10 CL = 2200 pF
10
CL = 2200 pF

IHBO (mA)
IDDO (mA)

CL = 4400 pF
CL = 4400 pF 1

1
CL = 0 pF
0.1
CL = 0 pF
CL = 470 pF
CL = 470 pF
0.1 0.01
1 10 100 1000 1 10 100 1000
FREQUENCY (kHz) FREQUENCY (kHz)
VDD = VHB = 12 V VSS = VHS = 0 V

Figure 2. VDD Operating Current vs Frequency Figure 3. HB Operating Current vs Frequency

2.2 0.45

0.40
2.0 IDDO
0.35
IDDO
CL = 0 pF
IDD, IHB (mA)

1.8 0.30
IDDO, IHBO (mA)

f = 500 kHz
VDD = VHB = 12V 0.25 LI = HI = 0V
1.6 VDD = VHB = 12V
VSS = VHS = 0V 0.20
VSS = VHS = 0V
1.4 0.15
IHBO
0.10 IHBO
1.2
0.05

1.0 0.00
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (oC)
Figure 4. Operating Current vs Temperature Figure 5. Quiescent Current vs Temperature
600 44
LI = HI = 0V CL = 0 pF tLPHL
VDD = VHB = 12V tHPHL
500 VDD = VHB 40
PROPAGATION DELAY (ns)

VSS= VHS = 0V VSS = VHS = 0V

IDD
400
CURRENT (PA)

36
turn off
300 32
tHPLH
200 28 tLPLH

IHB turn on
100 24

0 20
8 10 12 14 16 18 -40 -25 -10 5 20 35 50 65 80 95 110 125
VDD, VHB (V) TEMPERATURE (oC)
Figure 6. Quiescent Current vs Voltage Figure 7. Propagation Delay vs Temperature

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Typical Characteristics (continued)

1.6 0.6
Output Current : -100 mA Output Current : -100 mA
1.4 VSS = VHS = 0V
VSS = VHS = 0V
1.2 0.5
VDD = VHB = 8V
VDD = VHB = 8V
VOH (V)

1.0

VOL (V)
0.8 0.4

0.6 VDD = VHB = 12V

VDD = VHB = 12V
0.4 0.3
VDD = VHB = 16V VDD = VHB = 16V
0.2

0 0.2
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C) TEMPERATURE (°C)

Figure 8. LO and HO High Level Output Voltage Figure 9. LO and HO Low Level Output Voltage
vs Temperature vs Temperature

7.0 0.50
VDDR = VDD - VSS
0.48
6.9 VHBR = VHB - VHS
0.46
6.8 HYSTERESIS (V) 0.44 VDDH
THRESHOLD (V)

VDDR 0.42
6.7
0.40
6.6 VHBR
0.38
VHBH
6.5 0.36
0.34
6.4
0.32
6.3 0.30
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125

TEMPERATURE (oC) TEMPERATURE (oC)

Figure 10. Undervoltage Rising Thresholds Figure 11. Undervoltage Hysteresis vs Temperature
vs Temperature
2.00 1.92
VDD = 12V 1.91
INPUT THRESHOLD VOLTAGE (V)
INPUT THRESHOLD VOLTAGE (V)

Rising
1.95 VSS = 0V 1.90
Rising 1.89
1.90 1.88
1.87
1.85 1.86
Falling
1.85 Falling
1.80 1.84
1.83
1.75 1.82
1.81
1.70
1.80
-40 -25 -10 5 20 35 50 65 80 95 110 125 8 9 10 11 12 13 14 15 16

TEMPERATURE ( C) o VDD (V)

Figure 12. Input Thresholds vs Temperature Figure 13. Input Thresholds vs Supply Voltage

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7 Detailed Description

7.1 Overview
The LM5109B is a cost-effective, high-voltage gate driver designed to drive both the high-side and the low-side
N-channel FETs in a synchronous buck or a half-bridge configuration. The outputs are independently controlled
with TTL and CMOS-compatible input thresholds. The floating high-side driver is capable of working with HB
voltage up to 108 V. An external high-voltage diode must be provided to charge high-side gate drive bootstrap
capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level
transitions from the control logic to the high-side gate driver. Undervoltage lockout (UVLO) is provided on both
the low-side and the high-side power rails.

7.2 Functional Block Diagram

VDD
HV

HB

HO
Level Driver
UVLO
Shift

HS

HI

VDD

UVLO

LO
Driver
LI

VSS

7.3 Feature Description

7.3.1 Start-Up and UVLO
Both top and bottom drivers include UVLO protection circuitry which monitors the supply voltage (VDD) and
bootstrap capacitor voltage (VHB–HS) independently. The UVLO circuit inhibits each output until sufficient supply
voltage is available to turn on the external MOSFETs, and the built-in UVLO hysteresis prevents chattering
during supply voltage variations. When the supply voltage is applied to the VDD pin of the LM5109B, the top and
bottom gates are held low until VDD exceeds the UVLO threshold, typically about 6.7 V. Any UVLO condition on
the bootstrap capacitor (VHB–HS) will only disable the high-side output (HO).

Table 1. VDD UVLO Feature Logic Operation

CONDITION (VHB-HS > VHBR) HI LI HO LO
VDD-VSS < VDDR during device start-up H L L L
VDD-VSS < VDDR during device start-up L H L L
VDD-VSS < VDDR during device start-up H H L L
VDD-VSS < VDDR during device start-up L L L L
VDD-VSS < VDDR – VDDH after device start-up H L L L
VDD-VSS < VDDR – VDDH after device start-up L H L L
VDD-VSS < VDDR – VDDH after device start-up H H L L
VDD-VSS < VDDR – VDDH after device start-up L L L L

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Table 2. VHB-HS UVLO Feature Logic Operation

CONDITION (VDD > VDDR) HI LI HO LO
VHB-HS < VHBR during device start-up H L L L
VHB-HS < VHBR during device start-up L H L H
VHB-HS < VHBR during device start-up H H L H
VHB-HS < VHBR during device start-up L L L L
VHB-HS < VHBR – VHBH after device start-up H L L L
VHB-HS < VHBR – VHBH after device start-up L H L H
VHB-HS < VHBR – VHBH after device start-up H H L H
VHB-HS < VHBR – VHBH after device start-up L L L L

7.3.2 Level Shift

The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output which is referenced to the HS pin and
provides excellent delay matching with the low-side driver.

7.3.3 Output Stages

The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance,
and high-peak current capability of both outputs allow for efficient switching of the power MOSFETs. The low-
side output stage is referenced to VSS and the high-side is referenced to HS.

7.4 Device Functional Modes

The device operates in normal mode and UVLO mode. See Start-Up and UVLO for more information on UVLO
operation mode. In normal mode when the VDD and VHB–HS are above UVLO threshold, the output stage is
dependent on the states of the HI and LI pins. The output HO and LO will be low if input state is floating.

Table 3. INPUT and OUTPUT Logic Table

HI LI HO (1) LO (2)
L L L L
L H L H
H L H L
H H H H
Floating Floating L L

(1) HO is measured with respect to the HS.

(2) LO is measured with respect to the VSS.

7.5 HS Transient Voltages Below Ground

The HS node will always be clamped by the body diode of the lower external FET. In some situations, board
resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS
node can swing below ground provided:
1. HS must always be at a lower potential than HO. Pulling HO more than –0.3 V below HS can activate
parasitic transistors resulting in excessive current flow from the HB supply, possibly resulting in damage to
the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed
externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must
be placed as close to the IC pins as possible to be effective.
2. HB to HS operating voltage must be 15 V or less. Hence, if the HS pin transient voltage is –5 V, VDD must
be ideally limited to 10 V to keep HB to HS below 15 V.
3. Low-ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation. The
capacitor must be located at the leads of the IC to minimize series inductance. The peak currents from LO
and HO can be quite large. Any series inductances with the bypass capacitor will cause voltage ringing at the
leads of the IC which must be avoided for reliable operation.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

To operate power MOSFETs at high switching frequencies and to reduce associated switching losses, a powerful
gate driver is employed between the PWM output of controller and the gates of the power semiconductor
devices. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly drive the
gates of the switching devices. With the advent of digital power, this situation is often encountered because the
PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power
switch. Level shift circuit is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) to fully turn
on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN and PNP
bipolar transistors in totem-pole arrangement prove inadequate with digital power because they lack level-shifting
capability. Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also
find other needs such as minimizing the effect of high-frequency switching noise (by placing the high-current
driver IC physically close to the power switch), driving gate-drive transformers and controlling floating power-
device gates, reducing power dissipation and thermal stress in controllers by moving gate charge power losses
from the controller into the driver.
The LM5109B is the high-voltage gate drivers designed to drive both the high-side and low-side N-channel
MOSFETs in a half-bridge configuration, full-bridge configuration, or in a synchronous buck circuit. The floating
high-side driver is capable of operating with supply voltages up to 90 V. This allows for N-channel MOSFETs
control in half-bridge, full-bridge, push-pull, two-switch forward and active clamp topologies. The outputs are
independently controlled. Each channel is controlled by its respective input pins (HI and LI), allowing full and
independent flexibility to control ON and OFF-time of the output.

8.2 Typical Application

VIN

VCC
Anti-parallel Diode
RBOOT DBOOT (Optional) Secondary
Side Circuit

HB RGATE
VDD VDD HO
CBOOT
0.1 µF

OUT1 HI HS
PWM T1
Controller LM5109
RGATE
OUT2 LI LO

1.0 µF

VSS

Figure 14. LM5109B Driving MOSFETs in a Half-Bridge Converter

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Typical Application (continued)

8.2.1 Design Requirements
Table 4 lists the design parameters of the LM5109B.

Table 4. Design Example

PARAMETER VALUE
Gate Driver LM5109B
MOSFET CSD19534KCS
VDD 10 V
QG 17 nC
fSW 500 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Select Bootstrap and VDD Capacitor

The bootstrap capacitor must maintain the VHB-HS voltage above the UVLO threshold for normal operation.
Calculate the maximum allowable drop across the bootstrap capacitor with Equation 1.
'VHB VDD VDH VHBL 10 V 1 V 6.7 V 2.3 V
where
• VDD = Supply voltage of the gate drive IC
• VDH = Bootstrap diode forward voltage drop
• VHBL = VHBRmax – VHBH, HB falling threshold (1)
Then, the total charge needed per switching cycle is estimated by Equation 2.
D IHB 0.95 0.2 mA
QTotal QG IHBS u Max 17 nC 10 PA u 17.5 nC
¦SW ¦SW 500 kHz 500 kHz
where
• QG = Total MOSFET gate charge
• IHBS = HB to VSS Leakage current
• DMax = Converter maximum duty cycle
• IHB = HB Quiescent current (2)
Therefore, the minimum CBoot must be:
QTotal 17.5 nC
CBoot 7.6 nF
'VHB 2.3 V (3)
In practice, the value of the CBoot capacitor must be greater than calculated to allow for situations where the
power stage may skip pulse due to load transients. TI recommends having enough margins and place the
bootstrap capacitor as close to the HB and HS pins as possible.
CBoot = 100 nF (4)
As a general rule the local VDD bypass capacitor must be 10 times greater than the value of CBoot, as shown in
Equation 5.
CVDD = 1 µF (5)
The bootstrap and bias capacitors must be ceramic types with X7R dielectric. The voltage rating must be twice
that of the maximum VDD considering capacitance tolerances once the devices have a DC bias voltage across
them and to ensure long-term reliability.

12 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated

Product Folder Links: LM5109B

 LM5109B
www.ti.com SNVS477C – FEBRUARY 2007 – REVISED JANUARY 2016

8.2.2.2 Select External Bootstrap Diode and Its Series Resistor

The bootstrap capacitor is charged by the VDD through the external bootstrap diode every cycle when low-side
MOSFET turns on. The charging of the capacitor involves high peak currents, and therefore transient power
dissipation in the bootstrap diode may be significant and the conduction loss also depends on its forward voltage
drop. Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate
driver circuit.
For the selection of external bootstrap diodes, refer to AN-1317 Selection of External Bootstrap Diode for
LM510X Devices, SNVA083. Bootstrap resistor RBOOT is selected to reduce the inrush current in DBOOT and limit
the ramp up slew rate of voltage of VHB-HS during each switching cycle, especially when HS pin have excessive
negative transient voltage. RBOOT recommended value is between 2 Ω and 10 Ω depending on diode selection. A
current limiting resistor of 2.2 Ω is selected to limit inrush current of bootstrap diode, and the estimated peak
current on the DBoot is shown in Equation 6.
VDD VDH 10 V 1 V
IDBoot(pk) |4A
RBoot 2.2 :
where
• VDH is the bootstrap diode forward voltage drop (6)

8.2.2.3 Selecting External Gate Driver Resistor

The external gate driver resistor, RGATE, is sized to reduce ringing caused by parasitic inductances and
capacitances and also to limit the current coming out of the gate driver.
Peak HO pullup current are calculated in Equation 7.
VDD VDH 10 V 1 V
IOHH 0.48 A
RHOH RGate RGFET_Int 1.2 V / 100 mA 4.7 : 2.2 :

where
• IOHH = Peak pullup current
• VDH = Bootstrap diode forward voltage drop
• RHOH = Gate driver internal HO pullup resistance, provide by driver data sheet directly or estimated from the
testing conditions, that is RHOH = VOHH / IHO
• RGate = External gate drive resistance
• RGFET_Int = MOSFET internal gate resistance, provided by transistor data sheet (7)
Similarly, Peak HO pulldown current is shown in Equation 8.
VDD VDH
IOLH
RHOL RGate RGFET_Int

where
• RHOL is the HO pulldown resistance (8)
Peak LO pullup current is shown in Equation 9.
VDD
IOHL
RLOH RGate RGFET_Int

where
• RLOH is the LO pullup resistance (9)
Peak LO pulldown current is shown in Equation 10.
VDD
IOLL
RLOL RGate RFET_Int

where
• RLOL is the LO pulldown resistance (10)
For some scenarios, if the applications require fast turnoff, an anti-paralleled diode on RGate could be used to
bypass the external gate drive resistor and speed up turnoff transition.
Copyright © 2007–2016, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM5109B
LM5109B
SNVS477C – FEBRUARY 2007 – REVISED JANUARY 2016 www.ti.com

8.2.2.4 Estimate the Driver Power Loss

The total driver IC power dissipation can be estimated through the following components.
1. Static power losses, PQC, due to quiescent current – IDD and IHB
PQC = VDD × IDD + (VDD – VDH) × IHB (11)
2. Level-shifter losses, PIHBS, due high-side leakage current – IHBS
PIHBS = VHB × IHBS × D
where
• D is the high-side switch duty cycle (12)
3. Dynamic losses, PQG1&2, due to the FETs gate charge – QG
RGD_R
PQG1&2 2 u VDD u QG u ¦SW u
RGD_R RGate RGFET_Int

where
• QG = Total FETs gate charge
• fSW = Switching frequency
• RGD_R = Average value of pullup and pulldown resistor
• RGate = External gate drive resistor
• RGFET_Int = Internal FETs gate resistor (13)
4. Level-shifter dynamic losses, PLS, during high-side switching due to required level-shifter charge on each
switching cycle – QP
PLS = VHB × QP × fSW (14)
In this example, the estimated gate driver loss in LM5109B is shown in Equation 15.
12 :
PLM5109B 10 V u 0.6 mA 9 V u 0.2 mA 72 V u 10 PA u 0.95 2 u 10 u 17 nC u 500 kHz u 72 V u 0.5 nC u 500 kHz 0.134 W
12 : 4.7 : 2.2 :
(15)
For a given ambient temperature, the maximum allowable power loss of the IC can be defined as shown in
Equation 16.
TJ TA
PLM5109B
RTJA
where
• PLM5109B = The total power dissipation of the driver
• TJ = Junction temperature
• TA = Ambient temperature
• RθJA = Junction-to-ambient thermal resistance (16)
The thermal metrics for the driver package is summarized in the Thermal Information table of the data sheet. For
detailed information regarding the thermal information table, please refer to the Texas Instruments application
note entitled Semiconductor and IC Package Thermal Metrics (SPRA953).

14 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated

Product Folder Links: LM5109B

 LM5109B
www.ti.com SNVS477C – FEBRUARY 2007 – REVISED JANUARY 2016

8.2.3 Application Curves

Figure 15 and Figure 16 shows the rising and falling time as well as turnon and turnoff propagation delay testing
waveform in room temperature, and waveform measurement data (see the bottom part of the waveform). Each
channel (HI, LI, HO, and LO) is labeled and displayed on the left hand of the waveforms.
The testing condition: load capacitance is 1 nF, VDD = 12 V, fSW = 500 kHz.
HI and LI share one same input from function generator, therefore, besides the propagation delay and rising and
falling time, the difference of the propagation delay between HO and LO gives the propagation delay matching
data.

CL = 1 nF VDD = 12 V fSW = 500 kHz CL = 1 nF VDD = 12 V fSW = 500 kHz

Figure 15. Rising Time and Turnon Propagation Delay Figure 16. Falling Time and Turnoff Propagation Delay

9 Power Supply Recommendations

The recommended bias supply voltage range for LM5109B is from 8 V to 14 V. The lower end of this range is
governed by the internal undervoltage lockout (UVLO) protection feature of the VDD supply circuit blocks. The
upper end of this range is driven by the 18-V absolute maximum voltage rating of the VDD. TI recommends
keeping a 4-V margin to allow for transient voltage spikes.
The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in
normal mode, if the VDD voltage drops, the device continues to operate in normal mode as long as the voltage
drop does not exceed the hysteresis specification, VDDH. If the voltage drop is more than hysteresis specification,
the device shuts down. Therefore, while operating at or near the 8-V range, the voltage ripple on the auxiliary
power supply output must be smaller than the hysteresis specification of LM5109B to avoid triggering device-
shutdown.
A local bypass capacitor must be placed between the VDD and GND pins. And this capacitor must be located as
close to the device as possible. A low-ESR, ceramic surface mount capacitor is recommended. TI recommends
using 2 capacitors across VDD and GND: a 100-nF, ceramic surface-mount capacitor for high-frequency filtering
placed very close to VDD and GND pin, and another surface-mount capacitor, 220-nF to 10-µF, for IC bias
requirements. In a similar manner, the current pulses delivered by the HO pin are sourced from the HB pin.
Therefore a 22-nF to 220-nF local decoupling capacitor is recommended between the HB and HS pins.

Copyright © 2007–2016, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: LM5109B
LM5109B
SNVS477C – FEBRUARY 2007 – REVISED JANUARY 2016 www.ti.com

10 Layout

10.1 Layout Guidelines

Optimum performance of high-side and low-side gate drivers cannot be achieved without taking due
considerations during circuit board layout. The following points are emphasized:
1. Low-ESR and low-ESL capacitors must be connected close to the IC between VDD and VSS pins and
between HB and HS pins to support high peak currents being drawn from VDD and HB during the turnon of
the external MOSFETs.
2. To prevent large voltage transients at the drain of the top MOSFET, a low-ESR electrolytic capacitor and a
good-quality ceramic capacitor must be connected between the MOSFET drain and ground (VSS).
3. To avoid large negative transients on the switch node (HS) pin, the parasitic inductances between the source
of the top MOSFET and the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding considerations:
– The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gates to a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminals of the MOSFETs. The gate driver must be placed as close as
possible to the MOSFETs.
– The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap
diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The
bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground
referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak
current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.

10.2 Layout Example

Figure 17. Layout Example

16 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated

Product Folder Links: LM5109B

 LM5109B
www.ti.com SNVS477C – FEBRUARY 2007 – REVISED JANUARY 2016

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation
For related documentation see the following:
• AN-1317 Selection of External Bootstrap Diode for LM510X Devices, SNVA083
• Semiconductor and IC Packaging Thermal Metrics, SPRA953

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2007–2016, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: LM5109B
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Sep-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LM5109BMA NRND SOIC D 8 95 Non-RoHS Call TI Level-1-235C-UNLIM -40 to 125 L5109

& Green BMA
LM5109BMA/NOPB ACTIVE SOIC D 8 95 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 L5109
BMA
LM5109BMAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 L5109
BMA
LM5109BSD/NOPB ACTIVE WSON NGT 8 1000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 5109BSD

LM5109BSDX/NOPB ACTIVE WSON NGT 8 4500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 5109BSD

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Sep-2021

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LM5109B :

• Automotive : LM5109B-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5109BMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5109BSD/NOPB WSON NGT 8 1000 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1
LM5109BSDX/NOPB WSON NGT 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5109BMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5109BSD/NOPB WSON NGT 8 1000 200.0 183.0 25.0
LM5109BSDX/NOPB WSON NGT 8 4500 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
LM5109BMA D SOIC 8 95 495 8 4064 3.05
LM5109BMA D SOIC 8 95 495 8 4064 3.05
LM5109BMA/NOPB D SOIC 8 95 495 8 4064 3.05
LM5109BMA/NOPB D SOIC 8 95 495 8 4064 3.05

Pack Materials-Page 3
 PACKAGE OUTLINE
NGT0008A SCALE 3.000
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

4.1 B
A
3.9

PIN 1 INDEX AREA

4.1
3.9

C
0.8 MAX
SEATING PLANE

0.05 0.08 C
0.00

EXPOSED
2.6 0.05 (0.2) TYP
THERMAL PAD

4 5

2X SYMM
9
2.4 3 0.05

8
1
6X 0.8
0.35
8X
SYMM 0.25
PIN 1 ID
0.5 0.1 C A B
8X
0.3 0.05 C

4214935/A 08/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
NGT0008A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(2.6)
8X (0.6) SYMM

1
8X (0.3) 8

SYMM 9
(3)

(1.25)
6X (0.8)
4 5

(R0.05) TYP
( 0.2) VIA
TYP (1.05)
(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

EXPOSED EXPOSED
METAL METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214935/A 08/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
NGT0008A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(0.675)

SYMM
METAL
8X (0.6) TYP

1
8X (0.3) 8

(0.755)
SYMM 9

6X (0.8) (1.31)

5
4

(R0.05) TYP
(1.15)

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4214935/A 08/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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