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    Design and Implementation of Static RAM Cell: Circuit Diagram of SRAM

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    komaladitya challa
    The document describes the design and implementation of a static RAM (SRAM) cell using Mentor Graphics tools. It provides details on: 1) The typical structure of an SRAM cell, which uses six transistors arranged in two cross-coupled inverters and two access transistors to store each bit. 2) The steps taken in Mentor Graphics to design the schematic, simulate it, create the layout, and verify the design through DRC, LVS, and parasitic extraction. 3) The key aspects of the SRAM cell design such as the schematic, simulation waveform, and layout creation. The overall goal of drawing and verifying the SRAM schematic and layout

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    © All Rights Reserved
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    Design and Implementation of Static RAM Cell: Circuit Diagram of SRAM

    Uploaded by

    komaladitya challa
    496 views4 pages
    The document describes the design and implementation of a static RAM (SRAM) cell using Mentor Graphics tools. It provides details on: 1) The typical structure of an SRAM cell, which uses six transistors arranged in two cross-coupled inverters and two access transistors to store each bit. 2) The steps taken in Mentor Graphics to design the schematic, simulate it, create the layout, and verify the design through DRC, LVS, and parasitic extraction. 3) The key aspects of the SRAM cell design such as the schematic, simulation waveform, and layout creation. The overall goal of drawing and verifying the SRAM schematic and layout

    Original Description:

    Sram

    Original Title

    SRAM

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    The document describes the design and implementation of a static RAM (SRAM) cell using Mentor Graphics tools. It provides details on: 1) The typical structure of an SRAM cell, which uses six transistors arranged in two cross-coupled inverters and two access transistors to store each bit. 2) The steps taken in Mentor Graphics to design the schematic, simulate it, create the layout, and verify the design through DRC, LVS, and parasitic extraction. 3) The key aspects of the SRAM cell design such as the schematic, simulation waveform, and layout creation. The overall goal of drawing and verifying the SRAM schematic and layout

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    496 views4 pages

    Design and Implementation of Static RAM Cell: Circuit Diagram of SRAM

    Uploaded by

    komaladitya challa
    The document describes the design and implementation of a static RAM (SRAM) cell using Mentor Graphics tools. It provides details on: 1) The typical structure of an SRAM cell, which uses six transistors arranged in two cross-coupled inverters and two access transistors to store each bit. 2) The steps taken in Mentor Graphics to design the schematic, simulate it, create the layout, and verify the design through DRC, LVS, and parasitic extraction. 3) The key aspects of the SRAM cell design such as the schematic, simulation waveform, and layout creation. The overall goal of drawing and verifying the SRAM schematic and layout

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 4

    Design and implementation of static RAM cell

    AIM:

    To draw the schematic and layout of the SRAM and to verify the simulation results using mentor
    graphics Tools

    APPARATUS:

     software mentor graphics

     hardware PC

    THEORY:

    SRAM (static RAM) is random access memory (RAM) that retains data bits in its memory as long as
    power is being supplied. Unlike dynamic RAM (DRAM), which stores bits in cells consisting of a capacitor
    and a transistor, SRAM does not have to be periodically refreshed. Static RAM provides faster access to
    data and is more expensive than DRAM.

    Circuit diagram of SRAM

    A typical SRAM cell is made up of six MOSFETs. Each bit in an SRAM is stored on four transistors (M1,
    M2, M3, and M4) that form two cross-coupled inverters. This storage cell has two stable states which
    are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell
    during read and write operations. In addition to such six-transistor (6T) SRAM, other kinds of SRAM chips
    use 4, 8, 10 (4T, 8T, 10T SRAM), or more transistors per bit. Four-transistor SRAM is quite common in
    stand-alone SRAM devices, implemented in special processes with an extra layer of poly silicon, allowing
    for very high-resistance pull-up resistors.

    The principal drawback of using 4T SRAM is increased static power due to the constant current flow
    through one of the pull-down transistors.
    Procedure:
    Mentor Graphics involves five basic steps.

    1. Design the schematic in Pyxis.


    2. Simulate the schematic and check for parameters.
    3. Layout the schematic in Pyxis.
    4. Perform physical verification using caliber which include DRC, LVS and PEX and net list
    extraction.
    5. Back annotation of parasitic into schematic.

    Schematic diagram

    Simulation:

    1. Create new project by clicking on File 🡪 new project. Assign the project name.
    2. Click on project name 🡪 select new library. Name the library and click ok.
    3. Click on library 🡪 new cell. Name the cell.
    4. Click on cell name 🡪 new schematic.
    5. Name the schematic and click ok which in turn leads to Pyxis schematic editor window.
    6. Place devices from add instance icon and change device properties from the object editor. Add IN
    and OUT ports, ground and VDD.
    7. Go to add 🡪 generate symbol. Select replace existing and activate symbol option. Click ok.
    8. Save the symbol and click for errors using check and save option.
    9. Close all schematic and symbol windows. Create test bench using cell name SRAM_tb. Add the
    symbol of schematic by add 🡪 instance 🡪 choose symbol.
    10. Now place required voltage sources and edit properties.
    11. Select simulation icon on left palette. Select a new configuration and then ac, dc, trans option.
    Select analysis setup and apply for dc and trans. Edit the parameters required.
    12. Select simulate 🡪 run simulation. View simulation results by selecting plot results from latest run
    icon from the left palette.

    Output waveform

    Creating a layout:

    1. Right click on cell name 🡪 new layout.


    2. Select pmos from schematic and pick and place icon from SDL tool bar. Similarly place nmos.
    3. To add substrate contacts to the MOSFET’s , select add device 🡪 path–based guard band 🡪psub.
    Similarly add nwell.
    4. Select DLA logic 🡪 port.
    5. Select DLA layout 🡪iroute*.
    6. Press space bar for metal change and complete the layout.
    7. Go to tools 🡪caliber🡪 run DRC. Check errors.
    8. Run LVS and check for tick mark. If not appeared, verify the errors.

    Creating a layout
    Precautions:

    1. Place the components and give the connections properly.


    2. Save the circuit immediately and check for errors.
    3. Connect the components in the layout carefully.

    RESULT:

    The schematic and layout of the SRAM is drawn and simulation results are observed and layout was
    drawn using mentor graphics tools.

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