A89307 Datasheet

A89307
Automotive FOC BLDC Motor Controller
FEATURES AND BENEFITS DESCRIPTION

• Code-free sensorless field-oriented control (FOC) The A89307 is a 3-phase, sensorless, brushless DC (BLDC)
• Constant speed, constant torque, constant power, and motor driver (gate driver) which can operate from 5.5 to 50 V.
open-loop operating modes
• I2C interface for speed control and status readback A field-oriented control (FOC) algorithm is fully integrated to
• Programmable, flexible in-to-output transformer achieve the best efficiency and acoustic noise performance.
• Ultra-quiet low speed operation Constant torque and constant power mode are provided as well
• Proprietary non-reverse fast startup as constant speed and open-loop operating modes.
• Soft-On Soft-Off (SOSO) for quiet operation The device also optimizes the motor startup performance in
• Analog / PWM / Clock mode speed control a stationary condition, a windmill condition, and even in a
• Closed-loop speed control reverse windmill condition.
• Configurable current limit
• Windmill startup operation Motor speed is controlled through analog, PWM, or CLOCK
• Lock detection input. Closed-loop speed control is optional, and RPM-to-clock
• Short-circuit protection (OCP) frequency ratio is programmable.
• Brake and direction inputs
• Adjustable gate drive A simple I2C interface is provided for setting motor-rated
• Automotive AEC-Q100 qualified voltage, rated current, rated speed, resistance, and startup
profiles. The I2C interface is also used for on/off control, speed
APPLICATIONS control, and speed readback.
• Battery cooling fan The A89307 is available in a 28-contact 5 mm × 5 mm QFN
• Radiator fan with exposed thermal pad (suffix ET) and wettable flank. The
• Fuel, oil pump package is lead (Pb) free, with 100% matte-tin leadframe plating.
PACKAGE
28-contact QFN
with exposed thermal pad
and wettable flank
5 mm × 5 mm × 0.90 mm
(ET package)
Not to scale
VBB
0.22 µF 0.22 µF
FG
CP1 CP2 VCP VBB
SPD GHx
FAULT
DIR
BRK
A89307 GLx
VREG
SENN SENP LSS
Figure 1: Typical Application – Functional Block Diagram
A89307-DS March 15, 2021

MCO-0001050
A89307 Automotive FOC BLDC Motor Controller
SELECTION GUIDE
Part Number Packaging Packing
A89307KETSR-J 28-contact QFN with exposed thermal pad and wettable flank 6000 pieces per 13-inch reel
ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Unit
Supply Voltage VBB 50 V
Logic Input Voltage Range VIN SPD, BRAKE, DIR –0.3 to 6 V
Logic Output VO FG, FAULT (I < 5 mA) 6 V
DC ±500 mV
LSS VLSS
tW < 500 ns ±4 V
VREG VREG –0.3 to 4 V
DC ±500 mV
SENN, SENP VSENN, VSENP
tW < 500 ns ±4 V
SA, SB, SC –2 to VBB + 2 V
Output Voltage VOUT
SA, SB, SC, tW < 50 ns –4 to VBB + 4 V
GHx VGHx VSx – 0.3 to VCP + 0.3 V
GLx VGLx VLSS – 0.3 to 8.5 V
VCP VCP VBB – 0.3 to VBB + 8 V
CP1 VCP1 –0.3 to VBB + 0.3 V
CP2 VCP2 VBB – 0.3 to VCP + 0.3 V
Junction Temperature TJ 150 °C
Storage Temperature Range Tstg –55 to 150 °C
THERMAL CHARACTERISTICS
Characteristic Symbol Test Conditions* Value Unit
Package Thermal Resistance RθJA 28-contact QFN (package ET), on 2-sided PCB 1-in.2 copper 40 °C/W
*Additional thermal information available on the Allegro website.
Table of Contents
Features and Benefits............................................................ 1 Motor Startup.................................................................... 9
Description........................................................................... 1 Motor Startup State Machine............................................. 10
Packages............................................................................. 1 External MOSFET Gate Drive............................................ 13
Typical Application................................................................. 1 Input-to-Output Transformer.............................................. 14
Selection Guide.................................................................... 2 Diagnostics..................................................................... 18
Absolute Maximum Ratings.................................................... 2 I2C Operation and EEPROM/Register Map......................... 20
Thermal Characteristics......................................................... 2 Write Command............................................................... 21
Terminal Diagram and Terminal List......................................... 3 Read Command.............................................................. 21
Functional Block Diagram...................................................... 4 Register and EEPROM Map................................................. 22
Electrical Characteristics........................................................ 5 Programming EEPROM....................................................... 31
Functional Description........................................................... 7 Application Information........................................................ 33
Speed Control................................................................... 7 Terminal Diagrams.............................................................. 34
Bus Current Sensing.......................................................... 9 Package Outline Drawing..................................................... 35
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
TERMINAL DIAGRAM AND LIST
22 BRAKE
26 FAULT
23 VREG
28 SENN
24 SPD
25 DIR
27 FG
SENP 1 21 NC
GND 2 20 CP1
NC 3 19 CP2
GLA 4 PAD 18 NC
GLB 5 17 VBB
GLC 6 16 NC
LSS 7 15 VCP
SB 10
SC 12
GHC 13
NC 14
GHB 11
SA 8
GHA 9
ET Package Terminals
Terminal List
Name Function Number
BRAKE Logic input 22
CP1 Charge pump 20
CP2 Charge pump 19
DIR Direction control 25
FAULT Fault indicator output 26
FG Motor speed output 27
GHA High-side gate drive output 9
GHB High-side gate drive output 11
GHC High-side gate drive output 13
GLA Low-side gate drive output 4
GLB Low-side gate drive output 5
GLC Low-side gate drive output 6
GND Ground 2
LSS Low-side source 7
3, 14, 16,
NC No connect
18, 21
SA Motor output 8
SB Motor output 10
SC Motor output 12
SENN Current sense negative terminal 28
SENP Current sense positive terminal 1
SPD PWM or clock mode speed control 24
VBB Power supply 17
VCP Charge pump 15
VREG 2.8 V regulator voltage 23
PAD Exposed pad for enhanced thermal dissipation PAD
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FUNCTIONAL BLOCK DIAGRAM
0.22 µF X5R
CP2
CP1
0.22 µF X5R 10 V
VREG
VREG
2.8 V 0.22 µF X5R
VREG Charge VCP
Clock 7.3 V Pump
mode
VBB
Analog to VBB
Duty
Universal
VREF
PWM to Curve
HSD GHA
Duty
GHB
SPD
GHC
VREF
SCL
OCP
SA
SDA
FG SB
Demand GATE
DRIVE SC
Control
I2C GLA
LSD GLB
EEPROM
BRAKE GLC
6
FOC
Controller LSS
Control
DIR Logic
VREF
Current SENP
Sense
FAULT Amp SENN
GND
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ELECTRICAL CHARACTERISTICS: Valid at TJ = –40 to 125°C, VBB = 5.5 to 28 V, unless noted otherwise
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
SUPPLY AND REFERENCE
Driving 5.5 – 48 V
Supply Voltage Range VBB
Operating 5.5 – 50 V
IVREG = 0 mA – 8 12 mA
VBB Supply Current IBB
Standby mode – 10 20 µA
Reference Voltage VREG IOUT = 10 mA 2.70 2.86 2.95 V
VREG Current Limit IVREGOCL VREG = 0 V 25 50 127 mA
VBB = 8 V, ICPAVG = 4.5 mA, relative to VBB 6.4 6.7 7.5 V
Charge Pump [2] VCP
VBB = 5 V, ICPAVG = 1 mA, relative to VBB 4.15 5 – V
GATE DRIVE UNIT
High-Side Gate Drive Output VGH VBB ≥ 8 V 6.75 6.9 – V
Low-Side Gate Drive Output VGL VBB ≥ 8 V 7.0 7.3 – V
Level 0, 45 V ≥ VBB ≥ 7 V 4.4 6.6 8.8 mA
Level 1, 45 V ≥ VBB ≥ 7 V 9.6 13 16.6 mA
Gate Drive Source Current ISO
Level 2, 45 V ≥ VBB ≥ 7 V 20.7 26.5 32.3 mA
Level 3, 45 V ≥ VBB ≥ 7 V 43.8 53.7 63.5 mA
Level 0, 45 V ≥ VBB ≥ 7 V 5.6 13.3 21.0 mA
Level 1, 45 V ≥ VBB ≥ 7 V 13.2 25.0 37.0 mA
Gate Drive Sink Current ISI
Level 2, 45 V ≥ VBB ≥ 7 V 33.8 50 66.5 mA
Level 3, 45 V ≥ VBB ≥ 7 V 73.5 98.4 123.3 mA
MOTOR DRIVE
PWM Duty On Threshold PWMON Relative to target –0.5 – +0.5 %
PWM Duty Off Threshold PWMOFF Relative to target –0.5 – +0.5 %
PWM input frequency setting = 0 2.5 – 100 kHz
PWM Input Frequency Range fPWM
PWM input frequency setting = 1 80 – 3200 Hz
Clock Input Frequency Range fCLOCK CLOCK mode 1 – 2000 Hz
SPD Standby Threshold
VSPD(TH_ENT) 50 100 150 mV
(Analog Enter)
SPD Standby Threshold
VSPD(TH_EXIT) 0.4 0.75 1.0 V
(Analog Exit)
SPD On Threshold VSPD(ON) ON/OFF setting = 10% 200 245 290 mV
SPD Maximum VSPD(MAX) – 2.5 – V
SPD ADC Resolution VSPDADC(RES) – 9.78 – mV
SPD ADC Accuracy VSPDADC(ACC) VSPD = 0.2 to 2.5 V –45 – 45 mV
PWM mode or Analog mode –5 – 5 %
Speed Closed-Loop Accuracy fSPD(ACC)
Clock mode –0.1 – 0.1 rpm
Dead Time tDT Code = 9 – 400 – ns
Motor PWM Frequency fPWM 23.06 24.4 25.74 kHz
Continued on next page...
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ELECTRICAL CHARACTERISTICS (continued): Valid over operating ambient temperature range and voltage range,
unless noted otherwise
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
PROTECTION
VBB UVLO VBB(UVLO) VBB rising – 4.75 4.95 V
VBB UVLO Hysteresis VBB(HYS) 200 300 450 mV
VREG UVLO VREGUVLO VREG falling – 2.6 – V
VCP falling 3.6 3.9 4.2 V
VCP UVLO VCPUVLO
VCP rising 3.9 4.2 4.5 V
Thermal Shutdown Temperature TJTSD Temperature increasing – 175 – °C
Thermal Shutdown Hysteresis ΔTJ Recovery = TJTSD – ΔTJ – 20 – °C
Level 0 0.89 1 1.11 V
VDS Comparator Threshold VDS_THR
Level 1 1.75 2 2.15 V
LOGIC, IO, I2C
Input Current (SPD, FG) IIN VIN = 0 to 5.5 V –5 1 5 µA
Input Current (BRK, DIR) IIN VIN = 5 V – 50 – µA
Logic Input Low Level VIL 0 – 0.8 V
Logic Input High Level VIH 2 – 5.5 V
Logic Input Hysteresis VHYS 200 300 600 mV
FG output leakage IFG V = 5.5 V – – 1 µA
FG, Fault saturation voltage VLOGIC_SAT I = 4 mA – – 0.3 V
SCL Clock Frequency fCLK 7 – 100 kHz
EEPROM
Number of Programming NPROG – – 1000 times
[1] Specified limits are tested at 25°C and 125°C and statistically assured over operating temperature range by design and characterization.
[2] The charge pump capacitors between CP1 and CP2, VBB and VCP are 220 nF ceramic capacitors.
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FUNCTIONAL DESCRIPTION
The A89307 is a three-phase BLDC controller with integrated close_loop_speed = rated_speed × duty_input
gate driver. It operates from 5.5 to 50 V, and targets battery cool- The SPD PWM frequency range is 80 Hz to 100 kHz. If it is higher
ing fan applications. than 2.8 kHz, set PWMfreq = 0; if it is lower than 2.8 kHz, set
The integrated FOC control algorithm achieves the best effi- PWMfreq = 1.
ciency and dynamic response and minimizes acoustic noise. Analog Mode: In the clock speed control mode, the closed-loop
Allegro’s proprietary Non-Reverse Startup algorithm improves speed is always enabled. Higher frequency on the SPD pin will
the startup performance. The motor will startup towards the target drive a higher motor speed as follows:
direction after power up without reverse shaking or vibration.
The Soft-On-Soft-Off feature gradually increases the current to closed_loop_speed = rated_speed × analog_input / SPDMAX
the motor at “on” command (windmill condition), and gradually
reduces the current from the motor at the “off” command, further The equivalent is true for closed-loop torque and power modes.
reducing the acoustic noise and operating the motor smoothly.
CLOCK Mode: When using clock mode, closed-loop speed
is always enabled. The default input for clock mode is the SPD
terminal, but there are options to use either the DIR or BRAKE
terminals instead. Either of these options allows use of the I2C
interface and clock mode at the same time. Higher frequency on
the clock input will drive a higher motor speed as follows:
close_loop_speed (rpm) = clock_input × speed_ctrl_ratio,
where the speed_ctrl_ratio can be programmed in the EEPROM.
For example, if the ratio is 4 and the clock input frequency is
60 Hz, the motor will operate at 240 rpm. Note the number of
motor pole pairs must be set properly in the programming appli-
cation for the rated speed (RPM) setting to be accurate.
If the clock frequency commands a speed that is higher than
twice the rated speed, A89307 treats it as a clock input error, and
stops the motor.
For all the three speed control modes with closed-loop speed
enabled, if the demand speed is higher than the maximum speed
Speed Control the system can run at a certain supply voltage and load condition,
the A89307 will just provide the maximum output voltage (if
Speed demand is provided via the SPD pin. Three speed control current limit is not triggered), or the maximum output current (if
modes are selectable through the EEPROM. The A89307 also current limit is triggered).
features closed-loop speed, torque, and power functions, which
can be enabled or disabled via the EEPROM. The SPD pin is also used as SCL in the I2C mode.
PWM Mode: In this mode, the motor speed is controlled by the Power Control: The A89307 has integrated power control
PWM duty cycle on the SPD pin, and higher duty cycle represents with speed control. The speed control will received the reference
higher speed demand. If open-loop mode is selected, the output speed from the demand interfaces. When the motor runs below
voltage amplitude will be proportional to the PWM duty cycle. If the current limit, the motor will operate as speed control. If the
closed-loop speed is enabled, the motor speed is proportional to the driving DC current reach to the DC current limit, ILIM, the control
PWM duty cycle, and 100% duty represents the rated speed of the overrides the speed control and provide the constant DC current
motor, when speed curve transformer is not active, which can be control.
programmed in the EEPROM. The equivalent is true for closed- The power control has two modes depending on VBB. If VBB is
loop torque and power modes. less than VPOW, the control will provide the DC current limit.
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When the motor runs with a load, which does not require ILIM, A rising edge on PWM or CLOCK will wake the IC in PWM and
the motor will run a constant speed as the demand interface CLOCK mode, and in Analog mode, the SPD voltage must be
requires. If the connected load requires ILIM to achive the target higher than SPDTH_EXIT to wake up the IC.
speed, the current control will be active and speed control will be
ignored. If VBB is greater than VPOW, the power control is active, Standby Mode will turn off all circuitry including the charge
and the controlled power is defined as PLIM. If the connected load pump and VREG.
requires greater than PLIM, the speed control is ignored and oper- After powering on, the device will always be in active mode
ates as constant power control. before entering standby mode.
VPOW can be selected by PowCon_Vol_lim. The DC current
Standby mode can be disabled in the EEPROM.
limit, ILIM, can be selected by IDC_lim. When VBB is above
VPOW, then the power limit, PLIM, is defined as VPOW × ILIM. Direction Input: Logic Input to control motor direction. For logic
high, the motor phases are ordered A→B→C. For logic low, the
Current Control Power Control
motor phases are ordered A→C→B. The A89307 supports chang-
ing the direction input while the motor is running. The direction
can also be controlled through register.
I LIM
DC Current [A]
BRAKE: Active High signal turns on all low sides for braking
PLIM = VPOW × I LIM function. The brake function overrides speed control input. Care
should be taken to avoid stress on the MOSFET when braking
while motor is running. With braking, the current will be limited
only by VBEMF/RMOTOR. The A89307 includes an optional
feature which holds off braking until the motor speed drops to a
low enough (configurable) level so that the braking current will
VPOW
not damage the MOSFET.
VBB[V] FAULT: Open-drain output provides motor operation fault status.
Figure 2 : Power Limit Default is high when there is no fault.
Motor Stop and Standby Mode: If the speed demand is less The detail of FAULT signal pattern is shown below. The priority
than the programmed threshold, the motor will stop. indicates that when multiple faults occur, higher priority signal
will be indicated.
On/Off setting On threshold Off threshold
5.8% 7.9% 5.8% Fault type Priority FAULT pin
9.7% 11.8% 9.7% Lock detected 5 low
12.8% 15.0% 12.8% OCP 4 0.67 seconds high

0.67 seconds low
19.5% 21.6% 19.5%
OTP 6 0.67 seconds low
0.17 seconds high
For example, consider 10% is set as the threshold. If PWM duty 0.08 seconds low
is less than 9.8% (in PWM mode), or the analog voltage is less 0.17 seconds high
than 250 mV (in Analog mode), or the CLOCK input frequency 0.08 seconds low
0.17 seconds high
is less than 9.8% of the “rated_speed” (in CLOCK mode), the IC
system error 2 0.08 seconds low
will stop the motor and enter the “idle” mode. 0.08 seconds high
0.08 seconds low
In order to enter standby, two conditions must be met: 1.09 seconds high
1. The motor must be stationary (this requirement can be re- OVP 1 0.17 seconds high
0.17 seconds low
moved by setting the EEPROM), and
zero speed demand 3 0.25 seconds high
2. PWM or CLOCK signal remains logic low (in PWM and 0.08 seconds low
CLOCK mode), or the analog voltage remains less than 0.34 seconds high
0.67 seconds low
SPDTH_ENT (in Analog mode) for longer than one second.
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FG: Open-drain output provides motor speed information to the to prevent the signal saturation. For example, if the rated current is
system. The open-drain output can be pulled up to VREG or an 4 A, using a 15 mΩ sensing resistor is recommended, so that 4 A ×
external 3.3 or 5 V supply. 15 mΩ is between 55 and 65 mV.
The FG pin is also used as SDA in the I2C mode. The first I2C Use Kelvin sensing connection for the shunt resistor.
command can pass only when FG is high (open drain off). After
the first I2C command, the FG pin is no longer used for speed
information, and the FG pin is dedicated as a data pin for the I2C
interface.
FG is default high after power on and exit from standby mode,
and it remains high for at least 9.8 ms. To ensure successful I2C
communication, it is recommended to have the first I2C demand
within 9.8 ms after power up or exit from standby mode.
FG function can be disabled in EEPROM; then the FG pin will
Lock Detect: A logic circuit monitors the motor position to
be dedicated as the SDA signal for I2C. If observing FG signal
determine if motor is running as expected. If a fault is detected,
is required in I2C mode, the FG signal can be reassigned to the
the motor drive will be disabled for the configurable tLOCK time,
FAULT pin by sending the I2C command 0x00A0 to address 195
before an auto-restart is attempted. For additional information,
(decimal). To return Fault to normal operation, send the I2C com-
refer to the application note.
mand 0x0000 to address 195 (decimal).
Current Control: The motor’s rated current at rated speed and
VREG: Voltage reference (2.8 V) to power internal digital logic normal load must be programmed to the EEPROM for proper
and analog circuitry. VREG can be used to power external cir- operation. The A89307 will limit the motor current (phase current
cuitry with up to 10 mA bias current if desired. A ceramic capaci- peak value) to 1.3 times the programmed rated current dur-
tor with 0.22 µF or greater is required on the pin to stabilize the ing acceleration or increasing load, which protects the IC and
supply (X8R rating or better is recommended). the motor. The current profile during startup can also be pro-
When VREG is loaded externally, the power consumption of the grammed.
internal LDO is calculated by the equation: Overcurrent Protection (Short Protection): The VDS
PLDO = (ILOAD + IINTERNAL) × (VBB – VREG). voltage across each power MOSFET is monitored by the A89307.
When a MOSFET is switched on, its VDS is ignored for the
Ensure that the system has sufficient power dissipation and the programmable blank time. Also, the VDS comparator is always
temperature remains within the operating temperature range. filtered with a programmable filter time. If an enabled MOSFET
A89307 thermal shutdown function does not protect the LDO. VDS is higher than the threshold after blank time and for longer
than filter time, an OCP fault is triggered and the IC will latch all
Bus Current Sensing MOSFETs off.
A single shunt-resistor connecting between SENN and SENP is
used to measure the bus current for FOC algorithm and current Motor Startup
limit. The resistor value is about tens of a milliohm, depends on the The A89307 provides a robust open-loop startup to ensure the
rated current of the system. The integrated shunt-resistor amplifier motor spins in feedback control. When the motor is in standstill,
has a gain of 14.5, and the output range is 0 to 1 V. The voltage there is no BEMF information available, so the open-loop startup is
difference between SENN and SENP should be less than 65 mV required.
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Motor Startup State Machine

The A89307 has its own dedicated state machine to determine
motor rotation conditions to provide robust startup. The following Start
flowchart displays mode processing.
When the device accepts the start command, the controls check
the BEMF comparator to determine windmilling condition.
If the motor is spinning backwards, the controller applies brake
until the brake current disappears.
If the motor spinning is forward, the controller synchronizes driv- Start
Command?
ing frequency and goes into full sensorless control.
When the motor is at a standstill, the controller applies the rotor
alignment and starts the motor control.
Yes
Forward
Windmilling Brake
?
Yes
zero braking
current?
Yes
Motor
spinning
forward?
Alignment
Yes
FOC
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Rotor Alignment: When the A89307 is commanded to spin the Open-Loop Startup: When the A89307 completes rotor align-
motor, the controller will execute motor rotor alignment to ensure ment, an open-loop startup will be executed. In this mode, the
the rotor is parked at a known position. There are four different amplitude of phase current will be regulated to provide a stable
modes to achieve rotor alignment or detection. torque. The driving frequency will be ramping up until stable
BEMF is generated. Once the open-loop startup is completed, the
The first option is “Align&Go”. The A89307 applies a low driv-
A89307 will be in sensorless FOC control technique.
ing frequency with current control to the winding in order to gen-
erate a known position flux into the rotor. The permanent magnet The regulated open-loop startup current can be selectable by pre-
integrated rotor will be gravitated to the flux. determined levels, which are stored in EEPROM. The A89307
provides three levels of configurations. There is an activation bit
The second option is “two-pulse IPD”. This method uses salient
in the I2C register, strtp_lock_rtry_curr_lvl_en. When it is 0, the
and winding saturation characteristics to determine rotor posi-
startup current will be always constant. If it is 1, the automatic
tion. There are two stages to complete two-pulse IPD. The first
startup current level control is active.
stage applies test pulse sequences to the motor. If there is enough
saliency, the A89307 will lock up the rotor position within At the first startup attempt, the A89307 always use Level 1,
30 degrees, from 0 to 180 degrees or 180 to 360 degrees. startup_current_lvl1[2:0], and if the startup is ended up with fail,
stopped by stall detection, next startup attempt will be Level
When the first stage is completed, the A89307 will apply a test
2, startup_current_lvl2[2:0]. The startup current level will be
sequence to check the inductance saturation in order to check
increased until Level 3, startup_current_lvl3[2:0]. If the startup
the magnet pole. Once these entire sequences are completed, the
fails using Level 3, the A89307 will continue using Level 3. When
A89307 can determine the rotor angle within 30-degree accuracy.
the demand is set to idle state, the current leveling system will be
The third option is “six-pulse IPD”. In this mode, the A89307 reset to Level 1. The current level sequence is shown below.
will only use inductance saturation characteristics to determine
the rotor position. Once the sequence is completed, the A89307
will determine rotor angle within 60 degrees.
The fourth option is “slight-move mode”. In this mode, a test
sequence will be inserted to check saliency characteristics, which Level 3
Level 2
are described in the second option. When the test sequence is Startup
completed, the controller determines a rough position. At this Current Level 1
stage, the error might be 180 degrees or none. After it completes,
t
the controller will energize the winding based on the determined
position. Two of the three phases are driven with duty cycle con-
trol, which can be programmed by slight_mv_demand[2:0] and Level 1
the remaining phase is undriven. While the controller is energiz-
Level 2
ing the bridge, the controller will wait for a BEMF zero-crossing First cycle
edge on undriven phase. When the zero-crossing event is happen- speed Level 3
ing, the rotor will spin and gravitate to the energized angle. After
completion, the controller inserts the saliency characterization t
sequence again for comparison. If there is no error, the deter- Startup Startup Startup
mined parked position is correct; if there is an error, the controller Fail Fail Fail
accounts for it and determines the parked position.
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Open-Loop Startup Current Profile: The A89307 has a eters that define startup current: I_limit_slope_1, I_limit_slope_2,
feature to modify the ramp-up period. This feature helps mini- Speed_1, Rated_Current, Startup_Current. Startup current is
mize acoustic noise from the open-loop startup to the sensorless defined by Startup_current when strtp_lock_rtry_curr_lvl_en is 0.
control. Current amplitude is a factor at any given driving speed When strtp_lock_rtry_curr_lvl_en is 1, Startup_current_lvX will
and load to maintain the appropriate phase advance. The appro- be used to determine the Startup Current level. Refer to Open-
priate current level depends on motor property and connected Loop Startup section for further details.
load. For reliable startup, the startup current must be high enough
After the alignment period is executed, the phase current limit
to spin the motor. The startup current is usually set higher than
will be ramping down by following I_limit_slope_1 until the
the required current to gain enough startup torque, but this incurs
driving frequency reaches Speed_1. When the driving frequency
phase advance error. It is also necessary to meet various startup
is greater than Speed_1, then the phase current limit will be
load conditions to have robust startup. To achieve a quieter transi-
ramping up by following I_limit_slope_2 until it reaches Rated_
tion, it may be possible to reduce the current towards the end of
current.
the open-loop startup period if load conditions permit. When the
current level is closer to the required current level in feedback Note that the phase current limit should be sufficient to drive at
control, then transition noise may be able to be minimized. any given driving condition; otherwise, the driving performance
may be insufficient.
The startup current profile can be enabled via two_slope_m.
When it is 1, two slope system is active. There are several param-
Alignment Open-Loop Startup Feedback Control

Rated_Current
I_limit_slope_2
Startup Current
I_limit_slope_1
CurLim_1
IPhase
Speed_1
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External MOSFET Gate Drive It is required to enable three-stage current control; otherwise,
two-stage current control is applied. If gdPulse[2:0] is set to a
The A89307 is designed to work with external, low on-resistance value other than 000, then the three-stage current control will
power N-channel MOSFETs. It will supply the large transient be enabled. If it is set to a non-zero value, the period of tslew is
currents necessary to quickly charge and discharge external defined. The amount of Islew is defined by gdPulseCurrent[1:0]. If
MOSFET gate capacitance in order to reduce dissipation in the it is 00, three-stage current control is disabled.
external MOSFET during switching. The charge current for the
low-side MOSFETs are provided from an internal regulated sup-
ply. The charge current for the high side is provided from VCP Gate
Gate
Command
Command
supply, which is delivered from the integrated charge pump.
The VCP voltage is regulated at 6.8 V in order to supply enough State OFF I1 ON
voltage to turn on the high-side MOSFETs. The VCP voltage is
monitored by dedicated monitor circuit. If the VCP voltage drops
Miller Region
to a certain level, defined as VCPUVLO, then the A89307 stops the VGS
control and the MOSFETs will be turned off in order to protect
the external MOSFET from an abnormal situation.
Gate Control: The A89307 provides multiple gate driving
strengths to optimize the emission level. Fast slewing rate on
VDS
VDS makes the emission level high, but it reduces switching
loss. If the slewing rate is slow, then the emission level is low but
switching loss is increased. It is essential to assess the tradeoff to
ensure target performance.
Figure 3: Off-to-On Transition (Slew Rate Control)
The A89307 has a four-level current control to drive the gate. The
gate control has two stage current control to turn on the external Gate
Gate
MOSFET. When the controller gives the command to turn on, Command
Command
it provides a constant current source, I1 in the figure, which can State ON Islew I1 OFF
be programmed by the register drive_gate_slew[1:0] to the gate.
The charging currents are defined in the Electrical Characteristics
table. When VDS voltage is reached lower than VDS thresh- VGS Miller Region
old voltage, defined by vds_threshold_sel, the control provides
maximum current to reach the higher gate voltage as quickly as
possible to minimize the on-resistance on the external MOSFET.
The gate control has a three-stage current control to turn off the
VDS
external MOSFET. This provides faster switching speed com- tslew
pared with two-stage control. Until reaching the Miller region,
VDS will not start slewing, so a faster rate can be applied in order
to minimize dead time without compromising emission perfor-
mance. Figure 4: On-to-Off Transition (Slew Rate Control)
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Input-to-Output Transformer That setting specifies the maximum speed, torque, or power that
the application requires, and corresponds to the value 511. For
The A89307 implements an optional, highly flexible input-to- example, in closed-loop speed mode, if the ‘control loop range’
output mapping ability. The configuration is stored in EEPROM setting is set to 1000 rpm, then a transformer output value of 255
addresses 32 through 63. Fundamentally, the transformer is a will result in the motor spinning at 500 rpm.
9-bit (0 to 511) to 9-bit (0 to 511) transfer function, where the
meaning of the output values changes depending on the selected Only the ‘corner points’ of the desired curve are stored in the
control mode. The transformer operates in whichever of the four EEPROM, one point per address, and the remaining points
control modes is chosen: as a speed curve transformer, a torque are calculated using linear interpolation. The 9 MSBs of the
curve transformer, a power curve transformer, or as a demand EEPROM address are the input demand at the corner point, and
transformer in open-loop control mode. the 9 LSBs of the address are the output demand for that point.
If open-loop mode is selected, the specified output value deter- Only as many addresses that are needed to define the desired
mines the duty cycle applied to the motor. Thus, a value of 511 curve must be programmed. The last point defining the curve
will cause the peak voltage applied to the motor to be the full must have 511 as the input value, and all the following addresses
VBB voltage. If one of the closed-loop modes is selected, the in the EREPOM will be ignored. As many as 32 corner points can
output range is determined by the ‘control loop range’ setting. be stored, allowing for precise control of the demand.
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Example 1: These screenshots are taken from the A89307 application—white boxes are the entered values. This is the most trivial
example, where input = output. This is the curve that is used when the transformer is disabled. Because 511 is the input value in the
second address, the 30 following addresses are ignored.
Example 2: In this example, the control loop is set to closed-loop speed, and so the resulting rpm is shown in the last column of the
table where the curve is defined. This curve is designed to avoid this motor’s resonant frequency at 2000 rpm, and its harmonics at
4000 rpm and 6000 rpm.
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Example 3: Hysteresis can be implemented by setting the input value of an address lower than the input value in the previous address.
In this example, as the input demand is rising, the output demand will jump to next higher level at the vertical lines on the right of
each transition. When the input demand is falling, the output demand will drop to next lower level following the vertical lines on the
left of each transition. This prevents output jitter when the input is around a boundary.
Example 4: In this example, the motor won’t turn on until the input is about 30% and will turn off when the output falls below about
20%. The output will be at maximum when the input is between about 88% to 98%, and the motor will stop when the input is > 98%.
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Example 5: The curve can be set to control bi-directional operation as well. When the bidirectional option is selected, the output value
511 is still the highest output in one direction, but the output value 255 will stop the motor, and the output value 0 is the highest output
in the reverse direction. Here, the motor will run at half speed reverse when input demand is 0, will stop when the input is between
230 and 280, and will run at full speed forward when the input is 511.
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Diagnostics There are two filter systems to avoid mis-triggering OCP. When a
gate command is inserted, OCP detection is masked for the period
Lock Detect: The A89307 provides two lock detection options. of tBLANK. The period and target MOSFET can be selected via
The first option is a BEMF lock detection scheme. The A89307 OCP_Masking. The blanking timer should cover up to the Miller
has Kt, a mechanic constant observer to monitor the motor region to have robust operation. There is also an additional filter,
rotation. When it is active, the observer continuously estimates which is filtering timer. While the gate is on, an overvoltage will
Kt based on the given control parameters, and the control is be masked for the blanking time, tFIL to avoid misdetection. The
compared with the given Kt. When the estimated Kt exceeds the filtering time can be selected via OCP_Enable. The timing chart
threshold, the control detects a stall. is described in the OCP timing diagram below. OCP threshold
The second option is startup lock detection. When the motor start voltage can be selected via vds_threshold_sel. The threshold is
to rotate, the controller is forcing the frequency to ramp up speed, specified in the Electrical Characteristics table as VDS_THR.
and at the same time, the internal observer monitors the generated
phase advance. At the end of the ramp-up period, the measure- Gate Comand
ment is taken of the motor phase advance; if the generated phase
VDS_THR
advance is more than the specified angle, the control detects a
stall. The threshold angle can be set via Angle_Error_Lock.
VDS
When a stall is detected, motor control is stopped, and the motor
will be coasting. The controller will attempt to restart after the
period of 5 or 10 seconds, which can be selected by Lock_ tBLANL tFIL
restart_set. When Lock_restart_cm is set as 0, the hold period is
specified as Lock_restart_set. If Lock_restart_cm is 1, there will OCP
be no hold period prior to restart.
The number of repeats can be set to 3, 5, 10, or ‘always’. When Figure 5: OCP timing diagram
‘always’ is selected, the controller will always restart the motor.
When ‘non-always’ values are selected, the controller will System Error: A system error occurs when the charge pump
attempt to restart up to the specified number; when exceeded, the voltage or the internal regulator which supplies the low-side gate
controller will hold at the lock detect state until zero-demand is drivers falls below the respective undervoltage threshold, VBB
inserted. When the controller receives zero-demand, then the lock voltage rises above the threshold voltage or a demand PWM
detect counter is reset. frequency error is detected. The motor outputs are disabled on a
system error and will remain off until the voltage that caused the
OCP: The A89307 has overcurrent detection in order to protect error rises above the respective UVLO threshold plus hysteresis.
the external power MOSFET. The OCP fault has highest priority; The FAULT terminal indicates system when it is triggered. The
when it is detected, the control immediately takes an action. detail is described in FAULT section.
The OCP monitors the all six VDS voltages on the external OVP: The A89307 has VBB overvoltage protection. If ovp_en is
power MOSFETs when it is commanded on. When excessive set as enable, when VBB exceed 18 V, the motor control will be
voltage appears, then the control will detect the fault and turn stopped, and the motor will coast. The exact overvoltage thresh-
off all MOSFETs. The control will be in OCP fault mode. Fault old is specified as VBBOV_RIS. When VBB goes below the level,
recovery depends on configuration, OCP_reset_mode. When it VBBOV_FAL then motor will try to restart immediately.
is 0, the motor will only restart when the zero-speed demand is
inserted. When it is 1, the control automatically restarts the motor If ovp_en is set as disable, VBB overvoltage protection is dis-
after 5 seconds. If OCP_rst_cnt is set as 0, the hold period speci- abled. There will be no flag on FAULT terminal by this fault and
no protection will be applied.
fied as OCP_reset_mode. If OCP_rst_cnt is 1, there will be no
hold period prior to restart. The external power FET devices may Zero Speed Demand: The A89307 provides zero-speed
overheat due to repeated overcurrent conditions while the fault demand indication. When the curve transformer is active, the
remains, and overheating may cause damage to the MOSFET. resultant demand will be considered. When the device receives
Care must be taken by the user for any abnormal conditions. zero demand, it will be detected. The zero-speed demand is indi-
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cation only. When the device receives a demand other than zero
speed, the flag will be removed automatically.
Overtemperature: The A89307 has internal self-protection
from overheating. When the internal temperature exceeds the
threshold, TJTSD, the motor control is stopped, and the motor will
coast. When the temperature returns to normal operating range,
TJTSD – ΔTJ, then the motor will automatically restart if the
demand is inserted
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I2C Operation and EEPROM/Register Map

The I2C interface allows the user to write to and read from the internal registers, and to program parameters into the EEPROM (writ-
ing to EEPROM is explained later in this document). The A89307 I2C 7-bit slave address, also referred to as the device ID, is fixed at
0x55. The figures below show the I2C interface timing.
Upon power-up, the data in the EEPROM is loaded into a group of the internal registers (referred to as shadow registers), and those
registers control the system operation. The register values can then be overwritten via the I2C port, and this will change the system
operation on the fly. Any changes to the shadow registers will be overwritten upon the next power-up. Likewise, any changes made to
the EEPROM will have no effect until the next power-up. The one exception to this is the data defining the input transformer curve,
which does not have associated shadow registers—the data defining the curve is read directly from EEPROM during operation.
The addresses of the shadow registers are offset from their associated EEPROM addresses by 64. For example, EEPROM address 10
is loaded into shadow register 74 upon power-up. To change a parameter on the fly that is contained in EEPROM address 10, the data
must be written to register 74 using the I2C port. There are no shadow registers associated with EEPROM addresses 0 through 7, or
with addresses 32 through 63.
The following diagrams illustrate how to read and write to the registers using the I2C port.
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Write to a register:
• Start condition
• 7-bit I2C slave address (1010101), R/W Bit = 0 (write)
• Internal register address
• 3 data bytes, MSB first
• Stop condition
from slave device from slave device from slave device from slave device from slave device
Slave Address Register Address Data Byte 3 Data Byte 2 Data Byte 1
START STOP
SDA A6 A5 A4 A3 A2 A1 A0 W ACK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 ACK D23 D22 D21 D20 D19 D18 D17 D16 ACK D15 D14 D13 D12 D11 D10 D9 D8 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
SCL
Figure 6: Write to an I2C register
Read from a register: a two-step process:

• Start condition
• 7-bit I2C slave address (1010101), R/W bit = 0 (write)
• Internal register address to be read
• Stop condition
from slave device from slave device

Slave Address Register Address
START STOP
SDA A6 A5 A4 A3 A2 A1 A0 W ACK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 ACK
SCL
• Start condition
• 7-bit I2C slave address (1010101), R/W Bit = 1 (read)
• Read 3 data bytes
• Stop condition
from slave device from master device from master device NACK (no ACK) from master device
Slave Address Data Byte 3 Data Byte 2 Data Byte 1
START STOP
SDA A6 A5 A4 A3 A2 A1 A0 R ACK D23 D22 D21 D20 D19 D18 D17 D16 ACK D15 D14 D13 D12 D11 D10 D9 D8 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
Figure 7: Read from an I2C register
I2C Continuous Read

Note the master sends an ACK after each byte is received. After the 3 bytes of one register address is received, the master typically
sends a NACK (no ACK) to indicate the transmission is complete. Alternatively, the master may continue reading from the next
address by sending an ACK after the last byte, and the A89307 will begin sending data byte 3 of the next higher register address on the
next clock edge. The A89307 will continue sending data from the next higher address until it receives a NACK. This allows for read-
ing data from multiple registers quickly, without needing to write each specific address per the first step of this process.
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REGISTER AND EEPROM MAP

Each register bit is associated with one EEPROM bit. The reg- application’s settings file contains one line for each EEPROM
ister address is the associated EEPROM bit address plus 64. For address, containing addresses 8 through 63, but skipping address
example, rated_speed is in EEPROM address 8, bits[10:0]; the 31 (55 lines/addresses total).
associated register address is 72, bits[10:0]. Addresses 0 through 5 and address 31 are factory-locked and can-
In the following table, the bits that are not described should be not be changed.
kept at their default values. Changing these values may cause Registers not shown in the table are not for users to access.
malfunction or damage to the part. If programming the EEPROM Changing the value in undocumented registers may cause mal-
with a custom programmer, it is recommended to use the A89307 function or damage to the part.
application to determine the appropriate settings, save the settings
file, and use the file contents to program to the EEPROM. The
EEPROM address 6, (No shadow register associated)

Bits Name Description
17:0 Reserved The contents shall be kept as default.
EEPROM address 7, (No shadow register associated)

EEPROM address 8, Shadow register address 72

15:15 PWMin_range Input PWM frequency range selection
0: > 2.8 kHz
1: ≤ 2.8 kHz
14:14 Direction Direction of motor rotation
0: A→C→B
1: A→B→C
13:13 Accelerate_range Acceleration range used for Startup Acceleration setting (Hz/s)
0: 0 to 816
1: 0 to 12.75
12:11 Clock_PWM SPD input mode
0: PWM mode
1: Clock mode (using PWM input)
2: Clock mode (using BRAKE input)
3: Clock mode (using DIR input)
10:0 Rated_speed This is the max speed used in the application.
In clock mode, this sets the max frequency, when PMW = 100%
Rated Speed (Hz) = Rated_speed_register_value × 0.530

17:8 I_limit_slope_1 Quieter Start-up current slope configuration 1
7:0 Acceleration Specifies the motor acceleration rate at startup.
This setting’s range is selected with the Accelerate_range setting, (Hz/s)
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15:13 Startup_current Initial startup current limit (scale factor relative to Rated Current).
1 through 7: Startup Current = Rated Current × 1/8 × (value + 1).
Do not set to 0.
11:11 SPD_mode SPD input mode.
0: Digital (PWM or Clock mode).
1: Analog.
10:0 Rated_Current This is the motor current when running at the Rated_speed setting.
Rated Current (mA) = Rated_current_register_value / (Sense_resistor_register_value / 125).

17:7 Speed_2 Quieter startup current slope transition frequency
6:6 Max_curr_start Start-up current setting
0: Startup current is limited by startup_current
1: Ignore the control demand for the startup use 100% demand
5:5 Reserved Shall set this bit as 0
4:4 open_ph_protection Open-phase protection

0: Disabled
1: Enabled
3:3 Open_Drive Open-drive debug control
0: Normal operation
1: Motor will be driven in open loop, Rated speed is then the target speed. Internally, the PID control
coefficient Kp will be set 0.
0:0 fg_standb_en FG feedback enable at standby mode

0: Disabled
1: Enabled
16:16 Open_Window Opens a window for inductance tuning – see Application Note
0: Normal operation
1: Window opened
15:5 PWM_output_frequency Controls the output PWM frequency
4:0 PID_P Position observer PI loop proportional constant
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14:14 delay_start Delay startup (for startup modes other than “Align & Go”)
0: VBB must be stable within 25 ms after applying start signal
1: VBB must be stable within 100 ms after applying start signal
7:6 Startup_mode 00: 6-pulse mode
01: 2-pulse mode
10: Slight-move mode
11: Align & Go
3:3 Power_Ctr_En Power Control Enable
0: Disable the current and accelerate and decelerate buffers
1: Enable the current limit and accelerate and decelerate buffers
2:0 PID_I Position observer PI loop integration constant


16:14 Safe_Brake_thrd Current below which to allow braking, relative to Rated current
00: 1×
01: 2×
10: 4×
11: 8×
13:8 Deadtime_setting Deadtime selection
0 through 64: (value + 1) × 40 ns
7:7 soft_on 0: Disabled
1: Gradually increases the current at startup during a windmilling startup
6:6 soft_off 0: Disabled
1: Gradually reduces the current at motor stop
3:2 Angle_Error_Lock Lock detect during startup.
00: disabled
01: 5 degree
10: 9 degree
11: 13 degree
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13:12 BEMF_Lock_filter Determines the filter time for the BEMF lock detection
00: Lock detection disabled
01: Robust
10: Medium
11: Sensitive
11:10 Decelerate_buffer Determines how quickly the output command can slew
00: No buffer
01: Fast buffer
10: Medium buffer
11: Slow buffer
9:8 Accelerate_buffer Determines how quickly the output command can slew
00: No buffer
01: Fast buffer
10: Medium buffer
11: Slow buffer
7:6 First_cycle_speed Determines the align duration for Align & Go startup mode
00: 2.23 Hz (0.4484 seconds)
01: 0.53 Hz (1.9 seconds)
10: 0.265 Hz (3.78 seconds)
11: 0.132 Hz (7.55 seconds)
5:4 OCP_Masking OCP comparators mask/blank time. Mask/blank occurs at output on/off transition
00: No masking
01: 320 ns mask
10: 640 ns mask
11: 1280 ns mask
3:3 OCP_reset_mode Determines when to restart motor after OCP is tripped
0: Upon motor restart
1: After 5 seconds
2:0 OCP_Enable OCP filter time and HS/LS OCP enabling. If an overcurrent condition exists at the time the OCP mask
expires, the OCP filter time must pass before an OCP fault is triggered.
000: No Filter, HS/LS OCP Enabled
001: 120 ns, HS/LS OCP Enabled
101: 480 ns, LS OCP Enabled, HS OCP Disabled
110: 480 ns, LS OCP Disabled, HS OCP Enabled
111: 480 ns, HS/LS OCP Disabled

17:11 Reserved This register needs to set TBD.
9:9 i2c_speed_mode Input command via I2C enable
0: IC terminals are used for user input command, according to settings
1: Speed_demand setting in this register is used for user input command
8:0 Speed_demand Speed demand input, when i2c_speed_mode is enabled
0→511 represents 0→100%
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15:14 drive_gate_slew Gate driver current control.
Refer to the Electronics Characteristics table
00: Level 0
01: Level 1
10: Level 2
11: Level 3
13:8 IPD_Current_Thr IPD current threshold (A) = IPD_current_thrd_value × 0.086

16:16 Brake_control I2C brake mode input when BRK_from_reg = 1
0: Normal running
1: Brake mode applied
15:12 mosfet_comp_falling MOSFET CISS compensation, current falling.
Refer to the application note.
11:8 mosfet_comp_rising MOSFET CISS compensation, current rising.
Refer to the application note.
7:5 gdPulse Duration control of high-side and low-side turn off pulse current
000: Disabled
001: 40 ns
010: 80 ns
011: 120 ns
100: 160 ns
101: 200 ns
110: 240 ns
111: 280 ns
4:3 gd_PulseCurrent Pulse current amplitude setting
00: Disabled
01: Level 1
10: Level 2
11: Level 3
2:0 inductance_shift Motor inductance multiplier – the inductance setting is multiplied by 2n

17:17 Brake_input Motor brake mode control option
0: Brake is controlled via the device terminal
1: Brake is controlled via the I2C direction register
16:16 DIR_from_reg Motor direction control option
0: Direction is controlled via the device terminal
1: Direction is controlled via the I2C direction register
15:8 Sense_Resistor Sense resistor value (mΩ) = sense_resistor_value / 3.7
7:0 Rated_Voltage Motor rated voltage (V) = Rated_voltage_register_value / 5
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17:8 I_limit_slope_2 Quieter Start-up current slope configuration 2
7:5 slight_mv_demand Amplitude demand used for slight move startup mode
(%) = value × 3.2 + 2.4
4:3 speed_input_off_ Input threshold below which the motor is turned off.
threshold If the input transformer curve is enabled, this is applied after (to the output of) the transformer curve.
00: 9.7 %
01: 5.8 %
10: 12.8 %
11: 19.5 %
2:2 two_slope_m Startup current profile enable
0: Disabled
1: Enabled

15:15 vds_threshold_sel Short-circuit protection VDS threshold
0: 1 V
1: 2 V
12:12 Deadtime_comp Deadtime compensation enable
0: Disabled
1: Enabled
11:11 Lock_restart_set How long to wait before restart after lock detect is triggered
0: 5 seconds
1: 10 seconds
10:10 vibration_lock Vibration lock detect
0: Disabled
1: Enabled
9:9 Soft_off_4s Soft-off duration
0: 1 second
1: 4 seconds
8:8 Brake_mode Brake mode
0: Brake when safe, according to the Safe_brake_thrd setting
1: Always brake, 100% uncontrolled
7:6 Restart_attempt When to restart after lock detect is triggered
00: Always
01: 3 times
10: 5 times
11: 10 times
5:0 clock_speed_ratio The ratio between input frequency and rpm, used during clock mode.
(rpm/Hz) = clock_speed_ratio_value × 0.25.
The maximum clock_speed_ratio value is 41; higher values will cause errors.
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17:17 check_curve Input transformer curve enable
0: Input curve disabled
1: Input curve enabled
16:16 speed_cur_bidir Input transformer curve single or bi-directional mode
0: Input curve operates in a unidirectional mode and the direction is set by the device terminal or via I2C register
1: Input curve operates in a bidirectional mode where the value 0 is the fastest reverse direction, 511 is the fasted
forward direction, and 255 will stop the motor
12:11 operation_mode Control loop mode
00: Open loop operation, output voltage magnitude set by input demand
01: Constant torque operation, torque range is set by parameterFull (eeprom_23[10:0]) × demand (as ratio) )
10: Constant speed operation, speed range is set by parameterFull (eeprom_23[10:0]) × demand (as ratio) )
11: Constant power operation, power range is set by parameterFull (eeprom_23[10:0]) × demand (as ratio) )
10:0 parameterFull Used in constant speed/torque/power control loops to set the maximum control setpoint. This value is the
setpoint when the input demand is 100%.

7:0 motor_resistor Motor phase terminal to center-tap resistance (phase-phase resistance / 2).

17:15 startup_current_lvl3 Retry startup current level 3
14:12 startup_current_lvl2 Retry startup current level 2
11:11 strp_lock_rtry_curr_ Startup lock retry current level enable
lvl_en 0: Disable
1: Enable
9:8 PowCon_Vol_lim Power control with speed regulation VBB voltage threshold, VPOW
00: Disabled
01: 12 V
10: 12.5 V
11: 14 V
7:0 inductance Motor inductance, set along with the Inductance_shift setting – this value is multiplied by 2inductance_shift

8:0 Kt_set Motor Kt constant

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17:15 current_loop_I Current PI loop integration constant
14:10 power_loop_p Power PI loop proportional constant
9:5 speed_loop_p Speed PI loop proportional constant
4:0 current_loop_p Current PI loop proportional constant

16:16 OCP_rst_cnt OCP restart period control
0: Specify as OCP_reset_mode register
1: Immediate
15:15 Lock_restart_cm Lock detection restart period control
0: Specify as Lock_restart_set register
1: Immediate
14:13 first_cycle_speed_3 Alignment frequency for the third attempt for Align&Go mode
00: 2.23 Hz (0.4484 seconds)
01: 0.53 Hz (1.9 seconds)
10: 0.265 Hz (3.78 seconds)
11: 0.132 Hz (7.55 seconds)
12:11 first_cycle_speed_2 Alignment frequency for the second attempt for Align&Go mode
00: 2.23 Hz (0.4484 seconds)
01: 0.53 Hz (1.9 seconds)
10: 0.265 Hz (3.78 seconds)
11: 0.132 Hz (7.55 seconds)
10:9 first_cycle_speed_1 Alignment frequency for the first attempt for Align&Go mode
00: 2.23 Hz (0.4484 seconds)
01: 0.53 Hz (1.9 seconds)
10: 0.265 Hz (3.78 seconds)
11: 0.132 Hz (7.55 seconds)
5:3 power_loop_I Power PI loop integration constant
2:0 speed_loop_I Speed PI loop integration constant

17:7 PowCon_DCCur_lim DC current limit for power control with speed control
6:4 Startup_current_lvl1 Start-up lock retry current level 1

15:0 Output_array_trim Allegro-determined trim values (locked)
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EEPROM addresses 32-63 (No shadow registers associated)

17:9 x_interpolation_point Corner point input value for the input transformer curve. No shadow register associated.
8:0 y_interpolation_point Corner point output value for the input transformer curve. No shadow register associated.
Note: Refer to application note and user interface for additional detail.
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PROGRAMMING EEPROM
The A89307 contains 64 words of EEPROM, and each word is require 3 writes to the I2C port. These registers, addresses 161,
24 bits long. The 6 most significant bits of each word are used 162, and 163, are described below and the sequence for writing
internally for error detection and correction (ECC), and the 18 to these registers is described on the following page. Reading a
least significant bits are used to store data. The handling of the single address from the EEPROM requires only 1 read from the
ECC data is done automatically by the IC, and the user does not I2C port. Each EEPROM address is mapped to the corresponding
need to (and cannot) read or write the ECC data. I2C address. To read EEPROM address 8, for example, simply
The EEPROM is programmed using the I2C interface. Before read I2C register address 8.
accessing the EEPROM, access must be enabled by writing the Each EEPROM address must be programmed individually. To
value 0x000001 I2C register address 196. There are three basic change the contents of an EEPROM address, the word must first be
actions which can be performed on the EEPROM: read, erase, erased before the new data is written. Programming each address
and write. Writing and erasing a single address in the EEPROM requires about 30 ms (15 ms each for erasing and writing).
EEPROM Control – Register 161: Used to control programming of EEPROM

Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD WR ER EN
Bit Name Description

0 EN Generate the high-voltage pulse required for writing or erasing. This bit self-clears when done, after 15 ms maximum.
1 ER Set this bit high when erasing data to the EEPROM.
2 WR Set this bit high when writing data to the EEPROM.
3 RD This bit is for reading data but is not required for the method described in this datasheet to read the EEPROM.
23:4 n/a Do not use; always set to zero (0) during programming process.
EEPROM Address – Register 162: Used to set the EEPROM address to be altered
Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 eeADDRESS

5:0 eeADDRESS Used to specify the EEPROM address to be erased or written. There are 64 addresses.
EEPROM Data_In – Register 163: Used to set the new EEPROM data to be programmed
Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name 0 0 0 0 0 0 eeDATAin

17:0 eeDATAin Used to specify the new EEPROM data. This must be set to 0 when erasing the current contents.
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Programming the EEPROM Examples

The example below is shown in the following format:
I2C Write/Read, I2C_register_address [data] // comment
*Before accessing the EEPROM, the value 0x000001 must be written to I2C address 196.
Example #1: Write 261 (0x000105) to EEPROM address 7
1. Erase the existing data:
A. I2C Write, 162 [7] // set which EEPROM address to erase.
B. I2C Write, 163 [0] // set Data_In = 0x000000.
C. I2C Write, 161 [3] // set control to erase and set voltage high.
D. Wait 15 ms // requires 15 ms high-voltage pulse to erase.
E. I2C Write, 161 [3] // set control to erase and set voltage high.
F. Wait 15 ms // requires 15 ms high-voltage pulse to erase.
2. Write the new data:
A. I2C Write, 162 [7] // set which EEPROM address to write.
B. I2C Write, 163 [261] // set Data_In = 261 (0x000105).
C. I2C Write, 161 [5] // set control to write and set voltage high.
D. Wait 15 ms // requires 15 ms high-voltage pulse to write.
Example #2: Read EEPROM address 7 to confirm the data was properly programmed
1. Read the word:
A. I2C Read, 7 // read I2C register 7; this will be contents of EEPROM address 7.
*When done accessing the EEPROM, write the value 0x000000 to I2C address 196.
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APPLICATION INFORMATION
BOM Requirement Charge Pump Capacitors: Two charge pump capacitors are
required for the high-side gate drive. One of capacitors should be
The A89307 requires several external passive components to between CP1 and CP2. This will be used to pump up the voltage
provide correct operation. The choice of right components is above VBB. The internal dedicated charge pump requires the fol-
essential to achieve desirable performance. lowing capacitance to have good stability and performance.
VBB Terminal (Input and Bypass Capacitors): The style
Terminal Min Typ Max Unit
and value of capacitors used with the A89307 determine input
CP1, CP2 0.1 0.2 0.47 µF
voltage and ripple. A low equivalent series resistance (ESR)
multilayer ceramic capacitor is required to bypass the VBB pin. A low ESR ceramic capacitor would be suitable for the charge
Additional bulk ceramic capacitors help to reduce AC imped- pump.
ance, reducing high frequency ringing and EMI. The value of the
An additional external capacitor is required for the high-side
capacitor on VBB directly controls the amount of input ripple
drive voltage purpose between VBB and VCP terminal. For this
for a given input current pulse, such as during the PWM control
capacitor, a low ESR ceramic capacitor is required. The following
of the three-phase bridges. Increasing the value of capacitor will
capacitance value is required.
reduce input ripple.
Multilayer ceramic chip capacitors (MLCC) typically have Terminal Min Typ Max Unit
exceptional ESR performance. MLCCs combined with a tight VCP 0.1 0.2 0.47 µF
board layout and an unbroken ground plane will yield very good
performance and low EMI emissions. There are several types of VREG Capacitor: A capacitor is required for the VREG termi-
ceramic capacitors available, each having considerably different nal. The VREG internal regulator generates stable DC voltage
characteristics. For example, X7R and X7S ceramic capacitors for various internal use. A good low ESR capacitor is required
have the best voltage and temperature stability. X5R ceramic to suppress a spike current from the device. A tight board layout
capacitors have higher packing density but poorer performance to the terminals gives the best performance of stability and EMI.
over their rated voltage and temperature ranges. Y5V ceramic The following capacitor is required for the VREG terminal.
capacitors are not recommended because of their extreme non-
Terminal Min Typ Max Unit
linear characteristics of capacitance versus voltage and poor
VREG 0.22 – 4.7 µF
temperature stability.
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TERMINAL DIAGRAMS
VBB
2 kΩ 8V 56 V
DIR
BRAKE
10 V 100 kΩ 6.5 V
VCP
GHx
10 V
Sx
2 kΩ
FG 1 pF 6.5 V
VBB
10 V
VREFINT
(internal regulator)
8V
GLx
CP2 VCP SENP

6V LSS
VBB SENN
6V
7V
CP1 VBB
FAULT
10 V
2 kΩ
SPD
10 V 6.5 V
VBB
VREG
6V
Figure 8: Terminal Diagrams
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PACKAGE OUTLINE DRAWING
0.30
1.15 0.50
0.85 ±0.05 28
28
1 1
A 2
2
5.00 ±0.05 3.15 4.80
5.00 ±0.05 0.0–0.05

// 0.10 C
DETAIL A 3.15
29× D
0.08 C 4.80
C 3.00 REF C PCB Layout Reference View

28
R0.15 REF R0.30 REF

1
2 Trimmed Length
3.15 ±0.10 0.55 ±0.10
0.203 REF
Terminal Thickness
3.00 REF 0.10 REF
3.15 ±0.10
R0.11 REF Plated Area 0.05 REF
B
DETAIL A
0.375 REF 0.55 ±0.10
0.50 BSC 0.22 ±0.05

XXXX
Date Code
0.25 REF 0.10 REF Lot Number
0.20 REF
For Reference Only; not for tooling use E Standard Branding Reference View 1
(reference JEDEC MO-220VHHD-1)
Line 1: Part Number
Dimensions in millimeters
Line 2: Logo A, 4-Digit Date Code
Exact case and lead configuration at supplier discretion within limits shown Line 3: Characters 5, 6, 7, 8 of Assembly Lot Number
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351 XXXX
QFN50P500X500X100-29V1M); Date Code
All pads a minimum of 0.20 mm from all adjacent pads; adjust as Lot Number
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference E Standard Branding Reference View 2
EIA/JEDEC Standard JESD51-5)
Line 1: Part Number
D Coplanarity includes exposed thermal pad and terminals
Line 2: Logo A, 4-Digit Date Code
Line 3: Characters 5, 6, 7, 8 of Assembly Lot Number
E Branding scale and appearance at supplier discretion
Figure 9: Package ET, 28-Contact QFN with Exposed Pad and Wettable Flank
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Revision History
Number Date Description
– March 15, 2021 Initial release
Copyright 2021, Allegro MicroSystems.

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:

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A89307 Datasheet

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A89307

Automotive FOC BLDC Motor Controller

FEATURES AND BENEFITS DESCRIPTION

Figure 1: Typical Application – Functional Block Diagram

A89307-DS March 15, 2021

ABSOLUTE MAXIMUM RATINGS

TERMINAL DIAGRAM AND LIST

FUNCTIONAL BLOCK DIAGRAM

Continued on next page...

9.7% 11.8% 9.7% Lock detected 5 low

12.8% 15.0% 12.8% OCP 4 0.67 seconds high

Motor Startup State Machine

accounts for it and determines the parked position.

Alignment Open-Loop Startup Feedback Control

I2C Operation and EEPROM/Register Map

Figure 6: Write to an I2C register

Read from a register: a two-step process:

from slave device from slave device

Figure 7: Read from an I2C register

I2C Continuous Read

REGISTER AND EEPROM MAP

EEPROM address 6, (No shadow register associated)

EEPROM address 7, (No shadow register associated)

EEPROM address 8, Shadow register address 72

EEPROM address 9, Shadow register address 73

EEPROM address 10, Shadow register address 74

EEPROM address 11, Shadow register address 75

4:4 open_ph_protection Open-phase protection

0:0 fg_standb_en FG feedback enable at standby mode

EEPROM address 12, Shadow register address 76

Bits Name Description

17:17 Reserved The contents shall be kept as default.

EEPROM address 13, Shadow register address 77

EEPROM address 14, Shadow register address 78

EEPROM address 15, Shadow register address 79

EEPROM address 16, Shadow register address 80

EEPROM address 17, Shadow register address 81

EEPROM address 18, Shadow register address 82

EEPROM address 19, Shadow register address 83

EEPROM address 20, Shadow register address 84

EEPROM address 21, Shadow register address 85

EEPROM address 22, Shadow register address 86

EEPROM address 23, Shadow register address 87

EEPROM address 24, Shadow register address 88

EEPROM address 25, Shadow register address 89

EEPROM address 26, Shadow register address 90

EEPROM address 27, Shadow register address 91

EEPROM address 28, Shadow register address 92

EEPROM address 29, Shadow register address 93

EEPROM address 30, Shadow register address 94

EEPROM address 31, Shadow register address 95

EEPROM addresses 32-63 (No shadow registers associated)

EEPROM Control – Register 161: Used to control programming of EEPROM

Bit Name Description

Bit Name Description

Bit Name Description

Programming the EEPROM Examples

CP2 VCP SENP

Figure 8: Terminal Diagrams