Upd78f0500a PDF
Upd78f0500a PDF
Upd78f0500a PDF
78K0/Kx2
8-Bit Single-Chip Microcontrollers
[MEMO]
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
Caution: This product uses SuperFlash technology licensed from Silicon Storage Technology, Inc.
The information in this document is current as of January, 2008. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
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Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
INTRODUCTION
Readers
This manual is intended for user engineers who wish to understand the functions of the
expanded-specification products (PD78F05xxA) of the 78K0/Kx2 microcontrollers and
design and develop application systems and programs for these devices.
The target products are as follows.
Expanded-specification products of the 78K0/KB2 (PD78F050xA):
the
conventional-specification
products
of
the
78K0/Kx2
microcontrollers
Document No.
U17328E
U17336E
U17312E
U17260E
U17397E
Purpose
This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization
78K0/Kx2
78K/0 Series
Users Manual
(This Manual)
Users Manual
Instructions
Pin functions
Internal block functions
Interrupts
Other on-chip peripheral functions
Electrical specifications
CPU functions
Instruction set
Explanation of each instruction
It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
When using this manual as the manual for (A) grade products of the expandedspecification products of 78K0/Kx2 microcontrollers:
Only the quality grade differs between standard products and (A) grade products.
Read the part number as follows.
PD78F050yA PD78F050yA(A) (y = 0 to 3)
PD78F051yA PD78F051yA(A) (y = 1 to 5)
PD78F052yA PD78F052yA(A) (y = 1 to 7)
PD78F053yA PD78F053yA(A) (y = 1 to 7)
PD78F054yA PD78F054yA(A) (y = 4 to 7)
To gain a general understanding of functions:
Read this manual in the order of the CONTENTS.
How to interpret the register format:
For a bit number enclosed in angle brackets, the bit name is defined as a
reserved word in the RA78K0, and is defined as an sfr variable using the
#pragma sfr directive in the CC78K0.
To check the details of a register when you know the register name:
See APPENDIX C REGISTER INDEX.
To know details of the 78K0 microcontroller instructions:
Refer to the separate document 78K/0 Series Instructions Users Manual
(U12326E).
Conventions
Data significance:
Active low representations:
Note:
Caution:
Remark:
Numerical representations:
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Document No.
This manual
U12326E
TM
U17739E
Note
U18274E
Note
U18275E
Note This document is under engineering management. For details, consult an NEC Electronics sales representative.
Documents Related to Development Tools (Software) (Users Manuals)
Document Name
RA78K0 Ver. 3.80 Assembler Package
Document No.
Operation
U17199E
Language
U17198E
U17197E
Operation
U17201E
Language
U17200E
Operation
U17246E
U17247E
Operation
U17437E
U17178E
Document No.
U17341E
U17029E
U18371E
Document No.
U18865E
U15260E
U17454E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
Other Documents
Document Name
Document No.
X13769X
Note
C11531E
C10983E
C11892E
CONTENTS
1.2
1.3
1.4
1.5
Features......................................................................................................................................... 30
Applications .................................................................................................................................. 31
Ordering Information.................................................................................................................... 32
Pin Configuration (Top View) ...................................................................................................... 35
1.5.1 78K0/KB2........................................................................................................................................ 35
1.5.2 78K0/KC2........................................................................................................................................ 37
1.5.3 78K0/KD2........................................................................................................................................ 40
1.5.4 78K0/KE2........................................................................................................................................ 41
1.5.5 78K0/KF2 ........................................................................................................................................ 43
10
11
5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function........... 211
5.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn).................................... 214
CHAPTER 6 CLOCK GENERATOR .................................................................................................... 215
6.1
6.2
6.3
6.4
12
13
14
15
17
78K0/KB2................................................................................................................................... 800
78K0/KC2................................................................................................................................... 802
78K0/KD2................................................................................................................................... 805
78K0/KE2 ................................................................................................................................... 806
78K0/KF2 ................................................................................................................................... 811
18
CHAPTER 1 OUTLINE
1.1 Differences Between Conventional-specification Products (PD78F05xx) and Expandedspecification Products (PD78F05xxA)
This manual describes the functions of the expanded-specification products (PD78F05xxA) of the 78K0/Kx2
microcontrollers.
The differences between the conventional-specification products (PD78F05xx) and expanded-specification
products (PD78F05xxA) of the 78K0/Kx2 microcontrollers are described below.
The number of flash memory rewrites and retention time of standard products and (A) grade products
Processing time of the self programming library
Interrupt response time of the self programming library
A/D conversion time
Remark
For the conventional-specification products (PD78F05xx) of the 78K0/Kx2 microcontrollers, refer to the
manual of each product. For the manual name and document number of each product, refer to the
INTRODUCTION.
1.1.1 Number of flash memory rewrites and retention time of standard products and (A) grade products
Item
Conventional-specification
Products (PD78F05xx)
(retention time)
the libraries
1,000 times
(15 years)
are used
Note 2
10,000 times
(3 years)
Note 3
100 times
(10 years)
Notes 1. The sample library specified by the 78K0/Kx2 Flash Memory Self Programming Users Manual
(Document No.: U17516E) is excluded.
2. The sample program specified by the 78K0/Kx2 EEPROM Emulation Application Note (Document No.:
U17517E) is excluded.
3. These include when the sample library specified by the 78K0/Kx2 Flash Memory Self Programming
Users Manual (Document No.: U17516E) and the sample program specified by the 78K0/Kx2 EEPROM
Emulation Application Note (Document No.: U17517E) are used.
19
CHAPTER 1 OUTLINE
Library Name
Max.
Min.
Max.
4.25
Initialize library
977.75
753.875
753.125
12770.875
12765.875
36909.5
356318
36904.5
356296.25
1214 (1214.375)
2409 (2409.375)
1207 (1207.375)
2402 (2402.375)
25618.875
25613.875
4.25
871.25 (871.375)
866 (866.125)
863.375 (863.5)
858.125 (858.25)
1024.75 (1043.625)
1037.5 (1038.375)
105524.75
790809.375
105523.75
1496.5
2691.5
1489.5
790808.375
2684.5
(1496.875)
(2691.875)
(1489.875)
(2684.875)
<2> When internal high-speed oscillation clock is used and entry RAM is located in short direct
addressing range
Processing Time (s)
Library Name
Max.
Min.
Max.
4.25
Initialize library
443.5
219.625
218.875
12236.625
12231.625
36363.25
355771.75
36358.25
355750
679.75
1874.75
672.75
1867.75
(1875.125)
(673.125)
(680.125)
Block verify library
25072.625
(1868.125)
25067.625
4.25
337 (337.125)
331.75 (331.875)
329.125 (239.25)
323.875 (324)
502.25 (503.125)
497 (497.875)
104978.5
541143.125
104977.5
962.25
2157.25
955.25
2150.25
(962.625)
(2157.625)
(955.625)
(2150.625)
Remark
Values in parentheses indicate values when a write start address structure is located other than in the
internal high-speed RAM.
20
541142.125
CHAPTER 1 OUTLINE
Library Name
Max.
Min.
Max.
34/fCPU
Initialize library
49/fCPU + 485.8125
35/fCPU + 374.75
29/fCPU + 374.75
174/fCPU + 6382.0625
134/fCPU + 6382.0625
174/fCPU +
174/fCPU +
134/fCPU +
134/fCPU +
31093.875
298948.125
31093.875
298948.125
318 (321)/fCPU +
318 (321)/fCPU +
262 (265)/fCPU +
262 (265)/fCPU +
644.125
1491.625
644.125
1491.625
174/fCPU + 13448.5625
134/fCPU + 13448.5625
34/fCPU
75/fCPU +
75/fCPU + 652400
79157.6875
EEPROM write library
67fCPU + 652400
79157.6875
318 (321)/fCPU +
318 (321)/fCPU +
262 (265)/fCPU +
262 (265)/fCPU +
799.875
1647.375
799.875
1647.375
Remarks 1. Values in parentheses indicate values when a write start address structure is located other than in the
internal high-speed RAM.
2. fCPU: CPU operation clock frequency
21
CHAPTER 1 OUTLINE
Library Name
Max.
Min.
Max.
34/fCPU
Initialize library
49/fCPU + 224.6875
35/fCPU + 113.625
29/fCPU + 113.625
174/fCPU + 6120.9375
134/fCPU + 6120.9375
174/fCPU +
174/fCPU +
134/fCPU +
30820.75
298675
30820.75
298675
318 (321)/fCPU +
318 (321)/fCPU +
262 (265)/fCPU +
262 (265)/fCPU +
383
1230.5
383
1230.5
174/fCPU + 13175.4375
134/fCPU +
134/fCPU + 13175.4375
34/fCPU
75/fCPU +
75/fCPU +
67/fCPU +
67/fCPU +
78884.5625
527566.875
78884.5625
527566.875
318 (321)/fCPU +
318 (321)/fCPU +
262 (265)/fCPU +
262 (265)/fCPU +
538.75
1386.25
538.75
1386.25
Remarks 1. Values in parentheses indicate values when a write start address structure is located other than in the
internal high-speed RAM.
2. fCPU: CPU operation clock frequency
22
CHAPTER 1 OUTLINE
Library Name
Min.
Max.
Min.
4.0
4.5
4.0
Max.
4.5
1105.9
1106.6
1105.9
1106.6
905.7
906.1
904.9
905.3
12776.1
12778.3
12770.9
12772.6
26050.4
349971.3
26045.3
349965.6
1180.1 + 203 w
1184.3 + 2241
1172.9 + 203 w
1176.3 + 2241
w
Block verify library
25337.9
25340.2
25332.8
4.0
4.5
4.0
4.5
1072.9
1075.2
1067.5
1069.1
1060.2
1062.6
1054.8
1056.6
1023.8
1028.2
1018.3
1022.1
70265.9
759995.0
70264.9
759994.0
1316.8 + 347 w
1320.9 + 2385
1309.0 + 347 w
1312.4 + 2385
25334.5
<2> When internal high-speed oscillation clock is used and entry RAM is located in short direct
addressing range
Processing Time (s)
Library Name
Min.
Max.
Min.
4.0
4.5
4.0
4.5
Initialize library
449.5
450.2
449.5
450.2
249.3
249.7
248.6
248.9
Max.
12119.7
12121.9
12114.6
12116.3
25344.7
349266.4
25339.6
349260.8
445.8 + 203 w
449.9 + 2241 w
438.5 + 203 w
441.9 + 2241 w
24682.7
24684.9
24677.6
24679.3
4.0
4.5
4.0
4.5
417.6
419.8
412.1
413.8
405.0
407.4
399.5
401.3
367.4
371.8
361.9
365.8
69569.3
759297.3
69568.3
759296.2
795.1 + 347 w
799.3 + 2385 w
787.4 + 347 w
790.8 + 2385 w
Remarks 1. The above processing times are those when a write start address structure is located in the internal
high-speed RAM and during stabilized operation of the internal high-speed oscillator (RSTS = 1).
2. RSTS: Bit 7 of the internal oscillation mode register (RCM)
3. w: Number of words in write data (1 word = 4 bytes)
23
CHAPTER 1 OUTLINE
Library Name
Max.
Min.
Max.
34/fCPU
Initialize library
55/fCPU + 594
36/fCPU + 495
30/fCPU + 495
179/fCPU + 6429
136/fCPU + 6429
179/fCPU + 19713
179/fCPU +
136/fCPU + 19713
136/fCPU +
268079
Word write library
268079
333/fCPU + 647 +
333/fCPU + 647 +
272/fCPU + 647 +
272/fCPU + 647 +
136 w
1647 w
136 w
1647 w
179/fCPU + 13284
136/fCPU + 13284
34/fCPU
180/fCPU + 581
134fCPU + 581
190/fCPU + 574
144/fCPU + 574
350/fCPU + 535
304/fCPU + 535
80/fCPU + 43181
80/fCPU + 572934
72/fCPU + 43181
72/fCPU + 572934
333/fCPU + 729 +
333/fCPU + 729 +
268/fCPU + 729 +
268/fCPU + 729 +
209 w
1722 w
209 w
1722 w
Remarks 1. The above processing times are those when a write start address structure is located in the internal
high-speed RAM and during stabilized operation of the internal high-speed oscillator (RSTS = 1).
2. RSTS: Bit 7 of the internal oscillation mode register (RCM)
3. fCPU: CPU operation clock frequency
4. w: Number of words in write data (1 word = 4 bytes)
24
CHAPTER 1 OUTLINE
Library Name
Max.
Min.
Max.
34/fCPU
Initialize library
55/fCPU + 272
36/fCPU + 173
30/fCPU + 173
179/fCPU + 6108
136/fCPU + 6108
179/fCPU + 19371
179/fCPU +
136/fCPU + 19371
136/fCPU +
267738
Word write library
267738
333/fCPU + 247 +
333/fCPU + 247 +
272/fCPU + 247 +
272/fCPU + 247 +
136 w
1647 w
136 w
1647 w
179/fCPU + 12964
136/fCPU + 12964
34/fCPU
180/fCPU + 261
134/fCPU + 261
190/fCPU + 254
144/fCPU + 254
350/fCPU + 213
304/fCPU + 213
80/fCPU + 42839
80/fCPU + 572592
72/fCPU + 42839
72/fCPU + 572592
333/fCPU + 516 +
333/fCPU + 516 +
268/fCPU + 516 +
268/fCPU + 516 +
209 w
1722 w
209 w
1722 w
Remarks 1. The above processing times are those when a write start address structure is located in the internal
high-speed RAM and during stabilized operation of the internal high-speed oscillator (RSTS = 1).
2. RSTS: Bit 7 of the internal oscillation mode register (RCM)
3. fCPU: CPU operation clock frequency
4. w: Number of words in write data (1 word = 4 bytes)
25
CHAPTER 1 OUTLINE
Library Name
is outside short
is in short direct
is outside short
is in short direct
direct addressing
addressing range
direct addressing
addressing range
range
range
933.6
668.6
927.9
662.9
1026.6
763.6
1020.9
757.9
2505.8
1942.8
2497.8
1934.8
958.6
693.6
952.9
687.9
476.5
211.5
475.5
210.5
2760.8
2168.8
2759.5
2167.5
Remarks 1. The above interrupt response times are those during stabilized operation of the internal high-speed
oscillator (RSTS = 1).
2. RSTS: Bit 7 of the internal oscillation mode register (RCM)
<2> When high-speed system clock is used (normal model of C compiler)
Interrupt Response Time (s (Max.))
Library Name
RSTOP = 0, RSTS = 1
RSTOP = 1
is outside short
is in short direct
is outside short
is in short direct
direct addressing
addressing range
direct addressing
addressing range
range
range
179/fCPU + 507
179/fCPU + 407
179/fCPU + 1650
179/fCPU + 559
179/fCPU + 460
179/fCPU + 1702
179/fCPU + 767
333/fCPU + 1589
333/fCPU + 1298
333/fCPU + 2732
333/fCPU + 1605
179/fCPU + 518
179/fCPU + 418
179/fCPU + 1661
179/fCPU + 725
80/fCPU + 370
80/fCPU + 165
80/fCPU + 1513
80/fCPU + 472
29/fCPU + 1759
29/fCPU + 1468
29/fCPU + 1759
29/fCPU + 1468
333/fCPU + 834
333/fCPU + 512
333/fCPU + 2061
333/fCPU + 873
Note
179/fCPU + 714
Note The longer value of the EEPROM write library interrupt response time becomes the Max. value, depending
on the value of fCPU.
Remarks 1. fCPU: CPU operation clock frequency
2. RSTOP: Bit 0 of the internal oscillation mode register (RCM)
3. RSTS: Bit 7 of the internal oscillation mode register (RCM)
26
CHAPTER 1 OUTLINE
Library Name
RSTOP = 0, RSTS = 1
RSTOP = 1
is outside short
is in short direct
is outside short
is in short direct
direct addressing
addressing range
direct addressing
addressing range
range
range
136/fCPU + 507
136/fCPU + 407
136/fCPU + 1650
136/fCPU + 714
136/fCPU + 559
136/fCPU + 460
136/fCPU + 1702
136/fCPU + 767
272/fCPU + 1589
272/fCPU + 1298
272/fCPU + 2732
272/fCPU + 1605
136/fCPU + 518
136/fCPU + 418
136/fCPU + 1661
136/fCPU + 725
72/fCPU + 370
72/fCPU + 165
72/fCPU + 1513
72/fCPU + 472
19/fCPU + 1759
19/fCPU + 1468
19/fCPU + 1759
19/fCPU + 1468
268/fCPU + 834
268/fCPU + 512
268/fCPU + 2061
268/fCPU + 873
Note
Note The longer value of the EEPROM write library interrupt response time becomes the Max. value, depending
on the value of fCPU.
Remarks 1. fCPU: CPU operation clock frequency
2. RSTOP: Bit 0 of the internal oscillation mode register (RCM)
3. RSTS: Bit 7 of the internal oscillation mode register (RCM)
27
CHAPTER 1 OUTLINE
Library Name
is outside short
is in short direct
is outside short
is in short direct
direct addressing
addressing range
direct addressing
addressing range
range
range
1100.9
431.9
1095.3
426.3
1452.9
783.9
1447.3
778.3
1247.2
579.2
1239.2
571.2
1125.9
455.9
1120.3
450.3
906.9
312.0
905.8
311.0
1215.2
547.2
1213.9
545.9
Remarks 1. The above interrupt response times are those during stabilized operation of the internal high-speed
oscillator (RSTS = 1).
2. RSTS: Bit 7 of the internal oscillation mode register (RCM)
<2> When high-speed system clock is used (normal model of C compiler)
Interrupt Response Time (s (Max.))
Library Name
RSTOP = 0, RSTS = 1
RSTOP = 1
is outside short
is in short direct
is outside short
is in short direct
direct addressing
addressing range
direct addressing
addressing range
range
range
179/fCPU + 567
179/fCPU + 246
179/fCPU + 1708
179/fCPU + 569
179/fCPU + 780
179/fCPU + 459
179/fCPU + 1921
179/fCPU + 782
333/fCPU + 763
333/fCPU + 443
333/fCPU + 1871
333/fCPU + 767
179/fCPU + 580
179/fCPU + 259
179/fCPU + 1721
179/fCPU + 582
80/fCPU + 456
80/fCPU + 200
80/fCPU + 1598
80/fCPU + 459
29/fCPU + 767
29/fCPU + 447
29/fCPU + 767
29/fCPU + 447
333/fCPU + 696
333/fCPU + 376
333/fCPU + 1838
333/fCPU + 700
Note
Note The longer value of the EEPROM write library interrupt response time becomes the Max. value, depending
on the value of fCPU.
Remarks 1. fCPU: CPU operation clock frequency
2. RSTOP: Bit 0 of the internal oscillation mode register (RCM)
3. RSTS: Bit 7 of the internal oscillation mode register (RCM)
28
CHAPTER 1 OUTLINE
Library Name
RSTOP = 0, RSTS = 1
RSTOP = 1
is outside short
is in short direct
is outside short
is in short direct
direct addressing
addressing range
direct addressing
addressing range
range
range
136/fCPU + 567
136/fCPU + 246
136/fCPU + 1708
136/fCPU + 569
136/fCPU + 780
136/fCPU + 459
136/fCPU + 1921
136/fCPU + 782
272/fCPU + 763
272/fCPU + 443
272/fCPU + 1871
272/fCPU + 767
136/fCPU + 580
136/fCPU + 259
136/fCPU + 1721
136/fCPU + 582
72/fCPU + 456
72/fCPU + 200
72/fCPU + 1598
72/fCPU + 459
19/fCPU + 767
19/fCPU + 447
19/fCPU + 767
19/fCPUv + 447
268/fCPU + 696
268/fCPU + 376
268/fCPU + 1838
268/fCPU + 700
Note
Note The longer value of the EEPROM write library interrupt response time becomes the Max. value, depending
on the value of fCPU.
Remarks 1. fCPU: CPU operation clock frequency
2. RSTOP: Bit 0 of the internal oscillation mode register (RCM)
3. RSTS: Bit 7 of the internal oscillation mode register (RCM)
1.1.4 A/D conversion time
The conversion time of A/D converter is as follows.
(1) Conventional-specification products (PD78F05xx)
Parameter
Conversion
Symbol
tCONW
time
Conditions
MIN.
MAX.
Unit
6.1
36.7
12.2
36.7
27
66.6
Symbol
tCONW
Conditions
MIN.
MAX.
Unit
6.1
66.6
12.2
66.6
27
66.6
29
CHAPTER 1 OUTLINE
1.2 Features
{ Minimum instruction execution time can be changed from high speed (0.1 s: @ 20 MHz operation with highspeed system clock) to ultra low-speed (122 s: @ 32.768 kHz operation with subsystem clock)
{ General-purpose register: 8 bits 32 registers (8 bits 8 registers 4 banks)
{ ROM (flash memory), RAM capacities
ROM
Note
128 KB
High- Expansion
Note
Speed RAM
Note
RAM
1 KB
78K0/KB2
6 KB
78K0/KC2
30/36 pins
38/44 pins
48 pins
96 KB
1 KB
4 KB
60 KB
1 KB
2 KB
48 KB
1 KB
1 KB
32 KB
1 KB
78K0/KD2
78K0/KE2
78K0/KF2
52 pins
64 pins
80 pins
PD78F0537A
PD78F0547A
PD78F0526A
PD78F0536A
PD78F0546A
PD78F0515DA PD78F0525A
PD78F0535A
PD78F0545A
PD78F0544A
PD78F0515A
24 KB
1 KB
PD78F0514A
PD78F0524A
PD78F0534A
PD78F0523A
PD78F0533A
PD78F0503A
PD78F0513A
PD78F0502A
PD78F0512A
PD78F0512A
PD78F0522A
PD78F0532A
PD78F0511A
PD78F0511A
PD78F0521A
PD78F0531A
16 KB
768 B
PD78F0501A
8 KB
512 B
PD78F0500A
Note The internal flash memory, internal high-speed RAM capacities, and internal expansion RAM capacities can
be changed using the internal memory size switching register (IMS) and the internal expansion RAM size
switching register (IXS). For IMS and IXS, see 27.1 Internal Memory Size Switching Register and 27.2
Internal Expansion RAM Size Switching Register.
{ Buffer RAM: 32 bytes (can be used for transfer in CSI with automatic transmit/receive function) (78K0/KF2 only)
{ On-chip single-power-supply flash memory
{ Self-programming (with boot swap function)
{ On-chip debug function (PD78F0503DA, 78F0513DA, 78F0515DA, 78F0527DA, 78F0537DA, and
78F0547DA only)Note
Note The PD78F0503DA, 78F0513DA, 78F0515DA, 78F0527DA, 78F0537DA, and 78F0547DA have an onchip debug function, which is provided for development and evaluation. Do not use the on-chip debug
function in products designated for mass production, because the guaranteed number of rewritable times of
the flash memory may be exceeded when this function is used, and product reliability therefore cannot be
guaranteed. NEC Electronics is not liable for problems occurring when the on-chip debug function is used.
{ On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
{ On-chip watchdog timer (operable with the on-chip internal low-speed oscillation clock)
{ On-chip 10-bit resolution A/D converter (AVREF = 2.3 to 5.5 V)
{ On-chip multiplier/divider (16 bits 16 bits, 32 bits/16 bits), key interrupt function, clock output/buzzer output
controller, I/O ports, timer, and serial interface
{ Power supply voltage: VDD = 1.8 to 5.5 V
{ Operating ambient temperature: TA = 40 to +85C
Remark The functions mounted depend on the product. See 1.7 Block Diagram and 1.8 Outline of Functions.
30
CHAPTER 1 OUTLINE
1.3 Applications
{ Automotive equipment (compatible with (A) and (A2) grade products)
System control for body electricals (power windows, keyless entry reception, etc.)
Sub-microcontrollers for control
{ Car audio
{ AV equipment, home audio
{ PC peripheral equipment (keyboards, etc.)
{ Household electrical appliances
Air conditioners
Microwave ovens, electric rice cookers
{ Industrial equipment
Pumps
Vending machines
FA (Factory Automation)
31
CHAPTER 1 OUTLINE
-AX
None
Standard
(A)
Special
-A
Quality Grade
Package Type
50y
MC-CAB
(KB2) FC-AA3
51y
MC-GAA
(KC2) GB-GAF
GA-GAM
Product Type
A
Expanded-specification
products
Not mounted
Mounted
Product Type
F
52y
GB-GAG
(KD2)
53y
GB-GAH
(KE2) GC-GAL
GK-GAJ
54y
(KF2)
GA-HAB
FC-AA1
GC-GAD
GK-GAK
5x1
High-speed
Expansion RAM Flash Memory
RAM Capacity
Capacity
Capacity
_
512 bytes
8 KB
_
768 bytes
16 KB
5x2
1 KB
24 KB
5x3
1 KB
32 KB
5x4
1 KB
1 KB
48 KB
5x5
1 KB
2 KB
60 KB
5x6
1 KB
4 KB
96 KB
5x7
1 KB
6 KB
128 KB
5x0
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
32
CHAPTER 1 OUTLINE
Package
Part Number
Microcontrollers
78K0/KB2
(7.62 mm (300))
78F0503AMC-CAB-AX, 78F0503DAMC-CAB-AX
Note 1
, 78F0500AMC(A)-CAB-AX,
78K0/KC2
(4x4)
78F0503AFC-AA3-A, 78F0503DAFC-AA3-A
(7.62 mm (300))
78F0513DAMC-GAA-AX
(10x10)
78F0513DAGB-GAF-AX
Notes 1, 2
Note 1
, 78F0511AGB(A)-GAF-AX, 78F0512AGB(A)-GAF-AX,
78F0513AGB(A)-GAF-AX
48-pin plastic LQFP
Note 1
(10x10)
Note 1
, 78F0521AGB(A)-GAG-AX,
Note 1
, 78F0531AGB(A)-GAH-AX,
(14x14)
Note 1
, 78F0531AGC(A)-GAL-AX,
Notes 1. The PD78F0503DA, 78F0513DA, 78F0515DA, 78F0527DA, and 78F0537DA have an on-chip debug
function, which is provided for development and evaluation. Do not use the on-chip debug function in
products designated for mass production, because the guaranteed number of rewritable times of the flash
memory may be exceeded when this function is used, and product reliability therefore cannot be
guaranteed. NEC Electronics is not liable for problems occurring when the on-chip debug function is used.
2. Under development
33
CHAPTER 1 OUTLINE
(2/2)
78K0/Kx2
Package
Part Number
Microcontrollers
78K0/KE2
(12x12)
Note
, 78F0531AGK(A)-GAJ-AX,
Note
, 78F0531AGA(A)-HAB-AX,
(5x5)
78F0537AFC-AA1-A, 78F0537DAFC-AA1-A
78K0/KF2
(14x14)
78F0547AGC-GAD-AX, 78F0547DAGC-GAD-AX
Note
, 78F0544AGC(A)-GAD-AX,
78F0547AGK-GAK-AX, 78F0547DAGK-GAK-AX
Note
, 78F0544AGK(A)-GAK-AX,
Note The PD78F0537DA and 78F0547DA have an on-chip debug function, which is provided for development
and evaluation.
Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and product reliability therefore cannot be guaranteed. NEC Electronics is not liable for
problems occurring when the on-chip debug function is used.
34
CHAPTER 1 OUTLINE
ANI1/P21
30
ANI2/P22
ANI0/P20
29
ANI3/P23
P01/TI010/TO00
28
AVSS
P00/TI000
27
AVREF
P120/INTP0/EXLVI
26
P10/SCK10/TxD0
RESET
25
P11/SI10/RxD0
FLMD0
24
P12/SO10
P122/X2/EXCLK/OCD0BNote
23
P13/TxD6
P121/X1/OCD0ANote
22
P14/RxD6
REGC
10
21
P15/TOH0
VSS
11
20
P16/TOH1/INTP5
VDD
12
19
P17/TI50/TO50
P60/SCL0
13
18
P30/INTP1
P61/SDA0
14
17
P31/INTP2/OCD1ANote
P33/TI51/TO51/INTP4
15
16
P32/INTP3/OCD1BNote
35
CHAPTER 1 OUTLINE
Top View
Bottom View
6
5
4
3
2
1
Index mark
Pin Name
Pin No.
A1
NC
Pin Name
Pin No.
Note 1
Note 2
Pin Name
Pin No.
C1
P17/TI50/TO50
E1
AVREF
A2
P32/INTP3/OCD1B
C2
P14/RxD6
E2
AVSS
A3
P30/INTP1
C3
P13/TxD6
E3
ANI2/P22
A4
P61/SDA0
C4
P00/TI000
E4
ANI1/P21
A5
P33/TI51/TO51/INTP4
C5
VDD
E5
FLMD0
E6
RESET
A6
NC
Note 1
Note 2
Note 2
C6
P121/X1/OCD0A
D1
P11/SI10/RxD0
F1
NC
Note 1
B1
P31/INTP2/OCD1A
B2
P16/TOH1/INTP5
D2
P12/SO10
F2
ANI3/P23
B3
P15/TOH0
D3
P10/SCK10/TxD0
F3
ANI0/P20
B4
P60/SCL0
D4
REGC
F4
P01/TI010/TO00
B5
EVDD
D5
VSS
F5
P120/INTP0/EXLVI
B6
EVSS
D6
P122/X2/EXCLK/
F6
NC
OCD0B
Note 1
Note 2
36
CHAPTER 1 OUTLINE
1.5.2 78K0/KC2
38-pin plastic SSOP (7.62 mm (300))
ANI1/P21
38
ANI2/P22
ANI0/P20
37
ANI3/P23
P01/TI010/TO00
36
ANI4/P24
P00/TI000
35
ANI5/P25
P120/INTP0/EXLVI
34
AVSS
RESET
33
AVREF
P124/XT2/EXCLKS
32
P10/SCK10/TxD0
P123/XT1
31
P11/SI10/RxD0
FLMD0
30
P12/SO10
P122/X2/EXCLK/OCD0BNote
10
29
P13/TxD6
Note
11
28
P14/RxD6
REGC
12
27
P15/TOH0
VSS
13
26
P16/TOH1/INTP5
VDD
14
25
P17/TI50/TO50
P60/SCL0
15
24
P30/INTP1
P61/SDA0
16
23
P31/INTP2/OCD1ANote
P62/EXSCL0
17
22
P32/INTP3/OCD1BNote
P63
18
21
P70/KR0
P33/TI51/TO51/INTP4
19
20
P71/KR1
P121/X1/OCD0A
37
CHAPTER 1 OUTLINE
ANI7/P27
ANI6/P26
ANI5/P25
ANI4/P24
ANI3/P23
ANI2/P22
ANI1/P21
ANI0/P20
P01/TI010/TO00
P00/TI000
P120/INTP0/EXLVI
44 43 42 41 40 39 38 37 36 35 34
P41
33
AVSS
P40
32
AVREF
RESET
31
P10/SCK10/TxD0
P124/XT2/EXCLKS
30
P11/SI10/RxD0
P123/XT1
29
P12/SO10
FLMD0
28
P13/TxD6
P122/X2/EXCLK/OCD0BNote
27
P14/RxD6
P121/X1/OCD0ANote
26
P15/TOH0
REGC
25
P16/TOH1/INTP5
VSS
10
24
P17/TI50/TO50
VDD
11
23
P30/INTP1
P31/INTP2/OCD1A
Note
P32/INTP3/OCD1BNote
P70/KR0
P71/KR1
P72/KR2
P73/KR3
P33/TI51/TO51/INTP4
P63
P61/SDA0
P62/EXSCL0
P60/SCL0
12 13 14 15 16 17 18 19 20 21 22
38
CHAPTER 1 OUTLINE
VDD
VSS
REGC
P121/X1/OCD0ANote
P122/X2/EXCLK/OCD0BNote
FLMD0
P123/XT1
P124/XT2/EXCLKS
RESET
P40
P41
P120/INTP0/EXLVI
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
P140/PCL/INTP6
P00/TI000
P01/TI010/TO00
P130
ANI0/P20
ANI1/P21
ANI2/P22
ANI3/P23
ANI4/P24
ANI5/P25
ANI6/P26
ANI7/P27
P31/INTP2/OCD1ANote
P30/INTP1
P17/TI50/TO50
P16/TOH1/INTP5
P15/TOH0
P14/RxD6
P13/TxD6
P12/SO10
P11/Sl10/RxD0
P10/SCK10/TxD0
AVREF
AVSS
P60/SCL0
P61/SDA0
P62/EXSCL0
P63
P33/TI51/TO51/INTP4
P75
P74
P73/KR3
P72/KR2
P71/KR1
P70/KR0
P32/INTP3/OCD1BNote
39
CHAPTER 1 OUTLINE
1.5.3 78K0/KD2
ANI7/P27
ANI6/P26
ANI5/P25
ANI4/P24
ANI3/P23
ANI2/P22
ANI1/P21
ANI0/P20
P130
P03
P02
P01/TI010/TO00
P00/TI000
52 51 50 49 48 47 46 45 44 43 42 41 40
P140/PCL/INTP6
39
AVSS
P120/INTP0/EXLVI
38
AVREF
P41
37
P10/SCK10/TXD0
P40
36
P11/SI10/RXD0
RESET
35
P12/SO10
P124/XT2/EXCLKS
34
P13/TXD6
P123/XT1
33
P14/RXD6
FLMD0
32
P15/TOH0
P122/X2/EXCLK/OCD0BNote
31
P16/TOH1/INTP5
P121/X1/OCD0ANote
10
30
P17/TI50/TO50
REGC
11
29
P30/INTP1
VSS
12
28
P31/INTP2/OCD1ANote
VDD
13
27
P32/INTP3/OCD1BNote
P70/KR0
P71/KR1
P72/KR2
P73/KR3
P74/KR4
P75/KR5
P76/KR6
P77/KR7
P33/TI51/TO51/INTP4
P63
P62/EXSCL0
P60/SCL0
P61/SDA0
14 15 16 17 18 19 20 21 22 23 24 25 26
40
CHAPTER 1 OUTLINE
1.5.4 78K0/KE2
64-pin plastic LQFP (fine pitch) (10 10)
64-pin plastic LQFP (14 14)
64-pin plastic LQFP (12 12)
P140/PCL/INTP6
P141/BUZ/INTP7
P00/TI000
P01/TI010/TO00
P02/SO11Note2
P03/SI11Note2
P04/SCK11Note2
P130
ANI0/P20
ANI1/P21
ANI2/P22
ANI3/P23
ANI4/P24
ANI5/P25
ANI6/P26
ANI7/P27
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P120/INTP0/EXLVI
P43
P42
P41
P40
RESET
P124/XT2/EXCLKS
P123/XT1
FLMD0
P122/X2/EXCLK/OCD0BNote1
P121/X1/OCD0ANote1
REGC
VSS
EVSS
VDD
EVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AVSS
AVREF
P10/SCK10/TxD0
P11/SI10/RxD0
P12/SO10
P13/TxD6
P14/RxD6
P15/TOH0
P16/TOH1/INTP5
P17/TI50/TO50
P30/INTP1
P53
P52
P51
P50
P31/INTP2/OCD1ANote1
P60/SCL0
P61/SDA0
P62/EXSCL0
P63
P33/TI51/TO51/INTP4
P77/KR7
P76/KR6
P75/KR5
P74/KR4
P73/KR3
P72/KR2
P71/KR1
P70/KR0
P06/TO01Note2/TI011Note2
P05/SSI11Note2/TI001Note2
P32/INTP3/OCD1BNote1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
41
CHAPTER 1 OUTLINE
Top View
Bottom View
8
7
6
5
4
3
2
1
H G F E D C B A
A B C D E F G H
Index mark
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
A1
AVSS
C1
ANI4/P24
E1
P130
A2
AVREF
C2
ANI3/P23
E2
ANI0/P20
Note 2
Pin No.
Pin Name
G1
P141/BUZ/INTP7
G2
P140/PCL/INTP6
G3
P43
A3
P11/SI10/RxD0
C3
ANI7/P27
E3
P03/SI11
A4
P13/TxD6
C4
P10/SCK10/TxD0
E4
P42
G4
RESET
A5
P16/TOH1/INTP5
C5
P17/TI50/TO50
E5
P77/KR7
G5
REGC
A6
P53
C6
P30/INTP1
E6
P33/TI51/TO51/INTP4 G6
VSS
A7
P51
C7
P31/INTP2/
Note 1
OCD1A
E7
P74/KR4
G7
VDD
A8
P32/INTP3/
Note 1
OCD1B
C8
P06/TO01
E8
P76/KR6
G8
P61/SDA0
B1
ANI5/P25
D1
ANI1/P21
F1
P01/TI010/TO00
H1
P120/INTP0/EXLVI
B2
ANI6/P26
D2
ANI2/P22
F2
P00/TI000
H2
P124/XT2/EXCLKS
H3
P123/XT1
Note 2
TI011
B3
P12/SO10
D3
P04/SCK11
B4
P15/TOH0
D4
B5
P14/RxD6
B6
P52
B7
P50
B8
P05/SSI11
Note 2
Note 2
Note 2
Note 2
F3
P02/SO11
P72/KR2
F4
P41
H4
FLMD0
D5
P70/KR0
F5
P40
H5
P122/X2/EXCLK/
Note 1
OCD0B
D6
P71/KR1
F6
P60/SCL0
H6
P121/X1/OCD0A
D7
P75/KR5
F7
P62/EXSCL0
H7
EVSS
D8
P73/KR3
F8
P63
H8
EVDD
Note 2
TI001
42
Note 1
CHAPTER 1 OUTLINE
1.5.5 78K0/KF2
80-pin plastic LQFP (14 14)
P140/PCL/INTP6
P141/BUZ/BUSY0/INTP7
P142/SCKA0
P143/SIA0
P144/SOA0
P145/STB0
P00/TI000
P01/TI010/TO00
P02/SO11
P03/SI11
P04/SCK11
P130
ANI0/P20
ANI1/P21
ANI2/P22
ANI3/P23
ANI4/P24
ANI5/P25
ANI6/P26
ANI7/P27
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P120/INTP0/EXLVI
P47
P46
P45
P44
P43
P42
P41
P40
RESET
P124/XT2/EXCLKS
P123/XT1
FLMD0
P122/X2/EXCLK/OCD0BNote
P121/X1/OCD0ANote
REGC
VSS
EVSS
VDD
EVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AVSS
AVREF
P57
P56
P55
P54
P10/SCK10/TxD0
P11/SI10/RxD0
P12/SO10
P13/TxD6
P14/RxD6
P15/TOH0
P16/TOH1/INTP5
P17/TI50/TO50
P30/INTP1
P53
P52
P51
P50
P31/INTP2/OCD1ANote
P60/SCL0
P61/SDA0
P62/EXSCL0
P63
P33/TI51/TO51/INTP4
P64
P65
P66
P67
P77/KR7
P76/KR6
P75/KR5
P74/KR4
P73/KR3
P72/KR2
P71/KR1
P70/KR0
P06/TI011/TO01
P05/TI001/SSI11
P32/INTP3/OCD1BNote
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
43
CHAPTER 1 OUTLINE
Analog input
P120 to P124:
Port 12
AVREF:
P130:
Port 13
AVSS:
Analog ground
P140 to P145:
Port 14
BUSY0:
PCL:
BUZ:
Buzzer output
REGC
Regulator capacitance
EVDD:
RESET:
Reset
EVSS:
RxD0, RxD6:
Receive data
EXCLK:
SCL0:
EXCLKS:
SDA0:
(subsystem clock)
EXLVI:
SSI11:
EXSCL0:
STB0:
Serial strobe
FLMD0:
TI000, TI010,
INTP0 to INTP7:
TI001, TI011,
KR0 to KR7:
Key return
TI50, TI51:
NC:
Non-connection
TO00, TO01,
Timer input
TO50, TO51,
OCD0A, OCD0B,
OCD1A, OCD1B:
TOH0, TOH1:
P00 to P06:
Port 0
TxD0, TxD6:
Transmit data
P10 to P17:
Port 1
VDD:
Power supply
P20 to P27:
Port 2
VSS:
Ground
P30 to P33:
Port 3
X1, X2:
P40 to P47:
Port 4
XT1, XT2:
P50 to P57:
Port 5
P60 to P67:
Port 6
P70 to P77:
Port 7
44
Timer output
CHAPTER 1 OUTLINE
16-bit timer/
event counter 00
TOH0/P15
Port 0
P00, P01
Port 1
P10 to P17
Port 2
P20 to P23
Port 3
P30 to P33
Port 6
P60, P61
Port 12
P120 to P122
8-bit timer H0
TOH1/P16
8-bit timer H1
Internal low-speed
oscillator
Watchdog timer
8-bit timer/
event counter 50
TI50/TO50/P17
8-bit timer/
event counter 51
TI51/TO51/P33
78K/0
CPU
core
Flash
memory
Power on clear/
low voltage
indicator
Serial
interface UART0
RxD6/P14
TxD6/P13
Serial
interface UART6
LINSEL
SI10/P11
SO10/P12
SCK10/P10
Serial
interface CSI10
Internal
high-speed
RAM
System
control
ANI0/P20 to
ANI3/P23
AVREF
AVSS
RxD6/P14 (LINSEL)
INTP0/P120
INTP1/P30 to
INTP4/P33
INTP5/P16
Notes 1.
2.
RESET
X1/P121
X2/EXCLK/P122
Internal high-speed
oscillator
Voltage regulator
SDA0/P61
SCL0/P60
EXLVI/P120
Reset control
POC/LVI
control
REGC
Serial
interface IIC0
4
A/D converter
Interrupt
control
VDD,
VSS, FLMD0
EVDDNote 2 EVSSNote 2
45
CHAPTER 1 OUTLINE
1.7.2 78K0/KC2
TO00/TI010/P01
TI000/P00
RxD6/P14 (LINSEL)
16-bit timer/
event counter 00
TOH0/P15
Port 0
P00, P01
Port 1
P10 to P17
Port 2
Port 3
P30 to P33
Port 4
P40Note 1, P41Note 1
Port 6
P60 to P63
Port 7
Port 12
P120 to P124
8-bit timer H0
TOH1/P16
8-bit timer H1
Internal
low-speed
oscillator
Watchdog timer
8-bit timer/
event counter 50
TI50/TO50/P17
8-bit timer/
event counter 51
TI51/TO51/P33
Watch timer
RxD0/P11
TxD0/P10
Serial
interface UART0
RxD6/P14
TxD6/P13
Serial
interface UART6
LINSEL
SI10/P11
SO10/P12
SCK10/P10
Serial
interface CSI10
EXSCL0/P62
SDA0/P61
SCL0/P60
ANI0/P20 to ANI5/P25,
ANI6/P26Note 1, ANI7/P27Note 1
AVREF
AVSS
78K/0
CPU
core
Flash
memory
P130Note 2
Port 14Note 2
P140Note 2
Clock output
controlNote 2
Internal
high-speed
RAM
Internal
expansion
RAMNote 3
Key return
On-chip debugNote 4
A/D converter
System control
Interrupt control
INTP5/P16
KR0/P70, KR1/P71,
KR2/P72Note 1, KR3/P73Note 1
VDD
VSS FLMD0
Internal
high-speed
oscillator
Voltage regulator
46
EXLVI/P120
Reset control
INTP6/P140Note 2
Notes 1.
POC/LVI
control
Multiplier &
dividerNote 3
PCL/P140Note 2
Power-on-clear/
low-voltage
indicator
RxD6/P14 (LINSEL)
INTP0/P120
INTP1/P30 to
INTP4/P33
Port 13Note 2
REGC
3.
4.
Available only in the PD78F0513DA and 78F0515DA (product with on-chip debug function).
CHAPTER 1 OUTLINE
1.7.3 78K0/KD2
TO00/TI010/P01
TI000/P00
RxD6/P14 (LINSEL)
16-bit timer/
event counter 00
TOH0/P15
Port 0
P00 to P03
Port 1
P10 to P17
Port 2
P20 to P27
Port 3
P30 to P33
Port 4
P40, P41
Port 6
P60 to P63
Port 7
P70 to P77
Port 12
P120 to P124
8-bit timer H0
TOH1/P16
8-bit timer H1
Internal low-speed
oscillator
Watchdog timer
8-bit timer/
event counter 50
TI50/TO50/P17
8-bit timer/
event counter 51
TI51/TO51/P33
Watch timer
78K/0
CPU
CORE
BANK
Flash
memory
Port 13
P130
Port 14
P140
Note 1
Serial
interface UART0
RxD6/P14
TxD6/P13
Serial
interface UART6
LINSEL
SI10/P11
SO10/P12
SCK10/P10
Serial
interface CSI10
EXSCL0/P62
SDA0/P61
SCL0/P60
ANI0/P20 to
ANI7/P27
AVREF
AVSS
Power on clear/low
voltage indicator
Internal
high-speed
RAM
Internal
expansion
RAMNote 2
INTP5/P16
Key return
POC/LVI
control
KR0/P70 to
KR7/P77
Reset control
On-chip debugNote 3
8
A/D converter
System control
EXLVI/P120
Multiplier &
dividerNote 2
RxD6/P14
INTP0/P120(LINSEL)
INTP1/P30 to
INTP4/P33
PCL/P140
Internal high-speed
oscillator
Interrupt control
VDD
VSS FLMD0
INTP6/P140
Voltage regulator
Notes 1.
REGC
2.
3.
47
CHAPTER 1 OUTLINE
1.7.4 78K0/KE2
TO00/TI010/P01
TI000/P00 (LINSEL)
RxD6/P14 (LINSEL)
16-bit TIMER/
EVENT COUNTER 00
TO01Note2/TI011Note2/P06
16-bit TIMER/
EVENT COUNTER 01Note2
TI001Note2/P05
TOH0/P15
PORT 0
P00 to P06
PORT 1
P10 to P17
PORT 2
P20 to P27
PORT 3
P30 to P33
PORT 4
P40 to P43
PORT 5
P50 to P53
PORT 6
P60 to P63
PORT 7
P70 to P77
PORT 12
P120 to P124
8-bit TIMER H0
TOH1/P16
8-bit TIMER H1
INTERNAL
LOW-SPEED
OSCILLATOR
WATCHDOG TIMER
8-bit TIMER/
EVENT COUNTER 50
TI50/TO50/P17
8-bit TIMER/
EVENT COUNTER 51
TI51/TO51/P33
WATCH TIMER
PORT 13
78K/0
CPU
CORE
BANK
RxD0/P11
TxD0/P10
SERIAL
INTERFACE UART0
RxD6/P14
TxD6/P13
SERIAL
INTERFACE UART6
LINSEL
SI10/P11
SO10/P12
SCK10/P10
SERIAL
INTERFACE CSI10
SI11Note2/P03
SO11Note2/P02
SCK11Note2/P04
SSI11Note2/P05
Notes 1.
48
INTERNAL
HIGH-SPEED
RAM
INTERNAL
EXPANSION
RAMNote2
P140, P141
BUZZER OUTPUT
BUZ/P141
CLOCK OUTPUT
CONTROL
PCL/P140
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
KEY RETURN
POC/LVI
CONTROL
EXLVI/P120
KR0/P70 to
KR7/P77
RESET CONTROL
SERIAL
INTERFACE IIC0
ON-CHIP DEBUGNote3
SYSTEM
CONTROL
A/D CONVERTER
VDD, VSS, FLMD0
EVDD EVSS
4
INTP5/P16
INTP6/P140,
INTP7/P141
MULTIPLIER&
DIVIDERNote2
RxD6/P14 (LINSEL)
INTP0/P120(LINSEL)
INTP1/P30 to
INTP4/P33
PORT 14
Note1
SERIAL INTERFACE
CSI11Note2
EXSCL0/P62
SDA0/P61
SCL0/P60
ANI0/P20 to
ANI7/P27
AVREF
AVSS
FLASH
MEMORY
P130
INTERRUPT
CONTROL
RESET
X1/P121
X2/EXCLK/P122
XT1/P123
XT2/EXCLKS/P124
INTERNAL
HIGH-SPEED
OSCILLATOR
VOLTAGE
REGULATOR
OCD0ANote3/X1, OCD1ANote3/P31
OCD0BNote3/X2, OCD1BNote3/P32
REGC
2.
3.
CHAPTER 1 OUTLINE
1.7.5 78K0/KF2
TO00/TI010/P01
TI000/P00
RxD6/P14 (LINSEL)
16-bit timer/
event counter 00
TO01/TI011/P06
TI001/P05
16-bit timer/
event counter 01
TOH0/P15
Port 0
P00 to P06
Port 1
P10 to P17
Port 2
P20 to P27
Port 3
P30 to P33
8-bit timer H1
Port 4
P40 to P47
Internal low-speed
oscillator
Port 5
P50 to P57
Port 6
P60 to P67
Port 7
P70 to P77
Port 12
P120 to P124
8-bit timer H0
TOH1/P16
Watchdog timer
8-bit timer/
event counter 50
TI50/TO50/P17
8-bit timer/
event counter 51
TI51/TO51/P33
Watch timer
Port 13
78K/0
CPU
core
Flash
memory
Port 14
P130
P140 to P145
BANKNote 1
RxD0/P11
TxD0/P10
Serial
interface UART0
RxD6/P14
TxD6/P13
Serial
interface UART6
LINSEL
SI10/P11
SO10/P12
SCK10/P10
Serial
interface CSI10
SI11/P03
SO11/P02
SCK11/P04
SSI11/P05
Serial
interface CSI11
SIA0/P143
SOA0/P144
SCKA0/P142
STB0/P145
BUSY0/P141
Serial
interface CSIA0
Notes 1.
2.
PCL/P140
Power on clear/
low voltage
indicator
POC/LVI
control
EXLVI/P120
KR0/P70 to
KR7/P77
Reset control
On-chip debugNote 2
System
control
Internal high-speed
oscillator
8
A/D converter
VDD, VSS, FLMD0
EVDD EVSS
4
INTP5/P16
INTP6/P140,
INTP7/P141
Clock output
control
Key return
Serial
interface IIC0
RxD6/P14 (LINSEL)
INTP0/P120
INTP1/P30 to
INTP4/P33
Internal
expansion
RAM
BUZ/P141
Multiplier &
divider
EXSCL0/P62
SDA0/P61
SCL0/P60
ANI0/P20 to
ANI7/P27
AVREF
AVSS
Internal
high-speed
RAM
Buzzer output
Voltage
regulator
REGC
Interrupt
control
49
CHAPTER 1 OUTLINE
78K0/KC2
(PD78F051yA: y = 1 to 5)
78K0/KB2
(PD78F050yA: y = 0 to 3)
30/36 Pins
38/44 Pins
48 Pins
16
24
32
16
24
32
16
24
32
48
60
0.5
0.75
0.75
0.75
Regulator
Provided
0.1 s (20 MHz: VDD = 4.0 to 5.5 V)/0.2 s (10 MHz: VDD = 2.7 to 5.5 V)/
0.4 s (5 MHz: VDD = 1.8 to 5.5 V)
Clock
Main
Minimum instruction
execution time
High-speed system
20 MHz: VDD = 4.0 to 5.5 V/10 MHz: VDD = 2.7 to 5.5 V/5 MHz: VDD = 1.8 to 5.5 V
Internal high-speed
oscillation
Subsystem
Timer
Port
Internal low-speed
oscillation
Total
23
31 (38 pins)/
37 (44 pins)
41
N-ch O.D. (6 V
tolerance)
16 bits (TM0)
1 ch
8 bits (TM5)
2 ch
8 bits (TMH)
2 ch
Watch
1 ch
Serial interface
WDT
1 ch
3-wire CSI
Automatic transmit/
receive 3-wire CSI
UART/3-wire CSI
Note
1 ch
1 ch
I C bus
Interrupt
10-bit A/D
1 ch
4 ch
6 ch (38 pins)/
8 ch (44 pins)
8 ch
External
Internal
14
Key interrupt
16
2 ch (38 pins)/
4 ch (44 pins)
Reset
RESET pin
POC
LVI
Provided
1.59 V 0.15 V (rise time to 1.8 V: 3.6 ms (MAX.))
The detection level of the supply voltage is selectable in 16 steps.
WDT
Provided
Operating ambient
temperature
Multiplier/divider
On-chip debug function
PD78F0503DA only
PD78F0513DA only
TA = 40 to +85C
50
4 ch
Provided
PD78F0515DA only
CHAPTER 1 OUTLINE
(2/2)
78K0/Kx2
Item
Flash memory (KB)
16
78K0/KD2
(PD78F052yA: y = 1 to 7)
78K0/KE2
(PD78F053yA: y = 1 to 7)
78K0/KF2
(PD78F054yA:
y = 4 to 7)
52 Pins
64 Pins
80 Pins
24
32
48
60
96
0.75
128
16
0.75
Main
Clock
Port
96
128
48
60
96
High-speed system
20 MHz: VDD = 4.0 to 5.5 V/10 MHz: VDD = 2.7 to 5.5 V/5 MHz: VDD = 1.8 to 5.5 V
Internal high-speed
oscillation
Subsystem
Total
45
55
71
N-ch O.D. (6 V
tolerance)
16 bits (TM0)
1 ch
2 ch
8 bits (TM5)
2 ch
8 bits (TMH)
2 ch
Watch
1 ch
WDT
1 ch
3-wire CSI
1 ch
Automatic transmit/
receive 3-wire CSI
UART/3-wire CSI
1 ch
Note
1 ch
1 ch
1 ch
10-bit A/D
8 ch
I C bus
External
Internal
9
16
19
Key interrupt
Provided
1.59 V 0.15 V (rise time to 1.8 V: 3.6 ms (MAX.))
POC
LVI
WDT
Provided
20
8 ch
RESET pin
Operating ambient
temperature
128
0.1 s (20 MHz: VDD = 4.0 to 5.5 V)/0.2 s (10 MHz: VDD = 2.7 to 5.5 V)/
0.4 s (5 MHz: VDD = 1.8 to 5.5 V)
Internal low-speed
oscillation
Interrupt
60
Provided
Minimum instruction
execution time
Reset
48
Regulator
Timer
32
Serial interface
24
Provided
Provided
PD78F0527DA only
Provided
PD78F0537DA only
PD78F0547DA only
TA = 40 to +85C
51
CHAPTER 1 OUTLINE
8-Bit Timer/
Event Counters
50 and 51
TM00
TM01
TM50
TM51
TMH0
TMH1
1 channel
1 channel
1 channel
1 channel
1 channel
1 channel
1 channel
1 channel
1 channel
1 channel
PPG output
1 output
1 output
PWM output
1 output
1 output
1 output
1 output
Pulse width
measurement
2 inputs
2 inputs
Square-wave
output
1 output
1 output
1 output
1 output
1 output
1 output
Carrier generator
Timer output
Watchdog timer
1 channel
Interrupt source
Notes 1.
Nore 2
1 output
Nore 1
1 channel
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0-3
y = 1-5
y = 1-7
y = 1-3
y = 4-7
y = 4-7
16-bit timer/event
counter 00
16-bit timer/event
counter 01
8-bit timer/event
counter 50
8-bit timer/event
counter 51
8-bit timer H0
8-bit timer H1
Watch timer
Watchdog timer
52
In the watch timer, the watch timer function and interval timer function can be used simultaneously.
2.
Remark
Note 1
1 channel
Corresponding Pins
AVREF
P20 to P27
VDD
Table 2-2. Pin I/O Buffer Power Supplies (AVREF, EVDD, VDD)
78K0/KB2: 36-pin plastic FLGA (4x4)
78K0/KE2: 64-pin plastic LQFP (fine pitch) (10x10), 64-pin plastic LQFP (14x14), 64-pin plastic LQFP (12x12),
64-pin plastic TQFP (fine pitch) (7x7), 64-pin plastic FLGA (5x5)
78K0/KF2: 80-pin plastic LQFP (14x14), 80-pin plastic LQFP (fine pitch) (12x12)
Power Supply
Corresponding Pins
AVREF
P20 to P27
EVDD
VDD
P121 to P124
Pins other than port
53
2.1.1 78K0/KB2
(1) Port functions: 78K0/KB2
Function Name
P00
I/O
I/O
Function
Port 0.
After Reset
Input port
P01
Alternate Function
TI000
TI010/TO00
I/O
Port 1.
Input port
P11
SI10/RxD0
P12
SO10
P13
SCK10/TxD0
TxD6
setting.
P14
RxD6
P15
TOH0
P16
TOH1/INTP5
P17
TI50/TO50
P20 to P23
I/O
Port 2.
Analog input
ANI0 to ANI3
Input port
INTP1
I/O
P31
P32
P33
P60
Port 3.
Port 6.
Input port
P61
Note
INTP3/OCD1B
Note
INTP4/TI51/TO51
setting.
I/O
INTP2/OCD1A
SCL0
SDA0
I/O
Port 12.
Input port
X1/OCD0A
54
INTP0/EXLVI
Note
X2/EXCLK/
OCD0B
Note
I/O
Input
Function
A/D converter analog input
After Reset
Analog
Alternate Function
P20 to P23
input
EXLVI
Input
FLMD0
INTP0
Input
Input port
Input port
INTP1
P120/INTP0
P120/EXLVI
P30
specified
P31/OCD1A
Note
INTP3
P32/OCD1B
Note
INTP4
P33/TI51/TO51
INTP5
P16/TOH1
INTP2
REGC
Input
RxD0
Input
Input port
P11/SI10
RxD6
Input
Input port
P14
TxD0
Output
Input port
P10/SCK10
TxD6
Output
Input port
P13
SCK10
I/O
Input port
P10/TxD0
SI10
Input
SO10
Output
SCL0
I/O
P12
Input port
SDA0
TI000
P11/RxD0
P60
P61
Input port
P00
Input port
P01/TO00
Input port
P17/TO50
Input
TI50
Input
TI51
TO00
Output
TO50
Output
TO51
TOH0
P33/TO51/INTP4
Input port
P01/TI010
Input port
P17/TI50
TOH1
P33/TI51/INTP4
Input port
X1
X2
EXCLK
Input
P15
P16/INTP5
Note
Input port
P121/OCD0A
Input port
P122/EXCLK/OCD0B
Input port
P122/X2/OCD0B
Note
Note
55
I/O
VDD
Function
For 30-pin products: Positive power supply for pins other
After Reset
Alternate Function
Note 1
AVREF
VSS
Note 1
EVSS
AVSS
OCD0A
Note 2
OCD1A
Note 2
OCD0B
Note 2
OCD1B
Note 2
Input
P121/X1
P31/INTP2
P122/X2/EXCLK
P32/INTP3
56
Input port
2.1.2 78K0/KC2
(1) Port functions (1/2): 78K0/KC2
Function Name
P00
I/O
I/O
Function
Port 0.
After Reset
Input port
P01
Alternate Function
TI000
TI010/TO00
P10
Port 1.
Input port
P11
SI10/RxD0
P12
SO10
P13
SCK10/TxD0
TxD6
setting.
P14
RxD6
P15
TOH0
P16
TOH1/INTP5
P17
TI50/TO50
I/O
P20 to P25
P26
Note 1
, P27
Port 2.
Analog input
Note 1
ANI0 to ANI5
ANI6
Note 1
, ANI7
Note 1
P30
P31
P32
P33
P40
Note 1
, P41
Note 1
I/O
Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
Input port
Port 4.
Input port
INTP1
INTP2/OCD1A
Note 2
INTP3/OCD1B
Note 2
TI51/TO51/INTP4
P60
Port 6.
Input port
P61
SDA0
P62
SCL0
EXSCL0
P63
P70, P71
P72
P74
I/O
Note 1
, P73
Note 3
, P75
Note 1
Note 3
Port 7.
Input port
KR0, KR1
KR2
Note 1
, KR3
Note 1
setting.
57
I/O
Port 12.
I/O
P120
Function
After Reset
Input port
P121
Note 1
XT1
P124
P130
Note 1
X2/EXCLK/OCD0B
P123
INTP0/EXLVI
X1/OCD0A
P122
Alternate Function
XT2/EXCLKS
Note 2
Output
Port 13.
Output port
Note 2
Port 14.
I/O
Input port
Note 2
PCL/INTP6
Notes 1. PD78F0513DA and 78F0515DA (product with on-chip debug function) only
2. 48-pin products only
(2) Non-port functions (1/2): 78K0/KC2
Function Name
ANI0 to ANI5
ANI6
Note 1
I/O
Input
, ANI7
Function
After Reset
Analog input
Note 1
Alternate Function
P20 to P25
P26
Note 1
, P27
EXLVI
Input
Input port
P120/INTP0
EXSCL0
Input
Input port
P62
Note 1
FLMD0
INTP0
Input
Input port
INTP1
P120/EXLVI
P30
specified
P31/OCD1A
Note 2
INTP3
P32/OCD1B
Note 2
INTP4
P33/TI51/TO51
INTP5
P16/TOH1
INTP2
INTP6
Note 3
P140/PCL
KR0, KR1
KR2
Note 1
PCL
Note 3
Input
, KR3
Input port
Note 1
P70, P71
P72
Output
Input port
Note 3
Note 1
, P73
P140/INTP6
Note 1
Note 3
subsystem clock)
58
I/O
REGC
After Reset
Alternate Function
Function
RESET
Input
RxD0
Input
Input port
P11/SI10
RxD6
Input
Input port
P14
SCK10
I/O
Input port
P10/TxD0
Input port
P60
SCL0
I/O
SDA0
I/O
Input port
P61
SI10
Input
Input port
P11/RxD0
SO10
Output
Input port
P12
TI000
Input
Input port
P00
TI010
TI50
TI51
P01/TO00
Input port
P17/TO50
P33/TO51/INTP4
TO00
Output
Input port
P01/TI010
TO50
Output
Input port
P17/TI50
TO51
P33/TI51/INTP4
Output
TxD0
Output
Input port
P10/SCK10
TxD6
Output
Input port
P13
Input port
P121/OCD0A
TOH0
TOH1
Input port
X1
X2
EXCLK
P15
P16/INTP5
Note
P122/EXCLK/
Note
OCD0B
Input
Input port
P122/X2/
Note
OCD0B
XT1
Input port
P123
XT2
Input port
P124/EXCLKS
Input port
P124/XT2
EXCLKS
Input
VDD
AVREF
VSS
AVSS
OCD0A
Note
OCD1A
Note
OCD0B
Note
OCD1B
Note
Input
Input port
P121/X1
P31/INTP2
P122/X2/EXCLK
P32/INTP3
Note PD78F0513DA and 78F0515DA (product with on-chip debug function) only
Users Manual U18598EJ1V0UD
59
2.1.3 78K0/KD2
(1) Port functions (1/2): 78K0/KD2
Function Name
P00
I/O
I/O
Port 0.
After Reset
Input port
P01
Alternate Function
TI000
TI010/TO00
P02
P03
P10
Function
I/O
setting.
Port 1.
Input port
P11
SI10/RxD0
P12
SO10
P13
SCK10/TxD0
TxD6
setting.
P14
RxD6
P15
TOH0
P16
TOH1/INTP5
P17
TI50/TO50
P20 to P27
I/O
Port 2.
Analog input
ANI0 to ANI7
Input port
INTP1
I/O
P31
P32
P33
P40, P41
Port 3.
Note
INTP3/OCD1B
Note
TI51/TO51/INTP4
setting.
I/O
INTP2/OCD1A
Port 4.
Input port
I/O
Port 6.
Input port
P61
SDA0
P62
SCL0
EXSCL0
P63
P70 to P77
I/O
Port 7.
Input port
KR0 to KR7
Input port
INTP0/EXLVI
I/O
Port 12.
5-bit I/O port.
X1/OCD0A
Note
X2/EXCLK/
OCD0B
Note
P123
XT1
P124
XT2/EXCLKS
60
I/O
Output
Function
After Reset
Port 13.
Alternate Function
Output port
I/O
Port 14.
Input port
PCL/INTP6
I/O
Input
Function
A/D converter analog input
After Reset
Analog
Alternate Function
P20 to P27
input
EXLVI
EXSCL0
Input
Input
Input port
P120/INTP0
Input port
P62
FLMD0
INTP0
Input
Input port
INTP1
P120/EXLVI
P30
can be specified
P31/OCD1A
Note
INTP3
P32/OCD1B
Note
INTP4
P33/TI51/TO51
INTP5
P16/TOH1
INTP6
P140/PCL
INTP2
KR0 to KR7
Input
Input port
P70 to P77
PCL
Output
Input port
P140/INTP6
subsystem clock)
REGC
RESET
Input
RxD0
Input
RxD6
SCK10
Input port
P14
Input port
SCL0
P11/SI10
P10/TxD0
P60
SDA0
I/O
Input port
P61
SI10
Input
Input port
P11/RxD0
SO10
Output
Input port
P12
TxD0
Output
Input port
TxD6
P10/SCK10
P13
61
I/O
Input
Function
External count clock input to 16-bit timer/event counter 00
After Reset
Input port
Alternate Function
P00
TI010
P01/TO00
timer/event counter 00
TI50
Input
TI51
Input port
P17/TO50
P33/TO51/INTP4
TO00
Output
Input port
P01/TI010
TO50
Output
Input port
P17/TI50
TO51
P33/TI51/INTP4
TOH0
P15
TOH1
P16/INTP5
X1
Input
X2
Input port
P121/OCD0A
Note
Note
P122/EXCLK/OCD0B
EXCLK
Input
Input port
P122/X2/OCD0B
XT1
Input
Input port
P123
XT2
Input port
P124/EXCLKS
Input port
P124/XT2
EXCLKS
Input
VDD
AVREF
Input
AVSS
VSS.
OCD0A
Note
OCD1A
Note
OCD0B
Note
OCD1B
Note
Input
P121/X1
P31/INTP2
P122/X2/EXCLK
P32/INTP3
62
Input port
Note
2.1.4 78K0/KE2
(1) Port functions (1/2): 78K0/KE2
Function Name
I/O
I/O
P00
Function
Port 0.
After Reset
Input port
P01
SO11
P03
TI000
TI010/TO00
P02
Alternate Function
SI11
setting.
Note 1
Note 1
P04
SCK11
P05
TI001
Note 1
Note 1
SSI11
Note 1
Note 1
TI011
P06
TO01
I/O
P10
Port 1.
Input port
P11
SO10
P13
SCK10/TxD0
SI10/RxD0
P12
Note 1
TxD6
setting.
P14
RxD6
P15
TOH0
P16
TOH1/INTP5
P17
TI50/TO50
P20 to P27
I/O
Port 2.
Analog input
ANI0 to ANI7
Input port
INTP1
P30
Port 3.
4-bit I/O port.
P31
INTP2/OCD1A
P32
INTP3/OCD1B
P33
TI51/TO51/INTP4
setting.
P40 to P43
I/O
Note 2
Note 2
Port 4.
Input port
Input port
I/O
Port 5.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
P60
P61
P62
I/O
Port 6.
Input port
SCL0
SDA0
EXSCL0
P63
Notes 1. Available only in the PD78F0534A, 78F0535A, 78F0536A, 78F0537A, and 78F0537DA.
2. PD78F0537DA (product with on-chip debug function) only
63
I/O
Function
Port 7.
I/O
After Reset
Alternate Function
Input port
KR0 to KR7
Input port
INTP0/EXLVI
Port 12.
I/O
P121
X1/OCD0A
P122
Note
X2/EXCLK/OCD0B
P123
XT1
P124
P130
Note
XT2/EXCLKS
Output
Port 13.
Output port
Port 14.
I/O
Input port
P141
PCL/INTP6
BUZ/INTP7
I/O
Function
After Reset
Alternate Function
ANI0 to ANI7
Input
Analog input
P20 to P27
BUZ
Output
Buzzer output
Input port
P141/INTP7
EXLVI
Input
Input port
P120/INTP0
Input port
P62
EXSCL0
Input
FLMD0
INTP0
Input
Input port
INTP1
P120/EXLVI
P30
specified
P31/OCD1A
Note
INTP3
P32/OCD1B
Note
INTP4
P33/TI51/TO51
INTP5
P16/TOH1
INTP6
P140/PCL
INTP7
P141/BUZ
INTP2
KR0 to KR7
Input
Input port
P70 to P77
PCL
Output
Input port
P140/INTP6
subsystem clock)
REGC
64
I/O
RESET
Input
RxD0
Input
RxD6
Function
System reset input
Serial data input to UART0
After Reset
Alternate Function
Input port
SCK10
SCK11
I/O
Note 1
SCL0
Input port
P11/SI10
P14
P10/TxD0
P04
Input port
P60
SDA0
I/O
Input port
P61
SI10
Input
Input port
P11/RxD0
SI11
Note 1
SO10
SO11
Note 1
SSI11
Note 1
TI000
P03
Input port
P12
P02
Input
Input port
P05/TI001
Input
Input port
P00
TI001
P05/SSI11
Note 1
TI010
P01/TO00
timer/event counter 00
Note 1
TI011
P06/TO01
Note 1
timer/event counter 01
Input
TI50
TI51
Input port
TO00
TO01
Note 1
TO50
Output
Output
Input port
TxD6
Input port
P17/TI50
P15
P16/INTP5
Input port
Note 1
P33/TI51/INTP4
P01/TI010
P06/TI011
TOH1
TxD0
P33/TO51/INTP4
Input port
TO51
TOH0
P17/TO50
P10/SCK10
P13
Input port
P121/OCD0A
Note 2
X1
Input
X2
EXCLK
Input
Input port
P122/X2/
Note 2
OCD0B
XT1
Input
Input port
P123
XT2
Input port
P124/EXCLKS
EXCLKS
Input
Input port
P124/XT2
P122/EXCLK/
Note 2
OCD0B
Notes 1. Available only in the PD78F0534A, 78F0535A, 78F0536A, 78F0537A, and 78F0537DA.
2. PD78F0537DA (product with on-chip debug function) only
Users Manual U18598EJ1V0UD
65
I/O
VDD
EVDD
Function
After Reset
Alternate Function
Positive power supply for P121 to P124 and other than ports
Positive power supply for ports other than P20 to P27 and
Input
VSS
EVSS
Ground potential for ports other than P20 to P27 and P121 to
AVSS
OCD0A
Note
OCD1A
Note
OCD0B
Note
OCD1B
Note
Input
P121/X1
P31/INTP2
P122/X2/EXCLK
P32/INTP3
66
Input port
2.1.5 78K0/KF2
(1) Port functions (1/2): 78K0/KF2
Function Name
P00
I/O
I/O
Function
Port 0.
After Reset
Input port
P01
SO11
P03
TI000
TI010/TO00
P02
Alternate Function
SI11
setting.
P04
SCK11
P05
TI001/SSI11
P06
TI011/TO01
P10
I/O
Port 1.
Input port
P11
SI10/RxD0
P12
SO10
P13
SCK10/TxD0
TxD6
setting.
P14
RxD6
P15
TOH0
P16
TOH1/INTP5
P17
TI50/TO50
P20 to P27
I/O
Port 2.
Analog input
ANI0 to ANI7
Input port
INTP1
I/O
P31
P32
P33
P40 to P47
Port 3.
Note
INTP3/OCD1B
Note
TI51/TO51/INTP4
setting.
I/O
INTP2/OCD1A
Port 4.
Input port
Input port
I/O
Port 5.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
P60
P61
P62
P63 to P67
I/O
Port 6.
Input port
SCL0
SDA0
EXSCL0
67
I/O
I/O
Function
Port 7.
After Reset
Alternate Function
Input port
KR0 to KR7
Input port
INTP0/EXLVI
I/O
Port 12.
5-bit I/O port.
P121
X1/OCD0A
P122
Note
X2/EXCLK/OCD0B
P123
XT1
P124
P130
Note
XT2/EXCLKS
Output
Port 13.
Output port
I/O
Port 14.
Input port
P141
BUZ/BUSY0/INTP7
P142
SCKA0
P143
PCL/INTP6
SIA0
software setting.
P144
SOA0
P145
STB0
I/O
Input
Function
A/D converter analog input
After Reset
Analog
Alternate Function
P20 to P27
input
BUSY0
Input
Input port
P141/BUZ/INTP7
BUZ
Output
Buzzer output
Input port
P141/BUSY0/INTP7
EXLVI
Input
Input port
P120/INTP0
Input port
P62
EXSCL0
Input
FLMD0
INTP0
Input
Input port
INTP1
P120/EXLVI
P30
can be specified
P31/OCD1A
Note
INTP3
P32/OCD1B
Note
INTP4
P33/TI51/TO51
INTP5
P16/TOH1
INTP6
P140/PCL
INTP7
P141/BUZ/BUSY0
INTP2
KR0 to KR7
Input
Input port
68
P70 to P77
I/O
Output
Function
Clock output (for trimming of high-speed system clock,
After Reset
Input port
Alternate Function
P140/INTP6
subsystem clock)
REGC
RESET
Input
RxD0
Input
Input port
P11/SI10
RxD6
Input
Input port
P14
SCK10
I/O
Input port
P10/TxD0
SCK11
SCKA0
SCL0
P04
I/O
I/O
Input port
P142
Input port
P60
SDA0
I/O
Input port
P61
SI10
Input
Input port
P11/RxD0
SI11
P03
SIA0
Input
Input port
P143
SO10
Output
Input port
P12
SO11
P02
SOA0
Output
Input port
P144
SSI11
Input
Input port
P05/TI001
STB0
Output
Input port
P145
TI000
Input
Input port
P00
TI001
P05/SSI11
Input
Input port
P01/TO00
timer/event counter 00
Capture trigger input to capture register (CR001) of 16-bit
TI011
P06/TO01
timer/event counter 01
TI50
Input
TI51
TO00
Output
Input port
P01/TI010
Input port
P17/TI50
P06/TI011
TOH1
P33/TI51/INTP4
Input port
P17/TO50
P33/TO51/INTP4
TO51
TOH0
Input port
TO01
TO50
P15
P16/INTP5
TxD0
Output
Input port
P10/SCK10
TxD6
Output
Input port
P13
69
I/O
X1
X2
EXCLK
Function
Connecting resonator for main system clock
After Reset
Alternate Function
Note
Input port
P121/OCD0A
Input port
P122/EXCLK/OCD0B
Input
Input port
P122/X2/OCD0B
XT1
Input port
P123
XT2
Input port
P124/EXCLKS
Input port
P124/XT2
EXCLKS
Input
VDD
Positive power supply for P121 to P124 and other than ports
EVDD
Positive power supply for ports other than P20 to P27 and
AVREF
VSS
EVSS
Ground potential for ports other than P20 to P27 and P121
AVSS
OCD0A
Note
OCD1A
Note
OCD0B
Note
OCD1B
Note
Input
P121/X1
P31/INTP2
P122/X2/EXCLK
P32/INTP3
70
Input port
Note
Note
The pins mounted depend on the product. See 1.4 Ordering Information and 2.1 Pin Function List.
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 3
P00/TI000
P01/TI010/TO00
P02/SO11
P03/SI11
y = 4 to 7
P02
Note
P03
Note
P04/SCK11
P05/TI001/SSI11
P06/TI011/TO01
y = 4 to 7
P02
Note
P03
Note
P04
Note
P05
Note
P06
Note
Note The 78K0/KD2 products and 78K0/KE2 products whose flash memory is less than 32 KB are only provided
with port functions and not alternate functions.
Remark : Mounted, : Not mounted
The following operation modes can be specified in 1-bit units.
(1) Port mode
P00 to P06 function as an I/O port. P00 to P06 can be set to input or output port in 1-bit units using port mode
register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).
(2) Control mode
P00 to P06 function as timer I/O, serial interface data I/O, clock I/O, and chip select input.
(a) TI000, TI001
These are the pins for inputting an external count clock to 16-bit timer/event counters 00 and 01 and are also
for inputting a capture trigger signal to the capture registers (CR000, CR010 or CR001, CR011) of 16-bit
timer/event counters 00 and 01.
(b) TI010, TI011
These are the pins for inputting a capture trigger signal to the capture register (CR000 or CR001) of 16-bit
timer/event counters 00 and 01.
(c) TO00, TO01
These are timer output pins of 16-bit timer/event counters 00 and 01.
(d) SI11
This is a serial data input pin of serial interface CSI11.
Users Manual U18598EJ1V0UD
71
(e) SO11
This is a serial data output pin of serial interface CSI11.
(f) SCK11
This is a serial clock I/O pin of serial interface CSI11.
(g) SSI11
This is a chip select input pin of serial interface CSI11.
2.2.2 P10 to P17 (port 1)
P10 to P17 function as an I/O port. These pins also function as pins for external interrupt request input, serial
interface data I/O, clock I/O, and timer I/O.
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 3
P10/SCK10/TxD0
P11/SI10/RxD0
P12/SO10
P13/TxD6
P14/RxD6
P15/TOH0
P16/TOH1/INTP5
P17/TI50/TO50
y = 4 to 7
y = 4 to 7
Remark : Mounted
The following operation modes can be specified in 1-bit units.
(1) Port mode
P10 to P17 function as an I/O port. P10 to P17 can be set to input or output port in 1-bit units using port mode
register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).
(2) Control mode
P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, and timer I/O.
(a) SI10
This is a serial data input pin of serial interface CSI10.
(b) SO10
This is a serial data output pin of serial interface CSI10.
(c) SCK10
This is a serial clock I/O pin of serial interface CSI10.
(d) RxD0
This is a serial data input pin of serial interface UART0.
72
(e) RxD6
This is a serial data input pin of serial interface UART6.
(f) TxD0
This is a serial data output pin of serial interface UART0.
(g) TxD6
This is a serial data output pin of serial interface UART6.
(h) TI50
This is the pin for inputting an external count clock to 8-bit timer/event counter 50.
(i)
TO50
This is a timer output pin of 8-it timer/event counter 50.
(j)
TOH0, TOH1
These are the timer output pins of 8-bit timers H0 and H1.
(k) INTP5
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
2.2.3 P20 to P27 (port 2)
P20 to P27 function as an I/O port. These pins also function as pins for A/D converter analog input.
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
Note
P27/ANI7
Note
y = 1 to 3
y = 4 to 7
y = 4 to 7
Note This is not mounted onto 38-pin products of the 78K0/KC2. For the 38-pin products, be sure to set bits 6 and 7
of PM2 to 1, and bits 6 and 7 of P2 to 0.
Remark : Mounted, : Not mounted
The following operation modes can be specified in 1-bit units.
(1) Port mode
P20 to P27 function as an I/O port. P20 to P27 can be set to input or output port in 1-bit units using port mode
register 2 (PM2).
Users Manual U18598EJ1V0UD
73
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 3
P30/INTP1
P31/INTP2/
OCD1A
y = 4 to 7
Note
P32/INTP3/
OCD1B
y = 4 to 7
Note
P33/INTP4/TI51/
TO51
Note OCD1A and OCD1B are provided to the products with an on-chip debug function (PD78F05xxDA) only.
Remark : Mounted
The following operation modes can be specified in 1-bit units.
(1) Port mode
P30 to P33 function as an I/O port. P30 to P33 can be set to input or output port in 1-bit units using port mode
register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).
(2) Control mode
P30 to P33 function as external interrupt request input and timer I/O.
(a) INTP1 to INTP4
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) TI51
This is an external count clock input pin to 8-bit timer/event counter 51.
(c) TO51
This is a timer output pin from 8-bit timer/event counter 51.
Caution 1. In the product with an on-chip debug function (PD78F05xxDA), be sure to pull the
P31/INTP2/OCD1A pin down before a reset release, to prevent malfunction.
74
Caution
2. Process the P31/INTP2/OCD1A pin of the products mounted with the on-chip debug
function (PD78F05xxDA) as follows, when it is not used when it is connected to a flash
memory programmer or an on-chip debug emulator.
P31/INTP2/OCD1A
Flash memory programmer connection
On-chip debug
During reset
emulator connection
Note
Connect to EVSS
Input:
via a resistor.
Connect to EVDD
Note
Note
or EVSS
via a resistor.
as an on-chip debug
Note With products without an EVSS pin, connect them to VSS. With products without an EVDD pin, connect
them to VDD.
Remark
P31 and P32 of the product with an on-chip debug function (PD78F05xxDA) can be used as onchip debug mode setting pins (OCD1A, OCD1B) when the on-chip debug function is used. For
how to connect an on-chip debug emulator (QB-78K0MINI or QB-MINI2), see CHAPTER 28 ONCHIP DEBUG FUNCTION (PD78F05xxDA ONLY).
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 3
y = 4 to 7
y = 4 to 7
P40
P41
P42
P43
P44
P45
P46
P47
Note
Note
Note This is not mounted onto 38-pin products of the 78K0/KC2. For the 38-pin products, be sure to set bits 0 and 1
of PM4 and P4 to 0.
Remark : Mounted, : Not mounted
75
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 3
y = 4 to 7
y = 4 to 7
P50
P51
P52
P53
P54
P55
P56
P57
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 3
y = 4 to 7
y = 4 to 7
P60/SCL0
P61/SDA0
P62/EXSCL0
P63
P64
P65
P66
P67
76
(a) SDA0
This is a serial data I/O pin for serial interface IIC0.
(b) SCL0
This is a serial clock I/O pin for serial interface IIC0.
(c) EXSCL0
This is an external clock input pin to serial interface IIC0. To input an external clock, input a clock of 6.4 MHz.
2.2.8 P70 to P77 (port 7)
P70 to P77 function as an I/O port. These pins also function as key interrupt input pins.
78K0/KB2
78K0/KC2
78K0/KD2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
P70/KR0
P71/KR1
P72/KR2
P73/KR3
P74/KR4
P75/KR5
Note 1
Note 1
78K0/KE2
78K0/KF2
(PD78F053yA)
(PD78F054yA)
y = 1 to 3
y = 4 to 7
P74
Note 2
P75
Note 2
P76/KR6
P77/KR7
Notes 1.
y = 4 to 7
This is not mounted onto 38-pin products of the 78K0/KC2. For the 38-pin products, be sure to set bits 2
and 3 of PM7 and P7 to 0.
2.
This is not mounted onto 38-pin and 44-pin products of the 78K0/KC2. The 48-pin products are only
provided with port functions and not alternate functions.
77
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 3
P120/INTP0/EXLVI
Note
P123/XT1
P124/XT2/EXCLKS
P121/X1/OCD0A
P122/X2/EXCLK/
OCD0B
y = 4 to 7
y = 4 to 7
Note
Note OCD0A and OCD0B are provided to the products with an on-chip debug function (PD78F05xxDA) only.
Remark : Mounted, : Not mounted
The following operation modes can be specified in 1-bit units.
(1) Port mode
P120 to P124 function as an I/O port. P120 to P124 can be set to input or output port using port mode register 12
(PM12). Only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12
(PU12).
(2) Control mode
P120 to P124 function as pins for external interrupt request input, potential input for external low-voltage
detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock
input for main system clock, and external clock input for subsystem clock.
(a) INTP0
This functions as an external interrupt request input (INTP0) for which the valid edge (rising edge, falling
edge, or both rising and falling edges) can be specified.
(b) EXLVI
This is a potential input pin for external low-voltage detection.
(c) X1, X2
These are the pins for connecting a resonator for main system clock.
(d) EXCLK
This is an external clock input pin for main system clock.
(e) XT1, XT2
These are the pins for connecting a resonator for subsystem clock.
78
(f) EXCLKS
This is an external clock input pin for subsystem clock.
Caution
Process the P121/X1/OCD0A pin of the products mounted with the on-chip debug function
(PD78F05xxDA) as follows, when it is not used when it is connected to a flash memory
programmer or an on-chip debug emulator.
P121/X1/OCD0A
Connect to VSS via a resistor.
During reset
emulator connection
Input:
as an on-chip debug
Remark
X1 and X2 of the product with an on-chip debug function (PD78F05xxDA) can be used as onchip debug mode setting pins (OCD0A, OCD0B) when the on-chip debug function is used. For
how to connect an on-chip debug emulator (QB-78K0MINI or QB-MINI2), see CHAPTER 28 ONCHIP DEBUG FUNCTION (PD78F05xxDA ONLY).
P130
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050xA)
(PD78F051xA)
(PD78F052xA)
(PD78F053xA)
(PD78F054xA)
x = 0 to 3
x = 1 to 5
x = 1 to 7
x = 1 to 3
x = 4 to 7
x = 4 to 7
Note
Note This is not mounted onto 38-pin and 44-pin products of the 78K0/KC2.
Remarks 1. When the device is reset, P130 outputs a low level. Therefore, to output a high level from P130 before
the device is reset, the output signal of P130 can be used as a pseudo reset signal of the CPU (see the
figure for Remark in 5.2.10 Port 13).
2. : Mounted, : Not mounted
79
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050xA)
(PD78F051xA)
(PD78F052xA)
(PD78F053xA)
(PD78F054xA)
x = 0 to 3
x = 1 to 5
x = 1 to 7
x = 1 to 3
x = 4 to 7
x = 4 to 7
P140/PCL/INTP6
P141/BUZ/BUSY0/
P142/SCKA0
P143/SIA0
P144/SOA0
P145/STB0
Note 1
P141/BUZ/INTP7
Note 2
INTP7
Notes 1.
2.
This is not mounted onto 38-pin and 44-pin products of the 78K0/KC2.
The 78K0/KE2 products are not provided with the BUSY0 input function.
80
(f) SOA0
This is a serial interface CSIA0 serial data output pin.
(g) SCKA0
This is a serial interface CSIA0 serial clock I/O pin.
(h) STB0
This is a serial interface CSIA0 strobe output pin.
2.2.12 AVREF, AVSS, VDD, EVDD, VSS, EVSS
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050xA)
(PD78F051xA)
(PD78F052xA)
(PD78F053xA)
(PD78F054xA)
x = 0 to 3
x = 1 to 5
x = 1 to 7
x = 1 to 3
x = 4 to 7
AVREF
AVSS
VDD
Note
EVDD
VSS
Note
EVSS
x = 4 to 7
81
VSS
Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
2.2.15 FLMD0
This is a pin for setting flash memory programming mode.
Connect FLMD0 to EVSS or VSS in the normal operation mode.
In flash memory programming mode, connect this pin to the flash memory programmer.
82
The pins mounted depend on the product. See 1.4 Ordering Information (Top View) and 2.1 Pin
Function List.
Table 2-3. Pin I/O Circuit Types (1/3)
Pin Name
P00/TI000
5-AQ
I/O
I/O
P01/TI010/TO00
P02/SO11
5-AG
P03/SI11
Note 1
P04/SCK11
P05/TI001/SSI11
P06/TI011/TO01
P10/SCK10/TxD0
5-AQ
P11/SI10/RxD0
P12/SO10
5-AG
P13/TxD6
P14/RxD6
5-AQ
P15/TOH0
5-AG
P16/TOH1/INTP5
5-AQ
P17/TI50/TO50
ANI0/P20 to ANI7/P27
Note 2
11-G
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
83
I/O
5-AQ
P30/INTP1
P31/INTP2/OCD1A
I/O
Note 1
P32/INTP3/OCD1B
P33/TI51/TO51/INTP4
P40 to P47
5-AG
P50 to P57
P60/SCL0
Input:
13-AI
P61/SDA0
P62/EXSCL0
P63
13-P
P64 to P67
5-AG
Input:
5-AQ
P70/KR0 to P77/KR7
P120/INTP0/EXLVI
P121/X1/OCD0A
Notes 1, 2
Input:
37
P122/X2/EXCLK/
OCD0B
Notes 2
P123/XT1
Note 2
P124/XT2/EXCLKS
Note 2
P130
3-C
Output
Leave open.
Notes 1. Process the P31/INTP2/OCD1A and P121/X1/OCD0A pins of the products mounted with the on-chip
debug function (PD78F05xxDA) as follows, when it is not used when it is connected to a flash memory
programmer or an on-chip debug emulator.
P31/INTP2/OCD1A
Flash memory programmer connection
On-chip debug
During reset
emulator
During reset
connection (when
released
it is not used as an
P121/X1/OCD0A
resistor.
resistor.
Input:
Connect to EVDD or
EVSS via a resistor.
Input:
Connect to VDD or
VSS via a resistor.
on-chip debug
mode setting pin)
2. Use recommended connection above in I/O port mode (see Figure 6-2 Format of Clock Operation
Mode Select Register (OSCCTL)) when these pins are not used.
Remark
84
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
I/O
Input:
I/O
5-AQ
P141/BUZ/BUSY0/INTP7
P142/SCKA0
P143/SIA0
P144/SOA0
5-AG
P145/STB0
AVREF
AVSS
FLMD0
38-A
RESET
Input
Note 1
Note 2
Notes 1. Make the same potential as the VDD pin when port 2 is used as a digital port.
2. FLMD0 is a pin that is used to write data to the flash memory. To rewrite the data of the flash memory
on-board, connect this pin to EVSS or VSS via a resistor (10 k: recommended). The same applies
when executing on-chip debugging with a product with an on-chip debug function (PD78F05xxDA).
Remark
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
85
Type 5-AG
EVDD
Pull-up
enable
P-ch
EVDD
IN
Data
P-ch
IN/OUT
Output
disable
N-ch
EVSS
Input
enable
Type 3-C
Type 5-AQ
EVDD
pullup
enable
EVDD
P-ch
Data
P-ch
EVDD
OUT
data
P-ch
IN/OUT
N-ch
output
disable
N-ch
EVSS
EVSS
input
enable
Remark
86
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
Type 37
VDD
Data
AVREF
P-ch
X2,
XT2
Data
P-ch
IN/OUT
Output
disable
N-ch
RESET
Output
disable
VSS
N-ch
VDD
P-ch
P-ch
Comparator
N-ch
Input
enable
AVSS
Data
P-ch
N-ch
X1,
XT1
Output
disable
AVSS
N-ch
RESET
VSS
Input enable
Input
enable
Type 13-P
Type 38-A
IN/OUT
Data
Output
disable
IN
N-ch
EVSS
input
enable
Input
enable
Type 13-AI
IN/OUT
data
output
disable
N-ch
EVSS
input
enable
Remark
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
87
IMS
ROM Capacity
(78K0/KB2)
Internal High-Speed
RAM Capacity
PD78F0500A
42H
8 KB
512 bytes
PD78F0501A
04H
16 KB
768 bytes
C6H
24 KB
1 KB
C8H
32 KB
1 KB
PD78F0502A
PD78F0503A, 78F0503DA
Note
Note The ROM and RAM capacities of the products with the on-chip debug function can
be debugged by setting IMS, according to the debug target products. Set IMS
according to the debug target products.
88
Table 3-2. Set Values of Internal Memory Size Switching Register (IMS) and Internal Expansion RAM Size
Switching Register (IXS) (78K0/KC2, 78K0/KD2, 78K0/KE2, 78K0/KF2)
78K0/KC2, 78K0/KD2,
IMS
IXS
ROM Capacity
78K0/KE2, 78K0/KF2
Internal High-Speed
Internal Expansion
RAM Capacity
RAM Capacity
PD78F05x1A (x = 1 to 3)
04H
0CH
16 KB
768 bytes
PD78F05x2A (x = 1 to 3)
C6H
0CH
24 KB
1 KB
PD78F05x3A (x = 1 to 3),
C8H
0CH
32 KB
1 KB
PD78F05x4A (x = 1 to 4)
CCH
0AH
48 KB
1 KB
PD78F05x5A (x = 1 to 4),
CFH
08H
60 KB
Note 2
04H
96 KB
Note 2
00H
128 KB
78F0513DA
78F0515DA
Note 1
2 KB
Note 1
PD78F05x6A (x = 2 to 4)
PD78F05x7A,
78F05x7DA
1 KB
Note 1
CCH
CCH
Note 2
Note 2
4 KB
6 KB
(x = 2 to 4)
Notes 1. The ROM and RAM capacities of the products with the on-chip debug function can be debugged
according to the debug target products. Set IMS and IXS according to the debug target products.
2. The PD78F05x6A (x = 2 to 4) has internal ROMs of 96 KB, and the PD78F05x7A and 78F05x7DA
(x = 2 to 4) have those of 128 KB. However, the set value of IMS of these devices is the same as those
of the 48 KB product because memory banks are used. For how to set the memory banks, see 4.3
Memory Bank Select Register (BANK).
89
General-purpose
registers
32 8 bits
1FFFH
Program area
1085H
1084H
1080H
107FH
FD00H
FCFFH
Boot cluster 1
Program area
Data memory
space
1000H
0FFFH
CALLF entry area
2048 8 bits
0800H
07FFH
Reserved
Program area
1915 8 bits
0085H
0084H
0080H
007FH
2000H
1FFFH
0040H
003FH
Program
memory space
Flash memory
8192 8 bits
0000H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used:
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8
Security
Setting).
Remark
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory.
1FFFH
Block 07H
1C00H
1BFFH
07FFH
0400H
03FFH
0000H
90
Block 01H
Block 00H
1 KB
General-purpose
registers
32 8 bits
3FFFH
Program area
1FFFH
1085H
1084H
1080H
107FH
FC00H
FBFFH
Boot cluster 1
Program area
Data memory
space
1000H
0FFFH
CALLF entry area
2048 8 bits
0800H
07FFH
Reserved
Program area
1915 8 bits
0085H
0084H
0080H
007FH
4000H
3FFFH
Program
memory space
0040H
003FH
Flash memory
16384 8 bits
0000H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used:
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8
Security
Setting).
Remark
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory.
3FFFH
Block 0FH
3C00H
3BFFH
07FFH
0400H
03FFH
0000H
Block 01H
Block 00H
1 KB
91
General-purpose
registers
32 8 bits
5FFFH
Program area
1FFFH
1085H
1084H
1080H
107FH
FB00H
FAFFH
Boot cluster 1
Program area
Data memory
space
1000H
0FFFH
CALLF entry area
2048 8 bits
0800H
07FFH
Reserved
0085H
0084H
0080H
007FH
Program area
1915 8 bits
Option byte areaNote 1
5 8 bits
6000H
5FFFH
Program
memory space
0040H
003FH
Flash memory
24576 8 bits
0000H
0000H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used:
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8
Security
Setting).
Remark
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory.
5FFFH
Block 17H
5C00H
5BFFH
07FFH
0400H
03FFH
0000H
92
Block 01H
Block 00H
1 KB
General-purpose
registers
32 8 bits
7FFFH
Program area
1085H
1084H
1080H
107FH
1FFFH
Boot cluster 1
Program area
Data memory
space
1000H
0FFFH
CALLF entry area
2048 8 bits
Reserved
0800H
07FFH
0085H
0084H
0080H
007FH
8000H
7FFFH
0040H
003FH
Program
memory space
Flash memory
32768 8 bits
0000H
0000H
Program area
1915 8 bits
Option byte areaNote 1
5 8 bits
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used:
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8
Security
Setting).
Remark
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory.
7FFFH
Block 1FH
7C00H
7BFFH
07FFH
0400H
03FFH
0000H
Block 01H
Block 00H
1 KB
93
7FFFH
Program area
108FH
108EH
General-purpose
registers
32 8 bits
1085H
1084H
Internal high-speed RAM
1024 8 bits
1FFFH
On-chip debug security
ID setting areaNote 1
10 8 bits
Option byte areaNote 1
5 8 bits
1080H
107FH
Boot cluster 1
Program area
1000H
0FFFH
FB00H
FAFFH
Data memory
space
0800H
07FFH
Program area
1905 8 bits
Reserved
008FH
008EH
0085H
0084H
0080H
007FH
8000H
7FFFH
Program
memory space
0040H
003FH
Flash memory
32768 8 bits
0000H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security
IDs to 0085H to 008EH.
When boot swap is used:
Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the
on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8
Security
Setting).
Remark
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory.
7FFFH
Block 1FH
7C00H
7BFFH
07FFH
0400H
03FFH
0000H
94
Block 01H
Block 00H
1 KB
General-purpose
registers
32 8 bits
BFFFH
Program area
1FFFH
1085H
1084H
1080H
107FH
Reserved
Buffer RAM
32 8 bitsNote 3
FA00H
F9FFH
F800H
F7FFH
1000H
0FFFH
Reserved
0800H
07FFH
Program area
1915 8 bits
F400H
F3FFH
0085H
0084H
0080H
007FH
Reserved
C000H
BFFFH
Program
memory space
Boot cluster 1
Program area
0040H
003FH
Flash memory
49152 8 bits
0000H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used:
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8
Security
Setting).
3. The buffer RAM is incorporated only in the PD78F0544A (78K0/KF2). The area from FA00H to
FA1FH cannot be used with the PD78F0514A, 78F0524A, and 78F0534A.
Remark
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory.
BFFFH
Block 2FH
BC00H
BBFFH
07FFH
0400H
03FFH
0000H
Block 01H
Block 00H
1 KB
95
General-purpose
registers
32 8 bits
EFFFH
Program area
1FFFH
1085H
1084H
1080H
107FH
Reserved
Buffer RAM
32 8 bitsNote 3
Data memory
space
FA00H
F9FFH
F800H
F7FFH
1000H
0FFFH
Reserved
0800H
07FFH
Program area
1915 8 bits
F000H
EFFFH
Program
memory space
Boot cluster 1
Program area
0085H
0084H
0080H
007FH
Flash memory
61440 8 bits
0040H
003FH
0000H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used:
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8
Security
Setting).
3. The buffer RAM is incorporated only in the PD78F0545A (78K0/KF2). The area from FA00H to
FA1FH cannot be used with the PD78F0515A, 78F0525A, and 78F0535A.
Remark
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory.
EFFFH
EC00H
EBFFH
Block 3BH
07FFH
0400H
03FFH
0000H
96
Block 01H
Block 00H
1 KB
EFFFH
Program area
1FFFH
General-purpose
registers
32 8 bits
108FH
108EH
1085H
1084H
1080H
107FH
FB00H
FAFFH
Boot cluster 1
Program area
1000H
0FFFH
Reserved
0800H
07FFH
Program area
1905 x 8 bits
008FH
008EH
F000H
EFFFH
0085H
0084H
0080H
007FH
Program
memory space
Flash memory
61440 8 bits
0040H
003FH
Vector table area
64 x 8 bits
0000H
0000H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security
IDs to 0085H to 008EH.
When boot swap is used:
Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the
on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8
Security
Setting).
Remark
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory.
EFFFH
EC00H
EBFFH
Block 3BH
07FFH
0400H
03FFH
0000H
Block 01H
Block 00H
1 KB
97
General-purpose
registers
32 8 bits
Internal high-speed RAM
1024 8 bits
7FFFH
Program area
Reserved
1FFFH
1085H
1084H
1080H
107FH
Buffer RAM
32 8 bitsNote 3
Data memory
space
FA00H
F9FFH
F800H
F7FFH
Program RAM area
RAM space in
which instruction
can be fetched
E800H
E7FFH
Reserved
1000H
0FFFH
(Memory bank 2)
C000H
BFFFH
0085H
0084H
0080H
007FH
Flash memory
16384 8 bits
(memory bank 0)
8000H
Program
7FFFH
memory
space
Common
area
(Memory bank 3)
Flash memory
32768 8 bits
Boot cluster 1
Program area
Reserved
Bank
area
(Memory bank 1)
0040H
003FH
0000H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used:
Set the option bytes to 0080H to 0084H and 1080H to 1084H.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security
Setting).
3. The buffer RAM is incorporated only in the PD78F0546A (78K0/KF2). The area from FA00H to
FA1FH cannot be used with the PD78F0526A and 78F0536A.
Remark
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory.
(Memory bank 0)
BFFFH
BC00H
BBFFH
Bank
area
(Memory bank 1)
(Memory bank 3)
Block 3FH
Block 4FH
Block 5FH
Block 20H
Block 30H
Block 40H
Block 50H
84FFH
83FFH
8000H
7FFFH
Block 1FH
7C00H
7BFFH
Common
area
07FFH
0400H
03FFH
1 KB
98
(Memory bank 2)
Block 2FH
0000H
Block 01H
Block 00H
General-purpose
registers
32 8 bits
Internal high-speed RAM
1024 8 bits
7FFFH
Program area
Reserved
1FFFH
1085H
1084H
1080H
107FH
Buffer RAM
32 8 bitsNote 3
Data memory
space
FA00H
F9FFH
F800H
F7FFH
Reserved
Program area
(Memory bank 2)
1000H
0FFFH
CALLF entry area
2048 8 bits
0800H
07FFH
Reserved
Program area
1915 8 bits
C000H
BFFFH
0085H
0084H
0080H
007FH
Flash memory
16384 8 bits
(memory bank 0)
Bank
area
Boot cluster 1
(Memory bank 4)
Note 1
8000H
Program
7FFFH
memory
space
Common
area
(Memory bank 5)
(Memory bank 3)
Flash memory
32768 8 bits
0040H
003FH
(Memory bank 1)
0000H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used:
Set the option bytes to 0080H to 0084H and 1080H to 1084H.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security
Setting).
3. The buffer RAM is incorporated only in the PD78F0547A (78K0/KF2). The area from FA00H to
FA1FH cannot be used with the PD78F0527A and 78F0537A.
Remark
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory.
(Memory bank 0)
(Memory bank 1)
(Memory bank 5)
(Memory bank 2)
BFFFH
BC00H
BBFFH
Bank
area
Block 2FH
Block 3FH
...
84FFH
83FFH
8000H
7FFFH
Block 7FH
Block 4FH
Block 20H
Block 30H
Block 40H
Block 70H
Block 1FH
7C00H
7BFFH
Common
area
07FFH
1 KB
0400H
03FFH
0000H
Block 01H
Block 00H
99
7FFFH
General-purpose
registers
32 8 bits
Program area
108FH
108EH
1085H
1084H
Reserved
1080H
107FH
Buffer RAM
32 8 bitsNote 3
Data memory
space
FA00H
F9FFH
F800H
F7FFH
Program RAM area
RAM space in
which instruction
can be fetched
E000H
DFFFH
Boot cluster 1
Program area
Reserved
CALLF entry area
2048 8 bits
(Memory bank 4)
(Memory bank 2)
0800H
07FFH
Program area
1905 8 bits
008FH
008EH
C000H
BFFFH
0085H
0084H
0080H
007FH
Flash memory
16384 8 bits
(memory bank 0)
8000H
7FFFH
Program
memory
space
Common
area
1000H
0FFFH
Reserved
Bank
area
1FFFH
(Memory bank 5)
(Memory bank 3)
Flash memory
32768 8 bits
0040H
003FH
(Memory bank 1)
0000H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security
IDs to 0085H to 008EH.
When boot swap is used:
Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the
on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security
Setting).
3. The buffer RAM is incorporated only in the PD78F0547DA (78K0/KF2). The area from FA00H to
FA1FH cannot be used with the PD78F0527DA and 78F0537DA.
Remark
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-3 Correspondence Between Address Values and Block Numbers in Flash Memory.
(Memory bank 0)
(Memory bank 1)
(Memory bank 5)
(Memory bank 2)
BFFFH
BC00H
BBFFH
Bank
area
Block 2FH
Block 3FH
...
84FFH
83FFH
8000H
7FFFH
Block 20H
Block 30H
Block 1FH
7C00H
7BFFH
Common
area
07FFH
1 KB
100
0400H
03FFH
0000H
Block 7FH
Block 4FH
Block 01H
Block 00H
Block 40H
Block 70H
Correspondence between the address values and block numbers in the flash memory are shown below.
Table 3-3. Correspondence Between Address Values and Block Numbers in Flash Memory (1/2)
(1) PD78F0500A, 78F05x1A (x = 0 to 3), 78F05x2A (x = 0 to 3), 78F05x3A (x = 0 to 3), 78F05x4A (x = 1 to 4),
78F05x5A (x = 1 to 4), 78F0503DA, 78F0513DA, 78F0515DA
Address Value
Block
Address Value
Number
Block
Address Value
Number
Block
Address Value
Number
Block
Number
0000H to 03FFH
00H
4000H to 43FFH
10H
8000H to 83FFH
20H
C000H to C3FFH
30H
0400H to 07FFH
01H
4400H to 47FFH
11H
8400H to 87FFH
21H
C400H to C7FFH
31H
0800H to 0BFFH
02H
4800H to 4BFFH
12H
8800H to 8BFFH
22H
C800H to CBFFH
32H
0C00H to 0FFFH
03H
4C00H to 4FFFH
13H
8C00H to 8FFFH
23H
CC00H to CFFFH
33H
1000H to 13FFH
04H
5000H to 53FFH
14H
9000H to 93FFH
24H
D000H to D3FFH
34H
1400H to 17FFH
05H
5400H to 57FFH
15H
9400H to 97FFH
25H
D400H to D7FFH
35H
1800H to 1BFFH
06H
5800H to 5BFFH
16H
9800H to 9BFFH
26H
D800H to DBFFH
36H
1C00H to 1FFFH
07H
5C00H to 5FFFH
17H
9C00H to 9FFFH
27H
DC00H to DFFFH
37H
2000H to 23FFH
08H
6000H to 63FFH
18H
A000H to A3FFH
28H
E000H to E3FFH
38H
2400H to 27FFH
09H
6400H to 67FFH
19H
A400H to A7FFH
29H
E400H to E7FFH
39H
2800H to 2BFFH
0AH
6800H to 6BFFH
1AH
A800H to ABFFH
2AH
E800H to EBFFH
3AH
2C00H to 2FFFH
0BH
6C00H to 6FFFH
1BH
AC00H to AFFFH
2BH
EC00H to EFFFH
3BH
3000H to 33FFH
0CH
7000H to 73FFH
1CH
B000H to B3FFH
2CH
3400H to 37FFH
0DH
7400H to 77FFH
1DH
B400H to B7FFH
2DH
3800H to 3BFFH
0EH
7800H to 7BFFH
1EH
B800H to BBFFH
2EH
3C00H to 3FFFH
0FH
7C00H to 7FFFH
1FH
BC00H to BFFFH
2FH
Remark
PD78F0500A:
Block numbers 00H to 07H
PD78F05x1A (x = 0 to 3):
Block numbers 00H to 0FH
PD78F05x2A (x = 0 to 3):
Block numbers 00H to 17H
PD78F05x3A (x = 0 to 3), 78F0503DA, 78F0513DA: Block numbers 00H to 1FH
PD78F05x4A (x = 1 to 4):
Block numbers 00H to 2FH
PD78F05x5A (x = 1 to 4), 78F0515DA:
Block numbers 00H to 3BH
101
Table 3-3. Correspondence Between Address Values and Block Numbers in Flash Memory (2/2)
Address Value
0000H to 03FFH
00H
8000H to 83FFH
0400H to 07FFH
01H
0800H to 0BFFH
Block
Address Value
Number
20H
8000H to 83FFH
8400H to 87FFH
21H
02H
8800H to 8BFFH
0C00H to 0FFFH
03H
1000H to 13FFH
Block
Address Value
Number
Memory Bank
Block
Number
Memory Bank
Address Value
Memory Bank
Block
Number
40H
8000H to 83FFH
8400H to 87FFH
41H
8400H to 87FFH
61H
22H
8800H to 8BFFH
42H
8800H to 8BFFH
62H
8C00H to 8FFFH
23H
8C00H to 8FFFH
43H
8C00H to 8FFFH
63H
04H
9000H to 93FFH
24H
9000H to 93FFH
44H
9000H to 93FFH
64H
1400H to 17FFH
05H
9400H to 97FFH
25H
9400H to 97FFH
45H
9400H to 97FFH
65H
1800H to 1BFFH
06H
9800H to 9BFFH
26H
9800H to 9BFFH
46H
9800H to 9BFFH
66H
1C00H to 1FFFH
07H
9C00H to 9FFFH
27H
9C00H to 9FFFH
47H
9C00H to 9FFFH
67H
2000H to 23FFH
08H
A000H to A3FFH
28H
A000H to A3FFH
48H
A000H to A3FFH
68H
2400H to 27FFH
09H
A400H to A7FFH
29H
A400H to A7FFH
49H
A400H to A7FFH
69H
2800H to 2BFFH
0AH
A800H to ABFFH
2AH
A800H to ABFFH
4AH
A800H to ABFFH
6AH
2C00H to 2FFFH
0BH
AC00H to AFFFH
2BH
AC00H to AFFFH
4BH
AC00H to AFFFH
6BH
3000H to 33FFH
0CH
B000H to B3FFH
2CH
B000H to B3FFH
4CH
B000H to B3FFH
6CH
3400H to 37FFH
0DH
B400H to B7FFH
2DH
B400H to B7FFH
4DH
B400H to B7FFH
6DH
3800H to 3BFFH
0EH
B800H to BBFFH
2EH
B800H to BBFFH
4EH
B800H to BBFFH
6EH
3C00H to 3FFFH
0FH
BC00H to BFFFH
2FH
BC00H to BFFFH
4FH
BC00H to BFFFH
6FH
4000H to 43FFH
10H
8000H to 83FFH
30H
8000H to 83FFH
50H
8000H to 83FFH
4400H to 47FFH
11H
8400H to 87FFH
31H
8400H to 87FFH
51H
8400H to 87FFH
71H
4800H to 4BFFH
12H
8800H to 8BFFH
32H
8800H to 8BFFH
52H
8800H to 8BFFH
72H
4C00H to 4FFFH
13H
8C00H to 8FFFH
33H
8C00H to 8FFFH
53H
8C00H to 8FFFH
73H
5000H to 53FFH
14H
9000H to 93FFH
34H
9000H to 93FFH
54H
9000H to 93FFH
74H
5400H to 57FFH
15H
9400H to 97FFH
35H
9400H to 97FFH
55H
9400H to 97FFH
75H
5800H to 5BFFH
16H
9800H to 9BFFH
36H
9800H to 9BFFH
56H
9800H to 9BFFH
76H
5C00H to 5FFFH
17H
9C00H to 9FFFH
37H
9C00H to 9FFFH
57H
9C00H to 9FFFH
77H
6000H to 63FFH
18H
A000H to A3FFH
38H
A000H to A3FFH
58H
A000H to A3FFH
78H
6400H to 67FFH
19H
A400H to A7FFH
39H
A400H to A7FFH
59H
A400H to A7FFH
79H
6800H to 6BFFH
1AH
A800H to ABFFH
3AH
A800H to ABFFH
5AH
A800H to ABFFH
7AH
6C00H to 6FFFH
1BH
AC00H to AFFFH
3BH
AC00H to AFFFH
5BH
AC00H to AFFFH
7BH
7000H to 73FFH
1CH
B000H to B3FFH
3CH
B000H to B3FFH
5CH
B000H to B3FFH
7CH
7400H to 77FFH
1DH
B400H to B7FFH
3DH
B400H to B7FFH
5DH
B400H to B7FFH
7DH
7800H to 7BFFH
1EH
B800H to BBFFH
3EH
B800H to BBFFH
5EH
B800H to BBFFH
7EH
7C00H to 7FFFH
1FH
BC00H to BFFFH
3FH
BC00H to BFFFH
5FH
BC00H to BFFFH
7FH
Remark
102
PD78F05x6A (x = 2 to 4):
Block numbers 00H to 5FH
PD78F05x7A, 78F05x7DA (x = 2 to 4): Block numbers 00H to 7FH
Users Manual U18598EJ1V0UD
60H
70H
Internal ROM
Structure
PD78F0500A
Flash memory
Capacity
8192 8 bits (0000H to 1FFFH)
PD78F05x1A (x = 0 to 3)
PD78F05x2A (x = 0 to 3)
78F0513DA
PD78F05x4A (x = 1 to 4)
PD78F05x6A (x = 2 to 4)
98304 8 bits
(0000H to 7FFFH (common area: 32 KB) +
8000H to BFFFH (bank area: 16 KB) 4)
PD78F05x7A, 78F05x7DA (x = 2 to 4)
131072 8 bits
(0000H to 7FFFH (common area: 32 KB) +
8000H to BFFFH (bank area: 16 KB) 6)
The internal program memory space is divided into the following areas.
(1) Vector table area
The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch
upon reset or generation of each interrupt request are stored in the vector table area.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd
addresses.
103
Interrupt Source
KB2
KC2
KD2
KE2
KF2
0000H
0004H
INTLVI
0006H
INTP0
0008H
INTP1
000AH
INTP2
000CH
INTP3
000EH
INTP4
0010H
INTP5
0012H
INTSRE6
0014H
INTSR6
0016H
INTST6
0018H
INTCSI10/INTST0
001AH
INTTMH1
001CH
INTTMH0
001EH
INTTM50
0020H
INTTM000
0022H
INTTM010
0024H
INTAD
0026H
INTSR0
0028H
INTWTI
002AH
INTTM51
002CH
INTKR
002EH
INTWT
0030H
INTP6
0032H
INTP7
0034H
0036H
0038H
Note 2
INTIIC0/NTDMU
Note 1
INTCSI11
INTTM001
Note 2
Note 3
Note 3
Note 3
INTTM011
003CH
INTACSI
003EH
BRK
2. INTIIC0:
104
Note 2
003AH
Remark
Note 2
105
PD78F0500A
PD78F05x1A (x = 0 to 3)
PD78F05x2A (x = 0 to 3)
PD78F05x3A (x = 0 to 3),
78F0503DA, 78F0513DA
PD78F05x4A (x = 1 to 4)
PD78F05x5A (x = 1 to 4),
78F0515DA
PD78F05x6A (x = 2 to 4)
PD78F05x7A, 78F05x7DA
(x = 2 to 4)
The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit
registers per bank.
This area cannot be used as a program area in which instructions are written and executed.
The internal high-speed RAM can also be used as a stack memory.
(2) Internal expansion RAM
Table 3-7. Internal Expansion RAM Capacity
Part Number
PD78F0500A
PD78F05x1A (x = 0 to 3)
PD78F05x2A (x = 0 to 3)
PD78F05x3A (x = 0 to 3),
78F0503DA, 78F0513DA
PD78F05x4A (x = 1 to 4)
PD78F05x5A (x = 1 to 4),
78F0515DA
PD78F05x6A (x = 2 to 4)
PD78F05x7A, 78F05x7DA
(x = 2 to 4)
The internal expansion RAM can also be used as a normal data area similar to the internal high-speed RAM, as
well as a program area in which instructions can be written and executed.
The internal expansion RAM cannot be used as a stack memory.
106
107
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
FE20H
FE1FH
General-purpose
registers
32 8 bits
SFR addressing
Register addressing
Short direct
addressing
FD00H
FCFFH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
2000H
1FFFH
Flash memory
8192 8 bits
0000H
108
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
General-purpose
registers
32 x 8 bits
Register addressing
Short direct
addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
4000H
3FFFH
Flash memory
16384 x 8 bits
0000H
109
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
General-purpose
registers
32 x 8 bits
Register addressing
Short direct
addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
6000H
5FFFH
Flash memory
24576 x 8 bits
0000H
110
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
General-purpose registers
32 8 bits
Register addressing
Short direct
addressing
FB00H
FAFFH
8000H
7FFFH
Flash memory
32768 8 bits
0000H
111
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
General-purpose registers
32 8 bits
Register addressing
Short direct
addressing
Reserved
Buffer RAM
32 8 bitsNote
FA00H
F9FFH
F800H
F7FFH
Direct addressing
Reserved
F400H
F3FFH
Reserved
C000H
BFFFH
Flash memory
49152 8 bits
0000H
Note The buffer RAM is incorporated only in the PD78F0544A (78K0/KF2). The area from FA00H to FA1FH
cannot be used with the PD78F0514A, 78F0524A, and 78F0534A.
112
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
General-purpose registers
32 8 bits
Register addressing
Short direct
addressing
Reserved
Buffer RAM
32 8 bitsNote
FA00H
F9FFH
F800H
F7FFH
Direct addressing
Register indirect addressing
Reserved
Based addressing
Based indexed addressing
Internal expansion RAM
2048 8 bits
F000H
EFFFH
Flash memory
61440 8 bits
0000H
Note The buffer RAM is incorporated only in the PD78F0545A (78K0/KF2). The area from FA00H to FA1FH
cannot be used with the PD78F0515A, 78F0525A, 78F0535A, and 78F0515DA.
113
Figure 3-18. Correspondence Between Data Memory and Addressing (PD78F0526A, 78F0536A, 78F0546A)
FFFFH
Special function registers (SFR)
256 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
General-purpose registers
32 8 bits
Register addressing
Short direct
addressing
Reserved
Buffer RAM
32 8 bitsNote 1
FA00H
F9FFH
F800H
F7FFH
Direct addressing
Register indirect addressing
Reserved
Based addressing
Based indexed addressing
Internal expansion RAM
4096 8 bits
16384 8 bits
(memory bank 2)Note 2
E800H
E7FFH
Reserved
C000H
BFFFH
Flash memory
16384 8 bits
(memory bank 0)Note 2
8000H
7FFFH
Flash memory
32768 8 bits
16384 8 bits
(memory bank 3)Note 2
16384 8 bits
(memory bank 1)Note 2
0000H
Notes 1. The buffer RAM is incorporated only in the PD78F0546A (78K0/KF2). The area from FA00H to
FA1FH cannot be used with the PD78F0526A and 78F0536A.
2. To branch to or address a memory bank that is not set by the memory bank select register (BANK),
change the setting of the memory bank by using BANK.
114
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
General-purpose registers
32 8 bits
Register addressing
Short direct
addressing
Reserved
Buffer RAM
32 8 bitsNote 1
FA00H
F9FFH
F800H
F7FFH
Direct addressing
Register indirect addressing
Reserved
Based addressing
Based indexed addressing
16384 8 bits
(memory bank 4)Note 2
16384 8 bits
(memory
bank 2)Note 2
E000H
DFFFH
Reserved
C000H
BFFFH
Flash memory
16384 8 bits
(memory bank 0)Note 2
8000H
7FFFH
16384 8 bits
(memory bank 5)Note 2
Flash memory
32768 8 bits
16384 8 bits
(memory bank 3)Note 2
16384 8 bits
(memory bank 1)Note 2
0000H
Notes 1. The buffer RAM is incorporated only in the PD78F0547A and 78F0547DA (78K0/KF2). The area from
FA00H to FA1FH cannot be used with the PD78F0527A, 78F0537A, 78F0527DA, and 78F0537DA.
2. To branch to or address a memory bank that is not set by the memory bank select register (BANK),
change the setting of the memory bank by using BANK.
115
15
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
IE
0
Z
RBS1
AC
RBS0
ISP
CY
116
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from
the stack memory.
Each stack operation saves/restores data as shown in Figures 3-23 and 3-24.
Caution Since reset signal generation makes the SP contents undefined, be sure to initialize the SP
before using the stack.
117
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
FEDEH
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
PC15 to PC8
FEDEH
PC7 to PC0
SP
SP
118
FEE0H
FEDDH
FEE0H
FEDFH
PSW
FEDEH
PC15 to PC8
FEDDH
PC7 to PC0
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
FEDEH
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
PC15 to PC8
FEDEH
PC7 to PC0
SP
SP
FEE0H
FEDDH
FEE0H
FEDFH
PSW
FEDEH
PC15 to PC8
FEDDH
PC7 to PC0
119
The
general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register
(AX, BC, DE, and HL).
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and
absolute names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of
the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for interrupts for each bank.
Figure 3-25. Configuration of General-Purpose Registers
(a) Function name
16-bit processing
8-bit processing
FEFFH
H
Register bank 0
HL
L
FEF8H
D
Register bank 1
DE
E
FEF0H
B
BC
Register bank 2
FEE8H
A
AX
Register bank 3
X
FEE0H
15
8-bit processing
FEFFH
R7
Register bank 0
RP3
R6
FEF8H
R5
Register bank 1
RP2
R4
FEF0H
R3
RP1
Register bank 2
R2
FEE8H
R1
RP0
Register bank 3
R0
FEE0H
15
120
Read only
W:
Write only
121
Symbol
R/W
8 Bits
16 Bits
After
Reset
K
B
2
K
C
2
K
D
2
K
E
2
K
F
2
FF00H
Port register 0
P0
R/W
00H
FF01H
Port register 1
P1
R/W
00H
FF02H
Port register 2
P2
R/W
00H
FF03H
Port register 3
P3
R/W
00H
FF04H
Port register 4
P4
R/W
00H
FF05H
Port register 5
P5
R/W
00H
FF06H
Port register 6
P6
R/W
00H
FF07H
Port register 7
P7
R/W
00H
FF08H
ADCR
0000H
FF09H
ADCRH
00H
FF0AH
RXB6
FFH
FF0BH
TXB6
R/W
FFH
FF0CH
Port register 12
P12
R/W
00H
FF0DH
Port register 13
P13
R/W
00H
Note
FF0EH
Port register 14
P14
R/W
00H
Note
FF0FH
SIO10
00H
FF10H
TM00
0000H
CR000
R/W
0000H
CR010
R/W
0000H
FF15H
FF16H
TM50
00H
FF17H
CR50
R/W
00H
FF18H
CMP00
R/W
00H
FF11H
FF12H
FF13H
FF14H
FF19H
CMP10
R/W
00H
FF1AH
CMP01
R/W
00H
FF1BH
CMP11
R/W
00H
FF1FH
TM51
00H
FF20H
PM0
R/W
FFH
FF21H
PM1
R/W
FFH
FF22H
PM2
R/W
FFH
FF23H
PM3
R/W
FFH
FF24H
PM4
R/W
FFH
FF25H
PM5
R/W
FFH
FF26H
PM6
R/W
FFH
FF27H
PM7
R/W
FFH
FF28H
ADM
R/W
00H
FF29H
ADS
R/W
00H
FF2CH
PM12
R/W
FFH
FF2EH
PM14
R/W
FFH
Note
FF2FH
ADPC
R/W
00H
122
Symbol
K
B
2
K
C
2
K
D
2
K
E
2
K
F
2
FF30H
PU0
R/W
00H
FF31H
PU1
R/W
00H
FF33H
PU3
R/W
00H
FF34H
PU4
R/W
00H
FF35H
PU5
R/W
00H
FF36H
PU6
R/W
00H
FF37H
PU7
R/W
00H
PU12
R/W
00H
FF3EH
PU14
R/W
00H
Note 1
FF40H
CKS
R/W
00H
Note 1
FF41H
CR51
R/W
00H
FF43H
TMC51
R/W
00H
FF48H
EGP
R/W
00H
FF49H
EGN
R/W
00H
FF4AH
SIO11
00H
Note 2
SOTB11
R/W
00H
Note 2
FF4FH
ISC
R/W
00H
FF50H
ASIM6
R/W
01H
FF53H
ASIS6
00H
FF55H
ASIF6
00H
FF56H
CKSR6
R/W
00H
FF57H
BRGC6
R/W
FFH
FF58H
ASICL6
R/W
16H
FF60H
00H
00H
00H
00H
00H
00H
00H
FF61H
SDR0H
FF62H
FF63H
MDA0LH
FF64H
R/W
FF65H
FF66H
SDR0 SDR0L
MDA0HH
MDB0 MDB0L
00H
FF68H
DMUC0
R/W
00H
FF69H
TMHMD0
R/W
00H
FF67H
MDB0H
Notes 1.
2.
123
Symbol
R/W
FF6AH
FF6BH
FF6CH
FF6DH
FF6EH
8 Bits 16 Bits
After
Reset
K
B
2
K
C
2
K
D
2
K
E
2
K
F
2
R/W
00H
TMC50
R/W
00H
TMHMD1
R/W
00H
TMCYC1
R/W
00H
KRM
R/W
00H
TCL50
FF6FH
WTM
R/W
00H
FF70H
ASIM0
R/W
01H
FF71H
BRGC0
R/W
1FH
FF72H
RXB0
FFH
FF73H
ASIS0
00H
FF74H
TXS0
FFH
FF80H
CSIM10
R/W
00H
FF81H
CSIC10
R/W
00H
FF84H
SOTB10
R/W
00H
FF88H
CSIM11
R/W
00H
Note
1
FF89H
CSIC11
R/W
00H
Note
FF8CH
TCL51
R/W
00H
FF90H
CSIMA0
R/W
00H
FF91H
CSIS0
R/W
00H
FF92H
CSIT0
R/W
00H
FF93H
BRGCA0
R/W
03H
FF94H
ADTP0
R/W
00H
FF95H
ADTI0
R/W
00H
FF96H
SIOA0
R/W
00H
FF97H
ADTC0
00H
FF99H
WDTE
R/W
1AH/
Note 2
9AH
FF9FH
OSCCTL
R/W
FFA0H
RCM
R/W
FFA1H
MCM
R/W
FFA2H
MOC
R/W
FFA3H
OSTC
FFA4H
OSTS
R/W
Notes 1.
00H
80H
00H
05H
00H
Note 3
80H
This register is incorporated only in products whose flash memory is at least 48 KB.
2.
The value of this register is 00H immediately after a reset release but automatically changes to 80H after
oscillation accuracy stabilization of high-speed internal oscillator has been waited.
124
Symbol
R/W
FFA5H
FFA6H
FFA7H
FFA8H
FFA9H
FFAAH
FFABH
After
Reset
8 Bits 16 Bits
K
B
2
K
C
2
K
D
2
K
E
2
K
F
2
R/W
00H
IICC0
R/W
00H
SVA0
R/W
00H
IICCL0
R/W
00H
IICX0
R/W
00H
IICS0
00H
IICF0
R/W
00H
IIC0
FFACH
RESF
00H
FFB0H
TM01
0000H
Note
CR001
R/W
0000H
CR011
FFB5H
FFB6H
TMC01
Note 1
FFB1H
FFB2H
FFB3H
FFB4H
Note
R/W
0000H
Note
R/W
00H
Note
FFB7H
PRM01
R/W
00H
Note
FFB8H
CRC01
R/W
00H
Note
FFB9H
TOC01
R/W
00H
Note
FFBAH
TMC00
R/W
00H
FFBBH
PRM00
R/W
00H
FFBCH
CRC00
R/W
00H
FFBDH
TOC00
R/W
00H
FFBEH
LVIM
R/W
00H
Note 3
FFBFH
LVIS
R/W
00H
Note 3
FFE0H
IF0
IF0L
R/W
00H
FFE1H
IF0H
R/W
00H
FFE2H
00H
FFE3H
00H
FFE4H
FFH
FFE5H
FFH
FFE6H
FFH
FFE7H
FFH
Notes 1.
IF1
MK0
MK1
IF1L
R/W
IF1H
R/W
MK0L
R/W
MK0H R/W
MK1L
R/W
MK1H R/W
2.
This register is incorporated only in products whose flash memory is at least 48 KB.
3.
The reset values of LVIM and LVIS vary depending on the reset source.
125
Symbol
R/W
1 Bit
FFE8H
FFE9H
FFEAH
After
Reset
8 Bits 16 Bits
K
B
2
K
C
2
K
D
2
K
E
2
K
F
2
FFH
R/W
PR0H
R/W
PR1L
R/W
PR0
PR0L
PR1
FFH
FFH
FFEBH
R/W
FFH
FFF0H
IMS
R/W
CFH
FFF3H
BANK
R/W
00H
FFF4H
IXS
R/W
0CH
FFFBH
PCC
R/W
01H
Notes 1.
2.
PR1H
This register is incorporated only in products whose flash memory is at least 96 KB.
Regardless of the internal memory capacity, the initial values of the internal memory size switching
register (IMS) and internal expansion RAM size switching register (IXS) of all products in the 78K0/Kx2
microcontrollers are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each
product as indicated below.
78K0/KB2
78K0/KB2
IMS
ROM Capacity
Internal High-Speed
RAM Capacity
PD78F0500A
42H
8 KB
512 bytes
PD78F0501A
04H
16 KB
768 bytes
1 KB
PD78F0502A
C6H
24 KB
PD78F0503A, 78F0503DANote 3
C8H
32 KB
IMS
IXS
ROM Capacity
Internal
Expansion
RAM Capacity
PD78F05x1A (x = 1 to 3)
04H
0CH
16 KB
768 bytes
PD78F05x2A (x = 1 to 3)
C6H
0CH
24 KB
1 KB
PD78F05x3A (x = 1 to 3),
C8H
0CH
32 KB
1 KB
PD78F05x4A (x = 1 to 4)
CCH
0AH
48KB
1 KB
1 KB
PD78F05x5A (x = 1 to 4),
CFH
08H
60KB
1 KB
2 KB
78F0513DA
78F0515DA
Note 4
Note 4
PD78F05x6A (x = 2 to 4)
CCH
04H
96 KB
1 KB
4 KB
PD78F05x7A, 78F05x7DANote 4
CCH
00H
128 KB
1 KB
6 KB
(x = 2 to 4)
3.
4.
126
The ROM and RAM capacities of the products with the on-chip debug function of 78K0/KB2 can be
debugged by setting IMS, according to the debug target products. Set IMS according to the debug target
products.
The ROM and RAM capacities of the products with the on-chip debug function of 78K0/KC2, 78K0/KD2,
78K0/KE2, and 78K0/KF2 can be debugged by setting IMS and IXS, according to the debug target
products. Set IMS and IXS according to the debug target products.
Users Manual U18598EJ1V0UD
The
displacement value is treated as signed twos complement data (128 to +127) and bit 7 becomes a sign bit.
In other words, relative addressing consists of relative branching from the start address of the following
instruction to the 128 to +127 range.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
0
... PC indicates the start address
of the instruction after the BR instruction.
PC
+
8
15
S
jdisp8
15
PC
127
0
CALL or BR
Low Addr.
High Addr.
15
8 7
PC
fa108
0
CALLF
fa70
15
PC
128
11 10
0
8 7
15
addr5
7
Operation code
ta40
1 0
ta40
15
Effective address
Memory (Table)
1 0
... The value of the effective address is
the same as that of addr5.
Low Addr.
High Addr.
Effective address+1
15
PC
129
15
0
X
PC
MULU
DIVUW
ADJBA/ADJBS
A register for storage of numeric values that become decimal correction targets
ROR4/ROL4
[Operand format]
Because implied addressing can be automatically determined with an instruction, no particular operand format is
necessary.
[Description example]
In the case of MULU X
With an 8-bit 8-bit multiply instruction, the product of the A register and X register is stored in AX. In this
example, the A and AX registers are specified by implied addressing.
130
Description
X, A, C, B, E, D, L, H
rp
r and rp can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; when selecting C register as r
Operation code
131
Description
addr16
[Description example]
MOV A, !0FE00H; when setting !addr16 to FE00H
Operation code
OP code
00H
FEH
[Illustration]
7
0
OP code
addr16 (lower)
addr16 (upper)
Memory
132
Description
saddr
saddrp
Immediate data that indicate label or FE20H to FF1FH (even address only)
[Description example]
LB1 EQU 0FE30H ; Defines FE30H by LB1.
:
MOV LB1, A
; When LB1 indicates FE30H of the saddr area and the value of register A is transferred to
that address
Operation code
OP code
30H (saddr-offset)
[Illustration]
7
0
OP code
saddr-offset
15
Effective address
133
Description
sfr
sfrp
[Description example]
MOV PM0, A; when selecting PM0 (FF20H) as sfr
Operation code
OP code
20H (sfr-offset)
[Illustration]
7
0
OP code
sfr-offset
SFR
15
Effective address
134
8 7
1
Description
[DE], [HL]
[Description example]
MOV A, [DE]; when selecting [DE] as register pair
Operation code
[Illustration]
16
8 7
D
DE
0
E
Memory
135
Description
[HL + byte]
[Description example]
MOV A, [HL + 10H]; when setting byte to 10H
Operation code
[Illustration]
16
8 7
H
HL
0
L
Memory
136
+10
Description
[HL + B], [HL + C]
[Description example]
MOV A, [HL +B]; when selecting B register
Operation code
[Illustration]
16
HL
L
+
7
0
B
Memory
137
[Illustration]
7
SP
SP
138
FEE0H
FEDEH
Memory
FEE0H
FEDFH
FEDEH
BFFFH
Flash memory
16384 8 bits
(memory bank 0)
Bank
area
8000H
7FFFH
Common
area
Flash memory
32768 8 bits
0000H
BFFFH
Flash memory
16384 8 bits
(memory bank 0)
Bank
area
8000H
7FFFH
Common
area
Flash memory
32768 8 bits
0000H
Remark
x = 2 to 4
139
CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F05x6A, 78F05x7A, AND 78F05x7DA (x = 2 to 4) ONLY)
BFFFH
Bank
area
Memory bank 0
(16 KB)
8000H
7FFFH
Common
area
Common
(32 KB)
08000H
07FFFH
Memory bank 5
(16 KB)
Memory bank 4
(16 KB)
Memory bank 3
(16 KB)
Memory bank 2
(16 KB)
Memory bank 1
(16 KB)
Memory bank 0
(16 KB)
Common
(32 KB)
00000H
0000H
Memory bank number + CPU address is represented with a vacancy in the address space, while the flash
memory real address is shown with no vacancy in the address space.
Memory bank number + CPU address is used for addressing in the user program. For on-board programming
and self programming not using the self programming sample libraryNote 1, the flash memory real address is used.
Note that the HEX file that is output by the assembler (RA78K0) by default uses the flash memory real address.
For address representation of the other tools such as the simulator and the debuggerNote 2, see Table 4-1.
Notes 1. Memory bank number + CPU address can be used when performing self programming, using the self
programming sample library, because the addresses are automatically translated.
2. SM+ for 78K0/Kx2, ID78K0-QB
140
CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F05x6A, 78F05x7A, AND 78F05x7DA (x = 2 to 4) ONLY)
CPU Address
Address Representation in
Simulator and Debugger
Memory bank 0
Note 2
08000H-0BFFFH
08000H-0BFFFH
Memory bank 1
0C000H-0FFFFH
18000H-1BFFFH
Memory bank 2
10000H-13FFFH
28000H-2BFFFH
Memory bank 3
14000H-17FFFH
38000H-3BFFFH
Memory bank 4
18000H-1BFFFH
48000H-4BFFFH
Memory bank 5
1C000H-1FFFFH
58000H-5BFFFH
08000H-0BFFFH
Note 1
BANK
BANK2
BANK1
BANK0
BANK2
BANK1
BANK0
Bank setting
PD78F05x6A
PD78F05x7A, 78F05x7DA
Setting prohibited
Caution
Setting prohibited
Be sure to change the value of the BANK register in the common area (0000H to 7FFFH).
If the value of the BANK register is changed in the bank area (8000H to BFFFH), an inadvertent
program loop occurs in the CPU. Therefore, never change the value of the BANK register in the
bank area.
Remark
x = 2 to 4
Users Manual U18598EJ1V0UD
141
CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F05x6A, 78F05x7A, AND 78F05x7DA (x = 2 to 4) ONLY)
Memory bank n
Bank
area
Memory bank m
Referencing value
Common
area
Memory bank n
Bank
area
Common
area
142
Memory bank m
Referencing value
CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F05x6A, 78F05x7A, AND 78F05x7DA (x = 2 to 4) ONLY)
DSEG
DS
DS
DS
SADDR
2
1
1
ETRC
ENTRY:
CSEG
UNIT
MOV
MOVW
CALL
R_BNKN,#BANKNUM
R_BNKA,#DATA1
!BNKRD
:
:
CSEG
AT
PUSH
MOV
XCH
HL
A,R_BNKN
A,BANK
MOV
XCHW
MOVW
XCHW
MOV
XCH
MOV
MOV
POP
R_BNKRN,A
AX,HL
AX,R_BNKA
AX,HL
A,[HL]
A,R_BNKRN
BANK,A
A,R_BNKRN
HL
BNKC
DATA
DATA1:
CSEG
DB
7000H
BNKRD:
RET
DATA1
BANK3
0AAH
END
143
CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F05x6A, 78F05x7A, AND 78F05x7DA (x = 2 to 4) ONLY)
Memory bank n
Bank
area
Memory bank m
Instruction branch
Common
area
Memory bank n
Bank
area
Memory bank m
Instruction branch
Common
area
144
CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F05x6A, 78F05x7A, AND 78F05x7DA (x = 2 to 4) ONLY)
DSEG
DS
DS
DS
SADDR
2
1
2
ETRC
ENTRY:
CSEG
UNIT
MOV
MOVW
BR
:
:
R_BNKN,#BANKNUM
R_BNKA,#TEST
!BNKBR
CSEG
AT
MOVW
MOV
MOV
MOVW
PUSH
MOVW
RET
RSAVEAX,AX
A,R_BNKN
BANK,A
AX,R_BNKA
AX
RSAVEAX,AX
CSEG
BANK3
BNKC
BNKBR:
BN3
TEST:
TEST
7000H
; Saves the AX register.
; Acquires the memory bank number at the branch destination.
; Specifies the memory bank number at the branch destination.
; Specifies the address at the branch destination.
; Sets the address at the branch destination to stack.
; Restores the AX register.
; Branch
MOV
:
:
END
Software example 2 (to branch from common area to any bank area)
ETRC
ENTRY:
BN3
TEST:
CSEG
AT
2000H
MOV
BR
R_BNKN,#BANKNUM TEST
!TEST
CSEG
BANK3
MOV
:
:
END
145
CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F05x6A, 78F05x7A, AND 78F05x7DA (x = 2 to 4) ONLY)
Memory bank n
Bank
area
Memory bank m
CALL instruction
Common
area
Memory bank n
Bank
area
Common
area
Memory bank m
CALL
instruction
RET instruction
BR instruction
CALL
instruction
RET instruction
146
CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F05x6A, 78F05x7A, AND 78F05x7DA (x = 2 to 4) ONLY)
Software example
RAMD
R_BNKA:
R_BNKN:
R_BNKRN:
RSAVEAX:
DSEG
DS
DS
DS
DS
SADDR
2
1
1
2
ETRC
ENTRY:
CSEG
UNIT
MOV
MOVW
CALL
R_BNKN,#BANKNUM
R_BNKA,#TEST
!BNKCAL
:
:
CSEG
AT
MOVW
MOV
XCH
MOV
CALL
RSAVEAX,AX
A,R_BNKN
A,BANK
R_BNKRN,A
!BNKCALS
MOVW
XCH
MOV
MOVW
RET
RSAVEAX,AX
A,R_BNKRN
BANK,A
AX,RSAVEAX
MOVW
PUSH
MOVW
RET
AX,R_BNKA
AX
AX,RSAVEAX
CSEG
BANK3
BNKC
BNKCAL:
TEST
7000H
; Inter-memory bank calling processing routine
; Saves the AX register.
; Acquires the memory bank number at the calling destination.
; Changes the bank and acquires the memory bank number at the calling source.
; Saves the memory bank number at the calling source to RAM.
; Calls a subroutine to branch to the calling destination.
BNKCALS:
BN3
TEST:
;
MOV
:
:
RET
END
Remark
147
CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F05x6A, 78F05x7A, AND 78F05x7DA (x = 2 to 4) ONLY)
Allocate interrupt servicing that requires a quick response in the common area.
Memory bank n
Instruction branch
Bank
area
Memory bank m
Common
area
Vector table
Software example (when using interrupt request of 16-bit timer/event counter 00)
VCTBL
CSEG
DW
AT
0020H
BNKITM000
RAMD
DSEG
R_BNKRN: DS
SADDR
1
; Secures RAM for saving the memory bank number before the interrupt occurs.
BNKC
CSEG
AT
BNKITM000:
PUSH
AX
7000H
; Inter-memory bank interrupt servicing routine
; Saves the contents of the AX register.
MOV
MOV
MOV
CALL
MOV
MOV
A,BANK
R_BNKRN,A
BANK,#BANKNUM TEST
!TEST
A,R_BNKRN
BANK,A
POP
AX
RETI
BN3
TEST:
CSEG
BANK3
; Interrupt servicing routine
MOV
:
:
RET
END
148
CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F05x6A, 78F05x7A, AND 78F05x7DA (x = 2 to 4) ONLY)
Remark
Note the following points to use the memory bank select function efficiently.
Allocate a routine that is used often in the common area.
If a value that is planned to be referenced is placed in RAM, it can be referenced from all of the areas.
If the reference destination and the branch destination of the routine placed in a memory bank are
placed in the same memory bank, then the code size and processing are more efficient.
Allocate interrupt servicing that requires a quick response in the common area.
149
Corresponding Pins
AVREF
P20 to P27
VDD
Table 5-2. Pin I/O Buffer Power Supplies (AVREF, EVDD, VDD)
78K0/KB2: 36-pin plastic FLGA (4x4)
78K0/KE2: 64-pin plastic LQFP (fine pitch) (10x10), 64-pin plastic LQFP (14x14), 64-pin plastic LQFP (12x12),
64-pin plastic TQFP (fine pitch) (7x7), 64-pin plastic FLGA (5x5)
78K0/KF2: 80-pin plastic LQFP (14x14), 80-pin plastic LQFP (fine pitch) (12x12)
Power Supply
Corresponding Pins
AVREF
P20 to P27
EVDD
VDD
P121 to P124
Non-port pins
78K0/Kx2 microcontrollers are provided with digital I/O ports, which enable variety of control operations. The
functions of each port are shown in Table 5-3.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the
alternate functions, see CHAPTER 2 PIN FUNCTIONS.
150
Function
I/O
Function
Name
P00
I/O
After
Alternate
Reset
Function
Port 0.
Input
I/O port.
port
TI000
P01
Note 1 Note 2
P02
Note 1 Note 2
P03
Note 2
P04
SCK11
Note 2
P05
TI001/SSI11
Note 2
P06
TI011/TO01
P10
SI11
a software setting.
I/O
TI010/TO00
SO11
Port 1.
Input
SCK10/TxD0
I/O port.
port
SI10/RxD0
P11
P12
P13
P14
RxD6
P15
TOH0
P16
TOH1/INTP5
P17
TI50/TO50
P20
SO10
TxD6
a software setting.
I/O
Port 2.
Analog
ANI0
I/O port.
input
ANI1
P21
P22
P23
ANI3
P24
ANI4
P25
ANI5
Note 3
P26
ANI6
Note 3
P27
ANI7
P30
I/O
P31
Port 3.
Analog
INTP1
I/O port.
input
INTP2/
ANI2
OCD1A
Note 4
INTP3/
OCD1B
Note 4
TI51/TO51/
P33
INTP4
Notes 1.
The 78K0/KD2 products are only provided with port functions (P02 and P03) and not alternate
functions.
2.
The 78K0/KE2 products whose flash memory is less than 32 KB are only provided with port functions
(P02 to P06) and not alternate functions. The 78K0/KE2 products whose flash memory is at least 48
KB are provided with port functions (P02 to P06) and alternate functions.
3.
This is not mounted onto 38-pin products of the 78K0/KC2. For the 38-pin products, be sure to set bits
6 and 7 of PM2 to 1 and bits 6 and 7 of P2 to 0.
4.
OCD1A and OCD1B are provided to the products with an on-chip debug function (PD78F05xxDA)
only.
Remark
151
Function
I/O
Function
Name
Note 1
P40
I/O
After
Alternate
Reset
Function
Port 4.
Input
I/O port.
port
Note 1
P41
P42
P43
P44
P45
P46
P47
P50
I/O
a software setting.
Port 5.
Input
I/O port.
port
P51
P52
P53
P54
P55
P56
P57
P60
I/O
a software setting.
Port 6.
Input
SCL0
I/O port.
port
SDA0
P61
P62
P63
P64
EXSCL0
(6 V tolerance).
P65
P66
P67
P70
I/O
Port 7.
Input
I/O port.
port
KR0
P71
Note 1
P72
Note 1
P73
Note 2
P74
KR4
Note 2
P75
KR5
P76
KR6
P77
KR7
Notes 1.
KR1
KR2
KR3
This is not mounted onto 38-pin products of the 78K0/KC2. For the 38-pin products, be sure to set bits
0 and 1 of PM4, bits 2 and 3 of PM7, bits 0 and 1 of P4, and bits 2 and 3 of P7 to 0.
2.
This is not mounted onto 38-pin and 44-pin products of the 78K0/KC2. The 48-pin products are only
provided with port functions (P74 to P75) and not alternate functions.
Remark
152
Function
I/O
Function
Name
P120
P121
P122
I/O
After
Alternate
Reset
Function
Port 12.
Input
INTP0/EXLVI
I/O port.
port
X1/OCD0A
Note 3
X2/EXCLK/
OCD0B
Note 3
P123
XT1
P124
XT2/EXCLKS
Note 1
P130
Note 1
Note 2
P140
Output
I/O
P141
Port 13.
Output
Output-only port.
port
Port 14.
Input
PCL/INTP6
I/O port.
port
BUZ/BUSY0/
INTP7
P142
P143
SIA0
P144
SOA0
P145
STB0
Notes 1.
a software setting.
SCKA0
This is not mounted onto 38-pin and 44-pin products of the 78K0/KC2.
2.
The 78K0/KE2 products are not provided with the BUSY0 input function.
3.
OCD0A and OCD0B are provided to the products with an on-chip debug function (PD78F05xxDA)
only.
Remark
153
Configuration
78K0/KB2
Port mode register (PMxx):
Pull-up resistor option register (PUxx): PU0, PU1, PU3, PU4, PU7, PU12
A/D port configuration register (ADPC)
48-pin products of 78K0/KC2, 78K0/KD2
Port mode register (PMxx):
Pull-up resistor option register (PUxx): PU0, PU1, PU3, PU4, PU7, PU12, PU14
A/D port configuration register (ADPC)
78K0/KE2
Port mode register (PMxx):
Pull-up resistor option register (PUxx): PU0, PU1, PU3 to PU5, PU7, PU12, PU14
A/D port configuration register (ADPC)
78K0/KF2
Port mode register (PMxx):
Pull-up resistor option register (PUxx): PU0, PU1, PU3 to PU7, PU12, PU14
A/D port configuration register (ADPC)
Port
78K0/KB2:
38-pin products of 78K0/KC2: Total: 31 (CMOS I/O: 27, N-ch open drain I/O: 4)
44-pin products of 78K0/KC2: Total: 37 (CMOS I/O: 33, N-ch open drain I/O: 4)
48-pin products of 78K0/KC2: Total: 41 (CMOS I/O: 36, CMOS output: 1, N-ch open drain I/O: 4)
Pull-up resistor
78K0/KD2:
Total: 45 (CMOS I/O: 40, CMOS output: 1, N-ch open drain I/O: 4)
78K0/KE2:
Total: 55 (CMOS I/O: 50, CMOS output: 1, N-ch open drain I/O: 4)
78K0/KF2:
Total: 71 (CMOS I/O: 66, CMOS output: 1, N-ch open drain I/O: 4)
78K0/KB2:
Total: 15
154
78K0/KD2:
Total: 28
78K0/KE2:
Total: 38
78K0/KF2:
Total: 54
5.2.1 Port 0
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 3
P00/TI000
P01/TI010/TO00
P02/SO11
P03/SI11
P02
Note
P03
Note
P04/SCK11
P05/TI001/SSI11
P06/TI011/TO01
y = 4 to 7
y = 4 to 7
P02
Note
P03
Note
P04
Note
P05
Note
P06
Note
Note The 78K0/KD2 products and 78K0/KE2 products whose flash memory is less than 32 KB are only provided
with port functions and not alternate functions.
Remark : Mounted, : Not mounted
Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using
port mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up resistor
can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
This port can also be used for timer I/O, serial interface data I/O, clock I/O, and chip select input.
Reset signal generation sets port 0 to input mode.
Figures 5-1 to 5-6 show block diagrams of port 0.
Caution To use P02/SO11 and P04/SCK11 as general-purpose ports, set serial operation mode register 11
(CSIM11) and serial clock selection register 11 (CSIC11) to the default status (00H).
155
P-ch
Alternate function
Internal bus
Selector
RD
WRPORT
P0
Output latch
(P00)
P00/TI000
WRPM
PM0
PM00
P0:
Port register 0
PU0:
PM0:
RD:
Read signal
156
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P0
Output latch
(P01)
P01/TI010/TO00
WRPM
PM0
PM01
Alternate
function
P0:
Port register 0
PU0:
PM0:
RD:
Read signal
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
157
P-ch
Internal bus
Selector
RD
WRPORT
P0
Output latch
(P02)
P02
WRPM
PM0
PM02
P0:
Port register 0
PU0:
PM0:
RD:
Read signal
158
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
P-ch
Internal bus
Selector
RD
WRPORT
P0
Output latch
(P02)
P02/SO11
WRPM
PM0
PM02
Alternate
function
P0:
Port register 0
PU0:
PM0:
RD:
Read signal
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
159
P-ch
Selector
Internal bus
RD
WRPORT
P0
Output latch
(P03, P05)
P03, P05
WRPM
PM0
PM03, PM05
P0:
Port register 0
PU0:
PM0:
RD:
Read signal
160
P-ch
Alternate function
Selector
Internal bus
RD
WRPORT
P0
Output latch
(P03, P05)
P03/SI11,
P05/SSI11/TI001
WRPM
PM0
PM03, PM05
P0:
Port register 0
PU0:
PM0:
RD:
Read signal
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
161
P-ch
Selector
Internal bus
RD
WRPORT
P0
Output latch
(P04)
P04
WRPM
PM0
PM04
P0:
Port register 0
PU0:
PM0:
RD:
Read signal
162
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P0
Output latch
(P04)
P04/SCK11
WRPM
PM0
PM04
Alternate
function
P0:
Port register 0
PU0:
PM0:
RD:
Read signal
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
163
P-ch
Internal bus
Selector
RD
WRPORT
P0
Output latch
(P06)
P06
WRPM
PM0
PM06
P0:
Port register 0
PU0:
PM0:
RD:
Read signal
164
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P0
Output latch
(P06)
P06/TI011/TO01
WRPM
PM0
PM06
Alternate
function
P0:
Port register 0
PU0:
PM0:
RD:
Read signal
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
165
5.2.2 Port 1
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 3
P10/SCK10/TxD0
P11/SI10/RxD0
P12/SO10
P13/TxD6
P14/RxD6
P15/TOH0
P16/TOH1/INTP5
P17/TI50/TO50
y = 4 to 7
y = 4 to 7
Remark : Mounted
Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using
port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor
can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O.
Reset signal generation sets port 1 to input mode.
Figures 5-7 to 5-11 show block diagrams of port 1.
Caution To use P10/SCK10/TxD0 and P12/SO10 as general-purpose ports, set serial operation mode
register 10 (CSIM10) and serial clock selection register 10 (CSIC10) to the default status (00H).
166
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P1
Output latch
(P10)
P10/SCK10/TxD0
WRPM
PM1
PM10
Alternate
function
P1:
Port register 1
PU1:
PM1:
RD:
Read signal
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
167
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P1
Output latch
(P11, P14)
P11/SI10/RxD0,
P14/RxD6
WRPM
PM1
PM11, PM14
P1:
Port register 1
PU1:
PM1:
RD:
Read signal
168
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
P-ch
Internal bus
Selector
RD
WRPORT
P1
Output latch
(P12, P15)
P12/SO10
P15/TOH0
WRPM
PM1
PM12, PM15
Alternate
function
P1:
Port register 1
PU1:
PM1:
RD:
Read signal
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
169
P-ch
Internal bus
Selector
RD
WRPORT
P1
Output latch
(P13)
P13/TxD6
WRPM
PM1
PM13
Alternate
function
P1:
Port register 1
PU1:
PM1:
RD:
Read signal
170
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P1
Output latch
(P16, P17)
P16/TOH1/INTP5,
P17/TI50/TO50
WRPM
PM1
PM16, PM17
Alternate
function
P1:
Port register 1
PU1:
PM1:
RD:
Read signal
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
171
5.2.3 Port 2
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
Note
P27/ANI7
y = 1 to 3
Note
y = 4 to 7
y = 4 to 7
Note This is not mounted onto 38-pin products of the 78K0/KC2. For the 38-pin products, be sure to set bits 6 and 7
of PM2 to 1, and bits 6 and 7 of P2 to 0.
Remark : Mounted, : Not mounted
Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using
port mode register 2 (PM2).
This port can also be used for A/D converter analog input.
To use P20/ANI0 to P27/ANI7 as digital input pins, set them in the digital I/O mode by using the A/D port
configuration register (ADPC) and in the input mode by using PM2. Use these pins starting from the lower bit.
To use P20/ANI0 to P27/ANI7 as digital output pins, set them in the digital I/O mode by using ADPC and in the
output mode by using PM2.
Table 5-5. Setting Functions of P20/ANI0 to P27/ANI7 Pins
ADPC
Digital I/O selection
PM2
ADS
Input mode
Digital input
Output mode
Digital output
Input mode
Output mode
Selects ANI.
Selects ANI.
Setting prohibited
All P20/ANI0 to P27/ANI7 are set in the analog input mode when the reset signal is generated.
Figure 5-12 shows a block diagram of port 2.
Caution Make the AVREF pin the same potential as the VDD pin when port 2 is used as a digital port.
172
Selector
Internal bus
RD
WRPORT
P2
Output latch
(P20 to P27)
P20/ANI0 to
P27/ANI7
WRPM
PM2
PM20 to PM27
A/D converter
P2:
Port register 2
PM2:
RD:
Read signal
173
5.2.4 Port 3
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 3
P30/INTP1
P31/INTP2/
OCD1A
y = 4 to 7
Note
P32/INTP3/
OCD1B
y = 4 to 7
Note
P33/INTP4/TI51/
TO51
Note OCD1A and OCD1B are provided to the products with an on-chip debug function (PD78F05xxDA) only.
Remark : Mounted
Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using
port mode register 3 (PM3). When the P30 to P33 pins are used as an input port, use of an on-chip pull-up resistor
can be specified in 1-bit units by pull-up resistor option register 3 (PU3).
This port can also be used for external interrupt request input and timer I/O.
Reset signal generation sets port 3 to input mode.
Figures 5-13 and 5-14 show block diagrams of port 3.
Cautions 1. In the product with an on-chip debug function (PD78F05xxDA), be sure to pull the
P31/INTP2/OCD1A pin down before a reset release, to prevent malfunction.
2. Process the P31/INTP2/OCD1A pin of the products mounted with the on-chip debug function
(PD78F05xxDA) as follows, when it is not used when it is connected to a flash memory
programmer or an on-chip debug emulator.
P31/INTP2/OCD1A
Flash memory programmer connection
On-chip debug
During reset
emulator connection
Note
Connect to EVSS
Input:
via a resistor.
Connect to EVDD
Note
Note
or EVSS
via a resistor.
as an on-chip debug
Note With products without an EVSS pin, connect them to VSS. With products without an EVDD pin, connect them
to VDD.
Remark
P31 and P32 of the product with an on-chip debug function (PD78F05xxDA) can be used as on-chip
debug mode setting pins (OCD1A, OCD1B) when the on-chip debug function is used. For how to
connect an on-chip debug emulator (QB-78K0MINI or QB-MINI2), see CHAPTER 28 ON-CHIP DEBUG
FUNCTION (PD78F05xxDA ONLY).
174
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P3
Output latch
(P30 to P32)
P30/INTP1,
P31/INTP2/OCD1A,
P32/INTP3/OCD1B
WRPM
PM3
PM30 to PM32
P3:
Port register 3
PU3:
PM3:
RD:
Read signal
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
175
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P3
Output latch
(P33)
P33/INTP4/TI51/TO51
WRPM
PM3
PM33
Alternate
function
P3:
Port register 3
PU3:
PM3:
RD:
Read signal
176
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
5.2.5 Port 4
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 3
y = 4 to 7
y = 4 to 7
P40
P41
P42
P43
P44
P45
P46
P47
Note
Note
Note This is not mounted onto 38-pin products of the 78K0/KC2. For the 38-pin products, be sure to set bits 0 and 1
of PM4 and P4 to 0.
Remark : Mounted, : Not mounted
Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using
port mode register 4 (PM4). When the P40 to P47 pins are used as an input port, use of an on-chip pull-up resistor
can be specified in 1-bit units by pull-up resistor option register 4 (PU4).
Reset signal generation sets port 4 to input mode.
Figure 5-15 shows a block diagram of port 4.
177
PU4
PU40 to PU47
P-ch
Internal bus
RD
Selector
WRPORT
P4
Output latch
(P40 to P47)
WRPM
P40 to P47
PM4
PM40 to PM47
P4:
Port register 4
PU4:
PM4:
RD:
Read signal
178
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
5.2.6 Port 5
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 3
y = 4 to 7
y = 4 to 7
P50
P51
P52
P53
P54
P55
P56
P57
PU5
PU50 to PU57
P-ch
RD
Internal bus
Selector
WRPORT
P5
Output latch
(P50 to P57)
WRPM
P50 to P57
PM5
PM50 to PM57
P5:
Port register 5
PU5:
PM5:
RD:
Read signal
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
Users Manual U18598EJ1V0UD
179
5.2.7 Port 6
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 3
y = 4 to 7
y = 4 to 7
P60/SCL0
P61/SDA0
P62/EXSCL0
P63
P64
P65
P66
P67
When using P62/EXSCL0 as an external clock input pin of the serial interface, input a clock of 6.4 MHz
to it.
180
Alternate
function
Selector
RD
Internal bus
WRPORT
P6
Output latch
(P60, P61)
P60/SCL0,
P61/SDA0
WRPM
PM6
PM60, PM61
Alternate
function
P6:
Port register 6
PM6:
RD:
Read signal
181
Alternate
function
Internal bus
Selector
RD
WRPORT
P6
Output latch
(P62)
P62/EXSCL0
WRPM
PM6
PM62
P6:
Port register 6
PM6:
RD:
Read signal
Selector
Internal bus
RD
WRPORT
P6
Output latch
(P63)
WRPM
PM6
PM63
P6:
Port register 6
PM6:
RD:
Read signal
182
P63
P-ch
Selector
Internal bus
RD
WRPORT
P6
Output latch
(P64 to P67)
P64 to P67
WRPM
PM6
PM64 to PM67
P6:
Port register 6
PM6:
RD:
Read signal
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
183
5.2.8 Port 7
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
P70/KR0
P71/KR1
P72/KR2
P73/KR3
P74/KR4
P75/KR5
Note 1
Note 1
y = 1 to 3
y = 4 to 7
P74
Note 2
P75
Note 2
P76/KR6
P77/KR7
Notes 1.
y = 4 to 7
This is not mounted onto 38-pin products of the 78K0/KC2. For the 38-pin products, be sure to set bits 2
and 3 of PM7 and P7 to 0.
2.
This is not mounted onto 38-pin and 44-pin products of the 78K0/KC2. The 48-pin products are only
provided with port functions and not alternate functions.
184
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P7
Output latch
(P70 to P77)
P70/KR0 to
P77/KR7
WRPM
PM7
PM70 to PM77
P7:
Port register 7
PU7:
PM7:
RD:
Read signal
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
185
5.2.9 Port 12
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 3
P120/INTP0/EXLVI
Note
P123/XT1
P124/XT2/EXCLKS
P121/X1/OCD0A
P122/X2/EXCLK/
OCD0B
y = 4 to 7
y = 4 to 7
Note
Note OCD0A and OCD0B are provided to the products with an on-chip debug function (PD78F05xxDA) only.
Remark : Mounted, : Not mounted
Port 12 is an I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using
port mode register 12 (PM12). When used as an input port only for P120, use of an on-chip pull-up resistor can be
specified by pull-up resistor option register 12 (PU12).
This port can also be used as pins for external interrupt request input, potential input for external low-voltage
detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input
for main system clock, and external clock input for subsystem clock.
Reset signal generation sets port 12 to input mode.
Figures 5-22 and 5-23 show block diagrams of port 12.
Caution
1. When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2)
or subsystem clock (XT1, XT2), or to input an external clock for the main system clock
(EXCLK) or subsystem clock (EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or
external clock input mode must be set by using the clock operation mode select register
(OSCCTL) (for details, see 6.3 (1) Clock operation mode select register (OSCCTL) and (3)
Setting of operation mode for subsystem clock pin). The reset value of OSCCTL is 00H (all of
the P121 to P124 pins are I/O port pins). At this time, setting of the PM121 to PM124 and P121
to P124 pins is not necessary.
186
Caution
2. Process the P121/X1/OCD0A pin of the products mounted with the on-chip debug function
(PD78F05xxDA) as follows, when it is not used when it is connected to a flash memory
programmer or an on-chip debug emulator.
P121/X1/OCD0A
Flash memory programmer connection
On-chip debug
During reset
emulator connection
Input:
as an on-chip debug
X1 and X2 of the product with an on-chip debug function (PD78F05xxDA) can be used as on-chip
Remark
debug mode setting pins (OCD0A, OCD0B) when the on-chip debug function is used. For how to
connect an on-chip debug emulator (QB-78K0MINI or QB-MINI2), see CHAPTER 28 ON-CHIP DEBUG
FUNCTION (PD78F05xxDA ONLY).
Figure 5-22. Block Diagram of P120
EVDD
WRPU
PU12
PU120
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P12
Output latch
(P120)
P120/INTP0/EXLVI
WRPM
PM12
PM120
P12:
Port register 12
PU12:
PM12:
RD:
Read signal
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
187
OSCCTL
OSCSEL/
OSCSELS
Selector
RD
WRPORT
P12
Output latch
(P122/P124)
P122/X2/EXCLK/OCD0B,
P124/XT2/EXCLKS
WRPM
PM12
PM122/PM124
OSCCTL
OSCSEL/
OSCSELS
Internal bus
OSCCTL
EXCLK, OSCSEL/
EXCLKS, OSCSELS
Selector
RD
WRPORT
P12
Output latch
(P121/P123)
P121/X1/OCD0A,
P123/XT1
WRPM
PM12
PM121/PM123
OSCCTL
OSCSEL/
OSCSELS
P12:
Port register 12
PU12:
PM12:
188
RD:
Read signal
WR:
Write signal
Users Manual U18598EJ1V0UD
5.2.10 Port 13
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050xA)
(PD78F051xA)
(PD78F052xA)
(PD78F053xA)
(PD78F054xA)
x = 0 to 3
x = 1 to 5
x = 1 to 7
P130
x = 1 to 3
x = 4 to 7
x = 4 to 7
Note
Note This is not mounted onto 38-pin and 44-pin products of the 78K0/KC2.
Remark : Mounted, : Not mounted
Port 13 is an output-only port.
Figure 5-24 shows a block diagram of port 13.
Figure 5-24. Block Diagram of P130
Internal bus
RD
WRPORT
P13
Output latch
(P130)
P13:
Port register 13
RD:
Read signal
P130
When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
Reset signal
P130
Set by software
189
5.2.11 Port 14
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050xA)
(PD78F051xA)
(PD78F052xA)
(PD78F053xA)
(PD78F054xA)
x = 0 to 3
x = 1 to 5
x = 1 to 7
x = 1 to 3
x = 4 to 7
x = 4 to 7
P140/PCL/INTP6
P141/BUZ/BUSY0/
P142/SCKA0
P143/SIA0
P144/SOA0
P145/STB0
Note 1
P141/BUZ/INTP7
Note 2
INTP7
Notes 1.
2.
This is not mounted onto 38-pin and 44-pin products of the 78K0/KC2.
The 78K0/KE2 products are not provided with the BUSY0 input function.
190
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P14
Output latch
(P140, P141)
P140/PCL/INTP6,
P141/BUZ/BUSY0/INTP7
WRPM
PM14
PM140, PM141
Alternate
function
P14:
Port register 14
PU14:
PM14:
RD:
Read signal
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
191
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P14
Output latch
(P142)
P142/SCKA0
WRPM
PM14
PM142
Alternate
function
P14:
Port register 14
PU14:
PM14:
RD:
Read signal
192
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P14
Output latch
(P143)
P143/SIA0
WRPM
PM14
PM143
P14:
Port register 14
PU14:
PM14:
RD:
Read signal
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
193
P-ch
Selector
Internal bus
RD
WRPORT
P14
Output latch
(P144, P145)
P144/SOA0,
P145/STB0
WRPM
PM14
PM144, PM145
Alternate
function
P14:
Port register 14
PU14:
PM14:
RD:
Read signal
With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS.
194
Address
After reset
R/W
PM0
PM01
PM00
FF20H
FFH
R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FF21H
FFH
R/W
PM2
PM23
PM22
PM21
PM20
FF22H
FFH
R/W
PM3
PM33
PM32
PM31
PM30
FF23H
FFH
R/W
PM6
PM61
PM60
FF26H
FFH
R/W
PM12
PM122
PM121
PM120
FF2CH
FFH
R/W
PMmn
(m = 0 to 3, 6, 12; n = 0 to 7)
0
Caution Be sure to set bits 2 to 7 of PM0, bits 4 to 7 of PM2, bits 4 to 7 of PM3, bits 2 to 7 of PM6,
bits 3 to 7 of PM12 to 1.
195
Address
After reset
R/W
PM0
PM01
PM00
FF20H
FFH
R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FF21H
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FF22H
FFH
R/W
PM3
PM33
PM32
PM31
PM30
FF23H
FFH
R/W
PM4
PM41
PM40
FF24H
FFH
R/W
PM6
PM63
PM62
PM61
PM60
FF26H
FFH
R/W
PM7
PM73
PM72
PM71
PM70
FF27H
FFH
R/W
PM12
PM124
PM123
PM122
PM121
PM120
FF2CH
FFH
R/W
PM14Note
PM140Note
FF2EH
FFH
R/W
PM75Note PM74Note
PMmn
(m = 0 to 4, 6, 7, 12, 14; n = 0 to 7)
0
Note
Caution For the 38-pin products, be sure to set bits 2 to 7 of PM0, bits 6 and 7 of PM2, bits 4 to 7 of
PM3, bits 2 to 7 of PM4, bits 4 to 7 of PM6, bits 4 to 7 of PM7, and bits 5 to 7 of PM12 to 1.
Also, be sure to set bits 0 and 1 of PM4, and bits 2 and 3 of PM7 to 0.
For the 44-pin products, be sure to set bits 2 to 7 of PM0, bits 4 to 7 of PM3, bits 2 to 7 of
PM4, bits 4 to 7 of PM6, bits 4 to 7 of PM7, and bits 5 to 7 of PM12 to 1.
For the 48-pin products, be sure to set bits 2 to 7 of PM0, bits 4 to 7 of PM3, bits 2 to 7 of
PM4, bits 4 to 7 of PM6, bits 6 and 7 of PM7, bits 5 to 7 of PM12, and bits 1 to 7 of PM14 to
1.
196
Address
After reset
R/W
PM0
PM03
PM02
PM01
PM00
FF20H
FFH
R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FF21H
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FF22H
FFH
R/W
PM3
PM33
PM32
PM31
PM30
FF23H
FFH
R/W
PM4
PM41
PM40
FF24H
FFH
R/W
PM6
PM63
PM62
PM61
PM60
FF26H
FFH
R/W
PM7
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
FF27H
FFH
R/W
PM12
PM124
PM123
PM122
PM121
PM120
FF2CH
FFH
R/W
PM14
PM140
FF2EH
FFH
R/W
PMmn
(m = 0 to 4, 6, 7, 12, 14; n = 0 to 7)
0
Caution Be sure to set bits 4 to 7 of PM0, bits 4 to 7 of PM3, bits 2 to 7 of PM4, bits 4 to 7 of PM6,
bits 5 to 7 of PM12, and bits 1 to 7 of PM14 to 1.
197
Address
After reset
R/W
PM0
PM06
PM05
PM04
PM03
PM02
PM01
PM00
FF20H
FFH
R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FF21H
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FF22H
FFH
R/W
PM3
PM33
PM32
PM31
PM30
FF23H
FFH
R/W
PM4
PM43
PM42
PM41
PM40
FF24H
FFH
R/W
PM5
PM53
PM52
PM51
PM50
FF25H
FFH
R/W
PM6
PM63
PM62
PM61
PM60
FF26H
FFH
R/W
PM7
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
FF27H
FFH
R/W
PM12
PM124
PM123
PM122
PM121
PM120
FF2CH
FFH
R/W
PM14
PM141
PM140
FF2EH
FFH
R/W
PMmn
(m = 0 to 7, 12, 14; n = 0 to 7)
0
Caution Be sure to set bit 7 of PM0, bits 4 to 7 of PM3, bits 4 to 7 of PM4, bits 4 to 7 of PM5, bits 4 to
7 of PM6, bits 5 to 7 of PM12, and bits 2 to 7 of PM14 to 1.
198
Address
After reset
R/W
PM0
PM06
PM05
PM04
PM03
PM02
PM01
PM00
FF20H
FFH
R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FF21H
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FF22H
FFH
R/W
PM3
PM33
PM32
PM31
PM30
FF23H
FFH
R/W
PM4
PM47
PM46
PM45
PM44
PM43
PM42
PM41
PM40
FF24H
FFH
R/W
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
FF25H
FFH
R/W
PM6
PM67
PM66
PM65
PM64
PM63
PM62
PM61
PM60
FF26H
FFH
R/W
PM7
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
FF27H
FFH
R/W
PM12
PM124
PM123
PM122
PM121
PM120
FF2CH
FFH
R/W
PM14
PM145
PM144
PM143
PM142
PM141
PM140
FF2EH
FFH
R/W
PMmn
(m = 0 to 7, 12, 14; n = 0 to 7)
0
Caution Be sure to set bit 7 of PM0, bits 4 to 7 of PM3, bits 5 to 7 of PM12, and bits 6 and 7 of PM14
to 1.
199
Address
After reset
R/W
P0
P01
P00
FF00H
R/W
P1
P17
P16
P15
P14
P13
P12
P11
P10
FF01H
R/W
P2
P23
P22
P21
P20
FF02H
R/W
P3
P33
P32
P31
P30
FF03H
R/W
P6
P61
P60
FF06H
R/W
P12
P120
FF0CH
R/W
m = 0 to 3, 6, 12; n = 0 to 7
Pmn
Output 0
Output 1
Note
0 is always read from the output latch of P121 and P122 if the pin is in the external clock input
mode.
200
Address
After reset
R/W
P0
P01
P00
FF00H
R/W
P1
P17
P16
P15
P14
P13
P12
P11
P10
FF01H
R/W
P2
P27
P26
P25
P24
P23
P22
P21
P20
FF02H
R/W
P3
P33
P32
P31
P30
FF03H
R/W
P4
P41
P40
FF04H
R/W
P6
P63
P62
P61
P60
FF06H
R/W
P7
P75Note 1
P74Note 1
P73
P72
P71
P70
FF07H
R/W
P12
P120
FF0CH
R/W
P13Note 1
P130Note 1
FF0DH
R/W
P14Note 1
P140Note 1
FF0EH
R/W
m = 0 to 4, 6, 7, 12 to 14; n = 0 to 7
Pmn
Output 0
Output 1
Notes 1.
2.
Caution For the 38-pin products, be sure to set bits 6 and 7 of P2, bits 0 and 1 of P4, and bits 2 and
3 of P7 to 0.
201
Address
After reset
R/W
P0
P03
P02
P01
P00
FF00H
R/W
P1
P17
P16
P15
P14
P13
P12
P11
P10
FF01H
R/W
P2
P27
P26
P25
P24
P23
P22
P21
P20
FF02H
R/W
P3
P33
P32
P31
P30
FF03H
R/W
P4
P41
P40
FF04H
R/W
P6
P63
P62
P61
P60
FF06H
R/W
P7
P77
P76
P75
P74
P73
P72
P71
P70
FF07H
R/W
P12
P120
FF0CH
R/W
P13
P130
FF0DH
R/W
P14
P140
FF0EH
R/W
m = 0 to 4, 6, 7, 12 to 14; n = 0 to 7
Pmn
Output 0
Output 1
Note
202
0 is always read from the output latch of P121 to P124 if the pin is in the external clock input mode.
Address
After reset
R/W
P0
P06
P05
P04
P03
P02
P01
P00
FF00H
R/W
P1
P17
P16
P15
P14
P13
P12
P11
P10
FF01H
R/W
P2
P27
P26
P25
P24
P23
P22
P21
P20
FF02H
R/W
P3
P33
P32
P31
P30
FF03H
R/W
P4
P43
P42
P41
P40
FF04H
R/W
P5
P53
P52
P51
P50
FF05H
R/W
P6
P63
P62
P61
P60
FF06H
R/W
P7
P77
P76
P75
P74
P73
P72
P71
P70
FF07H
R/W
P12
P120
FF0CH
R/W
P13
P130
FF0DH
R/W
P14
P141
P140
FF0EH
R/W
m = 0 to 7, 12 to 14; n = 0 to 7
Pmn
Output 0
Output 1
Note
0 is always read from the output latch of P121 to P124 if the pin is in the external clock input mode.
203
Address
After reset
R/W
P0
P06
P05
P04
P03
P02
P01
P00
FF00H
R/W
P1
P17
P16
P15
P14
P13
P12
P11
P10
FF01H
R/W
P2
P27
P26
P25
P24
P23
P22
P21
P20
FF02H
R/W
P3
P33
P32
P31
P30
FF03H
R/W
P4
P47
P46
P45
P44
P43
P42
P41
P40
FF04H
R/W
P5
P57
P56
P55
P54
P53
P52
P51
P50
FF05H
R/W
P6
P67
P66
P65
P64
P63
P62
P61
P60
FF06H
R/W
P7
P77
P76
P75
P74
P73
P72
P71
P70
FF07H
R/W
P12
P120
FF0CH
R/W
P13
P130
FF0DH
R/W
P14
P145
P144
P143
P142
P141
P140
FF0EH
R/W
m = 0 to 7, 12 to 14; n = 0 to 7
Pmn
Output 0
Output 1
Note
204
0 is always read from the output latch of P121 to P124 if the pin is in the external clock input mode.
Address
After reset
R/W
PU0
PU01
PU00
FF30H
00H
R/W
PU1
PU17
PU16
PU15
PU14
PU13
PU12
PU11
PU10
FF31H
00H
R/W
PU3
PU33
PU32
PU31
PU30
FF33H
00H
R/W
PU12
PU120
FF3CH
00H
R/W
PUmn
205
Address
After reset
R/W
PU0
PU01
PU00
FF30H
00H
R/W
PU1
PU17
PU16
PU15
PU14
PU13
PU12
PU11
PU10
FF31H
00H
R/W
PU3
PU33
PU32
PU31
PU30
FF33H
00H
R/W
PU4
PU41
PU40
FF34H
00H
R/W
PU7
PU73
PU72
PU71
PU70
FF37H
00H
R/W
PU12
PU120
FF3CH
00H
R/W
PU14Note
PU140Note
FF3EH
00H
R/W
PU75Note PU74Note
PUmn
(m = 0, 1, 3, 4, 7, 12, 14; n = 0 to 7)
Note
206
Address
After reset
R/W
PU0
PU03
PU02
PU01
PU00
FF30H
00H
R/W
PU1
PU17
PU16
PU15
PU14
PU13
PU12
PU11
PU10
FF31H
00H
R/W
PU3
PU33
PU32
PU31
PU30
FF33H
00H
R/W
PU4
PU41
PU40
FF34H
00H
R/W
PU7
PU77
PU76
PU75
PU74
PU73
PU72
PU71
PU70
FF37H
00H
R/W
PU12
PU120
FF3CH
00H
R/W
PU14
PU140
FF3EH
00H
R/W
PUmn
207
Address
After reset
R/W
PU0
PU06
PU05
PU04
PU03
PU02
PU01
PU00
FF30H
00H
R/W
PU1
PU17
PU16
PU15
PU14
PU13
PU12
PU11
PU10
FF31H
00H
R/W
PU3
PU33
PU32
PU31
PU30
FF33H
00H
R/W
PU4
PU43
PU42
PU41
PU40
FF34H
00H
R/W
PU5
PU53
PU52
PU51
PU50
FF35H
00H
R/W
PU7
PU77
PU76
PU75
PU74
PU73
PU72
PU71
PU70
FF37H
00H
R/W
PU12
PU120
FF3CH
00H
R/W
PU14
PU141
PU140
FF3EH
00H
R/W
PUmn
208
Address
After reset
R/W
PU0
PU06
PU05
PU04
PU03
PU02
PU01
PU00
FF30H
00H
R/W
PU1
PU17
PU16
PU15
PU14
PU13
PU12
PU11
PU10
FF31H
00H
R/W
PU3
PU33
PU32
PU31
PU30
FF33H
00H
R/W
PU4
PU47
PU46
PU45
PU44
PU43
PU42
PU41
PU40
FF34H
00H
R/W
PU5
PU57
PU56
PU55
PU54
PU53
PU52
PU51
PU50
FF35H
00H
R/W
PU6
PU67
PU66
PU65
PU64
FF36H
00H
R/W
PU7
PU77
PU76
PU75
PU74
PU73
PU72
PU71
PU70
FF37H
00H
R/W
PU12
PU120
FF3CH
00H
R/W
PU14
PU145
PU144
PU143
PU142
PU141
PU140
FF3EH
00H
R/W
PUmn
(m = 0, 1, 3 to 7, 12, 14; n = 0 to 7)
0
209
Products 38-pin
other than products
the right of KC2
R/W
Symbol
ADPC
ADPC3
ADPC2
ADPC1
ADPC0
ADPC3
ADPC2
ADPC1
ADPC0
KB2
Note 1
Note 1
Note 1
Note 2
Note 2
Notes 1.
Setting permitted
2.
Setting prohibited
Setting prohibited
Cautions 1. Set the channel used for A/D conversion to the input mode by using port mode register 2
(PM2).
2. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the
peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT.
210
5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function
To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 5-6.
Remark
The port pins mounted depend on the product. See Table 5-3. Port Functions.
211
Table 5-6. Settings of Port Mode Register and Output Latch When Using Alternate Function (1/2)
Pin Name
Alternate Function
Function Name
PM
I/O
P00
TI000
Input
P01
TI010
Input
TO00
Output
P02
SO11
Output
P03
SI11
Input
P04
SCK11
P05
P06
P10
Input
Output
SSI11
Input
TI001
Input
TI011
Input
TO01
Output
SCK10
Input
Output
TxD0
Output
SI10
Input
RxD0
Input
P12
SO10
Output
P13
TxD6
Output
P14
RxD6
Input
P15
TOH0
Output
P16
TOH1
Output
INTP5
Input
TI50
Input
Output
Input
P11
P17
TO50
P20 to P27
Note
Note
ANI0 to ANI7
Note
The function of the ANI0/P20 to ANI7/P27 pins can be selected by using the A/D port configuration register
(ADPC), the analog input channel specification register (ADS), and PM2.
Table 5-7. Setting Functions of ANI0/P20 to ANI7/P27 Pins
ADPC
Analog input selection
PM2
Input mode
Output mode
ADS
Selects ANI.
Selects ANI.
Setting prohibited
Remark
Input mode
Digital input
Output mode
Digital output
Dont care
212
Table 5-6. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2)
Pin Name
Alternate Function
Function Name
PM
I/O
P30 to P32
INTP1 to INTP3
Input
P33
INTP4
Input
TI51
Input
TO51
Output
P60
SCL0
I/O
P61
SDA0
I/O
P62
EXSCL0
Input
P70 to P77
KR0 to KR7
Input
P120
P121
P122
INTP0
Input
EXLVI
Input
X2
P124
Note
EXCLK
P123
Note
X1
XT1
Note
XT2
Note
Note
P141
P142
Input
PCL
Output
INTP6
Input
BUZ
Output
INTP7
Input
BUSY0
Input
EXCLKS
P140
Input
Note
SCKA0
Input
Output
Input
P143
SIA0
P144
SOA0
Output
P145
STB0
Output
Note
When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or subsystem
clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or subsystem clock
(EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock input mode must be set by
using the clock operation mode select register (OSCCTL) (for details, see 6.3 (1) Clock operation mode
select register (OSCCTL) and (3) Setting of operation mode for subsystem clock pin). The reset
value of OSCCTL is 00H (all of the P121 to P124 are I/O port pins). At this time, setting of PM121 to
PM124 and P121 to P124 is not necessary.
Remarks 1. :
Dont care
2. X1, X2, P31, and P32 of the product with an on-chip debug function (PD78F05xxDA) can be used
as on-chip debug mode setting pins (OCD0A, OCD0B, OCD1A, and OCD1B) when the on-chip
debug function is used. For how to connect an on-chip debug emulator (QB-78K0MINI or QB-MINI2),
see CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F05xxDA ONLY).
213
When P10 is an output port, P11 to P17 are input ports (all pin statuses are high level), and the port
latch value of port 1 is 00H, if the output of output port P10 is changed from low level to high level
via a 1-bit manipulation instruction, the output latch value of port 1 is FFH.
Explanation:
The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the
output latch and pin status, respectively.
A 1-bit manipulation instruction is executed in the following order in the 78K0/Kx2 microcontrollers.
<1> The Pn register is read in 8-bit units.
<2> The targeted one bit is manipulated.
<3> The Pn register is written in 8-bit units.
In step <1>, the output latch value (0) of P10, which is an output port, is read, while the pin statuses
of P11 to P17, which are input ports, are read. If the pin statuses of P11 to P17 are high level at
this time, the read value is FEH.
The value is changed to FFH by the manipulation in <2>.
FFH is written to the output latch by the manipulation in <3>.
Figure 5-45. Bit Manipulation Instruction (P10)
1-bit manipulation
instruction
(set1 P1.0)
is executed for P10
bit.
P10
Low-level output
P11 to P17
P10
High-level output
P11 to P17
214
Oscillation can be stopped by using the processor clock control register (PCC) and clock
Remark
fX:
fRH:
fEXCLK:
fXT:
fEXCLKS:
215
fRL:
Oscillators
X1 oscillator
Note
XT1 oscillator
Internal high-speed oscillator
Internal low-speed oscillator
Note
216
Configuration
Main clock
mode register
(MCM)
MCS
MSTOP
Main clock
mode register
(MCM)
Oscillation stabilization
time select register (OSTS)
OSTS2 OSTS1 OSTS0
Processor clock
control register
(PCC)
PCC2 PCC1 PCC0
XSEL MCM0
3
STOP
X1 oscillation
stabilization time counter
Oscillation
stabilization
MOST MOST MOST MOST MOST time counter
11 13 14
15 16 status register
(OSTC)
Peripheral
hardware
clock switch
X2/EXCLK
/P122
Crystal/ceramic
oscillation
fX
External input
clock
fEXCLK
Peripheral
hardware
clock (fPRS)
Controller
fXP
System
clock switch
Internal highfRH
speed oscillator
(8 MHz (TYP.))
Prescaler
fXP
2
fXP
22
fXP
23
fXP
24
Internal lowfRL
speed oscillator
(240 kHz (TYP.))
RSTS
LSRSTOP RSTOP
Internal oscillation
mode register
(RCM)
Internal bus
Option byte
1: Cannot be stopped
0: Can be stopped
CPU clock
(fCPU)
Watchdog timer,
8-bit timer H1
X1/P121
fXH
Selector
High-speed system
clock oscillator
217
218
Figure 6-2. Block Diagram of Clock Generator (78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2)
Internal bus
Main OSC
control register
(MOC)
Main clock
mode register
(MCM)
MCS
MSTOP
Main clock
mode register
(MCM)
Oscillation stabilization
time select register (OSTS)
OSTS2 OSTS1 OSTS0
Processor clock
control register
(PCC)
XTSTART CLS
XSEL MCM0
4
STOP
X2/EXCLK/
P122
Oscillation
stabilization
MOST MOST MOST MOST MOST time counter
11 13 14
15 16 status register
(OSTC)
fXH
Crystal/ceramic
oscillation
fX
External input
clock
fEXCLK
Peripheral
hardware
clock switch
Controller
Internal highfRH
speed oscillator
(8 MHz (TYP.))
Crystal
oscillation
XT2/EXCLKS/
P124
External input
clock
1/2
fXT
fSUB
fXP
22
RSTS
LSRSTOP RSTOP
Internal oscillation
mode register
(RCM)
Internal bus
fXP
24
fSUB
2
fEXCLKS
fXP
23
Watch timer,
clock output
Processor clock
control register
(PCC)
Prescaler
fXP
2
Subsystem
clock oscillator
XT1/P123
Peripheral
hardware
clock (fPRS)
Option byte
1: Cannot be stopped
0: Can be stopped
CPU clock
(fCPU)
Watchdog timer,
8-bit timer H1
X1/P121
To subsystem
clock oscillator
Selector
High-speed system
clock oscillator
X1 oscillation
stabilization time counter
Remark
fX:
fRH:
fEXCLK:
fXH:
fXP:
fPRS:
fCPU:
fXT:
fEXCLKS:
fSUB:
fRL:
219
Figure 6-3. Format of Clock Operation Mode Select Register (OSCCTL) (78K0/KB2)
Address: FF9FH
R/W
Symbol
<7>
<6>
<0>
OSCCTL
EXCLK
OSCSEL
AMPH
EXCLK
OSCSEL
I/O port
X1 oscillation mode
I/O port
I/O port
AMPH
P121/X1 pin
P122/X2/EXCLK pin
Cautions 1. Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency
exceeds 10 MHz.
2. Set AMPH before setting the peripheral functions after a reset release. The value
of AMPH can be changed only once after a reset release. When the high-speed
system clock (X1 oscillation) is selected as the CPU clock, supply of the CPU
clock is stopped for 4.06 to 16.12 s after AMPH is set to 1. When the highspeed system clock (external clock input) is selected as the CPU clock, supply of
the CPU clock is stopped for the duration of 160 external clocks after AMPH is
set to 1.
3. If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is
stopped for 4.06 to 16.12 s after the STOP mode is released when the internal
high-speed oscillation clock is selected as the CPU clock, or for the duration of
160 external clocks when the high-speed system clock (external clock input) is
selected as the CPU clock. When the high-speed system clock (X1 oscillation) is
selected as the CPU clock, the oscillation stabilization time is counted after the
STOP mode is released.
4. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7
(MSTOP) of the main OSC control register (MOC) is 1 (the X1 oscillator stops or
the external clock from the EXCLK pin is disabled).
5. Be sure to clear bits 1 to 5 to 0.
Remark fXH: High-speed system clock oscillation frequency
220
<6>
R/W
<5>
<4>
Note
Note
<0>
AMPH
EXCLK
OSCSEL
EXCLKS
EXCLK
OSCSEL
I/O port
X1 oscillation mode
I/O port
I/O port
OSCSELS
AMPH
Note
P121/X1 pin
P122/X2/EXCLK pin
EXCLKS and OSCSELS are used in combination with XTSTART (bit 6 of the processor clock
control register (PCC)). See (3) Setting of operation mode for subsystem clock pin.
Cautions 1. Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency
exceeds 10 MHz.
2. Set AMPH before setting the peripheral functions after a reset release. The value
of AMPH can be changed only once after a reset release. When the high-speed
system clock (X1 oscillation) is selected as the CPU clock, supply of the CPU
clock is stopped for 4.06 to 16.12 s after AMPH is set to 1. When the highspeed system clock (external clock input) is selected as the CPU clock, supply of
the CPU clock is stopped for the duration of 160 external clocks after AMPH is
set to 1.
3. If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is
stopped for 4.06 to 16.12 s after the STOP mode is released when the internal
high-speed oscillation clock is selected as the CPU clock, or for the duration of
160 external clocks when the high-speed system clock (external clock input) is
selected as the CPU clock. When the high-speed system clock (X1 oscillation) is
selected as the CPU clock, the oscillation stabilization time is counted after the
STOP mode is released.
4. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7
(MSTOP) of the main OSC control register (MOC) is 1 (the X1 oscillator stops or
the external clock from the EXCLK pin is disabled).
5. Be sure to clear bits 1 to 3 to 0.
Remark fXH: High-speed system clock oscillation frequency
221
R/W
Symbol
PCC
PCC2
PCC1
PCC0
PCC2
PCC1
PCC0
fXP
fXP/2 (default)
fXP/2
fXP/2
fXP/2
Cautions 1.
2.
Remark
222
Setting prohibited
R/W
6
XTSTART
Note2
Note 1
<5>
<4>
CLS
CSS
PCC2
PCC1
PCC0
CLS
Subsystem clock
CSS
PCC2
PCC1
PCC0
fXP
fXP/2 (default)
fXP/2
fXP/2
fXP/2
fSUB/2
Setting prohibited
fXP:
fSUB:
The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/Kx2 microcontrollers. Therefore,
the relationship between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table
6-2.
223
Table 6-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
CPU Clock (fCPU)
Note 1
At 20 MHz
Operation
Subsystem Clock
Internal High-Speed
Note 1
Oscillation Clock
At 8 MHz (TYP.) Operation
fXP
0.2 s
0.1 s
0.25 s (TYP.)
fXP/2
0.4 s
0.2 s
0.5 s (TYP.)
fXP/2
0.8 s
0.4 s
1.0 s (TYP.)
fXP/2
1.6 s
0.8 s
2.0 s (TYP.)
fXP/2
1.6 s
4.0 s (TYP.)
fSUB/2
3.2 s
Note 2
Notes 1.
122.1 s
The main clock mode register (MCM) is used to set the main system clock supplied to CPU clock
(high-speed system clock/internal high-speed oscillation clock) (see Figure 6-6).
2.
PCC
OSCCTL
Bit 6
Bit 5
Bit 4
XTSTART
EXCLKS
OSCSELS
P123/XT1 Pin
I/O port
P124/XT2/EXCLKS
Pin
I/O port
I/O port
Caution
Confirm that bit 5 (CLS) of the processor clock control register (PCC) is 0 (CPU is operating
with main system clock) when changing the current values of XTSTART, EXCLKS, and
OSCSELS.
Remark
224
: dont care
Address: FFA0H
R/W
Note 2
Symbol
<7>
<1>
<0>
RCM
RSTS
LSRSTOP
RSTOP
RSTS
LSRSTOP
RSTOP
Notes 1. The value of this register is 00H immediately after a reset release but automatically
changes to 80H after internal high-speed oscillator has been stabilized.
2. Bit 7 is read-only.
Caution When setting RSTOP to 1, be sure to confirm that the CPU operates with a clock
other than the internal high-speed oscillation clock. Specifically, set under either of
the following conditions.
<1> 78K0/KB2
When MCS = 1 (when CPU operates with the high-speed system clock)
<2> 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2
When MCS = 1 (when CPU operates with the high-speed system clock)
When CLS = 1 (when CPU operates with the subsystem clock)
In addition, stop peripheral hardware that is operating on the internal high-speed
oscillation clock before setting RSTOP to 1.
225
R/W
Symbol
<7>
MOC
MSTOP
MSTOP
X1 oscillation mode
X1 oscillator operating
X1 oscillator stopped
Cautions 1. When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock
other than the high-speed system clock. Specifically, set under either of the
following conditions.
<1> 78K0/KB2
When MCS = 0 (when CPU operates with the internal high-speed oscillation
clock)
<2> 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2
When MCS = 0 (when CPU operates with the internal high-speed oscillation
clock)
When CLS = 1 (when CPU operates with the subsystem clock)
In addition, stop peripheral hardware that is operating on the high-speed system
clock before setting MSTOP to 1.
2. Do not clear MSTOP to 0 while bit 6 (OSCSEL) of the clock operation mode select
register (OSCCTL) is 0 (I/O port mode).
3. The peripheral hardware cannot operate when the peripheral hardware clock is
stopped.
peripheral hardware clock has been stopped, initialize the peripheral hardware.
226
R/W
Note
Symbol
<2>
<1>
<0>
MCM
XSEL
MCS
MCM0
XSEL
MCM0
0
0
(fRH)
(fRH)
MCS
227
Symbol
OSTC
MOST11
MOST13
MOST14
MOST15
MOST16
MOST11
MOST13
MOST14
MOST15
MOST16
1
1
1
fX = 20 MHz
11
13
14
15
16
2 /fX min.
2 /fX min.
2 /fX min.
2 /fX min.
2 /fX min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
2. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
Desired OSTC oscillation stabilization time Oscillation stabilization time
set by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
3. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (a below).
STOP mode release
X1 pin voltage
waveform
a
Remark
228
R/W
Symbol
OSTS
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
0
0
204.8 s
102.4 s
13
819.2 s
409.6 s
2 /fX
2 /fX
14
1.64 ms
819.2 s
15
3.27 ms
1.64 ms
16
6.55 ms
3.27 ms
2 /fX
2 /fX
2 /fX
fX = 20 MHz
11
Setting prohibited
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
before executing the STOP instruction.
2. Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
3. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
Desired OSTC oscillation stabilization time Oscillation stabilization time
set by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
4. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (a below).
STOP mode release
X1 pin voltage
waveform
a
Remark
229
VSS
X1
X2
External clock
EXCLK
VSS
XT1
32.768
kHz
XT2
External clock
230
EXCLKS
Caution
1. When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the
broken lines in the Figures 6-12 and 6-13 to avoid an adverse effect from wiring capacitance.
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines. Do not route the wiring near a signal
line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS. Do
not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
Note that the XT1 oscillator is designed as a low-amplitude circuit for reducing power
consumption.
PORT
VSS
Remark
X1
X2
VSS
X1
X2
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert
resistors in series on the XT2 side.
231
Pmn
X1
X2
VSS
High current
VSS
X1
X2
High current
VSS
Remark
X1
X2
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert
resistors in series on the XT2 side.
Caution
2. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1,
resulting in malfunctioning.
232
OSCSELS:
233
Note
The CPU starts operation when the internal high-speed oscillator starts outputting after a reset release in the
78K0/Kx2 microcontrollers, thus enabling the following.
(1) Enhancement of security function
When the X1 clock is set as the CPU clock by the default setting, the device cannot operate if the X1 clock is
damaged or badly connected and therefore does not operate after reset is released. However, the start clock of
the CPU is the internal high-speed oscillation clock, so the device can be started by the internal high-speed
oscillation clock after a reset release. Consequently, the system can be safely shut down by performing a
minimum operation, such as acknowledging a reset source by software or performing safety processing when
there is a malfunction.
(2) Improvement of performance
Because the CPU can be started without waiting for the X1 clock oscillation stabilization time, the total
performance can be improved.
When the power supply voltage is turned on, the clock generator operation is shown in Figure 6-15.
234
Figure 6-15. Clock Generator Operation When Power Supply Voltage Is Turned On
(When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0))
Power supply
voltage (VDD)
1.8 VNote 1
1.59 V
(TYP.)
0.5 V/ms
(MIN.)Note 1
0V
CPU clock
Reset processing
(11 to 45 s)
<5>
Internal high-speed oscillation clock
Switched by
software
High-speed system clock
<5>
Subsystem clock
<2>
Internal high-speed
oscillation clock (fRH)
High-speed
system clock (fXH)
(when X1 oscillation
selected)
Note 2
<4>
X1 clock
oscillation stabilization time:
11
2 /fX to 216/fXNote 3
Starting X1 oscillation <4>
is set by software.
<1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit.
<2> When the power supply voltage exceeds 1.59 V (TYP.), the reset is released and the internal high-speed
oscillator automatically starts oscillation.
<3> When the power supply voltage rises with a slope of 0.5 V/ms (MIN.), the CPU starts operation on the
internal high-speed oscillation clock after the reset is released and after the stabilization times for the voltage
of the power supply and regulator have elapsed, and then reset processing is performed.
<4> Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 6.6.1 Example of controlling highspeed system clock and (1) in 6.6.3 Example of controlling subsystem clock).
<5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
switching via software (see (3) in 6.6.1 Example of controlling high-speed system clock and (3) in 6.6.3
Example of controlling subsystem clock).
Notes 1.
2.
3.
4.
If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application until the voltage
reaches 1.8 V, input a low level to the RESET pin from power application until the voltage reaches 1.8
V, or set the 2.7 V/1.59 V POC mode by using the option byte (POCMODE = 1) (see Figure 6-16).
When a low level has been input to the RESET pin until the voltage reaches 1.8 V, the CPU operates
with the same timing as <2> and thereafter in Figure 6-15, after the reset has been released by the
RESET pin.
The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the
internal high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the
oscillation stabilization time counter status register (OSTC). If the CPU operates on the high-speed
system clock (X1 oscillation), set the oscillation stabilization time when releasing STOP mode using the
oscillation stabilization time select register (OSTS).
The 78K0/KB2 is not provided with a subsystem clock.
Users Manual U18598EJ1V0UD
235
Caution
It is not necessary to wait for the oscillation stabilization time when an external clock input from
the EXCLK and EXCLKS pins is used.
Remark
While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via
software settings.
The internal high-speed oscillation clock and high-speed system clock can be
stopped by executing the STOP instruction (see (4) in 6.6.1 Example of controlling high-speed
system clock, (3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (4) in
6.6.3 Example of controlling subsystem clock).
Figure 6-16. Clock Generator Operation When Power Supply Voltage Is Turned On
(When 2.7 V/1.59 V POC Mode Is Set (Option Byte: POCMODE = 1))
2.7 V (TYP.)
Power supply
voltage (VDD)
0V
CPU clock
Switched by
software
High-speed system clock
<5>
Subsystem clock
<2>
Internal high-speed
oscillation clock (fRH)
High-speed
system clock (fXH)
(when X1 oscillation
selected)
<1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit.
<2> When the power supply voltage exceeds 2.7 V (TYP.), the reset is released and the internal high-speed
oscillator automatically starts oscillation.
<3> After the reset is released and reset processing is performed, the CPU starts operation on the internal highspeed oscillation clock.
<4> Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 6.6.1 Example of controlling highspeed system clock and (1) in 6.6.3 Example of controlling subsystem clock).
<5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
switching via software (see (3) in 6.6.1 Example of controlling high-speed system clock and (3) in 6.6.3
Example of controlling subsystem clock).
Notes 1.
2.
236
When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the
internal high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the
oscillation stabilization time counter status register (OSTC). If the CPU operates on the high-speed
system clock (X1 oscillation), set the oscillation stabilization time when releasing STOP mode using the
oscillation stabilization time select register (OSTS).
The 78K0/KB2 is not provided with a subsystem clock.
Users Manual U18598EJ1V0UD
Cautions 1. A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply voltage
reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93
ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated
before reset processing.
2. It is not necessary to wait for the oscillation stabilization time when an external clock input
from the EXCLK and EXCLKS pins is used.
Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via
software settings.
The internal high-speed oscillation clock and high-speed system clock can be
system clock, (3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (4) in
6.6.3 Example of controlling subsystem clock).
External main system clock: External clock is input to the EXCLK pin.
When the high-speed system clock is not used, the X1/P121 and X2/EXCLK/P122 pins can be used as I/O port
pins.
Caution The X1/P121 and X2/EXCLK/P122 pins are in the I/O port mode after a reset release.
The following describes examples of setting procedures for the following cases.
(1) When oscillating X1 clock
(2) When using external main system clock
(3) When using high-speed system clock as CPU clock and peripheral hardware clock
(4) When stopping high-speed system clock
(1) Example of setting procedure when oscillating the X1 clock
<1> Setting frequency (OSCCTL register)
Using AMPH, set the gain of the on-chip oscillator according to the frequency to be used.
Note
AMPH
1 MHz f XH 10 MHz
Note Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can
be changed only once after a reset release. When AMPH is set to 1, the clock supply to the CPU
is stopped for 4.06 to 16.12 s.
Remark fXH: High-speed system clock oscillation frequency
237
<2> Setting P121/X1 and P122/X2/EXCLK pins and selecting X1 clock or external clock (OSCCTL register)
When EXCLK is cleared to 0 and OSCSEL is set to 1, the mode is switched from port mode to X1
oscillation mode.
EXCLK
OSCSEL
P121/X1 Pin
P122/X2/EXCLK Pin
X1 oscillation mode
AMPH
1 MHz f XH 10 MHz
Note Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can
be changed only once after a reset release. The clock supply to the CPU is stopped for the
duration of 160 external clocks after AMPH is set to 1.
Remark fXH: High-speed system clock oscillation frequency
<2> Setting P121/X1 and P122/X2/EXCLK pins and selecting operation mode (OSCCTL register)
When EXCLK and OSCSEL are set to 1, the mode is switched from port mode to external clock input
mode.
EXCLK
OSCSEL
P121/X1 Pin
P122/X2/EXCLK Pin
I/O port
ELECTRICAL SPECIFICATIONS
238
(3) Example of setting procedure when using high-speed system clock as CPU clock and peripheral
hardware clock
<1> Setting high-speed system clock oscillationNote
(See 6.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of
setting procedure when using the external main system clock.)
Note The setting of <1> is not necessary when high-speed system clock is already operating.
<2> Setting the high-speed system clock as the main system clock (MCM register)
When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock
and peripheral hardware clock.
XSEL
MCM0
Caution If the high-speed system clock is selected as the main system clock, a clock other than
the high-speed system clock cannot be set as the peripheral hardware clock.
<3> Setting the main system clock as the CPU clock and selecting the division ratio (PCC register)
When CSS is cleared to 0, the main system clock is supplied to the CPU. To select the CPU clock
division ratio, use PCC0, PCC1, and PCC2.
CSS
PCC2
PCC1
PCC0
fXP
fXP/2 (default)
fXP/2
fXP/2
fXP/2
Setting prohibited
(4) Example of setting procedure when stopping the high-speed system clock
The high-speed system clock can be stopped in the following two ways.
Executing the STOP instruction and stopping the X1 oscillation (disabling clock input if the external clock is
used)
Setting MSTOP to 1 and stopping the X1 oscillation (disabling clock input if the external clock is used)
(a) To execute a STOP instruction
<1> Setting to stop peripheral hardware
Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that
cannot be used in STOP mode, see CHAPTER 22 STANDBY FUNCTION).
<2> Setting the X1 clock oscillation stabilization time after standby release
When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP
instruction is executed.
<3> Executing the STOP instruction
When the STOP instruction is executed, the system is placed in the STOP mode and X1 oscillation
is stopped (the input of the external clock is disabled).
Users Manual U18598EJ1V0UD
239
78K0/KB2
MCS
MCS
Subsystem clock
240
(1) Example of setting procedure when restarting oscillation of the internal high-speed oscillation clockNote 1
<1> Setting restart of oscillation of the internal high-speed oscillation clock (RCM register)
When RSTOP is cleared to 0, the internal high-speed oscillation clock starts operating.
<2> Waiting for the oscillation accuracy stabilization time of internal high-speed oscillation clock (RCM
register)
Wait until RSTS is set to 1Note 2.
Notes 1. After a reset release, the internal high-speed oscillator automatically starts oscillating and the
internal high-speed oscillation clock is selected as the CPU clock.
2. This wait time is not necessary if high accuracy is not necessary for the CPU clock and peripheral
hardware clock.
(2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and
internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock
<1> Restarting oscillation of the internal high-speed oscillation clockNote
(See 6.6.2 (1) Example of setting procedure when restarting oscillation of the internal highspeed oscillation clock).
Oscillating the high-speed system clockNote
(This setting is required when using the high-speed system clock as the peripheral hardware clock.
See 6.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of
setting procedure when using the external main system clock.)
Note The setting of <1> is not necessary when the internal high-speed oscillation clock or highspeed system clock is already operating.
<2> Selecting the clock supplied as the main system clock and peripheral hardware clock (MCM register)
Set the main system clock and peripheral hardware clock using XSEL and MCM0.
XSEL
MCM0
PCC2
PCC1
PCC0
fXP
fXP/2 (default)
fXP/2
fXP/2
fXP/2
Setting prohibited
241
(3) Example of setting procedure when stopping the internal high-speed oscillation clock
The internal high-speed oscillation clock can be stopped in the following two ways.
Executing the STOP instruction to set the STOP mode
Setting RSTOP to 1 and stopping the internal high-speed oscillation clock
(a) To execute a STOP instruction
<1> Setting of peripheral hardware
Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that
cannot be used in STOP mode, see CHAPTER 22 STANDBY FUNCTION).
<2> Setting the X1 clock oscillation stabilization time after standby release
When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP
instruction is executed. To operate the CPU immediately after the STOP mode has been released,
set MCM0 to 0, switch the CPU clock to the internal high-speed oscillation clock, and check that
RSTS is 1.
<3> Executing the STOP instruction
When the STOP instruction is executed, the system is placed in the STOP mode and internal highspeed oscillation clock is stopped.
(b) To stop internal high-speed oscillation clock by setting RSTOP to 1
<1> Confirming the CPU clock status (PCC and MCM registers)
Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed
oscillation clock.
When CLS = 0 and MCS = 0, the internal high-speed oscillation clock is supplied to the CPU, so
change the CPU clock to a clock other than the internal high-speed oscillation clock.
78K0/KB2
MCS
MCS
Subsystem clock
242
Cautions 1. The XT1/P123 and XT2/EXCLKS/P124 pins are in the I/O port mode after a reset release.
2. Do not start the peripheral hardware operation with the external clock from peripheral
hardware pins when the internal high-speed oscillation clock and high-speed system clock
are stopped while the CPU operates with the subsystem clock, or when in the STOP mode.
The following describes examples of setting procedures for the following cases.
(1) When oscillating XT1 clock
(2) When using external subsystem clock
(3) When using subsystem clock as CPU clock
(4) When stopping subsystem clock
(1) Example of setting procedure when oscillating the XT1 clock
<1> Setting XT1 and XT2 pins and selecting operation mode (PCC and OSCCTL registers)
When XTSTART, EXCLKS, and OSCSELS are set as any of the following, the mode is switched from
port mode to XT1 oscillation mode.
XTSTART
EXCLKS
OSCSELS
Operation Mode of
P123/XT1 Pin
Remark
P124/XT2/
EXCLKS Pin
: dont care
EXCLKS
OSCSELS
Operation Mode of
Subsystem Clock Pin
External clock input
mode
P123/XT1 Pin
I/O port
P124/XT2/
EXCLKS Pin
External clock input
Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is
operating.
Users Manual U18598EJ1V0UD
243
(3) Example of setting procedure when using the subsystem clock as the CPU clock
<1> Setting subsystem clock oscillationNote
(See 6.6.3 (1) Example of setting procedure when oscillating the XT1 clock and (2) Example of
setting procedure when using the external subsystem clock.)
Note The setting of <1> is not necessary when while the subsystem clock is operating.
<2> Switching the CPU clock (PCC register)
When CSS is set to 1, the subsystem clock is supplied to the CPU.
CSS
PCC2
PCC1
PCC0
Setting prohibited
MCS
Subsystem clock
Be sure to confirm that CLS = 0 when clearing OSCSELS to 0. In addition, stop the watch
timer if it is operating on the subsystem clock.
2.
244
The subsystem clock oscillation cannot be stopped using the STOP instruction.
245
XSEL
MCM0
EXCLK
X1 clock
X1 clock
dont care
Table 6-5. Clocks Supplied to CPU and Peripheral Hardware, and Register Setting
(78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2)
Supplied Clock
XSEL
CSS
MCM0
EXCLK
X1 clock
X1 clock
X1 clock
Subsystem clock
Remark
XSEL:
CSS:
MCM0:
Bit 0 of MCM
246
dont care
Power ON
(A)
Reset release
(B)
(F)
CPU: Internal highspeed oscillation
STOP
(D)
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input: Operating
(C)
CPU: Operating
with X1 oscillation or
EXCLK input
(E)
(G)
CPU: X1
oscillation/EXCLK
input HALT
CPU: X1
oscillation/EXCLK
input STOP
Remark
In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the CPU clock status changes to (A) in the
above figure when the supply voltage exceeds 2.7 V (TYP.), and to (B) after reset processing (11 to
45 s).
247
Power ON
(A)
Reset release
(D)
CPU: Operating
with internal highspeed oscillation
(H)
CPU: Internal highspeed oscillation
STOP
CPU: Operating
with XT1 oscillation or
EXCLKS input
(E)
CPU: Internal highspeed oscillation
HALT
(C)
(G)
CPU: XT1
oscillation/EXCLKS
input HALT
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operable
X1 oscillation/EXCLK input: Operable
XT1 oscillation/EXCLKS input:
Operating
(B)
CPU: Operating
with X1 oscillation or
EXCLK input
(I)
CPU: X1
oscillation/EXCLK
input STOP
(F)
CPU: X1
oscillation/EXCLK
input HALT
Remark
In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the CPU clock status changes to (A) in the
above figure when the supply voltage exceeds 2.7 V (TYP.), and to (B) after reset processing (11 to
45 s).
248
Table 6-6 shows transition of the CPU clock and examples of setting the SFR registers.
Table 6-6. CPU Clock Transition and SFR Register Setting Examples (1/5)
(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
Status Transition
(A) (B)
SFR registers do not have to be set (default status after reset release).
(2) CPU operating with high-speed system clock (C) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
AMPH
EXCLK
OSCSEL
MSTOP
Status Transition
(A) (B) (C) (X1 clock: 1 MHz fXH
10 MHz)
XSEL
MCM0
Must be
checked
fXH 10 MHz)
Must not be
checked
20 MHz)
Must be
checked
fXH 20 MHz)
Caution
OSTC
Register
Must not be
checked
Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 30
XTSTART
EXCLKS
Waiting for
OSCSELS
CSS
Oscillation
Status Transition
Stabilization
Necessary
Unnecessary
Remarks 1. (A) to (I) in Table 6-6 correspond to (A) to (I) in Figure 6-17 and 6-18.
2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH:
Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL)
MSTOP:
XSEL, MCM0:
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
:
Dont care
Users Manual U18598EJ1V0UD
249
Table 6-6. CPU Clock Transition and SFR Register Setting Examples (2/5)
(4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Note
AMPH
EXCLK
OSCSEL
OSTC
MSTOP
XSEL
Note
MCM0
Register
Status Transition
(B) (C) (X1 clock: 1 MHz fXH 10 MHz)
Must be
checked
(B) (C) (external main clock: 1 MHz fXH
10 MHz)
Must not be
checked
Must be
checked
20 MHz)
Must not be
checked
Unnecessary if the
CPU is operating
with the high-speed
system clock
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has
already been set.
Caution
Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 30
XTSTART
EXCLKS
OSCSELS
Waiting for
CSS
Oscillation
Status Transition
(B) (D) (XT1 clock)
Stabilization
0
Necessary
Unnecessary
Remarks 1. (A) to (I) in Table 6-6 correspond to (A) to (I) in Figure 6-17 and 6-18.
2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH:
Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL)
MSTOP:
Bit 7 of the main OSC control register (MOC)
XSEL, MCM0:
Bits 2 and 0 of the main clock mode register (MCM)
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
:
Dont care
250
Table 6-6. CPU Clock Transition and SFR Register Setting Examples (3/5)
(6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
RSTOP
RSTS
MCM0
Status Transition
(C) (B)
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)Note
Note The 78K0/KB2 is not provided with a subsystem clock.
(Setting sequence of SFR registers)
Setting Flag of SFR Register
XTSTART
EXCLKS
Waiting for
OSCSELS
CSS
Oscillation
Status Transition
Stabilization
Necessary
Unnecessary
(8) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B)
Note The 78K0/KB2 is not provided with a subsystem clock.
(Setting sequence of SFR registers)
Setting Flag of SFR Register
RSTOP
RSTS
MCM0
CSS
Status Transition
(D) (B)
is 1.
Unnecessary if
XSEL is 0
oscillation clock
Remarks 1. (A) to (I) in Table 6-6 correspond to (A) to (I) in Figure 6-17 and 6-18.
2. MCM0:
EXCLKS, OSCSELS: Bits 5 and 4 of the clock operation mode select register (OSCCTL)
RSTS, RSTOP:
XTSTART, CSS:
Dont care
251
Table 6-6. CPU Clock Transition and SFR Register Setting Examples (4/5)
(9) CPU clock changing from subsystem clock (D) to high-speed system clock (C)Note
Note The 78K0/KB2 is not provided with a subsystem clock.
(Setting sequence of SFR registers)
Note
EXCLK
OSCSEL
MSTOP
OSTC
Note
MCM0
CSS
XSEL
Register
Status Transition
(D) (C) (X1 clock: 1 MHz fXH
10 MHz)
Must be
checked
fXH 10 MHz
Must not be
checked
20 MHz)
Must be
checked
fXH 20 MHz)
Must not be
checked
Unnecessary if the
CPU is operating
is already set
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has
already been set.
Caution
Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 30
Setting
Executing HALT instruction
(C) (F)
(D) (G)
Note
252
MSTOP:
XSEL, MCM0:
CSS:
Table 6-6. CPU Clock Transition and SFR Register Setting Examples (5/5)
(11) STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
STOP mode (I) set while CPU is operating with high-speed system clock (C)
(Setting sequence)
Status Transition
Setting
(B) (H)
(C) (I)
Remarks 1. (A) to (I) in Table 6-6 correspond to (A) to (I) in Figure 6-17 and 6-18.
2. EXCLK, OSCSEL, AMPH: Bits 7, 6 and 0 of the clock operation mode select register (OSCCTL)
MSTOP:
XSEL, MCM0:
CSS:
253
6.6.7 Condition before changing CPU clock and processing after changing CPU clock
Condition before changing the CPU clock and processing after changing the CPU clock are shown below.
Table 6-7. Changing CPU Clock
CPU Clock
Before Change
KB2,
KC2,
KD2,
KE2,
KF2
Internal highspeed
oscillation
clock
X1 clock
External main
system clock
KC2,
KD2,
KE2,
KF2
(other
than
KB2)
Internal highspeed
oscillation
clock
After Change
X1 clock
Stabilization of X1 oscillation
MSTOP = 0, OSCSEL = 1, EXCLK = 0
After elapse of oscillation stabilization
time
External main
system clock
Internal highspeed
oscillation
clock
XT1 clock
X1 clock
External main
system clock
Internal highspeed
oscillation
clock
External
subsystem
clock
X1 clock
External main
system clock
XT1 clock,
external
subsystem
clock
Remark
254
Internal highspeed
oscillation
clock
X1 clock
External main
system clock
6.6.8 Time required for switchover of CPU clock and main system clock
By setting bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock
can be switched (between the main system clock and the subsystem clock) and the division ratio of the main system
clock can be changed.
The actual switchover operation is not performed immediately after rewriting to PCC; operation continues on the
pre-switchover clock for several clocks (see Table 6-8 and 6-9).
Whether the CPU is operating on the main system clock or the subsystem clockNote can be ascertained using bit 5
(CLS) of the PCC register.
Note The 78K0/KB2 is not provided with a subsystem clock.
Table 6-8. Time Required for Switchover of CPU Clock and Main System Clock Cycle Division Factor
(78K0/KB2)
Set Value Before
Switchover
PCC2
PCC1
PCC0
PCC2
PCC1
PCC0
PCC2
PCC1
PCC0
PCC2
PCC1
PCC0
PCC2
PCC1
PCC0
PCC2
PCC1
PCC0
8 clocks
4 clocks
4 clocks
2 clocks
2 clocks
2 clocks
1 clock
1 clock
1 clock
Remark
16 clocks
16 clocks
16 clocks
16 clocks
8 clocks
8 clocks
8 clocks
4 clocks
4 clocks
2 clocks
1 clock
The number of clocks listed in Table 6-8 is the number of CPU clocks before switchover.
Table 6-9. Time Required for Switchover of CPU Clock and Main System Clock Cycle Division Factor
(78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2)
Set Value Before
Switchover
CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0
0
0
8 clocks
4 clocks
4 clocks
16 clocks
16 clocks
16 clocks
16 clocks
2fXP/fSUB clocks
8 clocks
8 clocks
8 clocks
fXP/fSUB clocks
4 clocks
4 clocks
fXP/2fSUB clocks
2 clocks
2 clocks
2 clocks
1 clock
1 clock
1 clock
1 clock
2 clocks
2 clocks
2 clocks
2 clocks
2 clocks
fXP/4fSUB clocks
fXP/8fSUB clocks
2 clocks
Caution Selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the
main system clock to the subsystem clock (changing CSS from 0 to 1) should not be set
simultaneously.
Simultaneous setting is possible, however, for selection of the main system clock cycle division
factor (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock
(changing CSS from 1 to 0).
Remark
1. The number of clocks listed in Table 6-9 is the number of CPU clocks before switchover.
Users Manual U18598EJ1V0UD
255
Remark
2. When switching the CPU clock from the main system clock to the subsystem clock, calculate the
number of clocks by rounding up to the next clock and discarding the decimal portion, as shown
below.
Example When switching CPU clock from fXP/2 to fSUB/2 (@ oscillation with fXP = 10 MHz, fSUB =
32.768 kHz)
fXP/fSUB = 10000/32.768 305.1 306 clocks
By setting bit 0 (MCM0) of the main clock mode register (MCM), the main system clock can be switched (between
the internal high-speed oscillation clock and the high-speed system clock).
The actual switchover operation is not performed immediately after rewriting to MCM0; operation continues on the
pre-switchover clock for several clocks (see Table 6-10).
Whether the CPU is operating on the internal high-speed oscillation clock or the high-speed system clock can be
ascertained using bit 1 (MCS) of MCM.
Table 6-10. Maximum Time Required for Main System Clock Switchover
Set Value Before Switchover
MCM0
MCM0
0
1 + 2fRH/fXH clock
Cautions 1.
1 + 2fXH/fRH clock
When switching the internal high-speed oscillation clock to the high-speed system clock, bit
2 (XSEL) of MCM must be set to 1 in advance. The value of XSEL can be changed only once
after a reset release.
2.
Do not rewrite MCM0 when the CPU clock operates with the subsystem clock.
Remarks 1. The number of clocks listed in Table 6-10 is the number of main system clocks before switchover.
2. Calculate the number of clocks in Table 6-10 by removing the decimal portion.
Example When switching the main system clock from the internal high-speed oscillation clock to the
high-speed system clock (@ oscillation with fRH = 8 MHz, fXH = 10 MHz)
1 + 2fRH/fXH = 1 + 2 8/10 = 1 + 2 0.8 = 1 + 1.6 = 2.6 2 clocks
256
Clock
Register
Internal high-speed
MCS = 1
oscillation clock
X1 clock
MCS = 0
RSTOP = 1
MSTOP = 1
Register
Internal high-speed
MCS = 1 or CLS = 1
oscillation clock
RSTOP = 1
oscillation clock)
X1 clock
MCS = 0 or CLS = 1
(The CPU is operating on a clock other than the high-speed system clock)
XT1 clock
CLS = 0
MSTOP = 1
OSCSELS = 0
257
See 1.7
Outline of
Functions.
Table 6-13. Peripheral Hardware and Source Clocks
Peripheral
Hardware Clock
(fPRS)
Subsystem Clock
Note 1
(fSUB)
TM50 Output
00
Y (TI000 pin)
01
Y (TI001 pin)
Source Clock
Peripheral Hardware
16-bit timer/
event counter
External Clock
from Peripheral
Hardware Pins
Note 2
Note 2
8-bit timer/
event counter
50
Y (TI50 pin)
Note 2
51
Y (TI51 pin)
Note 2
8-Bit timer
H0
H1
Watch timer
Watchdog timer
Buzzer output
Clock output
A/D converter
Serial interface
UART0
UART6
CSI10
Y (SCK10 pin)
CSI11
Y (SCK11 pin)
CSIA0
Y (SCKA0 pin)
IIC0
Note 2
Note 2
Note 2
Y (EXSCL0,
Note 2
SCL0 pin)
258
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 3
y = 4 to 7
y = 4 to 7
16-bit timer/event
counters 00
16-bit timer/event
counters 00
259
Configuration
Time/counter
Register
Timer input
Timer output
Control registers
Remark
n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
Selector
CRC002CRC001 CRC000
Noise
eliminator
TI010/TO00/P01
Selector
To CR010
16-bit timer capture/compare
register 000 (CR000)
INTTM000
Match
Noise
eliminator
Output
controller
TO00 output
Output latch
(P01)
16-bit timer capture/compare
register 010 (CR010)
INTTM010
CRC002
PRM001 PRM000
Prescaler mode
register 00 (PRM00)
TMC003 TMC002 TMC001 OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
16-bit timer output
16-bit timer mode
control register 00
control register 00
(TOC00)
(TMC00)
Internal bus
260
TO00/TI010/
P01
Match
2
Noise
eliminator
TI000/P00
Clear
Selector
fPRS
Selector
fPRS
fPRS/22
fPRS/28
PM01
Selector
CRC012CRC011 CRC010
Noise
eliminator
TI011/TO01/P06
Selector
To CR011
16-bit timer capture/compare
register 001 (CR001)
INTTM001
Match
Clear
Output
controller
TO01 output
TO01/TI011/
P06
Match
Noise
eliminator
Output latch
(P06)
Noise
eliminator
TI001/P05/
SSI11
PM06
fPRS
Selector
fPRS
fPRS/24
fPRS/26
INTTM011
CRC012
PRM011 PRM010
Prescaler mode
register 01 (PRM01)
TMC013 TMC012 TMC011 OVF01 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01
16-bit timer output
16-bit timer mode
control register 01
control register 01
(TOC01)
(TMC01)
Internal bus
Cautions 1. The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at the same
time, and the valid edge of TI011 and timer output (TO01) cannot be used for the P06 pin at
the same time. Select either of the functions.
2. If clearing of bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n
(TMC0n) to 00 and input of the capture trigger conflict, then the captured data is undefined.
3. To change the mode from the capture mode to the comparison mode, first clear the TMC0n3
and TMC0n2 bits to 00, and then change the setting.
A value that has been once captured remains stored in CR00n unless the device is reset. If
the mode has been changed to the comparison mode, be sure to set a comparison value.
(1) 16-bit timer counter 0n (TM0n)
TM0n is a 16-bit read-only register that counts count pulses.
The counter is incremented in synchronization with the rising edge of the count clock.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
261
14
13
12
11
10
TM0n
(n = 0, 1)
The count value of TM0n can be read by reading TM0n when the value of bits 3 and 2 (TMC0n3 and TMC0n2) of
16-bit timer mode control register 0n (TMC0n) is other than 00. The value of TM0n is 0000H if it is read when
TMC0n3 and TMC0n2 = 00.
The count value is reset to 0000H in the following cases.
At reset signal generation
If TMC0n3 and TMC0n2 are cleared to 00
If the valid edge of the TI00n pin is input in the mode in which the clear & start occurs when inputting the valid
edge to the TI00n pin
If TM0n and CR00n match in the mode in which the clear & start occurs when TM0n and CR00n match
OSPT0n is set to 1 in one-shot pulse output mode or the valid edge is input to the TI00n pin
Caution
(2) 16-bit timer capture/compare register 00n (CR00n), 16-bit timer capture/compare register 01n (CR01n)
CR00n and CR01n are 16-bit registers that are used with a capture function or comparison function selected by
using CRC0n.
Change the value of CR00n while the timer is stopped (TMC0n3 and TMC0n2 = 00).
The value of CR01n can be changed during operation if the value has been set in a specific way. For details, see
7.5.1 Rewriting CR01n during TM0n operation.
These registers can be read or written in 16-bit units.
Reset signal generation clears these registers to 0000H.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
262
14
13
12
11
10
R/W
CR00n
(n = 0, 1)
14
13
12
11
10
R/W
CR01n
(n = 0, 1)
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
263
Note
M FFFFH
0000H
Note
N FFFFH
0000H
Note
M FFFFH
0000H
Note
M<N
Note
M FFFFH (M N)
Note
0000H
N FFFFH (N M)
0000H
Note When 0000H is set, a match interrupt immediately after the timer operation does not occur and timer output
is not changed, and the first match timing is as follows. A match interrupt occurs at the timing when the
timer counter (TM0n register) is changed from 0000H to 0001H.
When the timer counter is cleared due to overflow
When the timer counter is cleared due to TI00n pin valid edge (when clear & start mode is entered by
TI00n pin valid edge input)
When the timer counter is cleared due to compare match (when clear & start mode is entered by match
between TM0n and CR00n (CR00n = other than 0000H, CR01n = 0000H))
Timer counter clear
TM0n register
Operation enabled
(other than 00)
Interrupt signal
is generated
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
264
Capture
Operation
Capture operation of
CRC0n1 = 1
CRC0n1 bit = 0
CR00n
ES0n0
ES1n0
(reverse phase)
Position of edge to be
Position of edge to be
captured
captured
01: Rising
01: Rising
00: Falling
00: Falling
(cannot be captured)
INTTM00n signal is not
Interrupt signal
Capture operation of
CR01n
Note
Interrupt signal
INTTM00n signal is
is captured.
value is captured.
00: Falling
Interrupt signal
INTTM01n signal is
generated each time
value is captured.
Note The capture operation of CR01n is not affected by the setting of the CRC0n1 bit.
Caution To capture the count value of the TM0n register to the CR00n register by using the phase
reverse to that input to the TI00n pin, the interrupt request signal (INTTM00n) is not generated
after the value has been captured. If the valid edge is detected on the TI01n pin during this
operation, the capture operation is not performed but the INTTM00n signal is generated as an
external interrupt signal. To not use the external interrupt, mask the INTTM00n signal.
Remarks 1. CRC0n1: See 7.3 (2) Capture/compare control register 0n (CRC0n).
ES1n1, ES1n0, ES0n1, ES0n0: See 7.3 (4) Prescaler mode register 0n (PRM0n).
2. n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
265
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
266
R/W
Symbol
<0>
TMC00
TMC003
TMC002
TMC001
OVF00
TMC003
TMC002
Clear & start mode entered by TI000 pin valid edge input
Clear & start mode entered upon a match between TM00 and CR000
Note
TMC001
Match between TM00 and CR000 or match between TM00 and CR010
Match between TM00 and CR000 or match between TM00 and CR010
Trigger input of TI000 pin valid edge
OVF00
Clear (0)
Set (1)
OVF00 is set to 1 when the value of TM00 changes from FFFFH to 0000H in all the operation modes (free-running
timer mode, clear & start mode entered by TI000 pin valid edge input, and clear & start mode entered upon a match
between TM00 and CR000).
It can also be set to 1 by writing 1 to OVF00.
Note The TI000 pin valid edge is set by bits 5 and 4 (ES001, ES000) of prescaler mode register 00 (PRM00).
267
R/W
Symbol
<0>
TMC01
TMC013
TMC012
TMC011
OVF01
TMC013
TMC012
Clear & start mode entered by TI001 pin valid edge input
Clear & start mode entered upon a match between TM01 and CR001
Note
TMC011
Match between TM01 and CR001 or match between TM01 and CR011
Match between TM01 and CR001 or match between TM01 and CR011
Trigger input of TI001 pin valid edge
OVF01
Clear (0)
Set (1)
OVF01 is set to 1 when the value of TM01 changes from FFFFH to 0000H in all the operation modes (free-running
timer mode, clear & start mode entered by TI001 pin valid edge input, and clear & start mode entered upon a match
between TM01 and CR001).
It can also be set to 1 by writing 1 to OVF01.
Note The TI001 pin valid edge is set by bits 5 and 4 (ES011, ES010) of prescaler mode register 01 (PRM01).
268
R/W
Symbol
CRC00
CRC002
CRC001
CRC000
CRC002
CRC001
Note
The valid edge of the TI010 and TI000 pin is set by PRM00.
If ES001 and ES000 are set to 11 (both edges) when CRC001 is 1, the valid edge of the TI000 pin cannot
be detected.
CRC000
If TMC003 and TMC002 are set to 11 (clear & start mode entered upon a match between TM00 and
CR000), be sure to set CRC000 to 0.
Note When the valid edge is detected from the TI010 pin, the capture operation is not performed but the
INTTM000 signal is generated as an external interrupt signal.
Caution To ensure that the capture operation is performed properly, the capture trigger requires a pulse
two cycles longer than the count clock selected by prescaler mode register 00 (PRM00).
Remark
n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than 32 KB
269
Figure 7-9. Example of CR01n Capture Operation (When Rising Edge Is Specified)
Valid edge
Count clock
TM0n
N3
N2
N1
N+1
TI00n
Rising edge detection
CR01n
INTTM01n
R/W
Symbol
CRC01
CRC012
CRC011
CRC010
CRC012
CRC011
Note
The valid edge of the TI011 and TI001 pin is set by PRM01.
If ES011 and ES010 are set to 11 (both edges) when CRC011 is 1, the valid edge of the TI001 pin cannot
be detected.
CRC010
If TMC013 and TMC012 are set to 11 (clear & start mode entered upon a match between TM01 and
CR001), be sure to set CRC010 to 0.
Note When the valid edge is detected from the TI011 pin, the capture operation is not performed but the
INTTM001 signal is generated as an external interrupt signal.
Caution To ensure that the capture operation is performed properly, the capture trigger requires a pulse
two cycles longer than the count clock selected by prescaler mode register 01 (PRM01) (see
Figure 7-9 Example of CR01n Capture Operation (When Rising Edge Is Specified)).
Remark
n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than 32 KB
270
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
271
R/W
Symbol
<6>
<5>
<3>
<2>
<0>
TOC00
OSPT00
OSPE00
TOC004
LVS00
LVR00
TOC001
TOE00
OSPT00
The value of this bit is always 0 when it is read. Do not set this bit to 1 in a mode other than the oneshot pulse output mode.
If it is set to 1, TM00 is cleared and started.
OSPE00
One-shot pulse output operates correctly in the free-running timer mode or clear & start mode entered by
TI000 pin valid edge input.
The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM00 and
CR000.
TOC004
LVS00
LVR00
No change
Initial value of TO00 output is low level (TO00 output is cleared to 0).
Initial value of TO00 output is high level (TO00 output is set to 1).
Setting prohibited
LVS00 and LVR00 can be used to set the initial value of the TO00 output level. If the initial value does
not have to be set, leave LVS00 and LVR00 as 00.
Be sure to set LVS00 and LVR00 when TOE00 = 1.
LVS00, LVR00, and TOE00 being simultaneously set to 1 is prohibited.
LVS00 and LVR00 are trigger bits. By setting these bits to 1, the initial value of the TO00 output level
can be set. Even if these bits are cleared to 0, TO00 output is not affected.
The values of LVS00 and LVR00 are always 0 when they are read.
For how to set LVS00 and LVR00, see 7.5.2 Setting LVS0n and LVR0n.
The actual TO00/TI010/P01 pin output is determined depending on PM01 and P01, besides TO00
output.
TOC001
TOE00
272
Enables output
R/W
Symbol
<6>
<5>
<3>
<2>
<0>
TOC01
OSPT01
OSPE01
TOC014
LVS01
LVR01
TOC011
TOE01
OSPT01
The value of this bit is always 0 when it is read. Do not set this bit to 1 in a mode other than the one-shot
pulse output mode.
If it is set to 1, TM01 is cleared and started.
OSPE01
One-shot pulse output operates correctly in the free-running timer mode or clear & start mode entered by
TI001 pin valid edge input.
The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM01 and
CR001.
TOC014
LVS01
LVR01
No change
Initial value of TO01 output is low level (TO01 output is cleared to 0).
Initial value of TO01 output is high level (TO01 output is set to 1).
Setting prohibited
LVS01 and LVR01 can be used to set the initial value of the TO01 output level. If the initial value does
not have to be set, leave LVS01 and LVR01 as 00.
Be sure to set LVS01 and LVR01 when TOE01 = 1.
LVS01, LVR01, and TOE01 being simultaneously set to 1 is prohibited.
LVS01 and LVR01 are trigger bits. By setting these bits to 1, the initial value of the TO01 output level
can be set. Even if these bits are cleared to 0, TO01 output is not affected.
The values of LVS01 and LVR01 are always 0 when they are read.
For how to set LVS01 and LVR01, see 7.5.2 Setting LVS0n and LVR0n.
The actual TO01/TI011/P06 pin output is determined depending on PM06 and P06, besides TO01
output.
TOC011
TOE01
Enables output
273
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
274
R/W
Symbol
PRM00
ES101
ES100
ES001
ES000
PRM001
PRM000
ES101
ES100
Falling edge
Rising edge
Setting prohibited
ES001
ES000
Falling edge
Rising edge
Setting prohibited
PRM001
PRM000
Note 1
0
0
1
1
Notes 1.
0
1
0
1
fPRS
Note 2
fPRS = 5 MHz
fPRS = 10 MHz
fPRS = 20 MHz
2 MHz
5 MHz
10 MHz
20 MHz
fPRS/2
500 kHz
1.25 MHz
2.5 MHz
5 MHz
fPRS/2
7.81 kHz
19.53 kHz
39.06 kHz
78.12 kHz
Notes 3, 4
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
VDD = 4.0 to 5.5 V: fPRS 20 MHz
VDD = 2.7 to 4.0 V: fPRS 10 MHz
VDD = 1.8 to 2.7 V: fPRS 5 MHz
2.
If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
= 0), when 1.8 V VDD < 2.7 V, the setting of PRM001 = PRM000 = 0 (count clock: fPRS) is prohibited.
3.
The external clock from the TI000 pin requires a pulse longer than twice the cycle of the peripheral
hardware clock (fPRS).
4.
Do not start timer operation with the external clock from the TI000 pin when the internal high-speed
oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem
clock, or when in the STOP mode.
Remark
275
R/W
Symbol
PRM01
ES111
ES110
ES011
ES010
PRM011
PRM010
ES111
ES110
Falling edge
Rising edge
Setting prohibited
ES011
ES010
Falling edge
Rising edge
Setting prohibited
PRM011
PRM010
Note 1
fPRS = 5 MHz
fPRS = 10 MHz
fPRS = 20 MHz
fPRS
2 MHz
5 MHz
10 MHz
20 MHz
fPRS/2
125 kHz
312.5 kHz
625 kHz
1.25 MHz
fPRS/2
31.25 kHz
78.125 kHz
156.25 kHz
312.5 kHz
Notes 1.
Note 2
Notes 3, 4
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
VDD = 4.0 to 5.5 V: fPRS 20 MHz
VDD = 2.7 to 4.0 V: fPRS 10 MHz
VDD = 1.8 to 2.7 V: fPRS 5 MHz
2.
If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
3.
The external clock from the TI001 pin requires a pulse longer than twice the cycle of the peripheral
4.
Do not start timer operation with the external clock from the TI000 pin when the internal high-speed
= 0), when 1.8 V VDD < 2.7 V, the setting of PRM011 = PRM010 = 0 (count clock: fPRS) is prohibited.
hardware clock (fPRS).
oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem
clock, or when in the STOP mode.
Remark
276
Symbol
PM0
PM0n
Remark
R/W
3
The figure shown above presents the format of port mode register 0 of 78K0/KF2
products. For the format of port mode register 0 of other products, see (1) Port
mode registers (PMxx) in 5.3 Registers Controlling Port Function.
277
INTTM00n signal
Operable bits
TMC0n3, TMC0n2
CR00n register
Interval
(N + 1)
Interval
(N + 1)
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
00
11
Compare register
(CR00n)
Remark
n = 0:
Interval
(N + 1)
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than 32 KB
278
OVF0n
0
Clears and starts on match
between TM0n and CR00n.
0
CR00n used as
compare register
LVS0n
LVR0n
TOC0n1
TOE0n
ES1n0
ES0n1
ES0n0
PRM0n1 PRM0n0
0/1
0/1
Selects count clock
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
279
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
00
11
CR00n register
INTTM00n signal
<1>
<2>
START
STOP
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
280
Output
controller
TO0n output
TO0n pin
INTTM00n signal
Operable bits
TMC0n3, TMC0n2
CR00n register
Interval
(N + 1)
Interval
(N + 1)
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
00
11
Compare register
(CR00n)
TO0n output
Compare match interrupt
(INTTM00n)
Interval
(N + 1)
Remark
n = 0:
Interval
(N + 1)
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than 32 KB
281
OVF0n
0
CR00n used as
compare register
LVS0n
LVR0n
TOC0n1
TOE0n
0/1
0/1
1
Enables TO0n output.
Inverts TO0n output on match
between TM0n and CR00n.
Specifies initial value of TO0n output F/F
ES1n0
ES0n1
ES0n0
PRM0n1 PRM0n0
0/1
0/1
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
282
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
00
11
00
CR00n register
TO0n output
INTTM00n signal
TO0n output control bit
(TOC0n1, TOE0n)
<1>
<2>
START
STOP
Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control
register 0n (TOC0n).
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
283
Edge
detection
Operable bits
TMC0n3, TMC0n2
Output
controller
TO0n output
TO0n pin
INTTM00n signal
CR00n register
Remark
n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than 32 KB
284
Figure 7-25. Example of Register Settings in External Event Counter Mode (1/2)
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n3 TMC0n2 TMC0n1
0
OVF0n
0
CR00n used as
compare register
0/1
LVS0n
LVR0n
TOC0n1
TOE0n
0/1
0/1
0/1
0/1
0: Disables TO0n output
1: Enables TO0n output
Specifies initial value of
TO0n output F/F
00: Does not invert TO0n output on match
between TM0n and CR00n/CR01n.
01: Inverts TO0n output on match between
TM0n and CR00n.
10: Inverts TO0n output on match between
TM0n and CR01n.
11: Inverts TO0n output on match between
TM0n and CR00n/CR01n.
ES1n0
ES0n1
ES0n0
0/1
0/1
PRM0n1 PRM0n0
1
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
285
Figure 7-25. Example of Register Settings in External Event Counter Mode (2/2)
(e) 16-bit timer counter 0n (TM0n)
By reading TM0n, the count value can be read.
(f) 16-bit capture/compare register 00n (CR00n)
If M is set to CR00n, the interrupt signal (INTTM00n) is generated when the number of external events
reaches (M + 1).
Setting CR00n to 0000H is prohibited.
(g) 16-bit capture/compare register 01n (CR01n)
Usually, CR01n is not used in the external event counter mode. However, a compare match interrupt
(INTTM01n) is generated when the set value of CR01n matches the value of TM0n.
Therefore, mask the interrupt request by using the interrupt mask flag (TMMK01n).
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
286
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
00
11
Compare register
(CR00n)
00
TO0n output
Compare match interrupt
(INTTM00n)
TO0n output control bits
(TOC0n4, TOC0n1, TOE0n)
<1>
<2>
START
STOP
Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control
register 0n (TOC0n).
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
287
7.4.4 Operation in clear & start mode entered by TI00n pin valid edge input
When bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 10 (clear &
start mode entered by the TI00n pin valid edge input) and the count clock (set by PRM0n) is supplied to the
timer/event counter, TM0n starts counting up. When the valid edge of the TI00n pin is detected during the counting
operation, TM0n is cleared to 0000H and starts counting up again. If the valid edge of the TI00n pin is not detected,
TM0n overflows and continues counting.
The valid edge of the TI00n pin is a cause to clear TM0n. Starting the counter is not controlled immediately after
the start of the operation.
CR00n and CR01n are used as compare registers and capture registers.
(a) When CR00n and CR01n are used as compare registers
Signals INTTM00n and INTTM01n are generated when the value of TM0n matches the value of CR00n and
CR01n.
(b) When CR00n and CR01n are used as capture registers
The count value of TM0n is captured to CR00n and the INTTM00n signal is generated when the valid edge is
input to the TI01n pin (or when the phase reverse to that of the valid edge is input to the TI00n pin).
When the valid edge is input to the TI00n pin, the count value of TM0n is captured to CR01n and the
INTTM01n signal is generated. As soon as the count value has been captured, the counter is cleared to
0000H.
Caution Do not set the count clock as the valid edge of the TI00n pin (PRM0n1 and PRM0n0 = 11). When
PRM0n1 and PRM0n0 = 11, TM0n is cleared.
Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
(1) Operation in clear & start mode entered by TI00n pin valid edge input
(CR00n: compare register, CR01n: compare register)
Figure 7-27. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Compare Register, CR01n: Compare Register)
TI00n pin
Edge
detection
Clear
Count clock
Timer counter
(TM0n)
Match signal
Interrupt signal
(INTTM00n)
Operable bits
TMC0n3, TMC0n2
Compare register
(CR00n)
Match signal
Output
controller
TO0n output
TO0n pin
Interrupt signal
(INTTM01n)
Compare register
(CR01n)
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
n = 0, 1: 78K0/KF2, 78K0/KE2 products whose flash memory is at least 48 KB
288
Figure 7-28. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Compare Register, CR01n: Compare Register)
(a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 00H, TMC0n = 08H
M
TM0n register
M
N
M
N
M
N
0000H
Operable bits
(TMC0n3, TMC0n2)
00
10
Compare register
(CR01n)
TM0n register
M
N
M
N
M
N
0000H
Operable bits
(TMC0n3, TMC0n2)
00
10
(a) and (b) differ as follows depending on the setting of bit 1 (TMC0n1) of the 16-bit timer mode control register 0n
(TMC0n).
(a) The TO0n output level is inverted when TM0n matches a compare register.
(b) The TO0n output level is inverted when TM0n matches a compare register or when the valid edge of the
TI00n pin is detected.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
289
(2) Operation in clear & start mode entered by TI00n pin valid edge input
(CR00n: compare register, CR01n: capture register)
Figure 7-29. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Compare Register, CR01n: Capture Register)
Edge
detector
TI00n pin
Clear
Timer counter
(TM0n)
Count clock
Match signal
Interrupt signal
(INTTM00n)
Operable bits
TMC0n3, TMC0n2
Compare register
(CR00n)
Capture signal
Output
controller
TO0n output
TO0n pin
Interrupt signal
(INTTM01n)
Capture register
(CR01n)
Figure 7-30. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Compare Register, CR01n: Capture Register) (1/2)
(a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 04H, TMC0n = 08H, CR00n = 0001H
M
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
10
00
0001H
0000H
Capture interrupt
(INTTM01n)
TO0n output
This is an application example where the TO0n output level is inverted when the count value has been captured
& cleared.
The count value is captured to CR01n and TM0n is cleared (to 0000H) when the valid edge of the TI00n pin is
detected. When the count value of TM0n is 0001H, a compare match interrupt signal (INTTM00n) is generated,
and the TO0n output level is inverted.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
290
Figure 7-30. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Compare Register, CR01n: Capture Register) (2/2)
(b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 04H, TMC0n = 0AH, CR00n = 0003H
M
TM0n register
0003H
0000H
Operable bits
(TMC0n3, TMC0n2)
00
10
0003H
0000H
Capture interrupt
(INTTM01n)
TO0n output
This is an application example where the width set to CR00n (4 clocks in this example) is to be output from the
TO0n pin when the count value has been captured & cleared.
The count value is captured to CR01n, a capture interrupt signal (INTTM01n) is generated, TM0n is cleared (to
0000H), and the TO0n output level is inverted when the valid edge of the TI00n pin is detected. When the count
value of TM0n is 0003H (four clocks have been counted), a compare match interrupt signal (INTTM00n) is
generated and the TO0n output level is inverted.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
291
(3) Operation in clear & start mode by entered TI00n pin valid edge input
(CR00n: capture register, CR01n: compare register)
Figure 7-31. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Compare Register)
TI00n pin
Edge
detection
Clear
Timer counter
(TM0n)
Count clock
Match signal
Interrupt signal
(INTTM01n)
Operable bits
TMC0n3, TMC0n2
Compare register
(CR01n)
Capture signal
Remark n = 0:
Capture register
(CR00n)
Output
controller
TO0n output
Interrupt signal
(INTTM00n)
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
292
TO0n pin
Figure 7-32. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Compare Register) (1/2)
(a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 03H, TMC0n = 08H, CR01n = 0001H
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
00
10
0000H
L
0001H
This is an application example where the TO0n output level is to be inverted when the count value has been
captured & cleared.
TM0n is cleared at the rising edge detection of the TI00n pin and it is captured to CR00n at the falling edge
detection of the TI00n pin.
When bit 1 (CRC0n1) of capture/compare control register 0n (CRC0n) is set to 1, the count value of TM0n is
captured to CR00n in the phase reverse to that of the signal input to the TI00n pin, but the capture interrupt signal
(INTTM00n) is not generated. However, the INTTM00n signal is generated when the valid edge of the TI01n pin
is detected. Mask the INTTM00n signal when it is not used.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
293
Figure 7-32. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Compare Register) (2/2)
(b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 03H, TMC0n = 0AH, CR01n = 0003H
TM0n register
0003H
0000H
Operable bits
(TMC0n3, TMC0n2)
00
10
0000H
L
0003H
This is an application example where the width set to CR01n (4 clocks in this example) is to be output from the
TO0n pin when the count value has been captured & cleared.
TM0n is cleared (to 0000H) at the rising edge detection of the TI00n pin and captured to CR00n at the falling
edge detection of the TI00n pin. The TO0n output level is inverted when TM0n is cleared (to 0000H) because the
rising edge of the TI00n pin has been detected or when the value of TM0n matches that of a compare register
(CR01n).
When bit 1 (CRC0n1) of capture/compare control register 0n (CRC0n) is 1, the count value of TM0n is captured
to CR00n in the phase reverse to that of the input signal of the TI00n pin, but the capture interrupt signal
(INTTM00n) is not generated. However, the INTTM00n interrupt is generated when the valid edge of the TI01n
pin is detected. Mask the INTTM00n signal when it is not used.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
294
(4) Operation in clear & start mode entered by TI00n pin valid edge input
(CR00n: capture register, CR01n: capture register)
Figure 7-33. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Capture Register)
Operable bits
TMC0n3, TMC0n2
Clear
Timer counter
(TM0n)
Count clock
Capture register
(CR01n)
Capture signal
Interrupt signal
(INTTM01n)
TI00n pin
Edge
detection
Note
Edge
detection
TI01n pin
Selector
TO0n output
Output
controller
Capture register
(CR00n)
Capture
signal
TO0n pinNote
Interrupt signal
(INTTM00n)
Note The timer output (TO0n) cannot be used when detecting the valid edge of the TI01n pin is used.
Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Capture Register) (1/3)
(a) TOC0n = 13H, PRM0n = 30H, CRC0n = 05H, TMC0n = 0AH
L
TM0n register
N
M
Q
P
0000H
Operable bits
(TMC0n3, TMC0n2)
00
10
0000H
L
0000H
Capture interrupt
(INTTM01n)
TO0n output
This is an application example where the count value is captured to CR01n, TM0n is cleared, and the TO0n
output is inverted when the rising or falling edge of the TI00n pin is detected.
When the edge of the TI01n pin is detected, an interrupt signal (INTTM00n) is generated. Mask the INTTM00n
signal when it is not used.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
295
Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Capture Register) (2/3)
(b) TOC0n = 13H, PRM0n = C0H, CRC0n = 05H, TMC0n = 0AH
FFFFH
N
M
00
Q
S
0000H
Operable bits
(TMC0n3, TMC0n2)
TM0n register
10
0000H
Capture interrupt
(INTTM00n)
Capture & count clear input
(TI00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
0000H
L
This is a timing example where an edge is not input to the TI00n pin, in an application where the count value is
captured to CR00n when the rising or falling edge of the TI01n pin is detected.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
296
Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Capture Register) (3/3)
(c) TOC0n = 13H, PRM0n = 00H, CRC0n = 07H, TMC0n = 0AH
O
M
TM0n register
S
Q
W
T
0000H
Operable bits
(TMC0n3, TMC0n2)
10
00
0000H
Capture register
(CR01n)
0000H
N
M
P
O
R
Q
T
S
Capture interrupt
(INTTM01n)
Capture input
(TI01n)
Capture interrupt
(INTTM00n)
This is an application example where the pulse width of the signal input to the TI00n pin is measured.
By setting CRC0n, the count value can be captured to CR00n in the phase reverse to the falling edge of the
TI00n pin (i.e., rising edge) and to CR01n at the falling edge of the TI00n pin.
The high- and low-level widths of the input pulse can be calculated by the following expressions.
High-level width = [CR01n value] [CR00n value] [Count clock cycle]
Low-level width = [CR00n value] [Count clock cycle]
If the reverse phase of the TI00n pin is selected as a trigger to capture the count value to CR00n, the INTTM00n
signal is not generated. Read the values of CR00n and CR01n to measure the pulse width immediately after the
INTTM01n signal is generated.
However, if the valid edge specified by bits 6 and 5 (ES1n1 and ES1n0) of prescaler mode register 0n (PRM0n) is
input to the TI01n pin, the count value is not captured but the INTTM00n signal is generated. To measure the
pulse width of the TI00n pin, mask the INTTM00n signal when it is not used.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
297
Figure 7-35. Example of Register Settings in Clear & Start Mode Entered by TI00n Pin Valid Edge Input (1/2)
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n3 TMC0n2 TMC0n1
0
OVF0n
0/1
0
0: Inverts TO0n output on match
between TM0n and CR00n/CR01n.
1: Inverts TO0n output on match
between TM0n and CR00n/CR01n
and valid edge of TI00n pin.
Clears and starts at valid
edge input of TI00n pin.
0/1
0/1
0/1
0/1
LVS0n
LVR0n
TOC0n1
TOE0n
0/1
0/1
0/1
0/1
0: Disables TO0n outputNote
1: Enables TO0n output
Specifies initial value of
TO0n output F/F
00: Does not invert TO0n output on match
between TM0n and CR00n/CR01n.
01: Inverts TO0n output on match between
TM0n and CR00n.
10: Inverts TO0n output on match between
TM0n and CR01n.
11: Inverts TO0n output on match between
TM0n and CR00n/CR01n.
Note The timer output (TO0n) cannot be used when detecting the valid edge of the TI01n pin is used.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
298
Figure 7-35. Example of Register Settings in Clear & Start Mode Entered by TI00n Pin Valid Edge Input (2/2)
(d) Prescaler mode register 0n (PRM0n)
ES1n1
ES1n0
ES0n1
ES0n0
0/1
0/1
0/1
0/1
PRM0n1 PRM0n0
0/1
0/1
00:
01:
10:
11:
n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than 32 KB
299
Figure 7-36. Example of Software Processing in Clear & Start Mode Entered by TI00n Pin Valid Edge Input
M
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
10
00
00
<1>
<2>
<2>
<2>
<2>
<3>
START
STOP
Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register
0n (TOC0n).
Remark
300
n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than 32 KB
n = 0, 1: 78K0/KF2, 78K0/KE2 products whose flash memory is at least 48 KB
Users Manual U18598EJ1V0UD
Count clock
Match signal
Operable bits
TMC0n3, TMC0n2
Compare register
(CR00n)
Match signal
Interrupt signal
(INTTM00n)
TO0n output
Output
controller
TO0n pin
Interrupt signal
(INTTM01n)
Compare register
(CR01n)
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
301
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
00
Compare register
(CR00n)
01
00
0 write clear
0 write clear
0 write clear
0 write clear
This is an application example where two compare registers are used in the free-running timer mode.
The TO0n output level is reversed each time the count value of TM0n matches the set value of CR00n or CR01n.
When the count value matches the register value, the INTTM00n or INTTM01n signal is generated.
(2) Free-running timer mode operation
(CR00n: compare register, CR01n: capture register)
Figure 7-39. Block Diagram of Free-Running Timer Mode
(CR00n: Compare Register, CR01n: Capture Register)
Timer counter
(TM0n)
Count clock
Match signal
Interrupt signal
(INTTM00n)
Operable bits
TMC0n3, TMC0n2
Compare register
(CR00n)
Edge
detection
TI00n pin
Remark n = 0:
Capture signal
Capture register
(CR01n)
Interrupt signal
(INTTM01n)
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
302
TO0n pin
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
00
01
0000H
0000H
Capture interrupt
(INTTM01n)
TO0n output
Overflow flag
(OVF0n)
0 write clear
0 write clear
0 write clear
0 write clear
This is an application example where a compare register and a capture register are used at the same time in the
free-running timer mode.
In this example, the INTTM00n signal is generated and the TO0n output level is reversed each time the count
value of TM0n matches the set value of CR00n (compare register).
generated and the count value of TM0n is captured to CR01n each time the valid edge of the TI00n pin is
detected.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
303
Count clock
TI00n pin
TI01n pin
Edge
detection
Edge
detection
Selector
Capture signal
Capture
signal
Capture register
(CR01n)
Capture register
(CR00n)
Interrupt signal
(INTTM01n)
Interrupt signal
(INTTM00n)
Remarks 1. If both CR00n and CR01n are used as capture registers in the free-running timer mode, the TO0n
output level is not inverted.
However, it can be inverted each time the valid edge of the TI00n pin is detected if bit 1 (TMC0n1)
of 16-bit timer mode control register 0n (TMC0n) is set to 1.
2. n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
304
TM0n register
A
0000H
Operable bits
(TMC0n3, TMC0n2)
00
S
C
01
0000H
Capture interrupt
(INTTM01n)
Capture trigger input
(TI01n)
Capture register
(CR00n)
0000H
Capture interrupt
(INTTM00n)
Overflow flag
(OVF0n)
0 write clear
0 write clear
0 write clear
0 write clear
This is an application example where the count values that have been captured at the valid edges of separate
capture trigger signals are stored in separate capture registers in the free-running timer mode.
The count value is captured to CR01n when the valid edge of the TI00n pin input is detected and to CR00n when
the valid edge of the TI01n pin input is detected.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
305
00
0000H
Operable bits
(TMC0n3, TMC0n2)
TM0n register
01
0000H
Capture interrupt
(INTTM00n)
Capture trigger input
(TI00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
0000H
L
This is an application example where both the edges of the TI01n pin are detected and the count value is
captured to CR00n in the free-running timer mode.
When both CR00n and CR01n are used as capture registers and when the valid edge of only the TI01n pin is to
be detected, the count value cannot be captured to CR01n.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
306
OVF0n
0/1
0/1
0/1
0/1
0/1
LVS0n
LVR0n
TOC0n1
TOE0n
0/1
0/1
0/1
0/1
0: Disables TO0n output
1: Enables TO0n output
Specifies initial value of
TO0n output F/F
00: Does not invert TO0n output on match
between TM0n and CR00n/CR01n.
01: Inverts TO0n output on match between
TM0n and CR00n.
10: Inverts TO0n output on match between
TM0n and CR01n.
11: Inverts TO0n output on match between
TM0n and CR00n/CR01n.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
307
ES1n0
ES0n1
ES0n0
0/1
0/1
0/1
0/1
PRM0n1 PRM0n0
0/1
0/1
00:
01:
10:
11:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
308
M
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
00
M
N
00
01
Compare register
(CR00n)
<1>
<2>
STOP
Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control
register 0n (TOC0n).
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
n = 0, 1: 78K0/KF2, 78K0/KE2 products whose flash memory is at least 48 KB
Users Manual U18598EJ1V0UD
309
Clear
Timer counter
(TM0n)
Count clock
Match signal
Operable bits
TMC0n3, TMC0n2
Compare register
(CR00n)
Match signal
Interrupt signal
(INTTM00n)
TO0n output
Output
controller
TO0n pin
Interrupt signal
(INTTM01n)
Compare register
(CR01n)
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
310
Figure 7-46. Example of Register Settings for PPG Output Operation (1/2)
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n3 TMC0n2 TMC0n1
0
OVF0n
CR00n used as
compare register
CR01n used as
compare register
LVS0n
LVR0n
TOC0n1
TOE0n
0/1
0/1
1
Enables TO0n output
Specifies initial value of
TO0n output F/F
11: Inverts TO0n output on
match between TM0n
and CR00n/CR01n.
00: Disables one-shot pulse
output
ES1n0
ES0n1
ES0n0
PRM0n1 PRM0n0
0/1
0/1
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
311
Figure 7-46. Example of Register Settings for PPG Output Operation (2/2)
(e) 16-bit timer counter 0n (TM0n)
By reading TM0n, the count value can be read.
(f) 16-bit capture/compare register 00n (CR00n)
An interrupt signal (INTTM00n) is generated when the value of this register matches the count value of TM0n.
The count value of TM0n is not cleared.
(g) 16-bit capture/compare register 01n (CR01n)
An interrupt signal (INTTM01n) is generated when the value of this register matches the count value of TM0n.
The count value of TM0n is not cleared.
Caution Set values to CR00n and CR01n such that the condition 0000H CR01n < CR00n FFFFH is
satisfied.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
312
M
N
M
N
0000H
Operable bits
(TMC0n3, TMC0n2)
00
00
11
Compare register
(CR00n)
N+1
M+1
N+1
M+1
<2>
<1>
<2> Count operation stop flow
START
STOP
Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control
register 0n (TOC0n).
Remarks 1. PPG pulse cycle = (M + 1) Count clock cycle
PPG duty = (N + 1)/(M + 1)
2. n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
313
Clear
OSPE0n bit
Count clock
Timer counter
(TM0n)
Match signal
Interrupt signal
(INTTM00n)
Operable bits
TMC0n3, TMC0n2
Compare register
(CR00n)
TO0n output
Output
controller
Match signal
TO0n pin
Interrupt signal
(INTTM01n)
Compare register
(CR01n)
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
314
Figure 7-49. Example of Register Settings for One-Shot Pulse Output Operation (1/2)
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n3 TMC0n2 TMC0n1
0
0/1
0/1
OVF0n
CR00n used as
compare register
CR01n used as
compare register
0/1
LVS0n
LVR0n
TOC0n1
TOE0n
0/1
0/1
1
Enables TO0n output
Specifies initial value of
TO0n output
Inverts TO0n output on
match between TM0n
and CR00n/CR01n.
Enables one-shot pulse
output
Software trigger is generated
by writing 1 to this bit
(operation is not affected
even if 0 is written to it).
ES1n0
ES0n1
ES0n0
PRM0n1 PRM0n0
0/1
0/1
Selects count clock
Remark
n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than 32 KB
315
Figure 7-49. Example of Register Settings for One-Shot Pulse Output Operation (2/2)
(e) 16-bit timer counter 0n (TM0n)
By reading TM0n, the count value can be read.
(f) 16-bit capture/compare register 00n (CR00n)
This register is used as a compare register when a one-shot pulse is output. When the value of TM0n
matches that of CR00n, an interrupt signal (INTTM00n) is generated and the TO0n output level is inverted.
(g) 16-bit capture/compare register 01n (CR01n)
This register is used as a compare register when a one-shot pulse is output. When the value of TM0n
matches that of CR01n, an interrupt signal (INTTM01n) is generated and the TO0n output level is inverted.
Caution Do not set the same value to CR00n and CR01n.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
316
Figure 7-50. Example of Software Processing for One-Shot Pulse Output Operation (1/2)
FFFFH
N
TM0n register
N
M
0000H
Operable bits
(TMC0n3, TMC0n2)
00
01 or 10
00
NM
M+1 NM
<3>
Time from when the one-shot pulse trigger is input until the one-shot pulse is output
= (M + 1) Count clock cycle
One-shot pulse output active level width
= (N M) Count clock cycle
Remark
n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than 32 KB
317
Figure 7-50. Example of Software Processing for One-Shot Pulse Output Operation (2/2)
START
TOC0n.OSPT0n bit = 1
or edge input to TI00n pin
STOP
Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control
register 0n (TOC0n).
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
318
Count clock
TI00n pin
Edge
detection
TI01n pin
Edge
detection
Selector
Capture signal
Capture
signal
Capture register
(CR01n)
Capture register
(CR00n)
Interrupt signal
(INTTM01n)
Interrupt signal
(INTTM00n)
Clear
Timer counter
(TM0n)
Count clock
TI00n pin
Edge
detection
TI01n pin
Edge
detection
Remark n = 0:
Selector
Capture signal
Capture
signal
Capture register
(CR01n)
Capture register
(CR00n)
Interrupt signal
(INTTM01n)
Interrupt signal
(INTTM00n)
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
319
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
00
S
C
01
0000H
Capture interrupt
(INTTM01n)
Capture trigger input
(TI01n)
Capture register
(CR00n)
0000H
Capture interrupt
(INTTM00n)
Overflow flag
(OVF0n)
0 write clear
Remark
n = 0:
0 write clear
0 write clear
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than 32 KB
320
0 write clear
(2) Measuring the pulse width by using one input signal of the TI00n pin (free-running timer mode)
Set the free-running timer mode (TMC0n3 and TMC0n2 = 01). The count value of TM0n is captured to CR00n in
the phase reverse to the valid edge detected on the TI00n pin. When the valid edge of the TI00n pin is detected,
the count value of TM0n is captured to CR01n.
By this measurement method, values are stored in separate capture registers when a width from one edge to
another is measured. Therefore, the capture values do not have to be saved. By subtracting the value of one
capture register from that of another, a high-level width, low-level width, and cycle are calculated.
If an overflow occurs, the value becomes negative if one captured value is simply subtracted from another and,
therefore, a borrow occurs (bit 0 (CY) of the program status word (PSW) is set to 1). If this happens, ignore CY
and take the calculated value as the pulse width. In addition, clear bit 0 (OVF0n) of 16-bit timer mode control
register 0n (TMC0n) to 0.
Figure 7-54. Timing Example of Pulse Width Measurement (2)
TMC0n = 04H, PRM0n = 10H, CRC0n = 07H
FFFFH
M
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
00
S
C
01
0000H
Capture register
(CR01n)
0000H
B
M
C
N
D
S
Capture interrupt
(INTTM01n)
Overflow flag
(OVF0n)
0 write clear
Capture trigger input
(TI01n)
Capture interrupt
(INTTM00n)
Remark n = 0:
0 write clear
0 write clear
0 write clear
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
321
(3) Measuring the pulse width by using one input signal of the TI00n pin (clear & start mode entered by the
TI00n pin valid edge input)
Set the clear & start mode entered by the TI00n pin valid edge (TMC0n3 and TMC0n2 = 10). The count value of
TM0n is captured to CR00n in the phase reverse to the valid edge of the TI00n pin, and the count value of TM0n
is captured to CR01n and TM0n is cleared (0000H) when the valid edge of the TI00n pin is detected. Therefore,
a cycle is stored in CR01n if TM0n does not overflow.
If an overflow occurs, take the value that results from adding 10000H to the value stored in CR01n as a cycle.
Clear bit 0 (OVF0n) of 16-bit timer mode control register 0n (TMC0n) to 0.
Figure 7-55. Timing Example of Pulse Width Measurement (3)
TMC0n = 08H, PRM0n = 10H, CRC0n = 07H
FFFFH
TM0n register
<1>
<1>
A
0000H
Operable bits
00
(TMC0n3, TMC0n2)
10
00
<1>
<1>
0000H
Capture register
(CR01n)
0000H
<3>
<2>
<3>
A
M
<2>
<3>
B
N
<2>
<3>
C
S
D
P
Capture interrupt
(INTTM01n)
Overflow flag
(OVF0n)
0 write clear
Capture trigger input
(TI01n) L
Capture interrupt
(INTTM00n) L
<1>
Pulse cycle =
<2>
High-level pulse width = (10000H Number of times OVF0n bit is set to 1 + Captured value of CR00n)
<3>
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
322
Figure 7-56. Example of Register Settings for Pulse Width Measurement (1/2)
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n3 TMC0n2 TMC0n1
0
0/1
0/1
OVF0n
0/1
LVS0n
LVR0n
TOC0n1
TOE0n
ES1n0
ES0n1
ES0n0
0/1
0/1
0/1
0/1
PRM0n1 PRM0n0
0/1
0/1
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
323
Figure 7-56. Example of Register Settings for Pulse Width Measurement (2/2)
(e) 16-bit timer counter 0n (TM0n)
By reading TM0n, the count value can be read.
(f) 16-bit capture/compare register 00n (CR00n)
This register is used as a capture register. Either the TI00n or TI01n pin is selected as a capture trigger.
When a specified edge of the capture trigger is detected, the count value of TM0n is stored in CR00n.
(g) 16-bit capture/compare register 01n (CR01n)
This register is used as a capture register. The signal input to the TI00n pin is used as a capture trigger.
When the capture trigger is detected, the count value of TM0n is stored in CR01n.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
324
Figure 7-57. Example of Software Processing for Pulse Width Measurement (1/2)
(a) Example of free-running timer mode
FFFFH
D10
TM0n register
D11
D00
D13
D12
D01
D02
D03
D04
0000H
Operable bits
(TMC0n3, TMC0n2)
00
01
00
D10
0000H
D11
D12
D13
Capture interrupt
(INTTM01n)
Capture trigger input
(TI01n)
Capture register
(CR00n)
0000H
D00
D01
D02
D03
D04
Capture interrupt
(INTTM00n)
<2>
<2>
<2> <2>
<2>
<2>
<2><3>
(b) Example of clear & start mode entered by TI00n pin valid edge
FFFFH
D3
D2
D5
D0
TM0n register
D8
D6
D7
D4
D1
0000H
Operable bits
(TMC0n3, TMC0n2)
00
10
00
D3
D1
D5
D7
Capture register
(CR01n) 0000H
D2
D0
D4
D6
D8
Capture interrupt
(INTTM01n)
<1>
Remark n = 0:
<2> <2>
<2>
<2>
<2>
<2> <2>
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
325
Figure 7-57. Example of Software Processing for Pulse Width Measurement (2/2)
<1> Count operation start flow
START
STOP
Note The capture interrupt signal (INTTM00n) is not generated when the reverse-phase edge of the TI00n pin
input is selected to the valid edge of CR00n.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
326
Remark n = 0:
LVS0n
LVR0n
Setting prohibited
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
327
Caution Be sure to set LVS0n and LVR0n following steps <1>, <2>, and <3> above.
Step <2> can be performed after <1> and before <3>.
Figure 7-59. Timing Example of LVR0n and LVS0n
TOC0n.LVS0n bit
TOC0n.LVR0n bit
Operable bits
(TMC0n3, TMC0n2)
00
01, 10, or 11
TO0n output
INTTM00n signal
<1> <2> <1> <3> <4>
<4>
<4>
<1> The TO0n output goes high when LVS0n and LVR0n = 10.
<2> The TO0n output goes low when LVS0n and LVR0n = 01 (the pin output remains unchanged from the high
level even if LVS0n and LVR0n are cleared to 00).
<3> The timer starts operating when TMC0n3 and TMC0n2 are set to 01, 10, or 11. Because LVS0n and
LVR0n were set to 10 before the operation was started, the TO0n output starts from the high level. After
the timer starts operating, setting LVS0n and LVR0n is prohibited until TMC0n3 and TMC0n2 = 00
(disabling the timer operation).
<4> The TO0n output level is inverted each time an interrupt signal (INTTM00n) is generated.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
328
Restriction
As interval timer
As square-wave output
As external event counter
As clear & start mode entered by
Using timer output (TO0n) is prohibited when detection of the valid edge of the TI01n pin is
As free-running timer
As PPG output
0000H
0001H
0002H
0003H
0004H
Timer start
(3) Setting of CR00n and CR01n (clear & start mode entered upon a match between TM0n and CR00n)
Set a value other than 0000H to CR00n and CR01n (TM0n cannot count one pulse when it is used as an external
event counter).
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
329
N+1
N+2
M+1
M+2
Edge input
INTTM01n
Capture read signal
Value captured to CR01n
N+1
Capture operation
(b) The values of CR00n and CR01n are not guaranteed after 16-bit timer/event counter 0n stops.
(5) Setting valid edge
Set the valid edge of the TI00n pin while the timer operation is stopped (TMC0n3 and TMC0n2 = 00). Set the
valid edge by using ES0n0 and ES0n1.
(6) Re-triggering one-shot pulse
Make sure that the trigger is not generated while an active level is being output in the one-shot pulse output mode.
Be sure to input the next trigger after the current active level is output.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
330
When TM0n matches CR00n and TM0n is cleared from FFFFH to 0000H
Figure 7-62. Operation Timing of OVF0n Flag
Count pulse
CR00n
FFFFH
TM0n
FFFEH
FFFFH
0000H
0001H
OVF0n
INTTM00n
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
331
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
332
0034H
Read buffer
0034H
0035H
0036H
0035H
0037H
0037H
0038H
0039H
0038H
003AH
003BH
003BH
Read signal
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
333
Configuration
Timer register
Register
Timer input
TI5n
Timer output
TO5n
Control registers
Figures 8-1 and 8-2 show the block diagrams of 8-bit timer/event counters 50 and 51.
334
Selector
Match
Selector
INTTM50
Note 1
S
Q
INV
8-bit timer
OVF
counter 50 (TM50)
Selector
TI50/TO50/P17
fPRS
fPRS/2
fPRS/22
fPRS/26
fPRS/28
fPRS/213
Mask circuit
To TMH0
To UART0
To UART6
TO50
output
TO50/TI50/
P17
Output latch
(P17)
Note 2
S
Invert
level
Clear
PM17
Internal bus
Selector
Match
Selector
INTTM51
Note 1
S
Q
INV
8-bit timer
OVF
counter 51 (TM51)
Selector
TI51/TO51/
P33/INTP4
fPRS
fPRS/2
fPRS/24
fPRS/26
fPRS/28
fPRS/212
Mask circuit
Note 2
S
3
Clear
Invert
level
TO51
output
TO51/TI51/
P33/INTP4
Output latch
(P33)
PM33
Notes 1.
2.
335
Symbol
TM5n
(n = 0, 1)
R/W
Symbol
CR5n
(n = 0, 1)
Cautions 1. In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6 = 0), do
not write other values to CR5n during operation.
2. In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock
selected by TCL5n) or more.
Remark
336
n = 0, 1
n = 0, 1
337
R/W
Symbol
TCL50
TCL502
TCL501
TCL500
TCL502
TCL501
TCL500
fPRS =
fPRS =
fPRS =
fPRS =
2 MHz
5 MHz
10 MHz
20 MHz
fPRS
fPRS/2
fPRS/2
1
1
1
Notes 1.
Note 1
0
1
1
1
0
1
Note 3
Note 2
Note 2
2 MHz
5 MHz
10 MHz
20 MHz
1 MHz
2.5 MHz
5 MHz
10 MHz
500 kHz
1.25 MHz
2.5 MHz
5 MHz
fPRS/2
31.25 kHz
78.13 kHz
fPRS/2
7.81 kHz
19.53 kHz
39.06 kHz
78.13 kHz
fPRS/2
13
0.24 kHz
0.61 kHz
1.22 kHz
2.44 kHz
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
VDD = 4.0 to 5.5 V: fPRS 20 MHz
VDD = 2.7 to 4.0 V: fPRS 10 MHz
VDD = 1.8 to 2.7 V: fPRS 5 MHz
2.
Do not start timer operation with the external clock from the TI50 pin when the internal high-speed
oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem
clock, or when in the STOP mode.
3.
If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
= 0), when 1.8 V VDD < 2.7 V, the setting of TCL502, TCL501, TCL500 = 0, 1, 0 (count clock: fPRS) is
prohibited.
Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand.
2. Be sure to clear bits 3 to 7 to 0.
Remark
338
R/W
Symbol
TCL51
TCL512
TCL511
TCL510
TCL512
TCL511
TCL510
fPRS =
fPRS =
fPRS =
fPRS =
2 MHz
5 MHz
10 MHz
20 MHz
fPRS
fPRS/2
fPRS/2
1
1
1
Notes 1.
Note 1
0
1
1
1
0
1
Note 3
Note 2
Note 2
2 MHz
5 MHz
10 MHz
20 MHz
1 MHz
2.5 MHz
5 MHz
10 MHz
125 kHz
312.5 kHz
625 kHz
1.25 MHz
fPRS/2
31.25 kHz
78.13 kHz
fPRS/2
7.81 kHz
19.53 kHz
39.06 kHz
78.13 kHz
fPRS/2
12
0.49 kHz
1.22 kHz
2.44 kHz
4.88 kHz
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
VDD = 4.0 to 5.5 V: fPRS 20 MHz
VDD = 2.7 to 4.0 V: fPRS 10 MHz
VDD = 1.8 to 2.7 V: fPRS 5 MHz
2.
Do not start timer operation with the external clock from the TI51 pin when the internal high-speed
oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem
clock, or when in the STOP mode.
3.
If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
= 0), when 1.8 V VDD < 2.7 V, the setting of TCL512, TCL511, TCL510 = 0, 1, 0 (count clock: fPRS) is
prohibited.
Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand.
2. Be sure to clear bits 3 to 7 to 0.
Remark
339
n = 0, 1
Figure 8-7. Format of 8-Bit Timer Mode Control Register 50 (TMC50)
Address: FF6BH
R/W
Note
Symbol
<7>
<3>
<2>
<0>
TMC50
TCE50
TMC506
LVS50
LVR50
TMC501
TOE50
TCE50
TMC506
Mode in which clear & start occurs on a match between TM50 and CR50
LVS50
LVR50
No change
Timer output F/F clear (0) (default value of TO50 output: low level)
Timer output F/F set (1) (default value of TO50 output: high level)
Setting prohibited
TMC501
Active-high
Active-low
TOE50
Output enabled
340
R/W
Note
Symbol
<7>
<3>
<2>
<0>
TMC51
TCE51
TMC516
LVS51
LVR51
TMC511
TOE51
TCE51
TMC516
Mode in which clear & start occurs on a match between TM51 and CR51
LVS51
LVR51
No change
Timer output F/F clear (0) (default value of TO51 output: low)
Timer output F/F set (1) (default value of TO51 output: high)
Setting prohibited
TMC511
Active-high
Active-low
TOE51
Output enabled
341
R/W
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
PM1n
R/W
Symbol
PM3
PM33
PM32
PM31
PM30
PM3n
342
CR5n:
Compare value
TMC5n:
Stop the count operation, select the mode in which clear & start occurs on a match of TM5n
and CR5n.
(TMC5n = 00000B = Dont care)
00H
01H
Count start
CR5n
00H
01H
Clear
00H
01H
Clear
TCE5n
INTTM5n
Interrupt acknowledged
Interval time
Remark
Interrupt acknowledged
Interval time
Interval time = (N + 1) t
N = 01H to FFH
n = 0, 1
343
00H
00H
CR5n
00H
00H
TCE5n
INTTM5n
Interval time
01H
FFH
FEH
FFH
00H
FEH FFH
FFH
00H
FFH
TCE5n
INTTM5n
Interrupt acknowledged
Interval time
Remark
344
n = 0, 1
Interrupt
acknowledged
Compare value
TMC5n: Stop the count operation, select the mode in which clear & start occurs on match of TM5n and
CR5n, disable the timer F/F inversion operation, disable timer output.
(TMC5n = 00000000B)
<2> When TCE5n = 1 is set, the number of pulses input from the TI5n pin is counted.
<3> When the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H).
<4> After these settings, INTTM5n is generated each time the values of TM5n and CR5n match.
Note 8-bit timer/event counter 50: PM17
8-bit timer/event counter 51: PM33
Remark
For how to enable the INTTM5n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
Figure 8-12. External Event Counter Operation Timing (with Rising Edge Specified)
TI5n
Count start
00H
01H
02H
03H
04H
05H
CR5n
N1
00H
01H
02H
03H
INTTM5n
Remark
N = 00H to FFH
n = 0, 1
345
Compare value
TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and
CR5n.
LVS5n
LVR5n
Timer output F/F clear (0) (default value of TO5n output: low level)
Timer output F/F set (1) (default value of TO5n output: high level)
346
00H
01H
02H
N1
00H
01H
02H
N1
00H
Count start
CR5n
TO5nNote
Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control
register 5n (TMC5n).
8.4.4 PWM output operation
8-bit timer/event counter 5n operates as a PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n
(TMC5n) is set to 1.
The duty pulse determined by the value set to 8-bit timer compare register 5n (CR5n) is output from TO5n.
Set the active level width of the PWM pulse to CR5n; the active level can be selected with bit 1 (TMC5n1) of
TMC5n.
The count clock can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n).
PWM output can be enabled/disabled with bit 0 (TOE5n) of TMC5n.
Caution In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by
TCL5n) or more.
Remark
n = 0, 1
347
Compare value
Active-high
Active-low
348
n = 0, 1
00H 01H
CR5n
N N+1
00H
TCE5n
INTTM5n
TO5n
<2> Active level
00H 01H
CR5n
00H
M 00H
TCE5n
INTTM5n
TO5n L (Inactive level)
TM5n
00H 01H
CR5n
FFH
M 00H
TCE5n
INTTM5n
TO5n
<1> Inactive level
Remarks 1. <1> to <3> and <5> in Figure 8-14 (a) and (c) correspond to <1> to <3> and <5> in PWM output
operation in 8.4.4 (1) PWM output basic operation.
2. n = 0, 1
349
N N+1 N+2
CR5n
TCE5n
INTTM5n
M M+1 M+2
M M+1 M+2
TO5n
<2>
<1> CR5n change (N M)
(b) CR5n value is changed from N to M after clock rising edge of FFH
Value is transferred to CR5n at second overflow.
t
Count clock
TM5n
N N+1 N+2
CR5n
TCE5n
INTTM5n
N N+1 N+2
M M+1 M+2
TO5n
<1> CR5n change (N M)
<2>
Caution When reading from CR5n between <1> and <2> in Figure 8-15, the value read differs from the
actual value (read value: M, actual value of CR5n: N).
350
00H
01H
02H
03H
04H
Timer start
34H
Read buffer
34H
35H
36H
35H
37H
37H
38H
39H
38H
3AH
3BH
3BH
Read signal
Remark
n = 0, 1
351
Configuration
Timer register
Registers
Timer output
Control registers
n = 0, 1
352
Note
8-bit timer H
compare register
10 (CMP10)
8-bit timer H
compare register
00 (CMP00)
2
TOH0
output
Decoder
TOH0/P15
fPRS
fPRS/2
fPRS/22
fPRS/26
fPRS/210
8-bit timer/
event counter 50
output
Selector
Match
Interrupt
generator
F/F
R
Output
controller
Level
inversion
Output latch
(P15)
8-bit timer
counter H0
Clear
PWM mode signal
1
0
INTTMH0
PM15
Selector
353
354
8-bit timer H
compare
register 0 1
(CMP01)
8-bit timer H
compare
register 1 1
(CMP11)
Reload/
interrupt control
TOH1
output
TOH1/
INTP5/
P16
Decoder
Selector
Match
fPRS
fPRS/22
fPRS/24
fPRS/26
fPRS/212
fRL
fRL/27
fRL/29
Interrupt
generator
F/F
R
Output
controller
Level
inversion
Output latch
(P16)
8-bit timer
counter H1
Carrier generator mode signal
Clear
1
0
INTTMH1
PM16
Selector
R/W
2
Caution CMP0n cannot be rewritten during timer count operation. CMP0n can be refreshed (the same
value is written) during timer count operation.
(2) 8-bit timer H compare register 1n (CMP1n)
This register can be read or written by an 8-bit memory manipulation instruction. This register is used in the
PWM output mode and carrier generator mode.
In the PWM output mode, this register constantly compares the value set to CMP1n with the count value of the 8bit timer counter Hn and, when the two values match, inverts the output level of TOHn. No interrupt request
signal is generated.
In the carrier generator mode, the CMP1n register always compares the value set to CMP1n with the count value
of the 8-bit timer counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn).
At the same time, the count value is cleared.
CMP1n can be refreshed (the same value is written) and rewritten during timer count operation.
If the value of CMP1n is rewritten while the timer is operating, the new value is latched and transferred to CMP1n
when the count value of the timer matches the old value of CMP1n, and then the value of CMP1n is changed to
the new value. If matching of the count value and the CMP1n value and writing a value to CMP1n conflict, the
value of CMP1n is not changed.
A reset signal generation clears this register to 00H.
Figure 9-4. Format of 8-Bit Timer H Compare Register 1n (CMP1n)
Address: FF19H (CMP10), FF1BH (CMP11)
Symbol
CMP1n
(n = 0, 1)
R/W
2
Caution In the PWM output mode and carrier generator mode, be sure to set CMP1n when starting the
timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be
sure to set again even if setting the same value to CMP1n).
Remark
n = 0, 1
355
356
TMHMD0
R/W
<7>
TMHE0
CKS02
CKS01
CKS00
TMHE0
<1>
<0>
TOEN0
CKS02
CKS01
CKS00
fPRS =
2 MHz
fPRS =
5 MHz
fPRS =
10 MHz
fPRS =
20 MHz
5 MHz
10 MHz
20 MHz
5 MHz
10 MHz
fPRSNote 2 2 MHz
fPRS/2
1 MHz
2.5 MHz
500 kHz
fPRS/2
fPRS/2
TM50 output
Setting prohibited
4.88 kHz
5 MHz
Note 3
TMMD01 TMMD00
Setting prohibited
TOLEV0
Low level
High level
TOEN0
Notes 1.
Disables output
Enables output
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
VDD = 4.0 to 5.5 V: fPRS 20 MHz
VDD = 2.7 to 4.0 V: fPRS 10 MHz
VDD = 1.8 to 2.7 V: fPRS 5 MHz
2.
If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
= 0), when 1.8 V VDD < 2.7 V, the setting of CKS02 = CKS01 = CKS00 = 0 (count clock: fPRS) is
prohibited.
357
Note
3.
Note the following points when selecting the TM50 output as the count clock.
Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion
operation (TMC501 = 1).
PWM mode (TMC506 = 1)
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty =
50%.
It is not necessary to enable (TOE50 = 1) TO50 output in any mode.
Cautions 1. When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited. However, TMHMD0 can be
refreshed (the same value is written).
2. In the PWM output mode, be sure to set the 8-bit timer H compare register 10 (CMP10) when
starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped
(TMHE0 = 0) (be sure to set again even if setting the same value to CMP10).
3. The actual TOH0/P15 pin output is determined depending on PM15 and P15, besides TOH0
output.
Remarks 1. fPRS: Peripheral hardware clock frequency
2. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50)
TMC501: Bit 1 of TMC50
358
TMHMD1
R/W
<7>
TMHE1
CKS12
CKS11
CKS10
TMHE1
<1>
<0>
TOEN1
CKS12
0
0
CKS11
CKS10
fPRS =
2 MHz
fPRS =
5 MHz
fPRS =
10 MHz
fPRS =
20 MHz
fPRSNote 2 2 MHz
5 MHz
10 MHz
20 MHz
500 kHz
5 MHz
125 kHz
1.25 MHz
fPRS/2
fPRS/2
fPRS/2
fRL/2
fRL/2
fRL
TMMD11 TMMD10
2.44 kHz
4.88 kHz
Setting prohibited
TOLEV1
Low level
High level
TOEN1
Notes 1.
Disables output
Enables output
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
VDD = 4.0 to 5.5 V: fPRS 20 MHz
VDD = 2.7 to 4.0 V: fPRS 10 MHz
VDD = 1.8 to 2.7 V: fPRS 5 MHz
2.
If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
= 0), when 1.8 V VDD < 2.7 V, the setting of CKS12 = CKS11 = CKS10 = 0 (count clock: fPRS) is
prohibited.
359
Cautions 1. When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited. However, TMHMD1 can be
refreshed (the same value is written).
2. In the PWM output mode and carrier generator mode, be sure to set the 8-bit timer H compare
register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count
operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to
CMP11).
3. When the carrier generator mode is used, set so that the count clock frequency of TMH1
becomes more than 6 times the count clock frequency of TM51.
4. The actual TOH1/INTP5/P16 pin output is determined depending on PM16 and P16, besides
TOH1 output.
Remarks 1. fPRS: Peripheral hardware clock frequency
2. fRL:
R/WNote
<0>
TMCYC1
RMC1
NRZB1
Low-level output
Low-level output
NRZ1
RMC1
NRZB1
NRZ1
360
R/W
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
PM1n
361
TMHMDn
CKSn2
CKSn1
CKSn0
0/1
0/1
0/1
0/1
TOENn
0/1
362
00H
01H
00H
01H
Clear
00H
01H 00H
Clear
CMP0n
TMHEn
INTTMHn
Interval time
TOHn
<2>
Level inversion,
match interrupt occurrence,
8-bit timer counter Hn clear
<1>
<3>
<2>
Level inversion,
match interrupt occurrence,
8-bit timer counter Hn clear
<1> The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than
1 clock after the operation is enabled.
<2> When the value of the 8-bit timer counter Hn matches the value of the CMP0n register, the value of the timer
counter is cleared, and the level of the TOHn output is inverted. In addition, the INTTMHn signal is output at
the rising edge of the count clock.
<3> If the TMHEn bit is cleared to 0 while timer H is operating, the INTTMHn signal and TOHn output are set to
the default level. If they are already at the default level before the TMHEn bit is cleared to 0, then that level
is maintained.
Remark
n = 0, 1
01H N FEH
363
Count clock
Count start
00H
01H
FEH
FFH
00H
FEH
Clear
TMHEn
INTTMHn
TOHn
Interval time
00H
CMP0n
00H
TMHEn
INTTMHn
TOHn
Interval time
Remark
364
n = 0, 1
00H
Clear
FFH
CMP0n
FFH
TMHMDn
CKSn2
CKSn1
CKSn0
0/1
0/1
0/1
0/1
TOENn
1
365
<5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained.
<6> To stop the count operation, set TMHEn = 0.
If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count
clock frequency is fCNT, the PWM pulse output cycle and duty are as follows.
PWM pulse output cycle = (N + 1)/fCNT
Duty = (M + 1)/(N + 1)
Cautions 1. The set value of the CMP1n register can be changed while the timer counter is operating.
However, this takes a duration of three operating clocks (signal selected by the CKSn2 to
CKSn0 bits of the TMHMDn register) from when the value of the CMP1n register is changed
until the value is transferred to the register.
2. Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) after
the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the
same value to the CMP1n register).
3. Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are
within the following range.
00H CMP1n (M) < CMP0n (N) FFH
Remarks 1. For the setting of the output pin, see 9.3 (3) Port mode register 1 (PM1).
2. For details on how to enable the INTTMHn signal interrupt, see CHAPTER 20
FUNCTIONS.
3. n = 0, 1
366
INTERRUPT
Count clock
00H 01H
CMP0n
A5H
CMP1n
01H
A5H 00H
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
<1>
<2>
<3>
<4>
TOHn
(TOLEVn = 1)
<1> The count operation is enabled by setting the TMHEn bit to 1. Start the 8-bit timer counter Hn by masking
one count clock to count up. At this time, PWM output outputs an inactive level.
<2> When the values of the 8-bit timer counter Hn and the CMP0n register match, an active level is output. At
this time, the value of the 8-bit timer counter Hn is cleared, and the INTTMHn signal is output.
<3> When the values of the 8-bit timer counter Hn and the CMP1n register match, an inactive level is output. At
this time, the 8-bit timer counter value is not cleared and the INTTMHn signal is not output.
<4> Clearing the TMHEn bit to 0 during timer Hn operation sets the INTTMHn signal to the default and PWM
output to an inactive level.
Remark n = 0, 1
367
Count clock
00H 01H
CMP0n
FFH
CMP1n
00H
FFH 00H
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
Count clock
00H 01H
CMP0n
FFH
CMP1n
FEH
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
Remark
368
n = 0, 1
Count clock
00H
CMP0n
01H
CMP1n
00H
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
Remark
n = 0, 1
369
8-bit timer
counter Hn
80H
A5H 00H
A5H
CMP01
02H
CMP11
02H (03H)
<2>
03H
<2>
TMHE1
INTTMH1
TOH1
(TOLEV1 = 0)
<1>
<3>
<4>
<5>
<6>
<1> The count operation is enabled by setting TMHEn = 1. Start the 8-bit timer counter Hn by masking one count
clock to count up. At this time, PWM output outputs an inactive level.
<2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous
to the count clock.
<3> When the values of the 8-bit timer counter Hn and the CMP0n register match, the value of the 8-bit timer
counter Hn is cleared, an active level is output, and the INTTMHn signal is output.
<4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the
values of the 8-bit timer counter Hn and the CMP1n register before the change match, the value is
transferred to the CMP1n register and the CMP1n register value is changed (<2>).
However, three count clocks or more are required from when the CMP1n register value is changed to when
the value is transferred to the register. If a match signal is generated within three count clocks, the changed
value cannot be transferred to the register.
<5> When the values of the 8-bit timer counter Hn and the CMP1n register after the change match, an inactive
level is output. The 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
<6> Clearing the TMHEn bit to 0 during timer Hn operation sets the INTTMHn signal to the default and PWM
output to an inactive level.
Remark n = 0, 1
370
NRZB1 Bit
Output
Low-level output
Low-level output
371
To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register
have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written.
The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal.
The INTTM5H1 signal becomes the data transfer signal of the NRZ1 bit, and the NRZB1 bit value is transferred to
the NRZ1 bit. The timing for transfer from the NRZB1 bit to the NRZ1 bit is as shown below.
Figure 9-13. Transfer Timing
TMHE1
8-bit timer H1
count clock
INTTM51
INTTM5H1
<1>
NRZ1
<2>
NRZB1
<3>
RMC1
<1>
The INTTM51 signal is synchronized with the count clock of the 8-bit timer H1 and is output as the
INTTM5H1 signal.
<2>
The value of the NRZB1 bit is transferred to the NRZ1 bit at the second clock from the rising edge of the
INTTM5H1 signal.
<3>
Write the next value to the NRZB1 bit in the interrupt servicing program that has been started by the
INTTM5H1 interrupt or after timing has been checked by polling the interrupt request flag. Write data to
count the next time to the CR51 register.
Cautions 1. Do not rewrite the NRZB1 bit again until at least the second clock after it has been rewritten,
or else the transfer from the NRZB1 bit to the NRZ1 bit is not guaranteed.
2. When the 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is
generated at the timing of <1>. When the 8-bit timer/event counter 51 is used in a mode other
than the carrier generator mode, the timing of the interrupt generation differs.
Remark
372
Setting
<1> Set each register.
Figure 9-14. Register Setting in Carrier Generator Mode
(i)
TMHMD1
TMHE1
CKS12
CKS11
CKS10
0/1
0/1
0/1
TOEN1
0/1
373
<10> By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation,
clear TMHE1 to 0.
If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count
clock frequency is fCNT, the carrier clock output cycle and duty are as follows.
Carrier clock output cycle = (N + M + 2)/fCNT
Duty = High-level width/carrier clock output width = (M + 1)/(N + M + 2)
Cautions 1. Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1)
after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if
setting the same value to the CMP11 register).
2. Set so that the count clock frequency of TMH1 becomes more than 6 times the count
clock frequency of TM51.
3. Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH.
4. The set value of the CMP11 register can be changed while the timer counter is
operating. However, it takes the duration of three operating clocks (signal selected by
the CKS12 to CKS10 bits of the TMHMD1 register) since the value of the CMP11
register has been changed until the value is transferred to the register.
5. Be sure to set the RMC1 bit before the count operation is started.
Remarks 1. For the setting of the output pin, see 9.3 (3) Port mode register 1 (PM1).
2. For how to enable the INTTMH1 signal interrupt, see CHAPTER 20
FUNCTIONS.
374
INTERRUPT
00H
N 00H
00H
N 00H
CMP01
CMP11
N 00H
00H
TMHE11
INTTMH1
<3>
<4>
<1><2>
Carrier clock
8-bit timer 51
count clock
TM51 count value
00H 01H
K 00H 01H
CR51
00H 01H
M 00H 01H
N 00H 01H
N
TCE51
<5>
INTTM51
INTTM5H1
NRZB1
<6>
NRZ1
Carrier clock
TOH1
<7>
<1> When TMHE1 = 0 and TCE51 = 0, the 8-bit timer counter H1 operation is stopped.
<2> When TMHE1 = 1 is set, the 8-bit timer counter H1 starts a count operation. At that time, the carrier clock
remains default.
<3> When the count value of the 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1
signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8bit timer counter H1 is switched from the CMP01 register to the CMP11 register. The 8-bit timer counter H1
is cleared to 00H.
<4> When the count value of the 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal
is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer
counter H1 is switched from the CMP11 register to the CMP01 register. The 8-bit timer counter H1 is cleared
to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to 50% is
generated.
<5> When the INTTM51 signal is generated, it is synchronized with the 8-bit timer H1 count clock and is output as
the INTTM5H1 signal.
<6> The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is
transferred to the NRZ1 bit.
<7> When NRZ1 = 0 is set, the TOH1 output becomes low level.
Remark
375
00H
00H 01H
M 00H
N 00H 01H
CMP01
CMP11
M 00H
00H
TMHE1
INTTMH1
<3>
<4>
<1><2>
Carrier clock
8-bit timer 51
count clock
TM51 count value
00H 01H
K 00H 01H
L 00H 01H
CR51
M 00H 01H
N 00H 01H
TCE51
<5>
INTTM51
INTTM5H1
NRZB1
NRZ1
0
1
Carrier clock
<6>
TOH1
<7>
<1> When TMHE1 = 0 and TCE51 = 0, the 8-bit timer counter H1 operation is stopped.
<2> When TMHE1 = 1 is set, the 8-bit timer counter H1 starts a count operation. At that time, the carrier clock
remains default.
<3> When the count value of the 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1
signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8bit timer counter H1 is switched from the CMP01 register to the CMP11 register. The 8-bit timer counter H1
is cleared to 00H.
<4> When the count value of the 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal
is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer
counter H1 is switched from the CMP11 register to the CMP01 register. The 8-bit timer counter H1 is cleared
to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to other than 50%
is generated.
<5> When the INTTM51 signal is generated, it is synchronized with the 8-bit timer H1 count clock and is output as
the INTTM5H1 signal.
<6> A carrier signal is output at the first rising edge of the carrier clock if NRZ1 is set to 1.
<7> When NRZ1 = 0, the TOH1 output is held at the high level and is not changed to low level while the carrier
clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed).
Remark
376
00H 01H
00H 01H
00H
00H 01H
00H
CMP01
<3>
M
CMP11
<3>
M (L)
TMHE1
INTTMH1
<2>
Carrier clock
<4>
<5>
<1>
<1> When TMHE1 = 1 is set, the 8-bit timer H1 starts a count operation. At that time, the carrier clock remains
default.
<2> When the count value of the 8-bit timer counter H1 matches the value of the CMP01 register, the INTTMH1
signal is output, the carrier signal is inverted, and the timer counter is cleared to 00H. At the same time, the
compare register whose value is to be compared with that of the 8-bit timer counter H1 is changed from the
CMP01 register to the CMP11 register.
<3> The CMP11 register is asynchronous to the count clock, and its value can be changed while the 8-bit timer
H1 is operating. The new value (L) to which the value of the register is to be changed is latched. When the
count value of the 8-bit timer counter H1 matches the value (M) of the CMP11 register before the change, the
CMP11 register is changed (<3>).
However, it takes three count clocks or more since the value of the CMP11 register has been changed until
the value is transferred to the register. Even if a match signal is generated before the duration of three count
clocks elapses, the new value is not transferred to the register.
<4> When the count value of 8-bit timer counter H1 matches the value (M) of the CMP1 register before the
change, the INTTMH1 signal is output, the carrier signal is inverted, and the timer counter is cleared to 00H.
At the same time, the compare register whose value is to be compared with that of the 8-bit timer counter H1
is changed from the CMP11 register to the CMP01 register.
<5> The timing at which the count value of the 8-bit timer counter H1 and the CMP11 register value match again
is indicated by the value after the change (L).
377
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 7
y = 4 to 7
Watch timer
fPRS/27
11-bit prescaler
fW
fWX
5-bit counter
fWX/24
fWX/25
Clear
WTM7
WTM6
WTM5
INTWTI
WTM4
WTM3
WTM2
WTM1
Remark
fWX: fW or fW/29
378
INTWT
Selector
fSUB
Selector
Clear
Selector
Selector
WTM0
When Operated at
When Operated at
When Operated at
When Operated at
When Operated at
fPRS = 2 MHz
fPRS = 5 MHz
fPRS = 10 MHz
fPRS = 20 MHz
488 s
2 /fW
1.02 ms
410 s
205 s
102 s
977 s
2.05 ms
819 s
410 s
205 s
13
0.25 s
0.52 s
0.210 s
0.105 s
52.5 ms
14
0.5 s
1.05 s
0.419 s
0.210 s
0.105 s
2 /fW
2 /fW
2 /fW
Remark
When Operated at
When Operated at
When Operated at
When Operated at
When Operated at
fPRS = 2 MHz
fPRS = 5 MHz
fPRS = 10 MHz
fPRS = 20 MHz
488 s
1.02 ms
410 s
205 s
102 s
977 s
2.05 ms
820 s
410 s
205 s
1.95 ms
4.10 ms
1.64 ms
820 s
410 s
3.91 ms
8.20 ms
3.28 ms
1.64 ms
820 s
7.81 ms
16.4 ms
6.55 ms
3.28 ms
1.64 ms
15.6 ms
32.8 ms
13.1 ms
6.55 ms
3.28 ms
10
31.3 ms
65.5 ms
26.2 ms
13.1 ms
6.55 ms
11
62.5 ms
131.1 ms
52.4 ms
26.2 ms
13.1 ms
2 /fW
2 /fW
2 /fW
2 /fW
2 /fW
2 /fW
2 /fW
2 /fW
Remark
379
Configuration
Counter
5 bits 1
Prescaler
11 bits 1
Control register
380
R/W
<1>
<0>
WTM7
WTM6
WTM5
WTM4
WTM3
WTM2
WTM1
WTM0
Note
WTM7
fPRS/2
fSUB
WTM6
fPRS = 2 MHz
15.625 kHz
fPRS = 5 MHz
39.062 kHz
fPRS = 20 MHz
78.125 kHz
156.25 kHz
32.768 kHz
WTM5
fPRS = 10 MHz
WTM4
2 /fW
2 /fW
2 /fW
2 /fW
2 /fW
2 /fW
2 /fW
2 /fW
WTM3
WTM2
10
11
2 /fW
2 /fW
2 /fW
2 /fW
13
WTM1
Start
WTM0
Operation enable
Note If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the fPRS
operating frequency varies depending on the supply voltage.
VDD = 4.0 to 5.5 V: fPRS 20 MHz
VDD = 2.7 to 4.0 V: fPRS 10 MHz
VDD = 1.8 to 2.7 V: fPRS 5 MHz
Caution
Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to WTM7) of WTM)
during watch timer operation.
7
Remarks 1. fW: Watch timer clock frequency (fPRS/2 or fSUB)
2. fPRS: Peripheral hardware clock frequency
3. fSUB: Subsystem clock frequency
381
WTM2
Interrupt Time When Operated at When Operated at When Operated at When Operated at When Operated at
Selection
fPRS = 20 MHz
(WTM7 = 0)
0.210 s
0.105 s
13
0.25 s
0.52 s
0.210 s
0.105 s
52.5 ms
977 s
2.05 ms
819 s
410 s
205 s
488 s
1.02 ms
410 s
205 s
102 s
2 /fW
Remarks 1. fW:
(WTM7 = 0)
0.419 s
fPRS = 10 MHz
(WTM7 = 0)
1.05 s
2 /fW
fPRS = 5 MHz
(WTM7 = 0)
0.5 s
fPRS = 2 MHz
(WTM7 = 1)
14
2 /fW
2 /fW
WTM5
WTM4
Interval Time
977 s
2.05 ms
820 s
410 s
205 s
1.95 ms
4.10 ms
1.64 ms
820 s
410 s
3.91 ms
8.20 ms
3.28 ms
1.64 ms
820 s
7.81 ms
16.4 ms
6.55 ms
3.28 ms
1.64 ms
15.6 ms
32.8 ms
13.1 ms
6.55 ms
3.28 ms
10
31.3 ms
65.5 ms
26.2 ms
13.1 ms
6.55 ms
11
62.5 ms
131.1 ms
52.4 ms
26.2 ms
13.1 ms
2 /fW
2 /fW
2 /fW
2 /fW
2 /fW
2 /fW
2 /fW
382
(WTM7 = 0)
Remarks 1. fW:
(WTM7 = 0)
102 s
(WTM7 = 0)
205 s
2 /fW
(WTM7 = 0)
1.02 ms
at fPRS = 2 MHz
488 s
at fSUB = 32.768
kHz (WTM7 = 1)
4
When Operated When Operated When Operated When Operated When Operated
5-bit counter
0H
Overflow
Start
Overflow
Count clock
Watch timer
interrupt INTWT
Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s)
Interval timer
interrupt INTWTI
Interval time
(T)
Remark
WTM0, WTM1
0.515625 s
0.5 s
0.5 s
INTWT
383
384
Configuration
Control register
How the counter operation is controlled, overflow time, and window open period are set by the option byte.
Table 11-2. Setting of Option Bytes and Watchdog Timer
Setting of Watchdog Timer
Bit 4 (WDTON)
Remark
WDCS2 to WDCS0 of
option byte (0080H)
fRL/2
Clock
input
controller
17-bit
counter
210/fRL to
217/fRL
Selector
Count clear
signal
WINDOW1 and WINDOW0
of option byte (0080H)
WDTON of option
byte (0080H)
Overflow
signal
Reset
output
controller
Window size
determination
signal
Internal bus
385
R/W
WDTE
Note The WDTE reset value differs depending on the WDTON setting value of the option byte (0080H). To
operate watchdog timer, set WDTON to 1.
WDTON Setting Value
1AH
9AH
Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. If the
source clock to the watchdog timer is stopped, however, an internal reset signal is
generated when the source clock to the watchdog timer resumes operation.
2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal
is generated. If the source clock to the watchdog timer is stopped, however, an internal
reset signal is generated when the source clock to the watchdog timer resumes operation.
3. The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)).
386
When the watchdog timer is used, its operation is specified by the option byte (0080H).
Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1
(the counter starts operating after a reset release) (for details, see CHAPTER 26).
WDTON
Counter operation disabled (counting stopped after reset), illegal access detection operation disabled
Counter operation enabled (counting started after reset), illegal access detection operation enabled
Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H) (for details, see
11.4.2 and CHAPTER 26).
Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (0080H) (for
details, see 11.4.3 and CHAPTER 26).
2.
3.
By writing ACH to WDTE after the watchdog timer starts counting and before the overflow time set by the
option byte, the watchdog timer is cleared and starts counting again.
4.
After that, write WDTE the second time or later after a reset release during the window open period. If WDTE
5.
If the overflow time expires without ACH written to WDTE, an internal reset signal is generated.
387
Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows
depending on the set value of bit 0 (LSROSC) of the option byte.
In HALT mode
In STOP mode
If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is not cleared to 0 but starts counting from the value at
which it was stopped.
If oscillation of the internal low-speed oscillator is stopped by setting LSRSTOP (bit 1 of the
internal oscillation mode register (RCM) = 1) when LSROSC = 0, the watchdog timer stops
operating. At this time, the counter is not cleared to 0.
5. The watchdog timer continues its operation during self-programming and EEPROM
emulation of the flash memory.
delayed. Set the overflow time and window size taking this delay into consideration.
11.4.2 Setting overflow time of watchdog timer
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer
starts counting again by writing ACH to WDTE during the window open period before the overflow time.
The following overflow time is set.
Table 11-3. Setting of Overflow Time of Watchdog Timer
WDCS2
WDCS1
WDCS0
11
12
13
14
15
16
17
Set the overflow time and window size taking this delay into
consideration.
Remarks 1. fRL: Internal low-speed oscillation clock frequency
2. ( ): fRL = 264 kHz (MAX.)
388
Overflow
time
Window close period (75%)
Window open
period (25%)
Caution The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the
overflow time regardless of the timing of the writing, and the watchdog timer starts counting
again.
The window open period to be set is as follows.
Table 11-4. Setting Window Open Period of Watchdog Timer
WINDOW1
WINDOW0
25%
50%
75%
100%
Set the overflow time and window size taking this delay into
consideration.
389
Remark If the overflow time is set to 210/fRL, the window close time and open time are as follows.
(when 2.7 V VDD 5.5 V)
Setting of Window Open Period
25%
50%
75%
100%
0 to 3.56 ms
0 to 2.37 ms
0 to 1.19 ms
None
3.56 to 3.88 ms
2.37 to 3.88 ms
1.19 to 3.88 ms
0 to 3.88 ms
390
Clock output
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 7
y = 4 to 7
38/44 pins:
48 pins:
Buzzer output
Prescaler
8
Selector
fPRS to fPRS/27
fSUB
Clock
controller
PCL/INTP6/P140
Output latch
(P140)
CLOE
CCS3
CCS2
CCS1
PM140
CCS0
391
Figure 12-2. Block Diagram of Clock Output/Buzzer Output Controller (78K0/KE2, 78K0/KF2)
fPRS
Prescaler
4
Selector
fPRS/210 to
fPRS/213
BUZ/BUSY0/INTP7/P141
Output latch
(P141)
BZOE
fSUB
BCS0, BCS1
Selector
fPRS to fPRS/27
Clock
controller
CLOE
BZOE
BCS1
BCS0
CLOE
CCS3
CCS2
PM141
CCS1
PCL/INTP6/P140
Output latch
(P140)
PM140
CCS0
Configuration
Clock output selection register (CKS)
Port mode register 14 (PM14)
Port register 14 (P14)
392
Figure 12-3. Format of Clock Output Selection Register (CKS) (48-pin products of 78K0/KC2, 78K0/KD2)
Address: FF40H
R/W
Symbol
<4>
CKS
CLOE
CCS3
CCS2
CCS1
CCS0
CLOE
CCS3
CCS2
CCS1
Note 1
CCS0
fPRS =
fPRS =
32.768 kHz
10 MHz
20 MHz
Note 2
fPRS
Setting
10 MHz
Note 3
prohibited
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
5 MHz
10 MHz
fPRS/2
2.5 MHz
5 MHz
fPRS/2
1.25 MHz
2.5 MHz
fPRS/2
625 kHz
1.25 MHz
fPRS/2
312.5 kHz
625 kHz
fPRS/2
156.25 kHz
312.5 kHz
fPRS/2
fSUB
Notes 1.
fPRS/2
78.125 kHz
32.768 kHz
156.25 kHz
Setting prohibited
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
VDD = 4.0 to 5.5 V: fPRS 20 MHz
VDD = 2.7 to 4.0 V: fPRS 10 MHz
VDD = 1.8 to 2.7 V: fPRS 5 MHz
2.
If the peripheral hardware clock operates on the internal high-speed oscillation clock when 1.8 V VDD
< 2.7 V, setting CCS3 = CCS2 = CCS1 = CCS0 = 0 (output clock of PCL: fPRS) is prohibited.
3.
Caution
393
Figure 12-4. Format of Clock Output Selection Register (CKS) (78K0/KE2, 78K0/KF2)
Address: FF40H
Symbol
CKS
R/W
<7>
<4>
BZOE
BCS1
BCS0
CLOE
CCS3
CCS2
CCS1
CCS0
BZOE
BCS1
BCS0
Note 1
fPRS = 10 MHz
0
0
1
1
0
1
0
1
fPRS/2
9.77 kHz
19.54 kHz
fPRS/2
11
4.88 kHz
9.77 kHz
fPRS/2
12
2.44 kHz
4.88 kHz
fPRS/2
13
1.22 kHz
2.44 kHz
CLOE
CCS3
fPRS = 20 MHz
10
CCS2
CCS1
Note 1
CCS0
fPRS
fSUB =
fPRS =
fPRS =
32.768 kHz
10 MHz
20 MHz
Note 2
Setting
10 MHz
prohibited
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
1
0
1
fPRS/2
5 MHz
10 MHz
fPRS/2
2.5 MHz
5 MHz
fPRS/2
1.25 MHz
2.5 MHz
fPRS/2
625 kHz
1.25 MHz
fPRS/2
312.5 kHz
625 kHz
156.25 kHz
312.5 kHz
78.125 kHz
156.25 kHz
fPRS/2
fPRS/2
fSUB
Notes 1.
Note 3
32.768 kHz
Setting prohibited
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
VDD = 4.0 to 5.5 V: fPRS 20 MHz
VDD = 2.7 to 4.0 V: fPRS 10 MHz
VDD = 1.8 to 2.7 V: fPRS 5 MHz
2.
If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (XSEL = 0)
when 1.8 V VDD < 2.7 V, setting CCS3 = CCS2 = CCS1 = CCS0 = 0 (output clock of PCL: fPRS) is
prohibited.
3.
394
Cautions 1. Set BCS1 and BCS0 when the buzzer output operation is stopped (BZOE = 0).
2. Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0).
Remarks 1. fPRS: Peripheral hardware clock frequency
2. fSUB: Subsystem clock frequency
(2) Port mode register 14 (PM14)
This register sets port 14 input/output in 1-bit units.
When using the P140/INTP6/PCL pin for clock output and the P141/INTP7/BUSY0/BUZ pin for buzzer output,
clear PM140 and PM141 and the output latches of P140 and P141 to 0.
PM14 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM14 to FFH.
Figure 12-5. Format of Port Mode Register 14 (PM14)
Address: FF2EH
R/W
Symbol
PM14
PM145
PM144
PM143
PM142
PM141
PM140
PM14n
Remark
The figure shown above presents the format of port mode register 14 of 78K0/KF2 products.
For the format of port mode register 14 of other products, see (1) Port mode registers
(PMxx) in 5.3 Registers Controlling Port Function.
395
The clock output controller is designed not to output pulses with a small width during output
enable/disable switching of the clock output. As shown in Figure 12-6, be sure to start output from the
low period of the clock (marked with * in the figure). When stopping output, do so after the high-level
period of the clock.
Figure 12-6. Remote Control Output Application Example
CLOE
*
Clock output
396
10-bit A/D
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 7
y = 4 to 7
38 pins:
4 ch
converter
6 ch
8 ch
44/48 pins: 8 ch
Voltage comparator
AVSS
Successive
approximation
register (SAR)
Controller
ADS2
ADS1
ADS0
ADCS
FR2
FR1
FR0
AVSS
INTAD
Tap selector
Selector
LV1
LV0
ADCE
Remark
397
AVREF
P-ch
ADCS
398
399
<7>
ADCS
R/W
5
FR2
Note 1
ADCS
4
FR1
FR0
Note 1
2
LV1
Note 1
Note 1
LV0
<0>
ADCE
ADCE
Notes 1.
Note 1
For details of FR2 to FR0, LV1, LV0, and A/D conversion, see Table 13-2 A/D Conversion Time
Selection.
2.
The operation of the comparator is controlled by ADCS and ADCE, and it takes 1 s from operation
start to operation stabilization. Therefore, when ADCS is set to 1 after 1 s or more has elapsed from
the time ADCE is set to 1, the conversion result at that time has priority over the first conversion
result. Otherwise, ignore data of the first conversion.
Table 13-1. Settings of ADCS and ADCE
ADCS
ADCE
400
Conversion
waiting
Conversion
operation
Conversion
stopped
ADCS
Note
Note To stabilize the internal circuit, the time from the rising of the ADCE bit to the falling of the ADCS bit must be
1 s or longer.
Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and LV0 to values
other than the identical data.
2. If data is written to ADM, a wait cycle is generated. Do not write data to ADM when the
peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 34 CAUTIONS FOR
WAIT.
401
Clock (fAD)
26.4 s
13.2 s
fPRS/12
35.2 s
17.6 s
8.8 s
fPRS/8
132/fPRS 66.0 s
26.4 s
13.2 s
6.6 s
fPRS/6
88/fPRS
44.0 s
17.6 s
8.8 s
FR2
FR1
FR0
LV1
LV0
fPRS = 2 MHz
176/fPRS
0
0
0
0
0
0
1
1
1
0
1
0
0
0
Conversion
fPRS = 5 MHz
66/fPRS
33.0 s
13.2 s
44/fPRS
22.0 s
8.8 s
Note
Note
Note
Note
Note
fPRS = 10 MHz
Note
Note
6.6 s
fPRS/3
Setting prohibited
fPRS/2
Setting prohibited
FR1
FR0
LV1
LV0
fPRS = 2 MHz
fPRS = 5 MHz
Conversion
fPRS =
Note 2
10 MHz
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
0
0
0
0
0
Note 2
fPRS =
Clock (fAD)
Note 1
20 MHz
24.0 s
fPRS/12
Note 1
320/fPRS
64.0 s
32.0 s
16.0 s
fPRS/8
240/fPRS
48.0 s
24.0 s
12.0 s
fPRS/6
160/fPRS
32.0 s
16.0 s
8.0 s
fPRS/4
120/fPRS 60.0 s
24.0 s
12.0 s
40.0 s
16.0 s
8.0 s
1
1
80/fPRS
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 1
Note 1
Note 1
Note 1
fPRS/2
Setting prohibited
Notes 1.
2.
402
ADCS
Sampling
timing
INTAD
Wait
periodNote
SAR
clear
Sampling
Sampling
Conversion time
Note For details of wait period, see CHAPTER 34 CAUTIONS FOR WAIT.
(2) 10-bit A/D conversion result register (ADCR)
This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time
A/D conversion ends, the conversion result is loaded from the successive approximation register. The higher 8
bits of the conversion result are stored in FF09H and the lower 2 bits are stored in the higher 2 bits of FF08H.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 13-6. Format of 10-Bit A/D Conversion Result Register (ADCR)
Address: FF08H, FF09H
FF09H
Symbol
FF08H
ADCR
Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of ADCR may
become undefined.
writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect
conversion result to be read.
2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the
peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 34 CAUTIONS FOR
WAIT.
403
R
5
ADCRH
Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of ADCRH may
become undefined.
writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect
conversion result to be read.
2. If data is read from ADCRH, a wait cycle is generated. Do not read data from ADCRH when
the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 34 CAUTIONS
FOR WAIT.
404
Products 38-pin
other than products
the right of KC2
R/W
Symbol
ADS
ADS2
ADS1
ADS0
KB2
ADS2
ADS1
ADS0
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
Note 1
Note 1
Note 1
Note 2
Note 2
Notes 1.
Setting permitted
2.
Setting prohibited
405
R/W
Symbol
ADPC
ADPC3
ADPC2
ADPC1
ADPC0
ADPC3
ADPC2
ADPC1
ADPC0
Products 38-pin
other than products
the right of KC2
KB2
Note 1
Note 1
Note 1
Note 2
Note 2
Notes 1.
Setting permitted
2.
Setting prohibited
Setting prohibited
Cautions 1. Set a channel to be used for A/D conversion in the input mode by using port mode register 2
(PM2).
2. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the
peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 34 CAUTIONS FOR
WAIT.
406
R/W
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
PM2n
Caution For the 38-pin products of 78K0/KC2, be sure to set bits 6 and 7 of PM2 to 1, and bits 6
and 7 of P2 to 0.
Remark
The format of port mode register 2 of 78K0/KB2 products is different from the above format. See
5.3 Registers Controlling Port Function (1) Port mode registers (PMxx).
ANI0/P20 to ANI7/P27 pins are as shown below depending on the settings of ADPC, ADS, and PM2.
Table 13-3. Setting Functions of ANI0/P20 to ANI7/P27 Pins
ADPC
Analog input selection
PM2
Input mode
Output mode
ADS
Selects ANI.
Selects ANI.
Setting prohibited
Input mode
Digital input
Output mode
Digital output
407
408
A/D converter
operation
Sampling
A/D conversion
Conversion
result
SAR Undefined
Conversion
result
ADCR
INTAD
A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM)
is reset (0) by software.
If a write operation is performed to the analog input channel specification register (ADS) during an A/D conversion
operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the
beginning.
Reset signal generation clears the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H.
13.4.2 Input voltage and conversion results
The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the theoretical
A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following
expression.
SAR = INT (
VAIN
AVREF
1024 + 0.5)
ADCR = SAR 64
or
(
ADCR
64
0.5)
where, INT( ):
AVREF
1024
VAIN < (
ADCR
64
+ 0.5)
AVREF
1024
VAIN:
AVREF:
409
Figure 13-12 shows the relationship between the analog input voltage and the A/D conversion result.
Figure 13-12. Relationship Between Analog Input Voltage and A/D Conversion Result
SAR
ADCR
1023
FFC0H
1022
FF80H
1021
FF40H
00C0H
0080H
0040H
0000H
1
1
3
2
5
3
2048 1024 2048 1024 2048 1024
Input voltage/AVREF
410
A/D conversion
ANIn
Rewriting ADS
ANIn
ANIn
ADCS = 0
ANIm
ANIm
Conversion is stopped
Conversion result immediately
before is retained
ADCR,
ADCRH
ANIn
ANIn
Stopped
Conversion result
immediately before
is retained
ANIm
INTAD
411
412
11
11
Overall
error
Digital output
Digital output
Ideal line
1/2LSB
Quantization error
1/2LSB
00
AVREF
00
Analog input
Analog input
AVREF
413
Full-scale error
Digital output (Lower 3 bits)
111
Ideal line
011
010
001
Zero-scale error
000
111
110
101
Ideal line
000
AVREF
AVREF3
AVREF2
AVREF1
AVREF
11
Digital output
Digital output
Ideal line
Differential
linearity error
Integral linearity
error
00
0
Analog input
00
0
AVREF
Analog input
AVREF
414
Conversion time
415
AVREF
ANI0 to ANI7
C = 100 to 1,000 pF
AVSS
VSS
416
A/D conversion
ADCR,
ADCRH
ANIn
ADS rewrite
(start of ANIm conversion)
ANIn
ANIn
ANIm
ANIn
ANIm
ANIm
ANIm
ADIF
417
C2
Table 13-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values)
AVREF
R1
C1
C2
8.1 k
8 pF
5 pF
31 k
8 pF
5 pF
381 k
8 pF
5 pF
Remarks 1. The resistance and capacitance values shown in Table 13-4 are not guaranteed values.
2. 78K0/KB2: n = 0 to 3, 38-pin products of the 78K0/KC2: n = 0 to 5, other products: n = 0 to 7
418
generator.
Maximum transfer rate: 625 kbps
Two-pin configuration
To enable
transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock
after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base
clock, the transmission circuit or reception circuit may not be initialized.
4. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1.
419
Configuration
Receive buffer register 0 (RXB0)
Receive shift register 0 (RXS0)
Transmit shift register 0 (TXS0)
Control registers
420
Filter
RXD0/
SI10/P11
Asynchronous serial
interface operation mode
register 0 (ASIM0)
fPRS/23
Asynchronous serial
interface reception error
status register 0 (ASIS0)
Baud rate
generator
INTSR0
Reception control
INTST0
Transmission control
Reception unit
fXCLK0
Internal bus
8-bit timer/
event counter
50 output
Baud rate
generator
7
TXD0/
SCK10/P10
Output latch
(P10)
Registers
Transmission unit
PM10
fPRS/25
Selector
fPRS/2
421
422
<7>
<6>
<5>
ASIM0
POWER0
TXE0
RXE0
PS01
PS00
CL0
SL0
POWER0
0
Note 1
Enables/disables transmission
Enables transmission.
RXE0
2.
TXE0
Notes 1.
Note 2
Enables/disables reception
Enables reception.
The input from the RXD0 pin is fixed to high level when POWER0 = 0.
Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0),
and receive buffer register 0 (RXB0) are reset.
423
Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2)
PS01
PS00
Transmission operation
Outputs 0 parity.
Reception as 0 parity
CL0
Reception operation
Note
SL0
Note If reception as 0 parity is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial
interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur.
Cautions 1. To start the transmission, set POWER0 to 1 and then set TXE0 to 1. To stop the transmission,
clear TXE0 to 0, and then clear POWER0 to 0.
2. To start the reception, set POWER0 to 1 and then set RXE0 to 1. To stop the reception, clear
RXE0 to 0, and then clear POWER0 to 0.
3. Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. If
POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started.
4. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0.
To enable
transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after
TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock,
the transmission circuit or reception circuit may not be initialized.
5. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1.
6. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits.
7. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with
number of stop bits = 1, and therefore, is not affected by the set value of the SL0 bit.
8. Be sure to set bit 0 to 1.
424
ASIS0
PE0
FE0
OVE0
PE0
If the parity of transmit data does not match the parity bit on completion of reception.
FE0
OVE0
If receive data is set to the RXB0 register and the next reception operation is completed before the
data is read.
Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of
asynchronous serial interface operation mode register 0 (ASIM0).
2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of
stop bits.
3. If an overrun error occurs, the next receive data is not written to receive buffer register 0
(RXB0) but discarded.
4. If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0 when the
peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 34 CAUTIONS FOR
WAIT.
425
BRGC0
TPS01
TPS00
MDL04
MDL03
MDL02
MDL01
MDL00
TPS01
TPS00
TM50 output
fPRS/2
fPRS = 5 MHz
Note 1
fPRS = 10 MHz
fPRS = 20 MHz
Note 2
1 MHz
2.5 MHz
5 MHz
10 MHz
fPRS/2
250 kHz
625 kHz
1.25 MHz
2.5 MHz
fPRS/2
62.5 kHz
156.25 kHz
312.5 kHz
625 kHz
MDL04
MDL03
MDL02
MDL01
MDL00
Setting prohibited
fXCLK0/8
fXCLK0/9
10
fXCLK0/10
26
fXCLK0/26
27
fXCLK0/27
28
fXCLK0/28
29
fXCLK0/29
30
fXCLK0/30
31
fXCLK0/31
Note 1. If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the fPRS
operating frequency varies depending on the supply voltage.
VDD = 4.0 to 5.5 V: fPRS 20 MHz
VDD = 2.7 to 4.0 V: fPRS 10 MHz
VDD = 1.8 to 2.7 V: fPRS 5 MHz
426
Note 2. Note the following points when selecting the TM50 output as the base clock.
Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion
operation (TMC501 = 1).
PWM mode (TMC506 = 1)
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty =
50%.
It is not necessary to enable (TOE50 = 1) TO50 output in any mode.
Cautions 1. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the
MDL04 to MDL00 bits.
2. Make sure that bit 7 (POWER0) of the ASIM0 register = 0 when rewriting the TPS01 and TPS00
bits.
3. The baud rate value is the output clock of the 5-bit counter divided by 2.
Remarks 1. fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits
2. fPRS:
3. k:
4. :
Dont care
R/W
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
PM1n
427
<7>
<6>
<5>
ASIM0
POWER0
TXE0
RXE0
PS01
PS00
CL0
SL0
POWER0
0
Note 1
TXE0
0
Notes 1.
2.
Enables/disables transmission
Disables transmission (synchronously resets the transmission circuit).
RXE0
0
Note 2
Enables/disables reception
Disables reception (synchronously resets the reception circuit).
The input from the RXD0 pin is fixed to high level when POWER0 = 0.
Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0),
and receive buffer register 0 (RXB0) are reset.
Caution Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation stop mode.
To start the communication, set POWER0 to 1, and then set TXE0 or RXE0 to 1.
Remark
To use the RxD0/SI10/P11 and TxD0/SCK10/P10 pins as general-purpose port pins, see CHAPTER 5
PORT FUNCTIONS.
428
0
1
TXE0
0
0
RXE0
PM10
P10
Note
Note
Note
PM11
Note
Note
P11
Note
Note
UART0
Pin Function
Operation
TxD0/SCK10/P10
RxD0/SI10/P11
Stop
SCK10/P10
SI10/P11
Reception
SCK10/P10
RxD0
Note
Transmission
TxD0
SI10/P11
Transmission/
TxD0
RxD0
reception
dont care
Bit 6 of ASIM0
RXE0:
Bit 5 of ASIM0
PM1:
P1:
429
Start
bit
D0
D1
D2
D3
D4
D5
D6
Parity
bit
D7
Stop bit
Character bits
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
2. Data length: 7 bits, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
Parity
Stop
3. Data length: 8 bits, Parity: None, Stop bit: 1 bit, Communication data: 87H
1 data frame
Start
430
D0
D1
D2
D3
D4
D5
D6
D7
Stop
Stop
Even parity
Transmission
Transmit data, including the parity bit, is controlled so that the number of bits that are 1 is even.
The value of the parity bit is as follows.
If transmit data has an odd number of bits that are 1: 1
If transmit data has an even number of bits that are 1: 0
Reception
The number of bits that are 1 in the receive data, including the parity bit, is counted. If it is odd, a
parity error occurs.
431
(c) Transmission
If bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and bit 6
(TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit
data to transmit shift register 0 (TXS0). The start bit, parity bit, and stop bit are automatically appended to
the data.
When transmission is started, the start bit is output from the TXD0 pin, and the transmit data is output
followed by the rest of the data in order starting from the LSB. When transmission is completed, the parity
and stop bits set by ASIM0 are appended and a transmission completion interrupt request (INTST0) is
generated.
Transmission is stopped until the data to be transmitted next is written to TXS0.
Figure 14-8 shows the timing of the transmission completion interrupt request (INTST0). This interrupt
occurs as soon as the last stop bit has been output.
Caution After transmit data is written to TXS0, do not write the next transmit data before the
transmission completion interrupt signal (INTST0) is generated.
Figure 14-8. Transmission Completion Interrupt Request Timing
1. Stop bit length: 1
TXD0 (output)
Start
D0
D1
D2
D6
D7
Parity
Start
D0
D1
D2
D6
D7
Parity
Stop
INTST0
TXD0 (output)
INTST0
432
Stop
(d) Reception
Reception is enabled and the RXD0 pin input is sampled when bit 7 (POWER0) of asynchronous serial
interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1.
The 5-bit counter of the baud rate generator starts counting when the falling edge of the RXD0 pin input is
detected. When the set value of baud rate generator control register 0 (BRGC0) has been counted, the
RXD0 pin input is sampled again (
in Figure 14-9). If the RXD0 pin is low level at this time, it is recognized
as a start bit.
When the start bit is detected, reception is started, and serial data is sequentially stored in receive shift
register 0 (RXS0) at the set baud rate. When the stop bit has been received, the reception completion
interrupt (INTSR0) is generated and the data of RXS0 is written to receive buffer register 0 (RXB0). If an
overrun error (OVE0) occurs, however, the receive data is not written to RXB0.
Even if a parity error (PE0) occurs while reception is in progress, reception continues to the reception
position of the stop bit, and an reception error interrupt (INTSR0) is generated after completion of reception.
INTSR0 occurs upon completion of reception and in case of a reception error.
Figure 14-9. Reception Completion Interrupt Request Timing
RXD0 (input)
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
INTSR0
RXB0
Cautions 1. If a reception error occurs, read asynchronous serial interface reception error status
register 0 (ASIS0) and then read receive buffer register 0 (RXB0) to clear the error flag.
Otherwise, an overrun error will occur when the next data is received, and the reception
error status will persist.
2. Reception is always performed with the number of stop bits = 1. The second stop bit
is ignored.
433
Cause
Parity error
The parity specified for transmission does not match the parity of the receive data.
Framing error
Overrun error
Reception of the next data is completed before data is read from receive buffer
register 0 (RXB0).
RXD0/SI10/P11
In
Internal signal A
Match detector
434
In
LD_EN
Internal signal B
fPRS/23
Selector
5-bit counter
fXCLK0
fPRS/25
8-bit timer/
event counter
50 output
Match detector
Remark
1/2
Baud rate
Bit 6 of ASIM0
RXE0:
Bit 5 of ASIM0
BRGC0:
435
fXCLK0
2k
[bps]
fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits of the BRGC0 register
k:
Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31)
Table 14-4. Set Value of TPS01 and TPS00
TPS01
TPS00
TM50 output
fPRS/2
fPRS = 5 MHz
Note 1
fPRS = 10 MHz
fPRS = 20 MHz
Note 2
1 MHz
2.5 MHz
5 MHz
10 MHz
fPRS/2
250 kHz
625 kHz
1.25 MHz
2.5 MHz
fPRS/2
62.5 kHz
156.25 kHz
312.5 kHz
625 kHz
Notes 1. If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
VDD = 4.0 to 5.5 V: fPRS 20 MHz
VDD = 2.7 to 4.0 V: fPRS 10 MHz
VDD = 1.8 to 2.7 V: fPRS 5 MHz
2. Note the following points when selecting the TM50 output as the base clock.
Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion
operation (TMC501 = 1).
PWM mode (TMC506 = 1)
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty =
50%.
It is not necessary to enable (TOE50 = 1) TO50 output in any mode.
(2) Error of baud rate
The baud rate error can be calculated by the following expression.
Error (%) =
1 100 [%]
Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the
reception destination.
2. Make sure that the baud rate error during reception satisfies the range shown in (4)
Permissible baud rate range during reception.
436
TPS00
[%]
TPS00
Value
[%]
TPS00
[%]
TPS00
Calculated ERR
Value
[%]
4800
2H
26
4808
0.16
3H
16
4883
1.73
9600
2H
13
9615
0.16
3H
9766
1.73
3H
16
9766
1.73
10400
2H
12
10417
0.16
2H
30
10417
0.16
3H
15
10417
0.16
3H
30
10417
0.16
19200
1H
26
19231
0.16
2H
16
19531
1.73
3H
19531
1.73
3H
16
19531
1.73
24000
1H
21
23810
0.79
2H
13
24038
0.16
2H
26
24038
0.16
3H
13
24038
0.16
31250
1H
16
31250
2H
10
31250
2H
20
31250
3H
10
31250
33660
1H
15
33333
0.79
2H
34722
3.34
2H
18
34722
3.34
3H
34722
3.34
38400
1H
13
38462
0.16
2H
39063
1.73
2H
16
39063
1.73
3H
39063
1.73
56000
1H
55556
0.79
1H
22
56818
1.46
2H
11
56818
1.46
2H
22
56818
1.46
62500
1H
62500
1H
20
62500
2H
10
62500
2H
20
62500
76800
1H
16
78125
1.73
2H
78125
1.73
2H
16
78125
1.73
115200
1H
11
113636 1.36
1H
22
113636 1.36
2H
11
113636 1.36
153600
1H
156250
1.73
1H
16
156250
1.73
2H
156250
1.73
312500
1H
312500
1H
16
312500
625000
1H
625000
Remark
TPS01, TPS00: Bits 7 and 6 of baud rate generator control register 0 (BRGC0) (setting of base clock
(fXCLK0))
k:
Value set by the MDL04 to MDL00 bits of BRGC0 (k = 8, 9, 10, ..., 31)
fPRS:
ERR:
437
Start bit
Bit 0
Bit 1
Bit 7
Stop bit
Parity bit
FL
1 data frame (11 FL)
Minimum permissible
data frame length
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmin
Maximum permissible
data frame length
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmax
As shown in Figure 14-12, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 0 (BRGC0) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
FL = (Brate)1
Brate: Baud rate of UART0
k:
FL:
438
k2
2k
FL =
21k + 2
2k
FL
Therefore, the maximum receivable baud rate at the transmission destination is as follows.
BRmax = (FLmin/11)1 =
22k
21k + 2
Brate
Similarly, the maximum permissible data frame length can be calculated as follows.
10
11
FLmax = 11 FL
FLmax =
21k 2
20k
k+2
2k
FL =
21k 2
2k
FL
FL 11
Therefore, the minimum receivable baud rate at the transmission destination is as follows.
BRmin = (FLmax/11)1 =
20k
21k 2
Brate
The permissible baud rate error between UART0 and the transmission destination can be calculated from the
above minimum and maximum baud rate expressions, as follows.
Table 14-6. Maximum/Minimum Permissible Baud Rate Error
Division Ratio (k)
+3.53%
3.61%
16
+4.14%
4.19%
24
+4.34%
4.38%
31
+4.44%
4.47%
Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock
frequency, and division ratio (k). The higher the input clock frequency and the higher the division
ratio (k), the higher the permissible error.
2. k: Set value of BRGC0
439
generator.
Maximum transfer rate: 625 kbps
Two-pin configuration
To enable
transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock
after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set within two clocks of the
base clock, the transmission circuit or reception circuit may not be initialized.
5. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1.
6. If data is continuously transmitted, the communication timing from the stop bit to the next
start bit is extended two operating clocks of the macro. However, this does not affect the
result of communication because the reception side initializes the timing when it has
detected a start bit. Do not use the continuous transmission function if the interface is
used in LIN communication operation.
440
Remark
LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication
protocol intended to aid the cost reduction of an automotive network.
LIN communication is single-master communication, and up to 15 slaves can be connected to one
master.
The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the
LIN master via the LIN network.
Normally, the LIN master is connected to a network such as CAN (Controller Area Network).
In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that
complies with ISO9141.
In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and
corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave
is 15% or less.
Figures 15-1 and 15-2 outline the transmission and reception operations of LIN.
Figure 15-1. LIN Transmission Operation
Wakeup
signal frame
Sync
break field
Sync field
Identifier
field
Data field
Data field
Checksum
field
LIN Bus
8 bits
Note 1
13-bitNote 2 SBF
transmission
55H
Data
Data
Data
Data
transmission transmission transmission transmission transmission
TX6
(output)
INTST6Note 3
Notes 1.
2.
The wakeup signal frame is substituted by 80H transmission in the 8-bit mode.
The sync break field is output by hardware. The output width is the bit length set by bits 4 to 2 (SBL62
to SBL60) of asynchronous serial interface control register 6 (ASICL6) (see 15.4.2 (2) (h)
SBF
transmission).
3.
Remark
INTST6 is output on completion of each transmission. It is also output when SBF is transmitted.
The interval between each field is controlled by software.
441
Sync
break field
Sync field
Identifier
field
Data field
13-bit
SBF reception
SF
reception
ID
reception
Data
reception
Data
reception
LIN Bus
<5>
<2>
RXD6
(input)
Disable
Data
reception
Enable
<3>
Reception interrupt
(INTSR6)
<1>
Edge detection
(INTP0)
<4>
Capture timer
Disable
Enable
suppressed, and error detection processing of UART communication and data transfer of the shift register
and RXB6 is not performed. The shift register holds the reset value FFH.
<4> Calculate the baud rate error from the bit interval of the sync field, disable UART6 after SF reception, and
then re-set baud rate generator control register 6 (BRGC6).
<5> Distinguish the checksum field by software. Also perform processing by software to initialize UART6 after
reception of the checksum field and to set the SBF reception mode again.
Figure 15-3 shows the port configuration for LIN reception operation.
The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt
(INTP0). The length of the sync field transmitted from the LIN master can be measured using the external event
capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated.
The input source of the reception port input (RXD6) can be input to the external interrupt (INTP0) and 16-bit
timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RXD6 and INTP0/TI000 externally.
442
Port mode
(PM14)
Output latch
(P14)
Selector
Selector
P120/INTP0/EXLVI
INTP0 input
Port mode
(PM120)
Output latch
(P120)
Port input
switch control
(ISC0)
<ISC0>
0: Select INTP0 (P120)
1: Select RxD6 (P14)
Selector
Selector
P00/TI000
TI000 input
Port mode
(PM00)
Output latch
(P00)
Remark
Port input
switch control
(ISC1)
<ISC1>
0: Select TI000 (P00)
1: Select RxD6 (P14)
ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 15-11)
The peripheral functions used in the LIN communication operation are shown below.
<Peripheral functions used>
External interrupt (INTP0); wakeup signal detection
Use: Detects the wakeup signal edges and detects start of communication.
16-bit timer/event counter 00 (TI000); baud rate error detection
Use: Detects the baud rate error (measures the TI000 input edge interval in the capture mode) by detecting the
sync field (SF) length and divides it by the number of bits.
Serial interface UART6
Users Manual U18598EJ1V0UD
443
Configuration
Receive buffer register 6 (RXB6)
Receive shift register 6 (RXS6)
Transmit buffer register 6 (TXB6)
Transmit shift register 6 (TXS6)
Control registers
444
Filter
INTSR6
Reception control
Asynchronous serial
interface operation mode
register 6 (ASIM6)
Asynchronous serial
interface reception error
status register 6 (ASIS6)
fXCLK6
Baud rate
generator
Transmission control
Reception unit
Internal bus
Asynchronous serial
Clock selection
interface transmission
register 6 (CKSR6) status register 6 (ASIF6)
Baud rate
generator
INTST6
TXD6/
P13
Registers
Output latch
(P13)
Transmission unit
PM13
Selector
INTSRE6
fPRS
fPRS/2
fPRS/22
fPRS/23
fPRS/24
fPRS/25
fPRS/26
fPRS/27
fPRS/28
fPRS/29
fPRS/210
8-bit timer/
event counter
50 output
RXD6/
P14
445
446
ASIM6 can be refreshed (the same value is written) by software during a communication operation
(when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1).
Figure 15-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2)
Address: FF50H After reset: 01H R/W
Symbol
<7>
<6>
<5>
ASIM6
POWER6
TXE6
RXE6
PS61
PS60
CL6
SL6
ISRM6
POWER6
0
Note 1
Note 2
TXE6
Enables/disables transmission
Enables transmission
RXE6
Notes 1.
Enables/disables reception
Enables reception
The output of the TXD6 pin goes high level and the input from the RXD6 pin is fixed to the high level
when POWER6 = 0 during transmission.
2.
Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface
transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial
interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.
447
Figure 15-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2)
PS61
PS60
Transmission operation
Outputs 0 parity.
Reception as 0 parity
CL6
Note
SL6
ISRM6
Reception operation
INTSRE6 occurs in case of error (at this time, INTSR6 does not occur).
INTSR6 occurs in case of error (at this time, INTSRE6 does not occur).
Note If reception as 0 parity is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial
interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur.
Cautions 1. To start the transmission, set POWER6 to 1 and then set TXE6 to 1. To stop the transmission,
clear TXE6 to 0, and then clear POWER6 to 0.
2. To start the reception, set POWER6 to 1 and then set RXE6 to 1. To stop the reception, clear
RXE6 to 0, and then clear POWER6 to 0.
3. Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RXD6 pin. If
POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started.
4. TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6.
To enable
transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock
after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set within two clocks of the
base clock, the transmission circuit or reception circuit may not be initialized.
5. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1.
6. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.
7. Fix the PS61 and PS60 bits to 0 when used in LIN communication operation.
8. Clear TXE6 to 0 before rewriting the SL6 bit.
number of stop bits = 1, and therefore, is not affected by the set value of the SL6 bit.
9. Make sure that RXE6 = 0 when rewriting the ISRM6 bit.
448
ASIS6
PE6
FE6
OVE6
PE6
If the parity of transmit data does not match the parity bit on completion of reception
FE6
OVE6
If receive data is set to the RXB6 register and the next reception operation is completed before the
data is read.
Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of
asynchronous serial interface operation mode register 6 (ASIM6).
2. For the stop bit of the receive data, only the first stop bit is checked regardless of the number
of stop bits.
3. If an overrun error occurs, the next receive data is not written to receive buffer register 6
(RXB6) but discarded.
4. If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6 when the
peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 34 CAUTIONS FOR
WAIT.
449
ASIF6
TXBF6
TXSF6
TXBF6
If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6)
TXSF6
0
If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress)
Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.
Be sure to check that the TXBF6 flag is 0. If so, write the next transmit data (second byte)
to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is 1, the
transmit data cannot be guaranteed.
2. To initialize the transmission unit upon completion of continuous transmission, be sure to
check that the TXSF6 flag is 0 after generation of the transmission completion interrupt,
and then execute initialization. If initialization is executed while the TXSF6 flag is 1, the
transmit data cannot be guaranteed.
(4) Clock selection register 6 (CKSR6)
This register selects the base clock of serial interface UART6.
CKSR6 can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Remark
CKSR6 can be refreshed (the same value is written) by software during a communication operation
(when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1).
450
CKSR6
TPS63
TPS62
TPS61
TPS60
TPS63
TPS62
TPS61
TPS60
Note 2
fPRS
fPRS/2
Note 1
fPRS =
fPRS =
fPRS =
fPRS =
2 MHz
5 MHz
10 MHz
20 MHz
2 MHz
5 MHz
10 MHz
20 MHz
1 MHz
2.5 MHz
5 MHz
10 MHz
fPRS/2
500 kHz
1.25 MHz
2.5 MHz
5 MHz
fPRS/2
250 kHz
625 kHz
1.25 MHz
2.5 MHz
fPRS/2
125 kHz
fPRS/2
62.5 kHz
fPRS/2
fPRS/2
fPRS/2
fPRS/2
10
9.77 kHz
0
0
0
0
1
1
1
1
1
1
0
0
fPRS/2
TM50 output
Notes 1.
1.25 MHz
19.53 kHz
Note 3
Setting prohibited
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
VDD = 4.0 to 5.5 V: fPRS 20 MHz
VDD = 2.7 to 4.0 V: fPRS 10 MHz
VDD = 1.8 to 2.7 V: fPRS 5 MHz
2.
If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
= 0), when 1.8 V VDD < 2.7 V, the setting of TPS63 = TPS62 = TPS61 = TPS60 = 0 (base clock: fPRS)
is prohibited.
3.
Note the following points when selecting the TM50 output as the base clock.
Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 =
0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion
operation (TMC501 = 1).
PWM mode (TMC506 = 1)
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty
= 50%.
It is not necessary to enable (TOE50 = 1) TO50 output in any mode.
451
BRGC6 can be refreshed (the same value is written) by software during a communication operation
(when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1).
Figure 15-9. Format of Baud Rate Generator Control Register 6 (BRGC6)
BRGC6
MDL67
MDL66
MDL65
MDL64
MDL63
MDL62
MDL61
MDL60
MDL67
MDL66
MDL65
MDL64
MDL63
MDL62
MDL61
MDL60
Setting prohibited
fXCLK6/4
fXCLK6/5
fXCLK6/6
252
fXCLK6/252
253
fXCLK6/253
254
fXCLK6/254
255
fXCLK6/255
Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the
MDL67 to MDL60 bits.
2. The baud rate is the output clock of the 8-bit counter divided by 2.
Remarks 1. fXCLK6: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register
2. k: Value set by MDL67 to MDL60 bits (k = 4, 5, 6, ..., 255)
3. : Dont care
452
Note
Symbol
<7>
<6>
ASICL6
SBRF6
SBRT6
SBTT6
SBL62
SBL61
SBL60
DIR6
TXDLV6
SBRF6
SBRT6
0
1
SBTT6
453
Figure 15-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2)
SBL62
SBL61
SBL60
DIR6
First-bit specification
MSB
LSB
TXDLV6
Cautions 1. In the case of an SBF reception error, the mode returns to the SBF reception mode. The
status of the SBRF6 flag is held (1).
2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1.
After setting the SBRT6 bit to 1, do not clear it to 0 before SBF reception is completed (before
an interrupt request signal is generated).
3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF
reception has been correctly completed.
4. Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 =
1. After setting the SBTT6 bit to 1, do not clear it to 0 before SBF transmission is completed
(before an interrupt request signal is generated).
5. The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of
SBF transmission.
6. Do not set the SBRT6 bit to 1 during reception, and do not set the SBTT6 bit to 1 during
transmission.
7. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0.
454
R/W
Symbol
ISC
ISC1
ISC0
ISC1
TI000 (P00)
RXD6 (P14)
ISC0
INTP0 (P120)
RXD6 (P14)
R/W
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
PM1n
455
<7>
<6>
<5>
ASIM6
POWER6
TXE6
RXE6
PS61
PS60
CL6
SL6
ISRM6
POWER6
0
Note 1
Note 2
TXE6
0
Enables/disables transmission
Disables transmission operation (synchronously resets the transmission circuit).
RXE6
0
Notes 1.
Enables/disables reception
Disables reception (synchronously resets the reception circuit).
The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to high level when
POWER6 = 0 during transmission.
2.
Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface
transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial
interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.
Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to stop the operation.
To start the communication, set POWER6 to 1, and then set TXE6 or RXE6 to 1.
Remark
To use the RXD6/P14 and TXD6/P13 pins as general-purpose port pins, see CHAPTER 5
FUNCTIONS.
456
PORT
TXE6
RXE6
PM13
P13
Note
Note
Note
PM14
Note
Note
P14
Note
Note
UART6
Operation
TXD6/P13
Pin Function
Stop
P13
P14
Reception
P13
RXD6
RXD6/P14
Note
Transmission
TXD6
P14
Transmission/
reception
TXD6
RXD6
dont care
Bit 6 of ASIM6
RXE6:
Bit 5 of ASIM6
PM1:
P1:
457
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity
bit
Stop bit
D1
D0
Parity
bit
Stop bit
Character bits
2. MSB-first transmission/reception
1 data frame
Start
bit
D7
D6
D5
D4
D3
D2
Character bits
458
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H
1 data frame
Start
D7
D6
D5
D4
D3
D2
D1
D0
Parity
Stop
3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H, TXD6 pin
inverted output
1 data frame
Start
D7
D6
D5
D4
D3
D2
D1
D0
Parity
Stop
4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
Parity
Stop
Stop
5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Communication data: 87H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
D7
Stop
459
Even parity
Transmission
Transmit data, including the parity bit, is controlled so that the number of bits that are 1 is even.
The value of the parity bit is as follows.
If transmit data has an odd number of bits that are 1: 1
If transmit data has an even number of bits that are 1: 0
Reception
The number of bits that are 1 in the receive data, including the parity bit, is counted. If it is odd, a
parity error occurs.
460
TXD6 (output)
Start
D0
D1
D2
D6
D7
Parity
Start
D0
D1
D2
D6
D7
Parity
Stop
INTST6
TXD6 (output)
Stop
INTST6
461
combination of the TXBF6 and TXSF6 flags for judgment. Read only the TXBF6 flag
when executing continuous transmission.
2. When the device is use in LIN communication operation, the continuous transmission
function cannot be used. Make sure that asynchronous serial interface transmission
status register 6 (ASIF6) is 00H before writing transmit data to transmit buffer register 6
(TXB6).
TXBF6
Writing enabled
Writing disabled
Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.
Be sure to check that the TXBF6 flag is 0. If so, write the next transmit data (second byte)
to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is 1, the
transmit data cannot be guaranteed.
The communication status can be checked using the TXSF6 flag.
TXSF6
Transmission Status
Transmission is completed.
Transmission is in progress.
Cautions 1. To initialize the transmission unit upon completion of continuous transmission, be sure
to check that the TXSF6 flag is 0 after generation of the transmission completion
interrupt, and then execute initialization. If initialization is executed while the TXSF6
flag is 1, the transmit data cannot be guaranteed.
2. During continuous transmission, the next transmission may complete before execution
of INTST6 interrupt servicing after transmission of one data frame.
As a
462
Set registers.
Write TXB6.
Transfer
executed necessary
number of times?
Yes
No
Read ASIF6
TXBF6 = 0?
No
Yes
Write TXB6.
Transmission
completion interrupt
occurs?
No
Yes
Transfer
executed necessary
number of times?
Yes
No
Read ASIF6
TXSF6 = 0?
No
Yes
Yes of
Completion
transmission processing
Remark
TXB6:
463
Figure 15-17 shows the timing of starting continuous transmission, and Figure 15-18 shows the timing of
ending continuous transmission.
Figure 15-17. Timing of Starting Continuous Transmission
Start
TXD6
Data (1)
Parity
Stop
Start
Data (2)
Parity
Stop
Start
INTST6
TXB6
FF
TXS6
FF
Data (1)
Data (2)
Data (1)
Data (3)
Data (2)
Data (3)
TXBF6
Note
TXSF6
Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1. Therefore, judge whether
writing is enabled using only the TXBF6 bit.
Remark
TXD6:
TXS6:
ASIF6:
464
Stop
Start
Data (n 1)
Parity
Stop
Start
Data (n)
Parity
Stop
INTST6
TXB6
Data (n 1)
Data (n)
Data (n 1)
TXS6
Data (n)
FF
TXBF6
TXSF6
POWER6 or TXE6
Remark
TXD6:
INTST6:
TXB6:
TXS6:
ASIF6:
TXBF6:
Bit 1 of ASIF6
TXSF6:
Bit 0 of ASIF6
465
in Figure 15-19). If the RXD6 pin is low level at this time, it is recognized
as a start bit.
When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift
register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt
(INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun
error (OVE6) occurs, however, the receive data is not written to RXB6.
Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception
position of the stop bit, and a reception error interrupt (INTSR6/INTSRE6) is generated on completion of
reception.
Figure 15-19. Reception Completion Interrupt Request Timing
RXD6 (input)
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
INTSR6
RXB6
Cautions 1. If a reception error occurs, read ASIS6 and then RXB6 to clear the error flag. Otherwise,
an overrun error will occur when the next data is received, and the reception error
status will persist.
2. Reception is always performed with the number of stop bits = 1. The second stop bit
is ignored.
3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6)
before reading RXB6.
466
Cause
Parity error
The parity specified for transmission does not match the parity of the receive data.
Framing error
Overrun error
Reception of the next data is completed before data is read from receive buffer
register 6 (RXB6).
The reception error interrupt can be separated into reception completion interrupt (INTSR6) and error
interrupt (INTSRE6) by clearing bit 0 (ISRM6) of asynchronous serial interface operation mode register 6
(ASIM6) to 0.
Figure 15-20. Reception Error Interrupt
1. If ISRM6 is cleared to 0 (reception completion interrupt (INTSR6) and error interrupt (INTSRE6) are
separated)
(a) No error during reception
INTSR6
INTSR6
INTSRE6
INTSRE6
INTSR6
INTSR6
INTSRE6
INTSRE6
467
RXD6/P14
In
Internal signal A
In
Internal signal B
LD_EN
Match detector
LIN
Transmission Operation.
When bit 7 (POWER6) of asynchronous serial interface mode register 6 (ASIM6) is set to 1, the TXD6 pin
outputs high level. Next, when bit 6 (TXE6) of ASIM6 is set to 1, the transmission enabled status is entered,
and SBF transmission is started by setting bit 5 (SBTT6) of asynchronous serial interface control register 6
(ASICL6) to 1.
Thereafter, a low level of bits 13 to 20 (set by bits 4 to 2 (SBL62 to SBL60) of ASICL6) is output. Following
the end of SBF transmission, the transmission completion interrupt request (INTST6) is generated and
SBTT6 is automatically cleared. Thereafter, the normal transmission mode is restored.
Transmission is suspended until the data to be transmitted next is written to transmit buffer register 6 (TXB6),
or until SBTT6 is set to 1.
Figure 15-22. SBF Transmission
1
TXD6
10
11
12
INTST6
SBTT6
Remark
TXD6:
468
13
Stop
(i)
SBF reception
When the device is used in LIN communication operation, the SBF (Synchronous Break Field) reception
control function is used for reception. For the reception operation of LIN, see Figure 15-2 LIN Reception
Operation.
Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6
(ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SBRT6)
of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status,
the RXD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable
status.
When the start bit has been detected, reception is started, and serial data is sequentially stored in the
receive shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of SBF is
11 bits or more, a reception completion interrupt request (INTSR6) is generated as normal processing. At
this time, the SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of
errors, such as OVE6, PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status
register 6 (ASIS6)) is suppressed, and error detection processing of UART communication is not performed.
In addition, data transfer between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not
performed, and the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not
occur as error processing after the stop bit has been received, and the SBF reception mode is restored. In
this case, the SBRF6 and SBRT6 bits are not cleared.
Figure 15-23. SBF Reception
1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits)
1
RXD6
10
11
SBRT6
/SBRF6
INTSR6
2. SBF reception error (stop bit is detected with a width of 10.5 bits or less)
1
RXD6
10
SBRT6
/SBRF6
INTSR6
Remark
RXD6:
469
470
fPRS
fPRS/2
fPRS/22
fPRS/23
fPRS/24
fPRS/25
Selector
fPRS/26
8-bit counter
fXCLK6
fPRS/27
fPRS/28
fPRS/29
fPRS/210
8-bit timer/
event counter
50 output
Match detector
Remark
1/2
Baud rate
Bit 6 of ASIM6
RXE6:
Bit 5 of ASIM6
CKSR6:
BRGC6:
471
fXCLK6
2k
[bps]
fXCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register
k:
TPS62
TPS61
TPS60
fPRS
fPRS/2
fPRS/2
fPRS/2
fPRS =
5 MHz
Note 1
fPRS =
10 MHz
fPRS =
20 MHz
2 MHz
5 MHz
10 MHz
20 MHz
1 MHz
2.5 MHz
5 MHz
10 MHz
500 kHz
1.25 MHz
2.5 MHz
5 MHz
250 kHz
625 kHz
1.25 MHz
2.5 MHz
fPRS/2
125 kHz
fPRS/2
62.5 kHz
fPRS/2
1.25 MHz
fPRS/2
fPRS/2
9.77 kHz
fPRS/2
fPRS/2
10
Notes 1.
TM50 output
19.53 kHz
Note 3
Setting prohibited
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1),
the fPRS operating frequency varies depending on the supply voltage.
VDD = 4.0 to 5.5 V: fPRS 20 MHz
VDD = 2.7 to 4.0 V: fPRS 10 MHz
VDD = 1.8 to 2.7 V: fPRS 5 MHz
2.
If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH)
(XSEL = 0), when 1.8 V VDD < 2.7 V, the setting of TPS63 = TPS62 = TPS61 = TPS60 = 0 (base
clock: fPRS) is prohibited.
3.
Note the following points when selecting the TM50 output as the base clock.
Mode in which the count clock is cleared and started upon a match of TM50 and CR50
(TMC506 = 0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion
operation (TMC501 = 1).
PWM mode (TMC506 = 1)
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the
duty = 50%.
It is not necessary to enable (TOE50 = 1) TO50 output in any mode.
472
1 100 [%]
Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the
reception destination.
2. Make sure that the baud rate error during reception satisfies the range shown in (4)
Permissible baud rate range during reception.
Example: Frequency of base clock = 10 MHz = 10,000,000 Hz
Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33)
Target baud rate = 153600 bps
Baud rate = 10 M / (2 33)
= 10000000 / (2 33) = 151,515 [bps]
Error = (151515/153600 1) 100
= 1.357 [%]
(3) Example of setting baud rate
Table 15-5. Set Data of Baud Rate Generator
Baud
Rate
[bps]
TPS60
[%]
TPS60
Value
[%]
TPS60
[%]
TPS60
Calculated ERR
Value
[%]
300
8H
13
301
0.16
7H
65
301
0.16
8H
65
301
0.16
9H
65
301
0.16
600
7H
13
601
0.16
6H
65
601
0.16
7H
65
601
0.16
8H
65
601
0.16
1200
6H
13
1202
0.16
5H
65
1202
0.16
6H
65
1202
0.16
7H
65
1202
0.16
2400
5H
13
2404
0.16
4H
65
2404
0.16
5H
65
2404
0.16
6H
65
2404
0.16
4800
4H
13
4808
0.16
3H
65
4808
0.16
4H
65
4808
0.16
5H
65
4808
0.16
9600
3H
13
9615
0.16
2H
65
9615
0.16
3H
65
9615
0.16
4H
65
9615
0.16
19200
2H
13
19231
0.16
1H
65
19231
0.16
2H
65
19231
0.16
3H
65
19231
0.16
24000
1H
21
23810
0.79
3H
13
24038
0.16
4H
13
24038
0.16
5H
13
24038
0.16
31250
1H
16
31250
4H
31250
5H
31250
6H
31250
38400
1H
13
38462
0.16
0H
65
38462
0.16
1H
65
38462
0.16
2H
65
38462
0.16
48000
0H
21
47619
0.79
2H
13
48077
0.16
3H
13
48077
0.16
4H
13
48077
0.16
76800
0H
13
76923
0.16
0H
33
75758
1.36
0H
65
76923
0.16
1H
65
76923
0.16
115200
0H
111111 3.55
1H
11
113636 1.36
0H
43
116279
0.94
0H
87
114943 0.22
153600
1H
156250
1.73
0H
33
151515 1.36
1H
33
151515 1.36
312500
0H
312500
1H
312500
2H
312500
625000
0H
625000
1H
625000
2H
625000
Remark
TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (fXCLK6))
k:
Value set by MDL67 to MDL60 bits of baud rate generator control register 6
(BRGC6) (k = 4, 5, 6, ..., 255)
Peripheral hardware clock frequency
fPRS:
ERR:
Baud rate error
Users Manual U18598EJ1V0UD
473
Start bit
Bit 0
Bit 1
Bit 7
Stop bit
Parity bit
FL
1 data frame (11 FL)
Minimum permissible
data frame length
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmin
Maximum permissible
data frame length
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmax
As shown in Figure 15-25, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
FL = (Brate)1
Brate: Baud rate of UART6
k:
FL:
474
k2
2k
FL =
21k + 2
2k
FL
Therefore, the maximum receivable baud rate at the transmission destination is as follows.
22k
BRmax = (FLmin/11)1 =
Brate
21k + 2
Similarly, the maximum permissible data frame length can be calculated as follows.
10
11
FLmax = 11 FL
FLmax =
21k 2
20k
k+2
2k
FL =
21k 2
2k
FL
FL 11
Therefore, the minimum receivable baud rate at the transmission destination is as follows.
BRmin = (FLmax/11)1 =
20k
21k 2
Brate
The permissible baud rate error between UART6 and the transmission destination can be calculated from the
above minimum and maximum baud rate expressions, as follows.
Table 15-6. Maximum/Minimum Permissible Baud Rate Error
Division Ratio (k)
+2.33%
2.44%
+3.53%
3.61%
20
+4.26%
4.31%
50
+4.56%
4.58%
100
+4.66%
4.67%
255
+4.72%
4.73%
Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock
frequency, and division ratio (k). The higher the input clock frequency and the higher the division
ratio (k), the higher the permissible error.
2. k: Set value of BRGC6
475
1 data frame
Start bit
FL
Bit 0
Bit 1
Bit 7
FL
FL
FL
Parity bit
FL
Stop bit
FLstp
Start bit
FL
Bit 0
FL
Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK6, the following
expression is satisfied.
FLstp = FL + 2/fXCLK6
Therefore, the data frame length during continuous transmission is:
Data frame length = 11 FL + 2/fXCLK6
476
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 3
y = 4 to 7
y = 4 to 7
Serial interface
CSI10
Serial interface
CSI11
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
477
Configuration
Transmit controller
Controller
Registers
Control registers
Remark
n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than 32 KB
8
SI10/P11/RXD0
Transmit data
controller
PM10
Transmit buffer
register 10 (SOTB10)
Output
selector
SO10
output
SO10/P12
Output latch
(P12)
Output latch
PM12
Output latch
(P10)
478
Selector
Transmit controller
SCK10/P10/TxD0
fPRS/2
fPRS/22
fPRS/23
fPRS/24
fPRS/25
fPRS/26
fPRS/27
INTCSI10
SI11/P03
Transmit buffer
register 11 (SOTB11)
Transmit data
controller
Output
selector
SO11
output
SO11/P02
Output latch
(P02)
Output latch
SSI11
PM04
PM02
Output latch
(P04)
Transmit controller
fPRS/2
fPRS/22
fPRS/23
fPRS/24
fPRS/25
fPRS/26
fPRS/27
Selector
SCK11/P04
SSI11
INTCSI11
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
n = 0, 1: 78K0/KF2, 78K0/KE2 products whose flash memory is at least 48 KB
Users Manual U18598EJ1V0UD
479
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
Note 1
Symbol
<7>
CSIM10
CSIE10
TRMD10
DIR10
CSOT10
CSIE10
Disables operation
Enables operation
Note 4
TRMD10
0
Note 5
DIR10
3.
4.
5.
6.
Note 6
MSB
LSB
Communication is stopped.
Communication is in progress.
480
CSOT10
Notes 1.
2.
Note 3
Note 1
Symbol
<7>
CSIM11
CSIE11
TRMD11
SSE11
DIR11
CSOT11
CSIE11
Disables operation
Enables operation
Note 4
TRMD11
0
Note 5
SSE11
Notes 6, 7
Note 8
MSB
LSB
CSOT11
2.
Transmit/receive mode
DIR11
Notes 1.
Note 3
Communication is stopped.
Communication is in progress.
3.
Bit 0 (CSOT11) of CSIM11 and serial I/O shift register 11 (SIO11) are reset.
4.
5.
The SO11 output (see Figure 16-2) is fixed to the low level when TRMD11 is 0. Reception is started
when data is read from SIO11.
6.
7.
Before setting this bit to 1, fix the SSI11 pin input level to 0 or 1.
8.
481
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
n = 0, 1: 78K0/KF2, 78K0/KE2 products whose flash memory is at least 48 KB
Figure 16-5. Format of Serial Clock Selection Register 10 (CSIC10)
CSIC10
CKP10
DAP10
CKS102
CKS101
CKS100
CKP10
DAP10
SCK10
SO10
Type
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
D7 D6 D5 D4 D3 D2 D1 D0
CKS102
fPRS =
2 MHz
fPRS =
5 MHz
fPRS =
10 MHz
fPRS =
20 MHz
1 MHz
2.5 MHz
5 MHz
Setting
prohibited
fPRS/2
fPRS/2
500 kHz
1.25 MHz
2.5 MHz
5 MHz
fPRS/2
250 kHz
625 kHz
1.25 MHz
2.5 MHz
fPRS/2
125 kHz
312.5 kHz
625 kHz
1.25 MHz
62.5 kHz
1
1
0
1
fPRS/2
fPRS/2
fPRS/2
482
Mode
1.
Notes 1, 2
CKS100
Note
CKS101
Master mode
625 kHz
Note 3
156.25 kHz
Slave mode
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
VDD = 4.0 to 5.5 V: fPRS 20 MHz
VDD = 2.7 to 4.0 V: fPRS 10 MHz
VDD = 1.8 to 2.7 V: fPRS 5 MHz
Users Manual U18598EJ1V0UD
Notes 2.
3.
Standard Products
Do not start communication with the external clock from the SCK10 pin when the internal high-speed
oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem
clock, or when in the STOP mode.
483
CSIC11
CKP11
DAP11
CKS112
CKS111
CKS110
CKP11
DAP11
Type
1
SCK11
D7 D6 D5 D4 D3 D2 D1 D0
SO11
SI11 input timing
SCK11
D7 D6 D5 D4 D3 D2 D1 D0
SO11
SI11 input timing
1
SCK11
D7 D6 D5 D4 D3 D2 D1 D0
SO11
SI11 input timing
1
SCK11
D7 D6 D5 D4 D3 D2 D1 D0
SO11
SI11 input timing
CKS112
CKS111
Notes 1, 2
CKS110
fPRS =
2 MHz
500 kHz
1.25 MHz
2.5 MHz
5 MHz
fPRS/2
250 kHz
625 kHz
1.25 MHz
2.5 MHz
fPRS/2
125 kHz
312.5 kHz
625 kHz
1.25 MHz
fPRS/2
62.5 kHz
fPRS/2
1
0
fPRS/2
fPRS/2
Notes 1.
Setting
prohibited
fPRS/2
fPRS =
20 MHz
5 MHz
fPRS =
10 MHz
2.5 MHz
fPRS =
5 MHz
1 MHz
Mode
625 kHz
156.25 kHz
Note 3
484
Slave mode
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
VDD = 4.0 to 5.5 V: fPRS 20 MHz
2.
Master mode
Standard Products
Note
3.
Do not start communication with the external clock from the SCK11 pin when the internal high-speed
oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem
clock, or when in the STOP mode.
Symbol
PM0
PM0n
Remark
R/W
3
The figure shown above presents the format of port mode register 0 of 78K0/KF2
products. For the format of port mode register 0 of other products, see (1) Port
mode registers (PMxx) in 5.3 Registers Controlling Port Function.
R/W
3
PM1n
485
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
<7>
CSIM10
CSIE10
TRMD10
DIR10
CSOT10
CSIE10
0
Notes 1.
Disables operation
Note 2
To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIM10 in the default
status (00H).
2.
Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset.
<7>
CSIM11
CSIE11
TRMD11
SSE11
DIR11
CSOT11
CSIE11
0
Notes 1.
Disables operation
Note 2
2.
486
Bit 0 (CSOT11) of CSIM11 and serial I/O shift register 11 (SIO11) are reset.
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
487
The relationship between the register settings and pins is shown below.
Table 16-2. Relationship Between Register Settings and Pins (1/2)
(a) Serial interface CSI10
CSIE10 TRMD10 PM11
P11
PM12
P12
PM10
CSI10
P10
Pin Function
Operation
SI10/RXD0/ SO10/P12
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Stop
SCK10/
TXD0/P10
P11
RXD0/P11
P12
TXD0/
P10
Note 1
Note 1
Slave
reception
Note 1
Note 1
SI10
P12
Note 3
Slave
Note 3
RXD0/P11
SO10
Note 3
Slave
reception
Note 1
SCK10
Note 3
(input)
SI10
SO10
SCK10
Note 3
transmission/
Note 1
SCK10
(input)
transmission
1
Note 2
(input)
Note 3
Master reception
SI10
P12
SCK10
(output)
Note 1
Note 1
Master
RXD0/P11
SO10
transmission
1
Master
SI10
SO10
transmission/
reception
dont care
CSIE10:
TRMD10:
Bit 6 of CSIM10
CKP10:
488
PM1:
P1:
SCK10
(output)
SCK10
(output)
CSIE11 TRMD11 SSE11 PM03 P03 PM02 P02 PM04 P04 PM05 P05
Pin Function
Operation
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Stop
SI11/
SO11/
SCK11/
SSI11/
P03
P02
P04
TI001/P05
P03
P02
P04
Note 2
TI001/
P05
Note 1
Note 1
Note 1
Note 1
Slave
reception
SI11
P02
Note 3
SCK11
TI001/
(input)
P05
Note 3
1
1
Note 1
Note 1
Note 1
SSI11
Note 1
Slave
P03
SO11
Note 3
transmission
SCK11
TI001/
(input)
P05
Note 3
1
1
Note 1
SSI11
Note 1
Slave
SI11
SO11
transmission/
1
1
Note 1
Note 1
Note 1
reception
Note 1
Note 3
Master
Note 1
Note 1
Note 1
Master
Note 1
Master
P05
SSI11
SI11
P02
P03
SO11
transmission
Note 1
TI001/
(input)
Note 3
reception
Note 1
SCK11
SI11
SO11
transmission/
SCK11
TI001/
(output)
P05
SCK11
TI001/
(output)
P05
SCK11
TI001/
(output)
P05
reception
dont care
CSIE11:
TRMD11:
Bit 6 of CSIM11
CKP11:
P0:
489
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
490
SSI11Note
SCK1n
Read/write trigger
SOTB1n
SIO1n
ABH
56H
ADH
5AH
B5H
6AH
D5H
AAH
CSOT1n
INTCSI1n
CSIIF1n
SO1n
Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11, and are used in the slave
mode.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
491
SSI11Note
SCK1n
Read/write trigger
SOTB1n
SIO1n
ABH
56H
ADH
5AH
B5H
6AH
D5H
AAH
CSOT1n
INTCSI1n
CSIIF1n
SO1n
Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11, and are used in the slave
mode.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
492
SCK1n
SI1n capture
SO1n
Writing to SOTB1n or
reading from SIO1n
CSIIF1n
D7
D6
D5
D4
D3
D2
D1
D0
CSOT1n
SCK1n
SI1n capture
SO1n
Writing to SOTB1n or
reading from SIO1n
CSIIF1n
D7
D6
D5
D4
D3
D2
D1
D0
CSOT1n
SCK1n
SI1n capture
SO1n
Writing to SOTB1n or
reading from SIO1n
CSIIF1n
D7
D6
D5
D4
D3
D2
D1
D0
CSOT1n
SCK1n
SI1n capture
SO1n
Writing to SOTB1n or
reading from SIO1n
CSIIF1n
D7
D6
D5
D4
D3
D2
D1
D0
CSOT1n
Remarks 1. n = 0: 78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
n = 0, 1: 78K0/KF2, 78K0/KE2 products whose flash memory is at least 48 KB
2. The above figure illustrates a communication operation where data is transmitted with the MSB first.
493
SCK1n
Writing to SOTB1n or
reading from SIO1n
SOTB1n
SIO1n
Output latch
First bit
SO1n
2nd bit
SCK1n
Writing to SOTB1n or
reading from SIO1n
SOTB1n
SIO1n
Output latch
SO1n
First bit
2nd bit
The first bit is directly latched by the SOTB1n register to the output latch at the falling (or rising) edge of SCK1n,
and output from the SO1n pin via an output selector. Then, the value of the SOTB1n register is transferred to the
SIO1n register at the next rising (or falling) edge of SCK1n, and shifted one bit. At the same time, the first bit of
the receive data is stored in the SIO1n register via the SI1n pin.
The second and subsequent bits are latched by the SIO1n register to the output latch at the next falling (or rising)
edge of SCK1n, and the data is output from the SO1n pin.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
494
SCK1n
Writing to SOTB1n or
reading from SIO1n
SOTB1n
SIO1n
Output latch
SO1n
First bit
2nd bit
3rd bit
SCK1n
Writing to SOTB1n or
reading from SIO1n
SOTB1n
SIO1n
Output latch
SO1n
First bit
2nd bit
3rd bit
The first bit is directly latched by the SOTB1n register at the falling edge of the write signal of the SOTB1n
register or the read signal of the SIO1n register, and output from the SO1n pin via an output selector. Then, the
value of the SOTB1n register is transferred to the SIO1n register at the next falling (or rising) edge of SCK1n, and
shifted one bit. At the same time, the first bit of the receive data is stored in the SIO1n register via the SI1n pin.
The second and subsequent bits are latched by the SIO1n register to the output latch at the next rising (or falling)
edge of SCK1n, and the data is output from the SO1n pin.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
495
SCK1n
( Next request is issued.)
Writing to SOTB1n or
reading from SIO1n
SOTB1n
SIO1n
Output latch
Last bit
SO1n
SCK1n
Writing to SOTB1n or
reading from SIO1n
SOTB1n
SIO1n
Output latch
SO1n
Remark n = 0:
Last bit
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
496
SCK1n
Writing to SOTB1n or
reading from SIO1n
SOTB1n
SIO1n
Output latch
SO1n
Last bit
SCK1n
Writing to SOTB1n or
reading from SIO1n
SOTB1n
SIO1n
Output latch
SO1n
Remark n = 0:
Last bit
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
497
DIR1n
DAP1n = 0
Note 2
TRMD1n = 1
Note 1
DAP1n
SO1n Output
Note 2
(low-level output)
DAP1n = 1
Notes 1.
DIR1n = 0
DIR1n = 1
The actual output of the SO10/P12 or SO11/P02 pin is determined according to PM12 and P12
or PM02 and P02, as well as the SO1n output.
2.
Caution If a value is written to TRMD1n, DAP1n, and DIR1n, the output value of SO1n changes.
Remark n = 0:
78K0/KB2, 78K0/KC2, 78K0/KD2, 78K0/KE2 products whose flash memory is less than
32 KB
498
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 7
y = 4 to 7
Serial interface
CSIA0
499
Strobe output
Configuration
Controller
Registers
Control registers
500
Buffer RAM
Automatic data
transfer address
point specification
register 0 (ADTP0)
Automatic data
transfer address
count register 0
(ADTC0)
Internal bus
ATE0
Serial trigger
register 0 (CSIT0)
DIR0
ATM0
Serial I/O shift
register 0 (SIOA0)
SIA0/P143
ATSTP0 ATSTA0
RXAE0
SOA0/P144
Serial status
register 0 (CSIS0)
P144
STB0/P145
PM145
Serial clock
counter
P145
Interrupt
generator
INTACSI
4
Serial transfer
controller
BUSY0/P141
SCKA0/P142
PM142
P142
Selector
fW/6 to fW/32
Automatic data
transfer interval
specification
register 0 (ADTI0)
Baud rate
generator
fW
Selector
TXAE0
PM144
MASTER0
CKS000
6-bit counter
fPRS
fPRS/2
Divisor selection
register 0
(BRGCA0)
501
communication. In addition, after a communication completion interrupt request (INTACSI) is output (bit 0
(TSF0) of serial status register 0 (CSIS0) = 0), data can be received by reading data from SIOA0.
This register can be written or read by an 8-bit memory manipulation instruction. However, writing to SIOA0
is prohibited when bit 0 (TSF0) of serial status register 0 (CSIS0) = 1.
Reset signal generation clears this register to 00H.
Cautions 1. A communication operation is started by writing to SIOA0.
Consequently, when
transmission is disabled (bit 3 (TXEA0) of CSIMA0 = 0), write dummy data to the SIOA0
register to start the communication operation, and then perform a receive operation.
2. Do not write data to SIOA0 while the automatic transmit/receive function is operating.
502
Symbol
< >
CSIMA0
CSIAE0
ATE0
CSIAE0
R/W
ATM0
MASTER0
< >
< >
TXEA0
RXEA0
DIR0
CSIA0 operation disabled (SOA0: Low level, SCKA0: High level) and
asynchronously resets the internal circuitNote 1.
ATE0
ATM0
Single transfer mode (stops at the address specified by the ADTP0 register)
Repeat transfer mode (after transfer is complete, clear the ADTC0 register to 00H to resume transfer)
MASTER0
TXEA0
0
RXEA0
0
DIR0
0
MSB
LSB
Notes 1.
Automatic data transfer address count register 0 (ADTC0), serial trigger register 0 (CSIT0), serial
2.
Do not start communication with the external clock from the SCKA0 pin when the internal high-
I/O shift register 0 (SIOA0), and bit 0 (TSF0) of serial status register 0 (CSIS0) are reset.
speed oscillation clock and high-speed system clock are stopped while the CPU operates with the
subsystem clock, or when in the STOP mode.
Cautions 1. When CSIAE0 = 0, the buffer RAM cannot be accessed.
2. When CSIAE0 is changed from 1 to 0, the registers and bits mentioned in Note above
are asynchronously initialized. To set CSIAE0 = 1 again, be sure to re-set the initialized
registers.
3. When CSIAE0 is re-set to 1 after CSIAE0 is changed from 1 to 0, it is not guaranteed that
the value of the buffer RAM will be retained.
503
R/WNote 1
Symbol
CSIS0
CKS00
STBE0
BUSYE0
BUSYLV0
ERRE0
ERRF0
TSF0
CKS00
fPRS = 2 MHz
fPRS = 5 MHz
fPRS = 10 MHz
fPRS = 20 MHz
fPRSNote 3
2 MHz
5 MHz
10 MHz
20 MHz
fPRS/2
1 MHz
2.5 MHz
5 MHz
10 MHz
STBE0Notes 4, 5
BUSYE0
Busy signal detection enabled and communication wait by busy signal is executed
BUSYLV0Note 6
Notes 1.
2.
Low level
High level
3.
If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
4.
5.
When STBE0 is set to 1, two transfer clocks are consumed between byte transfers regardless of the
= 0), when 1.8 V VDD < 2.7 V, the setting of CKS00 = 0 (base clock: fPRS) is prohibited.
setting of automatic data transfer interval specification register 0 (ADTI0). That is, 10 transfer clocks
are used for 1-byte transfer if ADTI0 = 00H is set.
6.
504
In bit error detection by busy input, the active level specified by BUSYLV0 is detected.
Caution
Remark
ERRF0
Bit error detected (when ERRE0 = 1, the level specified by BUSYLV0 during the data bit transfer
period is detected via BUSY0 pin input).
TSF0
During transfer (TSF0 = 1), rewriting serial operation mode specification register 0 (CSIMA0),
serial status register 0 (CSIS0), divisor selection register 0 (BRGCA0), automatic data transfer
address point specification register 0 (ADTP0), automatic data transfer interval specification
register 0 (ADTI0), and serial I/O shift register 0 (SIOA0) are prohibited.
However, these
registers can be read and re-written to the same value. In addition, the buffer RAM can be
rewritten during transfer.
505
R/W
Symbol
<1>
<0>
CSIT0
ATSTP0
ATSTA0
ATSTP0
ATSTA0
Cautions 1. Even if ATSTP0 or ATSTA0 is set to 1, automatic transfer cannot be started/stopped until 1byte transfer is complete.
2. ATSTP0 and ATSTA0 change to 0 automatically after the interrupt signal INTACSI is
generated.
3. After automatic data transfer is stopped, the data address when the transfer stopped is
stored in automatic data transfer address count register 0 (ADTC0). However, since no
function to restart automatic data transfer is incorporated, when transfer is stopped by
setting ATSTP0 = 1, start automatic data transfer by setting ATSTA0 to 1 after re-setting the
registers.
506
R/W
Symbol
BRGCA0
BRGCA01
BRGCA00
BRGCA01
BRGCA00
fW/6
3
fW/2
fW/24
fW/2
166.67 kHz 333.3 kHz 416.67 kHz 833.33 kHz 1.67 MHz
Setting prohibited
125 kHz
250 kHz
Setting prohibited
62.5 kHz
125 kHz
1.25 MHz
1.25 MHz
Base clock frequency selected by CKS00 bit of CSIS0 register (fPRS or fPRS/2)
507
R/W
Symbol
ADTP0
ADTP04
ADTP03
ADTP02
ADTP01
ADTP00
Caution
The relationship between transfer end buffer RAM address values and ADTP0 setting values is shown below.
Table 17-2. Relationship Between Transfer End Buffer RAM Address Values and ADTP0 Setting Values
Transfer End Buffer RAM
Address Value
FAxxH
xxH
Remark
508
xx: 00 to 1F
R/W
Symbol
ADTI0
ADTI05
ADTI04
ADTI03
ADTI02
ADTI01
ADTI00
Caution
Because the setting of bit 5 (STBE0) and bit 4 (BUSYE0) of serial status register 0 (CSIS0) takes
priority over the ADTI0 setting, the interval time based on the setting of STBE0 and BUSYE0 is
generated even when ADTI0 is cleared to 00H.
Example Interval time when ADTI0 = 00H and busy signal is not generated
<1> When STBE0 = 1, BUSYE0 = 0: Interval time of two serial clocks is generated
<2> When STBE0 = 0, BUSYE0 = 1: Interval time of one serial clock is generated
<3> When STBE0 = 1, BUSYE0 = 1: Interval time of two serial clocks is generated
Therefore, clearing STBE0 and BUSYE0 to 0 is required to perform no-wait transfer.
The specified interval time is the serial clock (specified by divisor selection register 0 (BRGCA0)) multiplied by
an integer value.
Example When ADTI0 = 03H
SCKA0
509
Symbol
ADTC0
ADTC04
ADTC03
ADTC02
ADTC01
ADTP00
R/W
PM14
PM145
PM144
PM143
PM142
PM141
PM140
PM14n
510
Symbol
R/W
< >
CSIMA0
CSIAE0
CSIAE0
0
ATE0
ATM0
MASTER0
< >
< >
TXEA0
RXEA0
DIR0
511
Note 1
<3> Set bits 4 to 1 (MASTER0, TXEA0, RXEA0, and DIR0) of the CSIMA0 register (see Figure 17-2).
<4> Set bit 7 (CSIAE0) of the CSIMA0 register to 1 and clear bit 6 (ATE0) to 0.
<5> Write data to serial I/O shift register 0 (SIOA0). Data transmission/reception is startedNote 2.
Notes 1. This register does not have to be set when the slave mode is specified (MASTER0 = 0).
2. Write dummy data to SIOA0 only for reception.
Caution
Take relationship with the other party of communication when setting the port mode
register and port register.
512
The relationship between the register settings and pins is shown below.
Table 17-3. Relationship Between Register Settings and Pins
CSIAE0 ATE0
MASTER0 PM143
Note 1
P143
Note 1
PM144
Note 1
P144
Note 1
PM142
Note 1
P142
Note 1
Serial I/O
Serial Clock
Shift
Counter
SIA0/
SOA0/
SCKA0/
Register 0
Operation
P143
P144
P142
Operation
Control
Operation
Pin Function
Clear
P143
P144
P142
Operation
Count
SIA0Note 2
SOA0Note 3
SCKA0
enabled
operation
stopped
1
1Note 2
Note 2
0Note 3
0Note 3
(input)
SCKA0
(output)
dont care
CSIAE0:
ATE0:
Bit 6 of CSIMA0
P14:
513
SIA0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
SOA0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DI0
DO0
TSF0
ACSIIF
Transfer starts at falling edge of SCKA0
SIOA0 write
Caution
514
End of transfer
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SOA0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
SOA0
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
515
Read/write gate
Read/write gate
SOA0 latch
SIA0
SOA0
SCKA0
Start bit switching is realized by switching the bit order for data written to SIOA0. The SIOA0 shift order
remains unchanged.
Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift
register.
(d) Communication start
Serial communication is started by setting communication data to serial I/O shift register 0 (SIOA0) when
the following two conditions are satisfied.
Serial interface CSIA0 operation control bit (CSIAE0) = 1
Serial communication is not in progress
Caution
If CSIAE0 is set to 1 after data is written to SIOA0, communication does not start.
Upon termination of 8-bit communication, serial communication automatically stops and the interrupt
request flag (ACSIIF) is set.
516
A wait state may be generated when data is written to the buffer RAM. For details, see
CHAPTER 34 CAUTIONS FOR WAIT.
517
518
0
1
Notes 1.
Note 1
Note 1
Note 1
Note 1
0/1
0/1
0/1
Note 1
Note 1
Note 1
0
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Pin Function
SIA0/ SOA0/ SCKA0/ STB0/ BUSY0/
P143
P144
P142
P145
P141
P143
P144
P142
P145
P141
SCKA0 P145
(input)
P141
Note 2
SIA0
Note 3
SOA10
3.
Can be used as P144 when only reception is performed. Clear bit 3 (TXEA0) of CSIMA0 to 0.
dont care
CSIAE0:
ATE0:
Bit 6 of CSIMA0
BUSYE0:
Bit 4 of CSIS0
ERRE0:
Bit 2 of CSIS0
PM14:
P14:
2.
Remark
Serial Clock
Counter
Operation
Control
Take the relationship with the other communicating party into consideration when
setting the port mode register and port register.
Data
transmission/reception continues until the ADTC0 incremental output matches the set value of
automatic data transfer address point specification register 0 (ADTP0) (end of automatic
transmission/reception). However, if bit 5 (ATM0) of CSIMA0 is set to 1 (repeat mode), ADTC0 is
cleared after a match between ADTP0 and ADTC0, and then repeated transmission/reception is
started.
When automatic transmission/reception is terminated, an interrupt request (INTACSI) is generated and
bit 0 (TSF0) of CSIS0 is cleared.
To continue transmitting the next data, set the new data to the buffer RAM, and set number of data to
be transmitted 1 to ADTP0. After setting the number of data, set ATSTA0 to 1.
519
520
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SIA0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
ACSIIF
TSF0
Cautions 1. Because,
in
the
automatic
transmission/reception
mode,
the
automatic
transmit/receive function writes/reads data to/from the internal buffer RAM after 1byte
transmission/reception,
an
interval
is
inserted
until
the
next
Automatic
521
Set CSIAE0 to 1
Set ATSTA0 to 1
Transmission/reception
operation
Increment ADTC0
Hardware execution
Write receive data from
SIOA0 to internal buffer RAMNote
ADTP0 = ADTC0
No
Yes
TSF0 = 0
No
Software execution
Yes
End
CSIAE0:
ADTP0:
ADTI0:
ATSTA0:
SIOA0:
ADTC0:
TSF0:
Note A wait state may be generated when data is written to the buffer RAM.
CHAPTER 34 CAUTIONS FOR WAIT.
522
FA1FH
FA05H
SIOA0
ADTP0
ADTC0
ACSIIF
FA1FH
Data transmission
FA05H
ADTP0
ADTC0
ACSIIF
523
FA1FH
Data reception
FA05H
SIOA0
ADTP0
ADTC0
ACSIIF
+1
FA1FH
FA05H
SIOA0
ADTP0
ADTC0
ACSIIF
524
FA1FH
Data reception
FA05H
SIOA0
ADTP0
ADTC0
ACSIIF
+1
FA1FH
FA05H
SIOA0
ADTP0
Match
Receive data 3 (R3)
ADTC0
ACSIIF
SIOA0
ADTP0
ADTC0
ACSIIF
FA1FH
FA05H
525
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
ACSIIF
TSF0
526
Set CSIAE0 to 1
Set ATSTA0 to 1
Increment ADTC0
Transmission operation
Hardware execution
ADTP0 = ADTC0
No
Yes
TSF0 = 0
No
Software execution
Yes
End
CSIAE0:
ADTP0:
ADTI0:
ATSTA0:
SIOA0:
ADTC0:
TSF0:
Note A wait state may be generated when data is written to the buffer RAM.
527
Interval
SCKA0
SOA0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5
Cautions 1. Because, in the repeat transmission mode, a read is performed on the buffer RAM
after the transmission of one byte, the interval is included in the period up to the
next transmission. As the buffer RAM read is performed at the same time as CPU
processing, the interval is dependent upon automatic data transfer interval
specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0)
of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time).
2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer
RAM by serial interface CSIA0 during the interval period, the interval time specified
by automatic data transfer interval specification register 0 (ADTI0) may be extended.
528
Set CSIAE0 to 1
Set ATSTA0 to 1
Increment ADTC0
Transmission operation
Hardware execution
No
ADTP0 = ADTC0
Yes
Reset ADTC0 to 0
CSIAE0:
ADTP0:
ADTI0:
ATSTA0:
SIOA0:
ADTC0:
Note A wait state may be generated when data is written to the buffer RAM.
529
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SOA0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
530
SIA0
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
SOA0
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
Restart command
(after each register setting, ATSTA0 = 1)
SCKA0
SOA0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SIA0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
531
Slave device
SCKA
SIA
SOA
Busy output
The master device inputs the busy signal output by the slave device to the BUSY0/BUZ/INTP7/P141 pin.
The master device samples the input busy signal in synchronization with the falling of the serial clock.
Even if the busy signal becomes active while 8-bit data is being transmitted or received,
transmission/reception by the master is not kept waiting. If the busy signal is active at the rising edge of
the serial clock one clock after completion of transmission/reception of the 8-bit data, the busy input
becomes valid. After that, the master transmission/reception is kept waiting while the busy signal is
active.
The active level of the busy signal is set by bit 3 (BUSYLV0) of CSIS0.
BUSYLV0 = 1: Active-high
BUSYLV0 = 0: Active-low
When using the busy control option, select the master mode. Control with the busy signal cannot be
implemented in the slave mode.
Figure 17-24 shows the example of the operation timing when the busy control option is used.
Caution
Busy control cannot be used simultaneously with the interval time control function of
automatic data transfer interval specification register 0 (ADTI0).
532
Figure 17-24. Example of Operation Timing When Busy Control Option Is Used (When BUSYLV0 = 1)
SCKA0
SOA0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SIA0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
BUSY0
Wait
ACSIIF
Busy input released
Busy input valid
TSF0
Remark
When the busy signal becomes inactive, waiting is released. If the sampled busy signal is inactive,
transmission/reception of the next 8-bit data is started at the falling edge of the next serial clock.
Because the busy signal is asynchronous with the serial clock, it takes up to 1 clock until the busy signal
is sampled, even if made inactive by the slave. It takes 0.5 clock until data transfer is started after the
busy signal was sampled.
To accurately release the waiting, keep the busy signal inactive at the slave side, until SCKA0 falls.
Figure 17-25 shows the example of the timing of the busy signal and releasing the waiting. This figure
shows an example in which the busy signal is active as soon as transmission/reception has been started.
Figure 17-25. Busy Signal and Wait Release (When BUSYLV0 = 1)
SCKA0
SOA0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SIA0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
BUSY0
(active-high)
Wait
Busy input released
Busy input valid
533
The master device outputs the strobe signal from the STB0/P145 pin when 8-bit
transmission/reception has been completed. By this signal, the slave device can determine the timing of
the end of data transmission. Therefore, synchronization is established even if a bit shift occurs because
noise is superimposed on the serial clock, and transmission of the next byte is not affected by the bit
shift.
To use the strobe control option, the following conditions must be satisfied:
Bit 6 (ATE0) of the serial operation mode specification register 0 (CSIMA0) is set to 1.
Bit 5 (STBE0) of serial status register 0 (CSIS0) is set to 1.
Usually, the busy control and strobe control options are simultaneously used as handshake signals. In
this case, the strobe signal is output from the STB0/P145 pin, the BUSY0/BUZ/INTP7/P141 pin can be
sampled to keep transmission/reception waiting while the busy signal is input.
A high level lasting for one transfer clock is output from the STB0/P145 pin in synchronization with the
falling edge of the ninth serial clock as the strobe signal. The busy signal is detected at the rising edge of
the serial clock two clocks after 8-bit data transmission/reception completion.
Figure 17-26 shows the example of the operation timing when the busy & strobe control options are
used.
When the strobe control option is used, the interrupt request flag (ACSIIF) that is set on completion of
transmission/reception is set after the strobe signal is output.
Figure 17-26. Example of Operation Timing When Busy & Strobe Control Options Are Used
(When BUSYLV0 = 1)
SCKA0
SOA0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SIA0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
STB0
BUSY0
ACSIIF
Busy input released
Busy input valid
TSF0
Caution
Remark
534
SOA0
D7 D6 D5 D4 D3 D2 D1 D0
D7
D7 D6 D5 D4 D3 D2 D1
D0
SIA0
D7 D6 D5 D4 D3 D2 D1 D0
D7
D7 D6 D5 D4 D3 D2 D1
D0
BUSY0
ACSIIF
CSIAE0
ERRF0
Busy not detected
ACSIIF:
535
transmit/receive operation.
Since the read/write operations from/to the buffer RAM are performed in parallel with the CPU processing
when using the automatic transmit/receive function by the internal clock, the interval depends on the value
which is set in automatic data transfer interval specification register 0 (ADTI0) and bits 5 (STBE0) and 4
(BUSYE0) of serial status register 0 (CSIS0).
When ADTI0 is cleared to 00H, an interval time based on the to STBE0 and BUSYE0 settings is inserted. If
ADTI0 = 00H and STBE0 = BUSYE0 = 1, for example, then an interval time of two clocks is inserted, and the
interval time can be further extended by using an external busy signal. If an interval time of two clocks or
more is set by using ADTI0, then the interval time set by ADTI0 is inserted, regardless of the settings of
STBE0 and BUSYE0. When BUSYE0 = 1, the interval time can be further extended by an external busy
signal.
Example Interval time when ADTI0 = 00H and busy signal is not generated
<1> When STBE0 = 1, BUSYE0 = 0: Interval time of two serial clocks is generated
<2> When STBE0 = 0, BUSYE0 = 1: Interval time of one serial clock is generated
<3> When STBE0 = 1, BUSYE0 = 1: Interval time of two serial clocks is generated
Figure 17-28. Example of Interval Time for Automatic Transmission/Reception
(When ADTI0 = 00H, STBE0 = 1, BUSYE0 = 0 (Two Clocks))
Interval
SCKA0
SOA0
SIA0
D7 D6 D5 D4 D3 D2 D1
D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
ACSIIF
ACSIIF:
536
Caution
Do not use serial interface IIC0 and the multiplier/divider simultaneously, because various flags
corresponding to interrupt request sources are shared among serial interface IIC0 and the
multiplier/divider.
Remark
The multiplier/divider is mounted only onto the 78K0/Kx2 microcontroller products whose flash memory is
at least 48 KB.
537
Slave address
register 0 (SVA0)
SDA0/
P61
Noise
eliminator
IIC shift
register 0 (IIC0)
DFC0
PM61
Set
D Q
Stop
condition
generator
SO latch
CL01,
CL00
Data hold
time correction
circuit
TRC0
N-ch opendrain output
Start
condition
generator
Clear
Match
signal
ACK
generator
Output control
Output latch
(P61)
Wake-up
controller
ACK detector
Start condition
detector
Stop condition
detector
SCL0/
P60
Noise
eliminator
DFC0
Interrupt request
signal generator
Serial clock
counter
Serial clock
controller
Serial clock
wait controller
Output latch
(P60)
IICS0.MSTS0,
EXC0, COI0
IIC shift register 0 (IIC0)
IICC0.STT0, SPT0
IICS0.MSTS0, EXC0, COI0
fPRS
EXSCL0/
P62
CLX0
STCF
538
Bus status
detector
Prescaler
Remark
INTIIC0
The 78K0/KB2 products are not mounted with the EXSCL0 pin.
Master CPU1
SDA0
Slave CPU1
Address 0
SCL0
SDA0
Slave CPU2
SCL0
SDA0
SCL0
SDA0
SCL0
SDA0
SCL0
Master CPU2
Address 1
Slave CPU3
Address 2
Slave IC
Address 3
Slave IC
Address N
539
Configuration
Registers
Control registers
R/W
5
IIC0
R/W
5
540
0
0Note
SVA0
(3) SO latch
The SO latch is used to retain the SDA0 pins output level.
(4) Wake-up controller
This circuit generates an interrupt request (INTIIC0) when the address received by this register matches the
address value set to slave address register 0 (SVA0) or when an extension code is received.
(5) Prescaler
This selects the sampling clock to be used.
(6) Serial clock counter
This counter counts the serial clocks that are output or input during transmit/receive operations and is used to
verify that 8-bit data was transmitted or received.
(7) Interrupt request signal generator
This circuit controls the generation of interrupt request signals (INTIIC0).
An I2C interrupt request is generated by the following two triggers.
Falling edge of eighth or ninth clock of the serial clock (set by WTIM0 bit)
Interrupt request generated when a stop condition is detected (set by SPIE0 bit)
Remark
541
STT0 bit:
SPT0 bit:
STCF bit:
542
543
R/W
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
IICC0
IICE0
LREL0
WREL0
SPIE0
WTIM0
ACKE0
STT0
SPT0
IICE0
I C operation enable
Enable operation.
Note 1
Be sure to set this bit (1) while the SCL0 and SDA0 lines are at high level.
Condition for clearing (IICE0 = 0)
Cleared by instruction
Set by instruction
Reset
LREL0
Note 2
Normal operation
This exits from the current communications and sets standby mode. This setting is automatically cleared to 0
after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCL0 and SDA0 lines are set to high impedance.
The following flags of IIC control register 0 (IICC0) and IIC status register 0 (IICS0) are cleared to 0.
STT0 SPT0 MSTS0 EXC0 COI0 TRC0 ACKD0 STD0
The standby mode following exit from communications remains in effect until the following communications entry conditions
are met.
After a stop condition is detected, restart is in master mode.
An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL0 = 0)
Set by instruction
Reset
WREL0
Note 2
Wait cancellation
When WREL0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC0 = 1), the
SDA0 line goes into the high impedance state (TRC0 = 0).
Condition for clearing (WREL0 = 0)
Set by instruction
Reset
Notes 1. The IICS0 register, the STCF0 and IICBSY bits of the IICF0 register, and the CLD0 and DAD0 bits of the
IICCL0 register are reset.
2. This flags signal is invalid when IICE0 = 0.
Caution
The start condition is detected immediately after I2C is enabled to operate (IICE0 = 1) while the
SCL0 line is at high level and the SDA0 line is at low level. Immediately after enabling I2C to
operate (IICE0 = 1), set LREL0 (1) by using a 1-bit memory manipulation instruction.
544
SPIE0
Disable
Enable
Cleared by instruction
Set by instruction
Reset
Note 1
WTIM0
An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bit.
The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is inserted at the falling
edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the
falling edge of the ninth clock after an acknowledge (ACK) is issued. However, when the slave device has received an
extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIM0 = 0)
Cleared by instruction
Set by instruction
Reset
Notes 1, 2
ACKE0
Acknowledgment control
Disable acknowledgment.
Enable acknowledgment. During the ninth clock period, the SDA0 line is set to low level.
Cleared by instruction
Set by instruction
Reset
545
Note
Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when ACKE0 has
been cleared to 0 and slave has been notified of final reception.
For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1 during
the wait period that follows output of the ninth clock.
Cannot be set to 1 at the same time as SPT0.
Setting STT0 to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (STT0 = 0)
Set by instruction
reservation is prohibited.
Cleared by loss in arbitration
Cleared after start condition is generated by master device
Cleared by LREL0 = 1 (exit from communications)
When IICE0 = 0 (operation stop)
Reset
546
For master transmission: A stop condition cannot be generated normally during the acknowledge period. Therefore, set it
during the wait period that follows output of the ninth clock.
Cannot be set to 1 at the same time as STT0.
SPT0 can be set to 1 only when in master mode
Note
When WTIM0 has been cleared to 0, if SPT0 is set to 1 during the wait period that follows output of eight clocks, note that a
stop condition will be generated during the high-level period of the ninth clock. WTIM0 should be changed from 0 to 1 during
the wait period following the output of eight clocks, and SPT0 should be set to 1 during the wait period that follows the output
of the ninth clock.
Setting SPT0 to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (SPT0 = 0)
Set by instruction
Note Set SPT0 to 1 only in master mode. However, SPT0 must be set to 1 and a stop condition generated before
the first stop condition is detected following the switch to the operation enabled status. For details, see
18.5.15 Cautions.
Caution
When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set to 1 during the ninth
clock and wait is canceled, after which TRC0 is cleared and the SDA0 line is set to high
impedance.
Remark
547
If data is read from IICS0, a wait cycle is generated. Do not read data from IICS0 when the
peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 34 CAUTIONS FOR
WAIT.
Figure 18-6. Format of IIC Status Register 0 (IICS0) (1/3)
Address: FFAAH
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
IICS0
MSTS0
ALD0
EXC0
COI0
TRC0
ACKD0
STD0
SPD0
MSTS0
ALD0
This status means either that there was no arbitration or that the arbitration result was a win.
This status indicates the arbitration result was a loss. MSTS0 is cleared.
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other
than IICS0. Therefore, when using the ALD0 bit, read the data of this bit before the data of the other
bits.
Remark
548
Addresses match.
TRC0
Receive status (other than transmit status). The SDA0 line is set for high impedance.
Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at the
falling edge of the first bytes ninth clock).
<Master>
Note
(wait cancel)
<Master>
When 1 is output to the first bytes LSB (transfer
direction specification bit)
<Slave>
When a start condition is detected
When 0 is input to the first bytes LSB (transfer direction
specification bit)
<When not used for communication>
Note If the wait state is canceled by setting bit 5 (WREL0) of IIC control register 0 (IICC0) to 1 at the ninth
clock when bit 3 (TRC0) of IIC status register 0 (IICS0) is 1, TRC0 is cleared, and the SDA0 line goes
into a high-impedance state.
Remark
549
After the SDA0 line is set to low level at the rising edge of
STD0
Start condition was detected. This indicates that the address transfer period is in effect.
SPD0
Stop condition was detected. The master devices communication is terminated and the bus is released.
Remark
550
R/WNote
Symbol
<7>
<6>
<1>
<0>
IICF0
STCF
IICBSY
STCEN
IICRSV
STCF
Cleared by STT0 = 1
When IICE0 = 0 (operation stop)
Reset
IICBSY
0
STCEN
After operation is enabled (IICE0 = 1), enable generation of a start condition upon detection of
a stop condition.
After operation is enabled (IICE0 = 1), enable generation of a start condition without detecting
a stop condition.
Set by instruction
IICRSV
Cleared by instruction
Reset
Set by instruction
551
R/W
Note
Symbol
<5>
<4>
<3>
<2>
IICCL0
CLD0
DAD0
SMC0
DFC0
CL01
CL00
CLD0
DFC0
552
R/W
Symbol
<0>
IICX0
CLX0
1/fW
tR:
tF:
For example, the I2C transfer clock frequency (fSCL) when fW = fPRS/2 = 4.19 MHz, m = 86, tR = 200 ns, and tF =
50 ns is calculated using following expression.
fSCL = 1/(88 238.7 ns + 200 ns + 50 ns) 48.1 kHz
m T + tR + tF
tR
m/2 T
tF
m/2 T
SCL0
SCL0 inversion
SCL0 inversion
SCL0 inversion
553
The selection clock is set using a combination of bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock selection
register 0 (IICCL0) and bit 0 (CLX0) of IIC function expansion register 0 (IICX0).
Table 18-2. Selection Clock Setting
IICX0
Selection Clock
IICCL0
Transfer Clock
(fW/m)
(fW) Range
Notes 1, 2
(fW)
Operation Mode
Bit 0
Bit 3
Bit 1
Bit 0
CLX0
SMC0
CL01
CL00
fPRS/2
fW/44
Normal mode
fPRS/2
fW/86
(SMC0 bit = 0)
fPRS/4
fW/86
Notes 3, 4
fEXSCL0
fW/66
6.4 MHz
fPRS/2
fW/24
fPRS/4
fW/24
fEXSCL0
Setting prohibited
Note 3, 4
High-speed mode
(SMC0 bit = 1)
fW/18
6.4 MHz
fPRS/2
fW/12
fPRS/4
fW/12
Setting prohibited
High-speed mode
(SMC0 bit = 1)
Notes 1. If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the fPRS
operating frequency varies depending on the supply voltage.
VDD = 4.0 to 5.5 V: fPRS 20 MHz
VDD = 2.7 to 4.0 V: fPRS 10 MHz
VDD = 1.8 to 2.7 V: fPRS 5 MHz
2. If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fXH) (XSEL =
0), set CLX0, SMC0, CL01 and CL00 as follows.
IICX0
IICCL0
Selection Clock
Transfer Clock
Settable Selection
(fW)
(fW/m)
Bit 0
Bit 3
Bit 1
Bit 0
CLX0
SMC0
CL01
CL00
fPRS/2
fW/44
Operation Mode
Normal mode
(SMC0 bit = 0)
fPRS/2
fW/24
High-speed mode
(SMC0 bit = 1)
3. This must not be set, because the 78K0/KB2 products are not mounted with the EXSCL0 pin.
4. Do not start communication with the external clock from the EXSCL0 pin when the internal high-speed
oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem
clock, or when in the STOP mode.
Caution
Determine the transfer clock frequency of I2C by using CLX0, SMC0, CL01, and CL00 before
enabling the operation (by setting bit 7 (IICE0) of IIC control register 0 (IICC0) to 1). To change
the transfer clock frequency, clear IICE0 once to 0.
Remarks 1. :
554
dont care
2. fPRS:
3. fEXSCL0:
R/W
PM67
PM66
PM65
PM64
PM63
PM62
PM61
PM60
PM6n
Remark
The figure shown above presents the format of port mode register 6 of 78K0/KF2 products. For
the format of port mode register 6 of other products, see (1) Port mode registers (PMxx) in 5.3
Registers Controlling Port Function.
555
Master device
SCL0
SCL0
Clock output
(Clock output)
VDD
VSS
VSS
(Clock input)
Clock input
SDA0
SDA0
Data output
Data output
VSS
VSS
Data input
556
Data input
SCL0
1-7
1-8
1-8
ACK
Data
ACK
SDA0
Start
condition
Data
Stop
condition
The master device generates the start condition, slave address, and stop condition.
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device
that receives 8-bit data).
The serial clock (SCL0) is continuously output by the master device. However, in the slave device, the SCL0s low
level period can be extended and a wait can be inserted.
18.5.1 Start conditions
A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level.
The start conditions for the SCL0 pin and SDA0 pin are signals that the master device generates to the slave device
when starting a serial transfer. When the device is used as a slave, start conditions can be detected.
Figure 18-13. Start Conditions
SCL0
SDA0
A start condition is output when bit 1 (STT0) of IIC control register 0 (IICC0) is set (to 1) after a stop condition has
been detected (SPD0: Bit 0 = 1 in IIC status register 0 (IICS0)). When a start condition is detected, bit 1 (STD0) of
IICS0 is set (to 1).
557
18.5.2 Addresses
The address is defined by the 7 bits of data that follow the start condition.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to
the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique
address.
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address
data matches the data values stored in slave address register 0 (SVA0). If the address data matches the SVA0
values, the slave device is selected and communicates with the master device until the master device generates a
start condition or stop condition.
Figure 18-14. Address
SCL0
SDA0
A6
A5
A4
A3
A2
A1
A0
R/W
Address
Note
INTIIC0
Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device
operation.
The slave address and the eighth bit, which specifies the transfer direction as described in 18.5.3
Transfer
direction specification below, are together written to IIC shift register 0 (IIC0) and are then output. Received
addresses are written to IIC0.
The slave address is assigned to the higher 7 bits of IIC0.
18.5.3 Transfer direction specification
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction.
When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting
data to a slave device. When the transfer direction specification bit has a value of 1, it indicates that the master
device is receiving data from a slave device.
Figure 18-15. Transfer Direction Specification
SCL0
SDA0
A6
A5
A4
A3
A2
A1
A0
R/W
INTIIC0
Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device
operation.
558
SCL0
SDA0
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
When the local address is received, ACK is automatically generated, regardless of the value of ACKE0. When an
address other than that of the local address is received, ACK is not generated (NACK).
When an extension code is received, ACK is generated if ACKE0 is set to 1 in advance.
How ACK is generated when data is received differs as follows depending on the setting of the wait timing.
When 8-clock wait state is selected (bit 3 (WTIM0) of IICC0 register = 0):
By setting ACKE0 to 1 before releasing the wait state, ACK is generated at the falling edge of the eighth clock of
the SCL0 pin.
When 9-clock wait state is selected (bit 3 (WTIM0) of IICC0 register = 1):
ACK is generated by setting ACKE0 to 1 in advance.
559
SCL0
SDA0
A stop condition is generated when bit 0 (SPT0) of IIC control register 0 (IICC0) is set to 1. When the stop
condition is detected, bit 0 (SPD0) of IIC status register 0 (IICS0) is set to 1 and INTIIC0 is generated when bit 4
(SPIE0) of IICC0 is set to 1.
560
18.5.6 Wait
The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or
receive data (i.e., is in a wait state).
Setting the SCL0 pin to low level notifies the communication partner of the wait state. When wait state has been
canceled for both the master and slave devices, the next data transfer can begin.
Figure 18-18. Wait (1/2)
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
(master transmits, slave receives, and ACKE0 = 1)
Master
Master returns to high
impedance but slave
is in wait state (low level).
IIC0
SCL0
Slave
Wait after output
of eighth clock
FFH is written to IIC0 or WREL0 is set to 1
IIC0
SCL0
ACKE0
Transfer lines
Wait from slave
SCL0
SDA0
D2
D1
D0
ACK
D7
D6
D5
561
Master
IIC0
SCL0
Slave
FFH is written to IIC0 or WREL0 is set to 1
IIC0
SCL0
ACKE0
H
Wait from
master and
slave
Transfer lines
SCL0
SDA0
D2
D1
D0
ACK
D7
D6
D5
Remark
A wait may be automatically generated depending on the setting of bit 3 (WTIM0) of IIC control register 0 (IICC0).
Normally, the receiving side cancels the wait state when bit 5 (WREL0) of IICC0 is set to 1 or when FFH is written
to IIC shift register 0 (IIC0), and the transmitting side cancels the wait state when data is written to IIC0.
The master device can also cancel the wait state via either of the following methods.
By setting bit 1 (STT0) of IICC0 to 1
By setting bit 0 (SPT0) of IICC0 to 1
562
0
1
Notes 1, 2
Notes 1, 2
Data Reception
8
Note 2
Note 2
Data Transmission
Address
Data Reception
Data Transmission
Note 2
Note 2
Notes 1. The slave devices INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when
there is a match with the address set to slave address register 0 (SVA0).
At this point, ACK is generated regardless of the value set to IICC0s bit 2 (ACKE0). For a slave device
that has received an extension code, INTIIC0 occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIIC0 is generated at the falling edge of the 9th
clock, but wait does not occur.
2. If the received address does not match the contents of slave address register 0 (SVA0) and extension
code is not received, neither INTIIC0 nor a wait occurs.
Remark
The numbers in the table indicate the number of the serial clocks clock signals. Interrupt requests and
wait control are both synchronized with the falling edge of these clock signals.
563
Interrupt and wait timing are determined depending on the conditions described in
Notes 1 and 2 above, regardless of the WTIM0 bit.
Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
the WTIM0 bit.
(2) During data reception
Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
(3) During data transmission
Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
(4) Wait cancellation method
The four wait cancellation methods are as follows.
Writing data to IIC shift register 0 (IIC0)
Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait)
Setting bit 1 (STT0) of IIC0 register (generating start condition)Note
Setting bit 0 (SPT0) of IIC0 register (generating stop condition)
Note
564
COI0 = 1
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension
code, such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is received, if you do not wish to operate the target device as a slave
device, set bit 6 (LREL0) of the IIC control register 0 (IICC0) to 1 to set the standby mode for the next
communication operation.
Table 18-4. Extension Code Bit Definitions
Slave Address
R/W Bit
Description
0000 000
0000 000
Start byte
0000 001
C-BUS address
0000 010
1111 0XX
565
18.5.12 Arbitration
When several master devices simultaneously generate a start condition (when STT0 is set to 1 before STD0 is set
to 1), communication among the master devices is performed as the number of clocks are adjusted until the data
differs. This kind of operation is called arbitration.
When one of the master devices loses in arbitration, an arbitration loss flag (ALD0) in IIC status register 0 (IICS0)
is set (1) via the timing by which the arbitration loss occurred, and the SCL0 and SDA0 lines are both set to high
impedance, which releases the bus.
The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a
stop condition is detected, etc.) and the ALD0 = 1 setting that has been made by software.
For details of interrupt request timing, see 18.5.17 Timing of I2C interrupt request (INTIIC0) occurrence.
Remark
Master 1
Hi-Z
SCL0
Hi-Z
SDA0
Master 2
SCL0
SDA0
Transfer lines
SCL0
SDA0
566
Table 18-5. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration
Note 1
Note 1
condition
When stop condition is detected while attempting to generate a
Note 2
restart condition
When data is at low level while attempting to generate a stop
Note 1
condition
When SCL0 is at low level while attempting to generate a
restart condition
Notes 1. When WTIM0 (bit 3 of IIC control register 0 (IICC0)) = 1, an interrupt request occurs at the falling edge
of the ninth clock. When WTIM0 = 0 and the extension codes slave address is received, an interrupt
request occurs at the falling edge of the eighth clock.
2. When there is a chance that arbitration will occur, set SPIE0 = 1 for master device operation.
Remark
567
SMC0
CL01
CL00
Wait Period
46 clocks
86 clocks
172 clocks
34 clocks
30 clocks
60 clocks
12 clocks
18 clocks
36 clocks
568
Program processing
Write to
IIC0
STT0 = 1
SCL0
Set SPD0
and
INTIIC0
Set
STD0
SDA0
Remark
IIC0:
STT0:
STD0:
SCL0
SDA0
STD0
SPD0
Standby mode
569
DI
SET1 STT0
Define communication
reservation
Wait
(Communication reservation)Note
Yes
MSTS0 = 0?
No
(Generate start condition)
Cancel communication
reservation
MOV IIC0, #H
EI
Note The communication reservation operation executes a write to IIC shift register 0 (IIC0) when a stop
condition interrupt request occurs.
Remark
STT0:
(2) When communication reservation function is disabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 1)
When bit 1 (STT0) of IIC control register 0 (IICC0) is set to 1 when the bus is not used in a communication
during bus communication, this request is rejected and a start condition is not generated. The following two
statuses are included in the status where bus is not used.
When arbitration results in neither master nor slave operation
When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
released when bit 6 (LREL0) of IICC0 was set to 1)
To confirm whether the start condition was generated or request was rejected, check STCF (bit 7 of IICF0).
The time shown in Table 18-7 is required until STCF is set to 1 after setting STT0 = 1. Therefore, secure the
time by software.
570
CL00
Wait Period
6 clocks
6 clocks
12 clocks
3 clocks
18.5.15 Cautions
(1) When STCEN (bit 1 of IIC flag register 0 (IICF0)) = 0
Immediately after I2C operation is enabled (IICE0 = 1), the bus communication status (IICBSY (bit 6 of IICF0) =
1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition
has been detected to a master device communication mode, first generate a stop condition to release the bus,
then perform master device communication.
When using multiple masters, it is not possible to perform master device communication when the bus has not
been released (when a stop condition has not been detected).
Use the following sequence for generating a stop condition.
<1> Set IIC clock selection register 0 (IICCL0).
<2> Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1.
<3> Set bit 0 (SPT0) of IICC0 to 1.
(2) When STCEN = 1
Immediately after I2C operation is enabled (IICE0 = 1), the bus released status (IICBSY = 0) is recognized
regardless of the actual bus status. To generate the first start condition (STT0 (bit 1 of IIC control register 0
(IICC0)) = 1), it is necessary to confirm that the bus has been released, so as to not disturb other
communications.
(3) If other I2C communications are already in progress
If I2C operation is enabled and the device participates in communication already in progress when the SDA0
pin is low and the SCL0 pin is high, the macro of I2C recognizes that the SDA0 pin has gone low (detects a
start condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned,
but this interferes with other I2C communications. To avoid this, start I2C in the following sequence.
<1> Clear bit 4 (SPIE0) of IICC0 to 0 to disable generation of an interrupt request signal (INTIIC0) when the
stop condition is detected.
<2> Set bit 7 (IICE0) of IICC0 to 1 to enable the operation of I2C.
<3> Wait for detection of the start condition.
<4> Set bit 6 (LREL0) of IICC0 to 1 before ACK is returned (4 to 80 clocks after setting IICE0 to 1), to forcibly
disable detection.
(4) Determine the transfer clock frequency by using SMC0, CL01, CL00 (bits 3, 1, and 0 of IICL0), and CLX0 (bit 0
of IICX0) before enabling the operation (IICE0 = 1). To change the transfer clock frequency, clear IICE0 to 0
once.
571
(5) Setting STT0 and SPT0 (bits 1 and 0 of IICC0) again after they are set and before they are cleared to 0 is
prohibited.
(6) When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt request is generated when
the stop condition is detected. Transfer is started when communication data is written to IIC0 after the interrupt
request is generated. Unless the interrupt is generated when the stop condition is detected, the device stops
in the wait state because the interrupt request is not generated when communication is started. However, it is
not necessary to set SPIE0 to 1 when MSTS0 (bit 7 of IICS0) is detected by software.
18.5.16 Communication operations
The following shows three operation procedures with the flowchart.
(1) Master operation in single master system
The flowchart when using the 78K0/Kx2 microcontrollers as the master in a single master system is shown
below.
This flowchart is broadly divided into the initial settings and communication processing. Execute the initial
settings at startup. If communication with the slave is required, prepare the communication and then execute
communication processing.
(2) Master operation in multimaster system
In the I2C bus multimaster system, whether the bus is released or used cannot be judged by the I2C bus
specifications when the bus takes part in a communication. Here, when data and clock are at a high level for a
certain period (1 frame), the 78K0/Kx2 microcontrollers takes part in a communication with bus released state.
This flowchart is broadly divided into the initial settings, communication waiting, and communication processing.
The processing when the 78K0/Kx2 microcontrollers looses in arbitration and is specified as the slave is
omitted here, and only the processing as the master is shown. Execute the initial settings at startup to take
part in a communication. Then, wait for the communication request as the master or wait for the specification
as the slave. The actual communication is performed in the communication processing, and it supports the
transmission/reception with the slave and the arbitration with other masters.
(3) Slave operation
An example of when the 78K0/Kx2 microcontrollers is used as the I2C bus slave is shown below.
When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait
for the INTIIC0 interrupt occurrence (communication waiting).
communication status is judged and its result is passed as a flag over to the main processing.
By checking the flags, necessary communication processing is performed.
572
SVA0 XXH
IICF0 0XH
Setting STCEN, IICRSV = 0
Initial setting
IICC0 XXH
ACKE0 = WTIM0 = SPIE0 = 1
IICE0 = 1
Setting port
STCEN = 1?
Sets each pin in the I2C mode (see 18.3 (7) Port mode register 6 (PM6)).
Yes
No
SPT0 = 1
INTIIC0
Interrupt occurs?
No
Waits for detection of the stop condition.
Yes
STT0 = 1
Writing IIC0
Starts communication
(specifies an address and transfer
direction).
INTIIC0
interrupt occurs?
No
Waits for detection of acknowledge.
Yes
No
ACKD0 = 1?
Yes
TRC0 = 1?
No
ACKE0 = 1
WTIM0 = 0
Communication processing
Yes
Writing IIC0
Starts transmission.
WREL0 = 1
INTIIC0
interrupt occurs?
No
Waits for data transmission.
INTIIC0
interrupt occurs?
Yes
Yes
ACKD0 = 1?
No
Starts reception.
No
Waits for data
reception.
Reading IIC0
Yes
No
End of transfer?
No
End of transfer?
Yes
Yes
Restart?
Yes
ACKE0 = 0
WTIM0 = WREL0 = 1
No
SPT0 = 1
INTIIC0
interrupt occurs?
Yes
No
Waits for detection
of acknowledge.
END
2
Note Release (SCL0 and SDA0 pins = high level) the I C bus in conformance with the specifications of the
product that is communicating. If EEPROM is outputting a low level to the SDA0 pin, for example, set the
SCL0 pin in the output port mode, and output a clock pulse from the output port until the SDA0 pin is
constantly at high level.
Remark
Conform to the specifications of the product that is communicating, with respect to the transmission and
reception formats.
Users Manual U18598EJ1V0UD
573
SVA0 XXH
IICF0 0XH
Setting STCEN and IICRSV
Initial setting
IICC0 XXH
ACKE0 = WTIM0 = SPIE0 = 1
IICE0 = 1
Setting port
Sets each pin in the I2C mode (see 18.3 (7) Port mode register 6 (PM6)).
Bus status is
being checked.
No
No
STCEN = 1?
INTIIC0
interrupt occurs?
SPT0 = 1
Yes
Yes
SPD0 = 1?
INTIIC0
interrupt occurs?
No
Yes
Yes
Slave operation
SPD0 = 1?
No
Waits for detection
of the stop condition.
No
Yes
1
Slave operation
Master operation
starts?
No
(No communication start request)
Yes
(Communication start request)
SPIE0 = 0
INTIIC0
interrupt occurs?
SPIE0 = 1
No
Waits for a communication request.
Yes
IICRSV = 0?
No
Slave operation
Yes
A
Note Confirm that the bus is released (CLD0 bit = 1, DAD0 bit = 1) for a specific period (for example, for a period
of one frame). If the SDA0 pin is constantly at low level, decide whether to release the I2C bus (SCL0 and
SDA0 pins = high level) in conformance with the specifications of the product that is communicating.
574
STT0 = 1
Wait
Communication processing
MSTS0 = 1?
No
Yes
INTIIC0
interrupt occurs?
Yes
No
Wait state after stop condition
was detected and start condition
was generated by the communication
reservation function.
Slave operation
IICBSY = 0?
No
Yes
Communication processing
No
Waits for bus release
(communication being reserved).
STT0 = 1
Wait
STCF = 0?
Yes
No
INTIIC0
interrupt occurs?
No
Waits for bus release
Yes
C
EXC0 = 1 or COI0 =1?
No
Detects a stop condition.
Yes
Slave operation
575
Writing IIC0
INTIIC0
interrupt occurs?
Starts communication
(specifies an address and transfer direction).
No
Waits for detection of ACK.
Yes
MSTS0 = 1?
No
Yes
No
ACKD0 = 1?
Yes
TRC0 = 1?
No
ACKE0 = 1
WTIM0 = 0
Yes
Communication processing
WTIM0 = 1
WREL0 = 1
Writing IIC0
Starts transmission.
INTIIC0
interrupt occurs?
INTIIC0
interrupt occurs?
No
Waits for data transmission.
Yes
MSTS0 = 1?
No
Waits for data reception.
Yes
MSTS0 = 1?
No
No
Yes
Yes
ACKD0 = 1?
Starts reception.
Reading IIC0
No
Transfer end?
No
Yes
Yes
No
WTIM0 = WREL0 = 1
ACKE0 = 0
Transfer end?
Yes
Restart?
INTIIC0
interrupt occurs?
No
No
Waits for detection of ACK.
Yes
SPT0 = 1
Yes
MSTS0 = 1?
STT0 = 1
END
Yes
No
2
Communication processing
EXC0 = 1 or COI0 = 1?
Yes
Slave operation
No
1
Does not participate
in communication.
Remarks 1. Conform to the specifications of the product that is communicating, with respect to the transmission
and reception formats.
2. To use the device as a master in a multi-master system, read the MSTS0 bit each time interrupt
INTIIC0 has occurred to check the arbitration result.
3. To use the device as a slave in a multi-master system, check the status by using the IICS0 and IICF0
registers each time interrupt INTIIC0 has occurred, and determine the processing to be performed
next.
576
INTIIC0
Flag
Interrupt servicing
Setting
Main processing
IIC0
Data
Setting
Therefore, data communication processing is performed by preparing the following three flags and passing
them to the main processing instead of INTIIC0.
<1> Communication mode flag
This flag indicates the following two communication statuses.
Clear mode:
Communication mode: Status in which data communication is performed (from valid address detection
to stop condition detection, no detection of ACK from master, address
mismatch)
<2> Ready flag
This flag indicates that data communication is enabled. Its function is the same as the INTIIC0 interrupt
for ordinary data communication.
processing. Clear this flag by interrupt servicing when communication is started. However, the ready flag
is not set by interrupt servicing when the first data is transmitted. Therefore, the first data is transmitted
without the flag being cleared (an address match is interpreted as a request for the next data).
<3> Communication direction flag
This flag indicates the direction of communication. Its value is the same as TRC0.
577
IICX0 0XH
IICCL0 XXH
Initial setting
SVA0 XXH
IICF0 0XH
Setting IICRSV
IICC0 XXH
ACKE0 = WTIM0 = 1
SPIE0 = 0, IICE0 = 1
Setting port
No
Sets each pin to the I2C mode (see 18.3 (7) Port mode register 6 (PM6)).
Communication
mode flag = 1?
Yes
No
Communication
direction flag = 1?
Yes
WREL0 = 1
Writing IIC0
Communication
mode flag = 1?
Communication processing
No
Communication
mode flag = 1?
No
Yes
Yes
No
Starts
reception.
Starts
transmission.
Communication
direction flag = 1?
Communication
direction flag = 1?
No
Yes
No
Yes
No
Ready flag = 1?
Ready flag = 1?
Yes
Yes
Reading IIC0
Clearing ready flag
Yes
ACKD0 = 1?
No
Clearing communication
mode flag
WREL0 = 1
Remark
Conform to the specifications of the product that is in communication, regarding the transmission and
reception formats.
578
An example of the processing procedure of the slave with the INTIIC0 interrupt is explained below (processing
is performed assuming that no extension code is used). The INTIIC0 interrupt checks the status, and the
following operations are performed.
<1> Communication is stopped if the stop condition is issued.
<2> If the start condition is issued, the address is checked and communication is completed if the address
does not match.
If the address matches, the communication mode is set, wait is cancelled, and
<1> to <3> above correspond to <1> to <3> in Figure 18-26 Slave Operation Flowchart (2).
Figure 18-26. Slave Operation Flowchart (2)
INTIIC0 generated
Yes
<1>
Yes
<2>
SPD0 = 1?
No
STD0 = 1?
No
No
<3>
COI0 = 1?
Yes
579
ST:
Start condition
580
R/W:
ACK:
Acknowledge
D7 to D0:
Data
SP:
Stop condition
SPT0 = 1
ST
D7 to D0
ACK
D7 to D0
ACK
SP
1: IICS0 = 1000110B
2: IICS0 = 1000000B
Note
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
SPT0 = 1
ST
D7 to D0
ACK
D7 to D0
2
ACK
SP
3
1: IICS0 = 1000110B
2: IICS0 = 1000100B
3: IICS0 = 100000B (Sets SPT0 to 1)
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
581
STT0 = 1
ST
D7 to D0
1
ACK
ST
SPT0 = 1
D7 to D0
4
ACK
SP
1: IICS0 = 1000110B
2: IICS0 = 1000000B (Sets WTIM0 to 1Note 1)
3: IICS0 = 100000B (Clears WTIM0 to 0Note 2, sets STT0 to 1)
4: IICS0 = 1000110B
5: IICS0 = 1000000B (Sets WTIM0 to 1Note 3)
6: IICS0 = 100000B (Sets SPT0 to 1)
7: IICS0 = 00000001B
Notes 1. To generate a start condition, set WTIM0 to 1 and change the timing for generating the INTIIC0
interrupt request signal.
2. Clear WTIM0 to 0 to restore the original setting.
3. To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0
interrupt request signal.
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
STT0 = 1
ST
D7 to D0
ACK
ST
SPT0 = 1
1: IICS0 = 1000110B
2: IICS0 = 100000B (Sets STT0 to 1)
3: IICS0 = 1000110B
4: IICS0 = 100000B (Sets SPT0 to 1)
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
582
Dont care
D7 to D0
3
ACK
SP
4
SPT0 = 1
ST
D7 to D0
ACK
D7 to D0
ACK
SP
1: IICS0 = 1010110B
2: IICS0 = 1010000B
3: IICS0 = 1010000B (Sets WTIM0 to 1Note)
4: IICS0 = 101000B (Sets SPT0 to 1)
5: IICS0 = 00000001B
Note To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt
request signal.
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
SPT0 = 1
ST
D7 to D0
ACK
D7 to D0
2
ACK
SP
3
1: IICS0 = 1010110B
2: IICS0 = 1010100B
3: IICS0 = 101000B (Sets SPT0 to 1)
4: IICS0 = 00001001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
583
ST
D7 to D0
ACK
D7 to D0
ACK
SP
1: IICS0 = 0001110B
2: IICS0 = 0001000B
3: IICS0 = 0001000B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
ST
D7 to D0
ACK
D7 to D0
2
1: IICS0 = 0001110B
2: IICS0 = 0001100B
3: IICS0 = 000100B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
584
Dont care
ACK
SP
3
ST
D7 to D0
1
ACK
ST
D7 to D0
3
ACK
SP
1: IICS0 = 0001110B
2: IICS0 = 0001000B
3: IICS0 = 0001110B
4: IICS0 = 0001000B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
ST
D7 to D0
ACK
ST
D7 to D0
3
ACK
SP
4
1: IICS0 = 0001110B
2: IICS0 = 000100B
3: IICS0 = 0001110B
4: IICS0 = 000100B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
585
ST
D7 to D0
1
ACK
ST
D7 to D0
ACK
SP
1: IICS0 = 0001110B
2: IICS0 = 0001000B
3: IICS0 = 0010010B
4: IICS0 = 0010000B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
(ii) When WTIM0 = 1 (after restart, does not match address (= extension code))
ST
D7 to D0
ACK
ST
1: IICS0 = 0001110B
2: IICS0 = 000100B
3: IICS0 = 0010010B
4: IICS0 = 0010110B
5: IICS0 = 001000B
6: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
586
Dont care
D7 to D0
4
ACK
SP
5
ST
D7 to D0
1
ACK
ST
D7 to D0
ACK
SP
1: IICS0 = 0001110B
2: IICS0 = 0001000B
3: IICS0 = 00000110B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
(ii) When WTIM0 = 1 (after restart, does not match address (= not extension code))
ST
D7 to D0
ACK
ST
D7 to D0
3
ACK
SP
4
1: IICS0 = 0001110B
2: IICS0 = 000100B
3: IICS0 = 00000110B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
587
ST
D7 to D0
ACK
D7 to D0
ACK
SP
1: IICS0 = 0010010B
2: IICS0 = 0010000B
3: IICS0 = 0010000B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
ST
D7 to D0
ACK
D7 to D0
3
1: IICS0 = 0010010B
2: IICS0 = 0010110B
3: IICS0 = 0010100B
4: IICS0 = 001000B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
588
Dont care
ACK
SP
4
ST
D7 to D0
ACK
ST
D7 to D0
3
ACK
SP
1: IICS0 = 0010010B
2: IICS0 = 0010000B
3: IICS0 = 0001110B
4: IICS0 = 0001000B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
ST
D7 to D0
ACK
ST
D7 to D0
4
ACK
SP
5
1: IICS0 = 0010010B
2: IICS0 = 0010110B
3: IICS0 = 001000B
4: IICS0 = 0001110B
5: IICS0 = 000100B
6: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
589
ST
D7 to D0
ACK
ST
D7 to D0
ACK
SP
1: IICS0 = 0010010B
2: IICS0 = 0010000B
3: IICS0 = 0010010B
4: IICS0 = 0010000B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
ST
D7 to D0
ACK
ST
1: IICS0 = 0010010B
2: IICS0 = 0010110B
3: IICS0 = 001000B
4: IICS0 = 0010010B
5: IICS0 = 0010110B
6: IICS0 = 001000B
7: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
590
Dont care
D7 to D0
5
ACK
SP
6
ST
D7 to D0
ACK
ST
D7 to D0
ACK
SP
1: IICS0 = 00100010B
2: IICS0 = 00100000B
3: IICS0 = 00000110B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
(ii) When WTIM0 = 1 (after restart, does not match address (= not extension code))
ST
D7 to D0
ACK
ST
D7 to D0
4
ACK
SP
5
1: IICS0 = 00100010B
2: IICS0 = 00100110B
3: IICS0 = 0010000B
4: IICS0 = 00000110B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
591
ST
D7 to D0
ACK
D7 to D0
ACK
SP
1
1: IICS0 = 00000001B
Remark
ST
D7 to D0
ACK
D7 to D0
1: IICS0 = 0101110B
2: IICS0 = 0001000B
3: IICS0 = 0001000B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
592
Dont care
ACK
3
SP
4
ST
D7 to D0
ACK
D7 to D0
ACK
SP
3
1: IICS0 = 0101110B
2: IICS0 = 0001100B
3: IICS0 = 000100B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
ST
D7 to D0
ACK
D7 to D0
ACK
3
SP
4
1: IICS0 = 0110010B
2: IICS0 = 0010000B
3: IICS0 = 0010000B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
593
ST
D7 to D0
ACK
D7 to D0
ACK
SP
4
1: IICS0 = 0110010B
2: IICS0 = 0010110B
3: IICS0 = 0010100B
4: IICS0 = 001000B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
(6) Operation when arbitration loss occurs (no communication after arbitration loss)
When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request
signal INTIIC0 has occurred to check the arbitration result.
(a) When arbitration loss occurs during transmission of slave address data (when WTIM0 = 1)
ST
D7 to D0
ACK
D7 to D0
2: IICS0 = 00000001B
: Always generated
: Generated only when SPIE0 = 1
594
SP
2
1: IICS0 = 01000110B
Remark
ACK
ST
D7 to D0
ACK
D7 to D0
ACK
SP
1: IICS0 = 0110010B
Sets LREL0 = 1 by software
2: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
ST
D7 to D0
ACK
D7 to D0
ACK
SP
3
1: IICS0 = 10001110B
2: IICS0 = 01000000B
3: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
595
ST
D7 to D0
ACK
D7 to D0
ACK
SP
1: IICS0 = 10001110B
2: IICS0 = 01000100B
3: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
(d) When loss occurs due to restart condition during data transfer
(i) Not extension code (Example: unmatches with SVA0)
ST
D7 to Dn
ST
1: IICS0 = 1000110B
2: IICS0 = 01000110B
3: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
n = 6 to 0
596
D7 to D0
ACK
SP
3
ST
D7 to Dn
ST
D7 to D0
ACK
SP
3
1: IICS0 = 1000110B
2: IICS0 = 01100010B
Sets LREL0 = 1 by software
3: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
n = 6 to 0
(e) When loss occurs due to stop condition during data transfer
ST
D7 to Dn
SP
1: IICS0 = 10000110B
2: IICS0 = 01000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
n = 6 to 0
597
(f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition
(i) When WTIM0 = 0
STT0 = 1
ST
D7 to D0
1
ACK
2
D7 to D0
3
ACK
D7 to D0
ACK
SP
1: IICS0 = 1000110B
2: IICS0 = 1000000B (Sets WTIM0 to 1)
3: IICS0 = 1000100B (Clears WTIM0 to 0)
4: IICS0 = 01000000B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
STT0 = 1
ST
D7 to D0
ACK
D7 to D0
2
ACK
D7 to D0
3
1: IICS0 = 1000110B
2: IICS0 = 1000100B (Sets STT0 to 1)
3: IICS0 = 01000100B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
598
Dont care
ACK
SP
4
(g) When arbitration loss occurs due to a stop condition when attempting to generate a restart
condition
(i) When WTIM0 = 0
STT0 = 1
ST
D7 to D0
1
ACK
2
SP
3
1: IICS0 = 1000110B
2: IICS0 = 1000000B (Sets WTIM0 to 1)
3: IICS0 = 100000B (Sets STT0 to 1)
4: IICS0 = 01000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
STT0 = 1
ST
D7 to D0
1
ACK
SP
2
1: IICS0 = 1000110B
2: IICS0 = 100000B (Sets STT0 to 1)
3: IICS0 = 01000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
599
(h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition
(i) When WTIM0 = 0
SPT0 = 1
ST
D7 to D0
1
ACK
2
D7 to D0
ACK
D7 to D0
ACK
SP
1: IICS0 = 1000110B
2: IICS0 = 1000000B (Sets WTIM0 to 1)
3: IICS0 = 1000100B (Clears WTIM0 to 0)
4: IICS0 = 01000100B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
Dont care
SPT0 = 1
ST
D7 to D0
ACK
D7 to D0
2
ACK
D7 to D0
3
1: IICS0 = 1000110B
2: IICS0 = 1000100B (Sets SPT0 to 1)
3: IICS0 = 01000100B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
:
600
Dont care
ACK
SP
4
601
IIC0
IIC0 data
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
Transmit
Transfer lines
1
SCL0
SDA0
ACK
D7
D6
D5
D4
Start condition
Processing by slave device
IIC0 FFH Note
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
Note
WREL0
INTIIC0
(When EXC0 = 1)
TRC0
Receive
602
IIC0
IIC0 data
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
Transmit
Transfer lines
SCL0
SDA0
D0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
D7
D6
D5
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
Note
WREL0
Note
INTIIC0
TRC0
Receive
603
IIC0
IIC0 address
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
(When SPIE0 = 1)
TRC0
H Transmit
Transfer lines
SCL0
SDA0
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Start
condition
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
Note
WREL0
Note
INTIIC0
(When SPIE0 = 1)
TRC0
L Receive
604
AD6 AD5
Stop
condition
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
L
SPT0
Note
WREL0
INTIIC0
TRC0
Transfer lines
1
SCL0
SDA0
ACK
1
D7
D6
D5
D4
D3
D2
Start condition
Processing by slave device
IIC0 data
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
605
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
Note
WREL0
Note
INTIIC0
L Receive
TRC0
Transfer lines
SCL0
SDA0
D0
ACK
1
D7
D6
D5
D4
D3
D2
D1
D0
ACK
1
D7
D6
D5
IIC0
IIC0 data
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
H Transmit
606
IIC0 address
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
Note
WREL0
INTIIC0
(When SPIE0 = 1)
TRC0
Transfer lines
SCL0
SDA0
D7
D6
D5
D4
D3
D2
D1
D0
1
AD6
NACK
Stop
condition
Start
condition
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
(When SPIE0 = 1)
TRC0
607
CHAPTER 19 MULTIPLIER/DIVIDER
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 3
y = 4, 5
Multiplier/divider
y = 1 to 3 y = 4 to 7 y = 1 to 3 y = 4 to 7
y = 4 to 7
Do not use serial interface IIC0 and the multiplier/divider simultaneously, because various flags
corresponding to interrupt request sources are shared among serial interface IIC0 and the
multiplier/divider.
Configuration
Remainder data register 0 (SDR0)
Multiplication/division data registers A0 (MDA0H, MDA0L)
Multiplication/division data registers B0 (MDB0)
Control register
608
Internal bus
Multiplier/divider control
register 0 (DMUC0)
Multiplication/division data register B0
(MDB0 (MDB0H + MDB0L)
DMUSEL0 DMUE
Start
MDA000
INTDMU
Clear
Controller
17-bit
adder
Controller
fPRS
CHAPTER 19 MULTIPLIER/DIVIDER
Controller
6-bit
counter
609
CHAPTER 19 MULTIPLIER/DIVIDER
Symbol
SDR0
FF61H (SDR0H)
FF60H (SDR0L)
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
015
014
013
012
011
010
009
008
007
006
005
004
003
002
001
000
Cautions 1. The value read from SDR0 during operation processing (while bit 7 (DMUE) of
multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed.
2. SDR0 is reset when the operation is started (when DMUE is set to 1).
(2) Multiplication/division data register A0 (MDA0H, MDA0L)
MDA0 is a 32-bit register that sets a 16-bit multiplier A in the multiplication mode and a 32-bit dividend in the
division mode, and stores the 32-bit result of the operation (higher 16 bits: MDA0H, lower 16 bits: MDA0L).
Figure 19-3. Format of Multiplication/Division Data Register A0 (MDA0H, MDA0L)
Address: FF62H, FF63H, FF64H, FF65H
Symbol
MDA0H
R/W
FF65H (MDA0HH)
FF64H (MDA0HL)
MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA
031
030
Symbol
MDA0L
029
028
027
026
025
024
023
022
FF63H (MDA0LH)
021
020
019
018
017
016
FF62H (MDA0LL)
MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA
015
014
013
012
011
010
009
008
007
006
005
004
003
002
001
000
Cautions 1. MDA0H is cleared to 0 when an operation is started in the multiplication mode (when
multiplier/divider control register 0 (DMUC0) is set to 81H).
2. Do not change the value of MDA0 during operation processing (while bit 7 (DMUE) of
multiplier/divider control register 0 (DMUC0) is 1).
610
CHAPTER 19 MULTIPLIER/DIVIDER
The functions of MDA0 when an operation is executed are shown in the table below.
Table 19-2. Functions of MDA0 During Operation Execution
DMUSEL0
Remark
Operation Mode
Setting
Operation Result
Division mode
Dividend
Multiplication mode
Multiplication result
(product)
The register configuration differs between when multiplication is executed and when division is executed, as
follows.
Register configuration during multiplication
<Multiplier A>
<Multiplier B>
<Product>
<Divisor>
<Quotient>
<Remainder>
Symbol
MDB0
R/W
FF67H (MDB0H)
FF66H (MDB0L)
MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB
015
014
013
012
011
010
009
008
007
006
005
004
003
002
001
000
Cautions 1. Do not change the value of MDB0 during operation processing (while bit 7 (DMUE) of
multiplier/divider control register 0 (DMUC0) is 1).
611
CHAPTER 19 MULTIPLIER/DIVIDER
R/W
Symbol
<7>
DMUC0
DMUE
DMUSEL0
DMUENote
Operation start/stop
Stops operation
Starts operation
DMUSEL0
Division mode
Multiplication mode
Note When DMUE is set to 1, the operation is started. DMUE is automatically cleared to 0 after the operation is
complete.
Cautions 1. If DMUE is cleared to 0 during operation processing (when DMUE is 1), the operation result
is not guaranteed. If the operation is completed while the clearing instruction is being
executed, the operation result is guaranteed, provided that the interrupt flag is set.
2. Do not change the value of DMUSEL0 during operation processing (while DMUE is 1). If it is
changed, undefined operation results are stored in multiplication/division data register A0
(MDA0) and remainder data register 0 (SDR0).
3. If DMUE is cleared to 0 during operation processing (while DMUE is 1), the operation
processing is stopped.
612
CHAPTER 19 MULTIPLIER/DIVIDER
613
614
fPRS
DMUE
DMUSEL0
Counter
XXXX
SDR0
MDA0
XXXX
XXXX
MDB0
XXXX
INTDMU
XXXX
00DA
0093
10
0000
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0000
00DA
0000 0049 0024 005B 0077 003B 0067 007D 003E 001F 000F 0007 0003 0001 0000 0000
006D 8036 C01B E00D 7006 B803 5C01 2E00 9700 4B80 A5C0 D2E0 E970 F4B8 FA5C 7D2E
CHAPTER 19 MULTIPLIER/DIVIDER
Internal clock
CHAPTER 19 MULTIPLIER/DIVIDER
615
616
fPRS
DMUE
DMUSEL0
Counter
XXXX
SDR0
0000
MDA0
XXXX
XXXX
DCBA
2586
MDB0
XXXX
0018
INTDMU
19
1A
1B
1C
1D 1E
1F
20
B974
4B0C
0C12
64D8
72E8
9618
E5D1 CBA2
2C30 5860
9744
B0C1
2E89
6182
5D12
C304
BA25
8609
1824
C9B0
3049
9361
6093
26C3
C126
4D87
824C
9B0E
0499
361D
0932
6C3A
CHAPTER 19 MULTIPLIER/DIVIDER
Internal clock
Maskable
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 3 y = 4 to 7
y = 4 to 7
External
interrupts
38/44 pins: 7 ch
48 pins:
internal
14
16
16
19
20
8 ch
16
617
Basic
Default
Interrupt Source
Note 2
Name
Trigger
Type
Maskable Internal
External
Internal
Note 3
Vector
Table
Address
0004H
(A)
INTLVI
Low-voltage detection
(B)
INTP0
0006H
INTP1
0008H
INTP2
000AH
INTP3
000CH
INTP4
000EH
INTP5
0010H
INTSRE6
0012H
INTSR6
0014H
INTST6
0016H
10
0018H
001AH
001CH
001EH
0020H
0022H
(A)
INTST0
11
UART0 transmission
12
13
INTTM50
14
15
16
INTAD
0024H
17
INTSR0
0026H
error generation
Notes 1.
2.
18
INTWTI
0028H
19
INTTM51
002AH
Note 4
Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 20-1.
The default priority determines the sequence of processing vectored interrupts if two or more maskable
interrupts occur simultaneously. Zero indicates the highest priority and 28 indicates the lowest priority.
3.
4.
When 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated upon
the timing when the INTTM5H1 signal is generated (see Figure 9-13 Transfer Timing).
618
Basic
Default
Interrupt Source
Note 2
Note 1
Name
Trigger
Type
Vector
Table
Address
(C)
20
INTKR
002CH
Internal
(A)
21
INTWT
002EH
External
(B)
22
INTP6
0030H
Maskable External
Note 4
Internal
(A)
23
INTP7
24
INTIIC0/
INTDMU
multiply/divide operation
25
0032H
0034H
0036H
Note 5
Note 5
Note 5
Note 5
Note 6
26
0038H
Note 6
003AH
Note 6
INTACSI
003CH
Software
(D)
BRK
003EH
Reset
RESET
Reset input
0000H
POC
Power-on clear
LVI
Low-voltage detection
WDT
WDT overflow
Notes 1.
2.
Note 3
Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 20-1.
The default priority determines the sequence of processing vectored interrupts if two or more maskable
interrupts occur simultaneously. Zero indicates the highest priority and 28 indicates the lowest priority.
3.
4.
5.
INTIIC0:
619
MK
Interrupt
request
IE
PR
ISP
Priority controller
IF
Vector table
address generator
Interrupt
request
Edge
detector
MK
IE
PR
ISP
Priority controller
IF
Vector table
address generator
620
IF:
IE:
ISP:
MK:
PR:
MK
Interrupt
request
Key
interrupt
detector
IE
PR
ISP
Priority controller
IF
Vector table
address generator
1 when KRMn = 1
Standby release signal
Remark n = 0, 1:
Internal bus
Interrupt
request
IF:
IE:
ISP:
MK:
PR:
Priority controller
Vector table
address generator
621
Interrupt
B C D E
Source
INTLVI
LVIIF
INTP0
PIF0
PMK0
PPR0
INTP1
PIF1
PMK1
PPR1
INTP2
PIF2
PMK2
PPR2
INTP3
PIF3
PMK3
PPR3
INTP4
PIF4
PMK4
PPR4
INTP5
PIF5
PMK5
PPR5
INTSRE6
SREIF6
SREMK6
SREPR6
INTSR6
SRIF6
INTST6
STIF6
STMK6
STPR6
INTCSI10
CSIIF10
DUALIF0
CSIMK10 DUALMK0
CSIPR10 DUALPR0
Note 1
Note 1
Note 2
INTST0
Register
IF0L
IF0H
Register
LVIMK
MK0L
SRMK6
MK0H
Note 2
Register
LVIPR
SRPR6
Note 3
STIF0
STMK0
STPR0
Note 1
Note 2
Note 3
INTTMH1
TMIFH1
TMMKH1
TMPRH1
INTTMH0
TMIFH0
TMMKH0
TMPRH0
INTTM50
TMIF50
TMMK50
TMPR50
INTTM000 TMIF000
TMMK000
TMPR000
INTTM010 TMIF010
TMMK010
TMPR010
Notes 1.
622
If either interrupt source INTCSI10 or INTST0 is generated, bit 2 of IF0H is set (1).
2.
3.
PR0L
PR0H
Note 3
Interrupt
B C D E
Source
INTAD
ADIF
INTSR0
SRIF0
SRMK0
SRPR0
INTWTI
WTIIF
WTIMK
WTIPR
INTTM51
TMIF51
TMMK51
TMPR51
Register
IF1L
Register
ADMK
MK1L
Register
ADPR
PR1L
Note 4
INTKR
KRIF
KRMK
KRPR
INTWT
WTIF
WTMK
WTPR
INTP6
PIF6
PMK6
PPR6
PIF7
Note 1
INTP7
INTIIC0
IICIF0
PMK7
Note 6
IF1H
IICMK0
PPR7
Note 7
MK1H
IICPR0
Note 7
PR1H
Note 5
INTDMU
Note 6
Note 7
Note 7
DMUIF
DMUMK
CSIIF11
CSIMK11
CSIPR11
INTTM001 TMIF001
TMMK001
TMPR001
INTTM011 TMIF011
TMMK011
TMPR011
INTACSI
ACSIMK
ACSIPR
DMUPR
Note 5
INTCSI11
Note 3
Note 3
Note 3
Notes 1.
2.
ACSIIF
4.
When 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated upon
the timing when the INTTM5H1 signal is generated (see Figure 9-13 Transfer Timing).
5.
Do not use serial interface IIC0 and multiplier/divider simultaneously, because the flags corresponding to
the interrupt request sources of serial interface IIC0 and multiplier/divider support both of these interrupt
request sources. If software which operates serial interface IIC0 is developed by CC78K0 which is C
compiler, do not select the check box of Using Multiplier/Divider on GUI of PM+.
6.
If either interrupt source INTIIC0 or INTDMU is generated, bit 0 of IF1H is set (1).
7.
Bit 0 of MK1H and PR1H supports both interrupt sources INTIIC0 and INTDMU.
623
624
Figure 20-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) (78K0/KB2)
Address: FFE0H After reset: 00H R/W
Symbol
IF0L
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
SREIF6
PIF5
PIF4
PIF3
PIF2
PIF1
PIF0
LVIIF
Address: FFE1H
Symbol
IF0H
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TMIF010
TMIF000
TMIF50
TMIFH0
TMIFH1
DUALIF0
STIF6
SRIF6
CSIIF10
STIF0
Address: FFE2H
R/W
Symbol
<3>
<1>
<0>
IF1L
TMIF51
SRIF0
ADIF
Address: FFE3H
R/W
Symbol
<0>
IF1H
IICIF0
XXIFX
Caution
625
Figure 20-3. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) (78K0/KC2)
Address: FFE0H After reset: 00H R/W
Symbol
IF0L
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
SREIF6
PIF5
PIF4
PIF3
PIF2
PIF1
PIF0
LVIIF
Address: FFE1H
Symbol
IF0H
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TMIF010
TMIF000
TMIF50
TMIFH0
TMIFH1
DUALIF0
STIF6
SRIF6
CSIIF10
STIF0
Address: FFE2H
Symbol
IF1L
Address: FFE3H
R/W
<6>
PIF6
Note 1
<5>
<4>
<3>
<2>
<1>
<0>
WTIF
KRIF
TMIF51
WTIIF
SRIF0
ADIF
<0>
R/W
Symbol
IF1H
IICIF0
DMUIF
XXIFX
Note 2
626
Figure 20-4. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) (78K0/KD2)
Address: FFE0H After reset: 00H R/W
Symbol
IF0L
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
SREIF6
PIF5
PIF4
PIF3
PIF2
PIF1
PIF0
LVIIF
Address: FFE1H
Symbol
IF0H
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TMIF010
TMIF000
TMIF50
TMIFH0
TMIFH1
DUALIF0
STIF6
SRIF6
CSIIF10
STIF0
Address: FFE2H
R/W
Symbol
<6>
<5>
<4>
<3>
<2>
<1>
<0>
IF1L
PIF6
WTIF
KRIF
TMIF51
WTIIF
SRIF0
ADIF
<0>
Address: FFE3H
R/W
Symbol
IF1H
IICIF0
DMUIF
XXIFX
Note
Note PD78F0524A, 78F0525A, 78F0526A, 78F0527A, and 78F0527DA (products whose flash memory is at
least 48 KB) only.
Caution
627
Figure 20-5. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) (78K0/KE2)
Address: FFE0H After reset: 00H R/W
Symbol
IF0L
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
SREIF6
PIF5
PIF4
PIF3
PIF2
PIF1
PIF0
LVIIF
Address: FFE1H
Symbol
IF0H
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TMIF010
TMIF000
TMIF50
TMIFH0
TMIFH1
DUALIF0
STIF6
SRIF6
CSIIF10
STIF0
Address: FFE2H
R/W
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
IF1L
PIF7
PIF6
WTIF
KRIF
TMIF51
WTIIF
SRIF0
ADIF
<3>
<2>
<1>
<0>
Address: FFE3H
Symbol
IF1H
6
0
R/W
TMIF011
Note
TMIF001
Note
Note
CSIIF11
IICIF0
DMUIF
XXIFX
Note
Note PD78F0534A, 78F0535A, 78F0536A, 78F0537A, and 78F0537DA (products whose flash memory is at
least 48 KB) only.
Caution
Be sure to clear bits 1 to 7 of IF1H to 0 for the PD78F0531A, 78F0532A, and 78F0533A (products
whose flash memory is less than 32 KB).
Be sure to clear bits 4 to 7 of IF1H to 0 for the PD78F0534A, 78F0535A, 78F0536A, 78F0537A,
and 78F0537DA (products whose flash memory is at least 48 KB).
628
Figure 20-6. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) (78K0/KF2)
Address: FFE0H After reset: 00H R/W
Symbol
IF0L
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
SREIF6
PIF5
PIF4
PIF3
PIF2
PIF1
PIF0
LVIIF
Address: FFE1H
Symbol
IF0H
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TMIF010
TMIF000
TMIF50
TMIFH0
TMIFH1
DUALIF0
STIF6
SRIF6
CSIIF10
STIF0
Address: FFE2H
R/W
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
IF1L
PIF7
PIF6
WTIF
KRIF
TMIF51
WTIIF
SRIF0
ADIF
<0>
Address: FFE3H
R/W
Symbol
<4>
<3>
<2>
<1>
IF1H
ACSIIF
TMIF011
TMIF001
CSIIF11
IICIF0
DMUIF
XXIFX
Caution
629
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
SREMK6
PMK5
PMK4
PMK3
PMK2
PMK1
PMK0
LVIMK
Address: FFE5H
R/W
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
MK0H
TMMK010
TMMK000
TMMK50
TMMKH0
TMMKH1
DUALMK0
STMK6
SRMK6
CSIMK10
STMK0
Address: FFE6H
R/W
Symbol
<3>
<1>
<0>
MK1L
TMMK51
SRMK0
ADMK
Address: FFE7H
R/W
Symbol
<0>
MK1H
IICMK0
XXMKX
630
Figure 20-8. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) (78K0/KC2)
Address: FFE4H
Symbol
MK0L
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
SREMK6
PMK5
PMK4
PMK3
PMK2
PMK1
PMK0
LVIMK
Address: FFE5H
R/W
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
MK0H
TMMK010
TMMK000
TMMK50
TMMKH0
TMMKH1
DUALMK0
STMK6
SRMK6
CSIMK10
STMK0
Address: FFE6H
Symbol
MK1L
Address: FFE7H
R/W
<6>
PMK6
Note 1
<5>
<4>
<3>
<2>
<1>
<0>
WTMK
KRMK
TMMK51
WTIMK
SRMK0
ADMK
<0>
R/W
Symbol
MK1H
IICMK0
DMUMK
XXMKX
Note 2
631
Figure 20-9. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) (78K0/KD2)
Address: FFE4H
Symbol
MK0L
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
SREMK6
PMK5
PMK4
PMK3
PMK2
PMK1
PMK0
LVIMK
Address: FFE5H
R/W
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
MK0H
TMMK010
TMMK000
TMMK50
TMMKH0
TMMKH1
DUALMK0
STMK6
SRMK6
CSIMK10
STMK0
Address: FFE6H
R/W
Symbol
<6>
<5>
<4>
<3>
<2>
<1>
<0>
MK1L
PMK6
WTMK
KRMK
TMMK51
WTIMK
SRMK0
ADMK
<0>
Address: FFE7H
R/W
Symbol
MK1H
IICMK0
DMUMK
XXMKX
Note
Note PD78F0524A, 78F0525A, 78F0526A, 78F0527A, and 78F0527DA (products whose flash memory is at
least 48 KB) only.
Caution Be sure to set bit 7 of MK1L and bits 1 to 7 of MK1H to 1.
632
Figure 20-10. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) (78K0/KE2)
Address: FFE4H
Symbol
MK0L
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
SREMK6
PMK5
PMK4
PMK3
PMK2
PMK1
PMK0
LVIMK
Address: FFE5H
R/W
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
MK0H
TMMK010
TMMK000
TMMK50
TMMKH0
TMMKH1
DUALMK0
STMK6
SRMK6
CSIMK10
STMK0
Address: FFE6H
Symbol
MK1L
Address: FFE7H
Symbol
MK1H
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
PMK7
PMK6
WTMK
KRMK
TMMK51
WTIMK
SRMK0
ADMK
<3>
<2>
<1>
<0>
6
1
R/W
5
1
TMMK011
Note
TMMK001
Note
CSIMK11
Note
IICMK0
DMUMK
XXMKX
Note
Note PD78F0534A, 78F0535A, 78F0536A, 78F0537A, and 78F0537DA (products whose flash memory is at
least 48 KB) only.
Caution Be sure to set bits 1 to 7 of MK1H to 1 for the PD78F0531A, 78F0532A, and 78F0533A (products
whose flash memory is less than 32 KB).
Be sure to set bits 4 to 7 of MK1H to 1 for the PD78F0534A, 78F0535A, 78F0536A, 78F0537A, and
78F0537DA (products whose flash memory is at least 48 KB).
633
Figure 20-11. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) (78K0/KF2)
Address: FFE4H
Symbol
MK0L
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
SREMK6
PMK5
PMK4
PMK3
PMK2
PMK1
PMK0
LVIMK
Address: FFE5H
R/W
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
MK0H
TMMK010
TMMK000
TMMK50
TMMKH0
TMMKH1
DUALMK0
STMK6
SRMK6
CSIMK10
STMK0
Address: FFE6H
Symbol
MK1L
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
PMK7
PMK6
WTMK
KRMK
TMMK51
WTIMK
SRMK0
ADMK
<0>
Address: FFE7H
R/W
Symbol
<4>
<3>
<2>
<1>
MK1H
ACSIMK
TMMK011
TMMK001
CSIMK11
IICMK0
DMUMK
XXMKX
634
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
SREPR6
PPR5
PPR4
PPR3
PPR2
PPR1
PPR0
LVIPR
Address: FFE9H
Symbol
PR0H
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TMPR010
TMPR000
TMPR50
TMPRH0
TMPRH1
DUALPR0
STPR6
SRPR6
CSIPR10
STPR0
Address: FFEAH
R/W
Symbol
<3>
<1>
<0>
PR1L
TMPR51
SRPR0
ADPR
Address: FFEBH
R/W
Symbol
<0>
PR1H
IICPR0
XXPRX
635
Figure 20-13. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) (78K0/KC2)
Address: FFE8H
Symbol
PR0L
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
SREPR6
PPR5
PPR4
PPR3
PPR2
PPR1
PPR0
LVIPR
Address: FFE9H
Symbol
PR0H
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TMPR010
TMPR000
TMPR50
TMPRH0
TMPRH1
DUALPR0
STPR6
SRPR6
CSIPR10
STPR0
Address: FFEAH
Symbol
PR1L
Address: FFEBH
R/W
<6>
PPR6
Note 1
<5>
<4>
<3>
<2>
<1>
<0>
WTPR
KRPR
TMPR51
WTIPR
SRPR0
ADPR
<0>
R/W
Symbol
PR1H
IICPR0
Note 2
DMUPR
XXPRX
636
Figure 20-14. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) (78K0/KD2)
Address: FFE8H
Symbol
PR0L
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
SREPR6
PPR5
PPR4
PPR3
PPR2
PPR1
PPR0
LVIPR
Address: FFE9H
Symbol
PR0H
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TMPR010
TMPR000
TMPR50
TMPRH0
TMPRH1
DUALPR0
STPR6
SRPR6
CSIPR10
STPR0
Address: FFEAH
R/W
Symbol
<6>
<5>
<4>
<3>
<2>
<1>
<0>
PR1L
PPR6
WTPR
KRPR
TMPR51
WTIPR
SRPR0
ADPR
<0>
Address: FFEBH
R/W
Symbol
PR1H
IICPR0
Note
DMUPR
XXPRX
Note PD78F0524A, 78F0525A, 78F0526A, 78F0527A, and 78F0527DA (products whose flash memory is at
least 48 KB) only.
Caution Be sure to set bit 7 of PR1L and bits 1 to 7 of PR1H to 1.
637
Figure 20-15. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) (78K0/KE2)
Address: FFE8H
Symbol
PR0L
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
SREPR6
PPR5
PPR4
PPR3
PPR2
PPR1
PPR0
LVIPR
Address: FFE9H
Symbol
PR0H
R/W
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TMPR010
TMPR000
TMPR50
TMPRH0
TMPRH1
DUALPR0
STPR6
SRPR6
CSIPR10
STPR0
Address: FFEAH
Symbol
PR1L
PR1H
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
PPR7
PPR6
WTPR
KRPR
TMPR51
WTIPR
SRPR0
ADPR
<3>
<2>
<1>
<0>
Address: FFEBH
Symbol
R/W
6
1
5
1
TMPR011
Note
TMPR001
Note
CSIPR11
Note
IICPR0
Note
DMUPR
XXPRX
Note PD78F0534A, 78F0535A, 78F0536A, 78F0537A, and 78F0537DA (products whose flash memory is at
least 48 KB) only.
Caution Be sure to set bits 1 to 7 of PR1H to 1 for the PD78F0531A, 78F0532A, and 78F0533A (products
whose flash memory is less than 32 KB).
Be sure to set bits 4 to 7 of PR1H to 1 for the PD78F0534A, 78F0535A, 78F0536A, 78F0537A, and
78F0537DA (products whose flash memory is at least 48 KB).
638
Figure 20-16. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) (78K0/KF2)
Address: FFE8H
Symbol
PR0L
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
SREPR6
PPR5
PPR4
PPR3
PPR2
PPR1
PPR0
LVIPR
Address: FFE9H
Symbol
PR0H
R/W
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TMPR010
TMPR000
TMPR50
TMPRH0
TMPRH1
DUALPR0
STPR6
SRPR6
CSIPR10
STPR0
Address: FFEAH
Symbol
PR1L
R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
PPR7
PPR6
WTPR
KRPR
TMPR51
WTIPR
SRPR0
ADPR
<0>
Address: FFEBH
R/W
Symbol
<4>
<3>
<2>
<1>
PR1H
ACSIPR
TMPR011
TMPR001
CSIPR11
IICPR0
DMUPR
XXPRX
639
Figure 20-17. Format of External Interrupt Rising Edge Enable Register (EGP)
and External Interrupt Falling Edge Enable Register (EGN) (1/2)
(1) 78K0/KB2
Address: FF48H
R/W
Symbol
EGP
EGP5
EGP4
EGP3
EGP2
EGP1
EGP0
Address: FF49H
Symbol
EGN
EGN5
EGN4
EGN3
EGN2
EGN1
EGN0
R/W
R/W
Symbol
EGP
EGP5
EGP4
EGP3
EGP2
EGP1
EGP0
Address: FF49H
Symbol
R/W
5
EGN
EGN5
EGN4
EGN3
EGN2
EGN1
EGN0
R/W
Symbol
EGP
EGP6
EGP5
EGP4
EGP3
EGP2
EGP1
EGP0
Address: FF49H
Symbol
EGN
EGN6
EGN5
EGN4
EGN3
EGN2
EGN1
EGN0
EGPn
EGNn
R/W
Falling edge
Rising edge
Caution Be sure to clear bits 6 and 7 of EGP and EGN to 0 in the 38-pin and 44-pin products of
78K0/KC2 and 78K0/KB2.
Be sure to clear bit 7 of EGP and EGN to 0 in the 48-pin products of 78K0/KC2 and
78K0/KD2.
Remark
640
Figure 20-17. Format of External Interrupt Rising Edge Enable Register (EGP)
and External Interrupt Falling Edge Enable Register (EGN) (2/2)
(4) 78K0/KE2, 78K0/KF2
Address: FF48H
Symbol
EGP7
EGP6
EGP5
EGP4
EGP3
EGP2
EGP1
EGP0
EGP
R/W
Address: FF49H
Symbol
EGN7
EGN6
EGN5
EGN4
EGN3
EGN2
EGN1
EGN0
EGPn
EGNn
EGN
R/W
Falling edge
Rising edge
Remark
n = 0 to 7: 78K0/KE2, 78K0/KF2
Note 1
Note 2
Edge Detection
Interrupt Request
Port
Signal
EGP0
EGN0
P120
INTP0
EGP1
EGN1
P30
INTP1
EGP2
EGN2
P31
INTP2
EGP3
EGN3
P32
INTP3
EGP4
EGN4
P33
INTP4
EGP5
EGN5
P16
INTP5
EGP6
EGN6
P140
INTP6
EGP7
EGN7
P141
INTP7
Note 3
641
PSW
<7>
<6>
<5>
<4>
<3>
<1>
After reset
IE
RBS1
AC
RBS0
ISP
CY
02H
Used when normal instruction is executed
ISP
642
IE
Disabled
Enabled
acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0).
The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed
in Table 20-4 below.
For the interrupt request acknowledgment timing, see Figures 20-20 and 20-21.
Table 20-4. Time from Generation of Maskable Interrupt Until Servicing
Note
Minimum Time
Maximum Time
When PR = 0
7 clocks
32 clocks
When PR = 1
8 clocks
33 clocks
Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer.
Remark
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same
priority level, the request with the highest default priority is acknowledged first.
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 20-7 shows the interrupt request acknowledgment algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then
PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged
interrupt are transferred to the ISP flag. The vector table data determined for each interrupt request is the loaded into
the PC and branched.
Restoring from an interrupt is possible by using the RETI instruction.
643
No
IF = 1?
Yes (interrupt request generation)
No
MK = 0?
Yes
PR = 0?
No (Low priority)
Yes
Any high-priority
interrupt request among those
simultaneously generated
with PR = 0?
Any high-priority
interrupt request among
those simultaneously generated
with PR = 0?
No
No
No
IE = 1?
Yes
Any high-priority
interrupt request among
those simultaneously
generated?
No
IE = 1?
Yes
ISP = 1?
Yes
Yes
Yes
IF:
ISP:
Flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt
servicing, 1 = No interrupt request acknowledged, or low-priority interrupt servicing)
644
Instruction
Instruction
Interrupt servicing
program
IF
(PR = 1)
8 clocks
IF
(PR = 0)
7 clocks
Remark
CPU processing
Instruction
25 clocks
6 clocks
Divide instruction
Interrupt servicing
program
IF
(PR = 1)
33 clocks
IF
(PR = 0)
32 clocks
Remark
645
PR = 0
IE = 1
IE = 0
IE = 1
IE = 0
ISP = 0
ISP = 1
Software interrupt
Remarks 1.
Interrupt
PR = 1
Request
Software
IE = 1:
646
INTxx servicing
INTyy servicing
IE = 0
EI
IE = 0
IE = 0
EI
INTxx
(PR = 1)
INTzz servicing
EI
INTyy
(PR = 0)
INTzz
(PR = 0)
RETI
IE = 1
RETI
IE = 1
RETI
IE = 1
During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple
interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be
issued to enable interrupt request acknowledgment.
Example 2. Multiple interrupt servicing does not occur due to priority control
Main processing
INTxx servicing
INTyy servicing
IE = 0
EI
EI
INTxx
(PR = 0)
INTyy
(PR = 1)
RETI
IE = 1
1 instruction execution
IE = 0
RETI
IE = 1
Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower
than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending,
and is acknowledged following execution of one main processing instruction.
PR = 0: Higher priority level
PR = 1: Lower priority level
IE = 0:
647
EI
INTyy
(PR = 0)
INTxx
(PR = 0)
RETI
IE = 1
1 instruction execution
IE = 0
RETI
IE = 1
Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt
request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request
is held pending, and is acknowledged following execution of one main processing instruction.
PR = 0: Higher priority level
IE = 0:
648
These
CPU processing
Instruction N
Instruction M
Interrupt servicing
program
IF
649
Key interrupt
78K0/KB2
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
(PD78F050yA)
(PD78F051yA)
(PD78F052yA)
(PD78F053yA)
(PD78F054yA)
y = 0 to 3
y = 1 to 5
y = 1 to 7
y = 1 to 7
y = 4 to 7
38 pins:
2 ch
8 ch
44/48 pins: 4 ch
Remark
Description
Controls KRn signal in 1-bit units.
n = 0, 1:
650
Configuration
Key return mode register (KRM)
651
R/W
Symbol
KRM
0
KRM1
KRM0
KRM1
KRM0
KRM1
KRM0
R/W
Symbol
KRM
KRM3
KRM2
R/W
KRM7
KRM6
KRM5
KRM4
KRM3
KRM2
KRMn
Cautions 1. If any of the KRMn bits used is set to 1, set bit n (PU7n) of the corresponding pull-up
resistor register 7 (PU7) to 1.
2. If KRM is changed, the interrupt request flag may be set. Therefore, disable interrupts and
then change the KRM register. Clear the interrupt request flag and enable interrupts.
3. The bits not used in the key interrupt mode can be used as normal ports.
4. For the 38-pin products of 78K0/KC2, be sure to set bits 2 to 7 of KRM to 0. For the 44-pin
and 48-pin products of 78K0/KC2, be sure to set bits 4 to 7 of KRM to 0.
Remark n = 0, 1:
652
653
For the registers that start, stop, or select the clock, see CHAPTER 6 CLOCK GENERATOR.
654
Figure 22-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H
Symbol
OSTC
MOST11
MOST13
MOST14
MOST15
MOST16
MOST11
MOST13
MOST14
MOST15
MOST16
1
1
1
fX = 20 MHz
11
13
14
15
16
2 /fX min.
2 /fX min.
2 /fX min.
2 /fX min.
2 /fX min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
2. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
Desired OSTC oscillation stabilization time Oscillation stabilization time
set by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
3. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (a below).
STOP mode release
X1 pin voltage
waveform
a
Remark
655
R/W
Symbol
OSTS
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
0
0
0
1
1
1
1
819.2 s
409.6 s
14
1.64 ms
819.2 s
15
3.27 ms
1.64 ms
16
6.55 ms
3.27 ms
2 /fX
102.4 s
2 /fX
204.8 s
13
2 /fX
2 /fX
2 /fX
fX = 20 MHz
11
Setting prohibited
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
before executing the STOP instruction.
2. Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
3. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
Desired OSTC oscillation stabilization time Oscillation stabilization time
set by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
4. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (a below).
STOP mode release
X1 pin voltage
waveform
a
Remark
656
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock
When CPU Is Operating on
Internal High-Speed
Oscillation Clock (fRH)
Item
System clock
Subsystem clock
fRH
fX
fEXCLK
fXT
fEXCLKS
fRL
CPU
Flash memory
RAM
Port (latch)
16-bit timer/event
counter
00
8-bit timer/event
counter
50
8-bit timer
H0
Operable
01
51
H1
Watch timer
Watchdog timer
Operable. Clock supply to watchdog timer stops when internal low-speed oscillator can be
stopped by software is set by option byte.
Clock output
Operable
Buzzer output
A/D converter
Serial interface
UART0
UART6
CSI10
CSI11
CSIA0
IIC0
Multiplier/divider
Power-on-clear function
Low-voltage detection function
External interrupt
Remarks 1.
2.
fRH:
fX: X1 clock
See 1.7
Outline of
Functions.
657
Item
System clock
fRH
fX
Subsystem clock
fEXCLK
fXT
fEXCLKS
fRL
CPU
Flash memory
RAM
Port (latch)
16-bit timer/event
counter
00
Note
01
Note
8-bit timer/event
counter
50
Note
51
Note
8-bit timer
H0
Operable
H1
Watch timer
Watchdog timer
Operable. Clock supply to watchdog timer stops when internal low-speed oscillator can be
stopped by software is set by option byte.
Clock output
Operable
Buzzer output
Operable. However, operation disabled when peripheral hardware clock (fPRS) is stopped.
A/D converter
Serial interface
UART0
Operable
UART6
CSI10
Note
CSI11
Note
CSIA0
IIC0
Note
Note
Multiplier/divider
Power-on-clear function
Low-voltage detection function
External interrupt
Note When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock and highspeed system clock have been stopped, do not start operation of these functions on the external clock input
from peripheral hardware pins.
Remarks 1.
2.
fRH:
fX: X1 clock
See 1.7
Functions.
658
Outline of
HALT
instruction
Interrupt
request
Standby
release signal
Status of CPU
Normal operation
WaitNote 1
HALT mode
Normal operation
Oscillation
8 or 9 clocks
The broken lines indicate the case when the interrupt request which has released the standby
mode is acknowledged.
659
Reset signal
Status of CPU
High-speed
system clock
(X1 oscillation)
Normal operation
(high-speed
system clock)
HALT mode
Reset
Reset processing
period (11 to 45 s)
Normal operation
(internal high-speed
oscillation clock)
Oscillation Oscillation
stopped stopped
Oscillates
Oscillates
Oscillation stabilization time
(211/fX to 216/fX)
Starting X1 oscillation is
specified by software.
Reset signal
Normal operation
(internal high-speed
oscillation clock)
Status of CPU
Internal high-speed
oscillation clock
HALT mode
Oscillates
Reset
Reset processing
period (11 to 45 s)
Normal operation
(internal high-speed
oscillation clock)
Oscillation
stopped
Oscillates
Status of CPU
Subsystem clock
(XT1 oscillation)
Normal operation
(subsystem clock)
HALT mode
Oscillates
Reset
period
Reset
Normal operation mode
processing
(internal high-speed
(11 to 45 s)
oscillation clock)
Oscillation Oscillation
stopped
stopped Oscillates
Note
660
MK
PR
IE
ISP
request
Operation
Next address
instruction execution
Next address
instruction execution
Interrupt servicing
Interrupt servicing
execution
execution
Reset
Reset processing
: dont care
22.2.2 STOP mode
(1) STOP mode setting and operating statuses
The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the
setting was the main system clock.
Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt
source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is
immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after
execution of the STOP instruction and the system returns to the operating mode as soon as the
wait time set using the oscillation stabilization time select register (OSTS) has elapsed.
The operating statuses in the STOP mode are shown below.
661
When STOP Instruction Is Executed While CPU Is Operating on Main System Clock
When CPU Is Operating on
Internal High-Speed
Oscillation Clock (fRH)
Item
System clock
Stopped
fRH
fX
fEXCLK
Subsystem clock
Input invalid
fXT
fEXCLKS
fRL
CPU
Flash memory
RAM
Port (latch)
16-bit timer/event
counter
00
Note 1
01
Note 1
Operation stopped
8-bit timer/event
counter
50
Note 1
51
Note 1
8-bit timer
H0
Operable only when TM50 output is selected as the count clock during 8-bit timer/event counter
50 operation
H1
Operable only when fRL, fRL/2 , fRL/2 is selected as the count clock
Watch timer
Watchdog timer
Operable. Clock supply to watchdog timer stops when internal low-speed oscillator can be
stopped by software is set by option byte.
Clock output
Buzzer output
Operation stopped
A/D converter
Serial interface
UART0
UART6
CSI10
Note 1
CSI11
Note 1
CSIA0
IIC0
Note 1
Note 1
Operable only when TM50 output is selected as the serial clock during 8-bit timer/event counter
50 operation
Operable only when external clock is selected as the serial clock
Operation stopped
Operable only when the external clock from EXSCL0/P62 pin is selected as the serial clock
Multiplier/divider
Operation stopped
Power-on-clear function
Operable
Note 2
Notes 1. Do not start operation of these functions on the external clock input from peripheral hardware pins in the
stop mode.
2. The operation of 78K0/KB2 products is stopped (The external clock from the EXSCL0/P62 pin cannot be
selected, because the EXSCL0/P62 pin is not mounted.).
Remarks 1.
2.
662
Outline of
Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral
hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is
released, restart the peripheral hardware.
2. Even if internal low-speed oscillator can be stopped by software is selected by the option
byte, the internal low-speed oscillation clock continues in the STOP mode in the status before
the STOP mode is set. To stop the internal low-speed oscillators oscillation in the STOP mode,
stop it by software and then execute the STOP instruction.
3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates
with the high-speed system clock (X1 oscillation), switch the CPU clock to the internal highspeed oscillation clock before the execution of the STOP instruction using the following
procedure.
<1> Set RSTOP to 0 (starting oscillation of the internal high-speed oscillator) <2> Set MCM0
to 0 (switching the CPU from X1 oscillation to internal high-speed oscillation) <3> Check that
MCS is 0 (checking the CPU clock) <4> Check that RSTS is 1 (checking internal high-speed
oscillation operation) <5> Execute the STOP instruction
Before changing the CPU clock from the internal high-speed oscillation clock to the high-speed
system clock (X1 oscillation) after the STOP mode is released, check the oscillation stabilization
time with the oscillation stabilization time counter status register (OSTC).
4. If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is stopped for 4.06
to 16.12 s after the STOP mode is released when the internal high-speed oscillation clock is
selected as the CPU clock, or for the duration of 160 external clocks when the high-speed
system clock (external clock input) is selected as the CPU clock.
663
STOP mode
High-speed system
clock (X1 oscillation)
High-speed system
clock (external clock
input)
Internal high-speed
oscillation clock
High-speed system
clock (X1 oscillation)
is selected as CPU
clock when STOP
instruction is executed
High-speed system
clock (external clock
input) is selected as
CPU clock when STOP
instruction is executed
Internal high-speed
oscillation clock is
selected as CPU clock
when STOP instruction
is executed
WaitNote2
Supply of the CPU clock is stopped (160 external clocks)Note1
Internal high-speed
oscillation clock
WaitNote2
8 or 9 clocks
2 or 3 clocks
stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried
out. If interrupt acknowledgment is disabled, the next address instruction is executed.
664
STOP
instruction
Wait
(set by OSTS)
Normal operation
(high-speed
system clock)
STOP mode
Oscillates
Oscillation stopped
Normal operation
(high-speed
system clock)
(2) When high-speed system clock (external clock input) is used as CPU clock
When AMPH = 1
STOP
instruction
Interrupt
request
Status of CPU
High-speed
system clock
(external clock input)
Normal operation
(high-speed
system clock)
STOP mode
Oscillates
Oscillation stopped
(160 external
clocks)
WaitNote
Normal operation
(high-speed
system clock)
Oscillates
When AMPH = 0
STOP
instruction
Interrupt
request
Status of CPU
High-speed
system clock
(external clock input)
Note
Normal operation
(high-speed
system clock)
STOP mode
Oscillates
Oscillation stopped
WaitNote
Normal operation
(high-speed
system clock)
Oscillates
8 or 9 clocks
2 or 3 clocks
Remark The broken lines indicate the case when the interrupt request that has released the standby mode
is acknowledged.
665
Interrupt
request
Status of CPU
Internal high-speed
oscillation clock
Normal operation
(internal high-speed
oscillation clock)
STOP mode
Oscillates
Oscillation stopped
WaitNote
Normal operation
(internal high-speed
oscillation clock)
(4.06 to 16.12 s)
Oscillates
Wait for oscillation
accuracy stabilization
(86 to 361 s)
When AMPH = 0
STOP
instruction
Interrupt
request
Status of CPU
Internal high-speed
oscillation clock
Normal operation
(internal high-speed
oscillation clock)
Oscillates
STOP mode
WaitNote
Oscillation stopped
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Note
8 or 9 clocks
2 or 3 clocks
Remark The broken lines indicate the case when the interrupt request that has released the standby mode
is acknowledged.
666
Reset signal
Status of CPU
Normal operation
(high-speed
system clock)
High-speed
system clock
(X1 oscillation)
STOP mode
Oscillation stopped
Oscillates
Reset
period
Reset
processing
(11 to 45 s)
Normal operation
(internal high-speed
oscillation clock)
Oscillation Oscillation
stopped stopped
Oscillates
Status of CPU
Internal high-speed
oscillation clock
Normal operation
(internal high-speed
oscillation clock)
Reset
Reset processing
period (11 to 45 s)
STOP mode
Oscillation
Oscillation stopped stopped
Oscillates
Normal operation
(internal high-speed
oscillation clock)
Oscillates
MK
PR
IE
ISP
request
Operation
Next address
instruction execution
Interrupt servicing
execution
Next address
instruction execution
Interrupt servicing
execution
Reset
Reset processing
: dont care
667
internal low-speed oscillation clock stop oscillating. External main system clock input and
external subsystem clockNote 1 input become invalid.
3. When the STOP mode is released by a reset, the STOP mode contents are held during reset
input. However, the port pins become high-impedance, except for P130Note 2, which is set to
low-level output.
Notes 1.
2.
668
The 78K0/KB2 is not provided with XT1 clock and external subsystem clock.
P130 pin is not mounted onto 38-pin and 44-pin products of the 78K0/KC2 and 78K0/KB2.
WDTRF
LVIRF
Set
Set
Watchdog timer reset signal
Clear
Caution An LVI circuit internal reset does not reset the LVI circuit.
Remarks 1. LVIM: Low-voltage detection register
2. LVIS: Low-voltage detection level selection register
Reset signal
RESET
Clear
669
Reset period
(oscillation stop)
Normal operation
Reset
processing
(11 to 45 s)
Normal operation
(internal high-speed oscillation clock)
RESET
Delay
(5 s (TYP.))
Port pin
(except P130)
Hi-Z
Port pin
(P130Note 1)
Notes 1.
2.
Remark
Note 2
P130 pin is not mounted onto 38-pin and 44-pin products of the 78K0/KC2 and 78K0/KB2.
Set P130 to high-level output by software.
When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
670
Normal operation
Reset period
(oscillation stop)
Reset
processing
(11 to 45 s)
Normal operation
(internal high-speed oscillation clock)
Watchdog timer
overflow
Port pin
(except P130)
Hi-Z
Port pin
(P130Note 1)
Notes 1.
2.
Note 2
P130 pin is not mounted onto 38-pin and 44-pin products of the 78K0/KC2 and 78K0/KB2.
Set P130 to high-level output by software.
When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
671
Internal high-speed
oscillation clock
Starting X1 oscillation is specified by software.
High-speed system clock
(when X1 oscillation is selected)
CPU clock
Normal
operation
Stop status
(oscillation stop)
Reset period
(oscillation stop)
Reset
processing
Normal operation
(internal high-speed oscillation clock)
(11 to 45 s)
RESET
Delay
Port pin
(except P130)
Delay
(5 s (TYP.))
Port pin
(P130Note 1)
Notes 1.
2.
Hi-Z
Note 2
P130 pin is not mounted onto 38-pin and 44-pin products of the 78K0/KC2 and 78K0/KB2.
Set P130 to high-level output by software.
Remarks 1. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
2. For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 24
POWER-ON-CLEAR CIRCUIT and CHAPTER 25 LOW-VOLTAGE DETECTOR.
672
System clock
Subsystem clock
fRH
Operation stopped
fX
fEXCLK
fXT
fEXCLKS
fRL
Operation stopped
CPU
Flash memory
RAM
Port (latch)
16-bit timer/event
00
counter
01
8-bit timer/event
50
counter
51
8-bit timer
H0
H1
Watch timer
Watchdog timer
Clock output
Buzzer output
A/D converter
Serial interface
UART0
UART6
CSI10
CSI11
CSIA0
IIC0
Multiplier/divider
Power-on-clear function
Operable
Operation stopped
External interrupt
Remarks 1.
2.
fRH:
fX: X1 clock
See 1.7
Outline of
Functions.
673
After Reset
Note 1
Acknowledgment
Undefined
02H
RAM
Data memory
Undefined
Note 2
General-purpose registers
Undefined
Note 2
00H
FFH
Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU12, PU14)
00H
0CH
CFH
Notes 1.
2.
3.
Note 3
Note 3
During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
When a reset is executed in the standby mode, the pre-reset status is held even after reset.
The initial values of the internal memory size switching register (IMS) and internal expansion RAM size
switching register (IXS) after a reset release are constant (IMS = CFH, IXS = 0CH) in all products of the
78K0/Kx2 microcontrollers, regardless of the internal memory capacity. Therefore, after a reset is
released, be sure to set the following values for each product.
78K0/KB2
78K0/KB2
IMS
ROM Capacity
Internal High-Speed
RAM Capacity
PD78F0500A
42H
8 KB
512 bytes
PD78F0501A
04H
16 KB
768 bytes
PD78F0502A
C6H
24 KB
1 KB
PD78F0503A, 78F0503DANote 4
C8H
32 KB
1 KB
PD78F05x1A (x = 1 to 3)
IMS
04H
IXS
0CH
ROM Capacity
16 KB
Internal
Expansion RAM
Capacity
768 bytes
PD78F05x2A (x = 1 to 3)
C6H
0CH
24 KB
1 KB
PD78F05x3A (x = 1 to 3),
C8H
0CH
32 KB
1 KB
1 KB
78F0513DA
Note 5
PD78F05x4A (x = 1 to 4)
CCH
0AH
48 KB
PD78F05x5A (x = 1 to 4),
CFH
08H
60 KB
78F0515DA
1 KB
2 KB
Note 5
PD78F05x6A (x = 2 to 4)
CCH
04H
96 KB
4 KB
PD78F05x7A, 78F05x7DANote 5
CCH
00H
128 KB
6 KB
(x = 2 to 4)
4.
5.
Remark
674
The ROM and RAM capacities of the products with the on-chip debug function of 78K0/KB2 can be debugged
by setting IMS, according to the debug target products. Set IMS according to the debug target products.
The ROM and RAM capacities of the products with the on-chip debug function of 78K0/KC2, 78K0/KD2,
78K0/KE2, and 78K0/KF2 can be debugged by setting IMS and IXS, according to the debug target
products. Set IMS and IXS according to the debug target products.
The functions mounted depend on the product. See 3.2.3 Special function registers (SFRs).
Users Manual U18598EJ1V0UD
00H
00H
01H
80H
80H
00H
00H
05H
16-bit timer/event
counters 00, 01
0000H
0000H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Note 2
00H
Watch timer
00H
Clock output/buzzer
output controller
00H
Watchdog timer
1AH/9AH
A/D converter
0000H
Notes 1.
Note 1
00H
00H
00H
00H
FFH
FFH
01H
00H
1FH
Note 3
During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
2.
3.
Remark
See 3.2.3
Special function
registers (SFRs).
Users Manual U18598EJ1V0UD
675
Hardware
Acknowledgment
Serial interface UART6
FFH
FFH
01H
00H
00H
00H
FFH
16H
00H
00H
CSI11
00H
00H
00H
00H
00H
00H
Multiplier/divider
Key interrupt
Note
03H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
0000H
0000H
0000H
00H
00H
Note
During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
Remark
676
See 3.2.3
Special function
Hardware
Acknowledgment
Note 2
Reset function
00H
Low-voltage detector
00H
00H
Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H)
00H
Mask flag registers 0L, 0H, 1L, 1H (MK0L, MK0H, MK1L, MK1H)
FFH
Priority specification flag registers 0L, 0H, 1L, 1H (PR0L, PR0H, PR1L,
FFH
Interrupt
Note 1
Note 2
Note 2
PR1H)
Notes 1.
00H
00H
During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
2.
RESET Input
Reset by POC
Reset by WDT
Reset by LVI
Register
RESF
Cleared (0)
LVIRF flag
LVIM
Cleared (00H)
Cleared (00H)
Set (1)
Held
Held
Set (1)
Cleared (00H)
Held
LVIS
Remark
See 3.2.3
Special function
registers (SFRs).
677
Note
Symbol
RESF
WDTRF
LVIRF
WDTRF
LVIRF
Note The value after reset varies depending on the reset source.
Caution Do not read data by a 1-bit memory manipulation instruction.
The status of RESF when a reset request is generated is shown in Table 23-3.
Table 23-3. RESF Status When Reset Request Is Generated
Reset Source
RESET Input
Reset by POC
Reset by WDT
Reset by LVI
Flag
WDTRF
LVIRF
678
Cleared (0)
Cleared (0)
Set (1)
Held
Held
Set (1)
679
Reference
voltage
source
detection voltage (VPOC = 1.59 V 0.15 V), the reset status is released.
The supply voltage (VDD) and detection voltage (VPOC = 1.59 V 0.15 V) are compared. When VDD < VPOC, the
internal reset signal is generated. It is released when VDD VPOC.
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
An internal reset signal is generated on power application.
detection voltage (VDDPOC = 2.7 V 0.2 V), the reset status is released.
The supply voltage (VDD) and detection voltage (VPOC = 1.59 V 0.15 V) are compared. When VDD < VPOC, the
internal reset signal is generated. It is released when VDD VDDPOC.
The timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is
shown below.
680
Set LVI to be
used for interrupt
Set LVI to be
used for reset
Supply voltage
(VDD)
VLVI
1.8 VNotes 1, 2
VPOC = 1.59 V (TYP.)
0V
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Note 3
Note 3
Internal high-speed
oscillation clock (fRH)
Starting oscillation is
specified by software.
High-speed
system clock (fXH)
(when X1 oscillation
is selected)
Operation
CPU
stops
Starting oscillation is
specified by software.
Starting oscillation is
specified by software.
Normal operation
Reset period Wait for voltage
(internal high-speed (oscillation
stabilization
oscillation clock)Note 4
(1.93 to 5.39 ms)
stop)
Normal operation
(internal high-speed
oscillation clock)Note 4
Operation stops
Notes 1.
guaranteed operation range to the reset state when the supply voltage falls, use the reset function of
the low-voltage detector, or input a low level to the RESET pin.
2.
If the voltage rises to 1.8 V at a rate slower than 0.5 V/ms (MIN.) on power application, input a low level
to the RESET pin after power application and before the voltage reaches 1.8 V, or set the 2.7 V/1.59 V
POC mode by using an option byte (POCMODE = 1).
3.
The oscillation accuracy stabilization time of the internal high-speed oscillation clock is included in the
internal voltage stabilization time.
4.
The CPU clock can be switched from the internal high-speed oscillation clock to the high-speed system
clock or to the subsystem clockNote 5. To use the X1 clock, use the OSTC register to confirm the lapse
of the oscillation stabilization time. To use the XT1 clock
Note 5
The 78K0/KB2 is not provided with subsystem clock and XT1 clock.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 25
LOW-VOLTAGE DETECTOR).
Remark
681
Set LVI to be
used for interrupt
Set LVI to be
used for reset
Supply voltage
(VDD)
VLVI
VDDPOC = 2.7 V (TYP.)
1.8 VNote 1
VPOC = 1.59 V (TYP.)
0V
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Internal high-speed
oscillation clock (fRH)
Starting oscillation is
specified by software.
High-speed
system clock (fXH)
(when X1 oscillation
is selected)
CPU
Operation
stops
Starting oscillation is
specified by software.
Starting oscillation is
specified by software.
Normal operation
(internal high-speed
oscillation clock)Note 2
Reset period
(oscillation
stop)
Normal operation
(internal high-speed
oscillation clock)Note 2
Operation stops
Notes 1.
guaranteed operation range to the reset state when the supply voltage falls, use the reset function of
the low-voltage detector, or input a low level to the RESET pin.
2.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clockNote 3 can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clockNote 3, use the timer function for confirmation of the
lapse of the stabilization time.
3.
The 78K0/KB2 is not provided with subsystem clock and XT1 clock.
Cautions 1. Set the low-voltage detector by software after the reset status is released (see CHAPTER 25
LOW-VOLTAGE DETECTOR).
2. A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply voltage
reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93
ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated
before reset processing.
Remark
682
Reset
Initialization
processing <1>
Power-on-clear
Clearing WDT
Note 1
No
50 ms has passed?
(TMIFH1 = 1?)
Yes
; Setting of division ratio of system clock,
such as setting of timer or A/D converter
Initialization
processing <2>
Notes 1.
2.
If reset is generated again during this period, initialization processing <2> is not started.
A flowchart is shown on the next page.
683
WDTRF of RESF
register = 1?
Yes
No
Reset processing by
watchdog timer
LVIRF of RESF
register = 1?
Yes
No
Reset processing by
low-voltage detector
Power-on-clear/external
reset generated
684
(LVISEL = 0)
VDD VLVI.
(VDD VLVI).
Remark
While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input
pin is more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0
of LVIM).
When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if
reset occurs. For details of RESF, see CHAPTER 23 RESET FUNCTION.
685
N-ch
Selector
EXLVI/P120/
INTP0
Selector
Low-voltage detection
level selector
VDD
INTLVI
Reference
voltage
source
LVIF
686
Address: FFBEH
R/WNote 2
Symbol
<7>
<2>
<1>
<0>
LVIM
LVION
LVISEL
LVIMD
LVIF
Notes 3, 4
LVION
Disables operation
Enables operation
Note 3
LVISEL
LVIMD
lower than the detection voltage (VLVI) (VDD < VLVI) or when VDD becomes
VLVI or higher (VDD VLVI).
LVISEL = 1: Generates an interrupt signal when the input voltage from an external
input pin (EXLVI) drops lower than the detection voltage (VEXLVI) (EXLVI <
VEXLVI) or when EXLVI becomes VEXLVI or higher (EXLVI VEXLVI).
LVISEL = 0: Generates an internal reset signal when the supply voltage (VDD) <
detection voltage (VLVI) and releases the reset signal when VDD VLVI.
LVISEL = 1: Generates an internal reset signal when the input voltage from an
external input pin (EXLVI) < detection voltage (VEXLVI) and releases the
reset signal when EXLVI VEXLVI.
LVIF
disabled
LVISEL = 1: Input voltage from external input pin (EXLVI) detection voltage (VEXLVI),
or when operation is disabled
LVISEL = 0: Supply voltage (VDD) < detection voltage (VLVI)
LVISEL = 1: Input voltage from external input pin (EXLVI) < detection voltage (VEXLVI)
Notes 1.
2.
3.
This bit is cleared to 00H upon a reset other than an LVI reset.
Bit 0 is read-only.
LVION, LVIMD, and LVISEL are cleared to 0 in the case of a reset other than an LVI reset.
These are not cleared to 0 in the case of an LVI reset.
4.
When LVION is set to 1, operation of the comparator in the LVI circuit is started.
Use
software to wait for an operation stabilization time (10 s (MAX.)) from when LVION is set to 1
until operation is stabilized. After operation has stabilized, 200 s (MIN.) are required from
when a state below LVI detection voltage has been entered, until LVIF is set (1).
Cautions 1. To stop LVI, follow either of the procedures below.
When using 8-bit memory manipulation instruction: Write 00H to LVIM.
When using 1-bit memory manipulation instruction: Clear LVION to 0.
2. Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
3. When using LVI as an interrupt, if LVION is cleared (0) in a state below the LVI
detection voltage, an INTLVI signal is generated and LVIIF becomes 1.
Users Manual U18598EJ1V0UD
687
Address: FFBFH
R/W
Symbol
LVIS
LVIS3
LVIS2
LVIS1
LVIS0
LVIS3
LVIS2
LVIS1
LVIS0
Note
Detection level
The value of LVIS is not reset but retained as is, upon a reset by LVI. It is cleared to 00H upon
other resets.
688
R/W
Symbol
PM12
PM124
PM123
PM122
PM121
PM120
PM12n
Remark The format of port mode register 12 of 78K0/KB2 products is different from the
above format. See 5.3 Registers Controlling Port Function (1) Port mode
registers (PMxx).
689
690
Time
LVIMK flag Note 1
(set by software) H
<1>
LVISEL flag
(set by software) L
LVION flag
(set by software)
<3>
<2>
Not cleared
Not cleared
<4>
Clear
<5> Wait time
LVIF flag
<6>
LVIMD flag
(set by software)
Clear
Note 2
Not cleared
Not cleared
<7>
Clear
LVIRF flagNote 3
Cleared by
software
Notes 1.
2.
3.
Remark
<1> to <7> in Figure 25-5 above correspond to <1> to <7> in the description of When starting
operation in 25.4.1 (1) When detecting level of supply voltage (VDD).
691
Time
LVIMK flag
(set by software)
HNote 1
LVISEL flag
(set by software)
LVION flag
(set by software)
<1>
<3>
<2>
Not cleared
Not cleared
<4>
Clear
<5> Wait time
LVIF flag
<6>
LVIMD flag
(set by software)
Clear
Note 2
Not cleared
Not cleared
<7>
Clear
LVIRF flagNote 3
Cleared by
software
Notes 1.
2.
3.
Remark
<1> to <7> in Figure 25-5 above correspond to <1> to <7> in the description of When starting
operation in 25.4.1 (1) When detecting level of supply voltage (VDD).
692
(2) When detecting level of input voltage from external input pin (EXLVI)
When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from
external input pin (EXLVI)).
<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<4> Use software to wait for an operation stabilization time (10 s (MAX.)Note).
<5> Wait until it is checked that (input voltage from external input pin (EXLVI) detection voltage (VEXLVI =
1.21 V (TYP.))) by bit 0 (LVIF) of LVIM.
<6> Set bit 1 (LVIMD) of LVIM to 1 (generates reset signal when the level is detected).
Figure 25-6 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers
in this timing chart correspond to <1> to <6> above.
Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately
after the processing in <3>.
2. If input voltage from external input pin (EXLVI) detection voltage (VEXLVI = 1.21 V (TYP.))
when LVIMD is set to 1, an internal reset signal is not generated.
3. Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
When stopping operation
Either of the following procedures must be executed.
693
Time
LVIMK flag
(set by software)
LVISEL flag
(set by software)
HNote 1
<1>
Not cleared
Not cleared
Not cleared
Not cleared
Not cleared
Not cleared
Not cleared
Not cleared
<2>
LVION flag
(set by software)
<3>
Note 2
Not cleared
<6>
LVIRF flagNote 3
Cleared by
software
Notes 1.
2.
3.
LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 23
RESET FUNCTION.
Remark
<1> to <6> in Figure 25-6 above correspond to <1> to <6> in the description of When starting
operation in 25.4.1 (2) When detecting level of input voltage from external input pin (EXLVI).
694
695
Note 3
Note 3
Time
LVIMK flag
(set by software)
<1>
Note 1
LVISEL flag
(set by software)
LVION flag
(set by software)
<2>
<5>
<6> Wait time
LVIF flag
<7>
Note 2
INTLVI
Note 2
LVIIF flag
Note 2
LVIMD flag
(set by software) L
<8>
Cleared by software
<4>
Internal reset signal
Notes 1.
2.
The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1).
3.
If LVION is cleared (0) in a state below the LVI detection voltage, an INTLVI signal is generated and
LVIIF becomes 1.
Remark
<1> to <9> in Figure 25-7 above correspond to <1> to <9> in the description of When starting
operation in 25.4.2 (1) When detecting level of supply voltage (VDD).
696
Note 3
Note 3
Time
LVIMK flag
(set by software)
<1>
Note 1
LVISEL flag
(set by software)
L
<2>
LVION flag
(set by software)
<5>
<6> Wait time
LVIF flag
<7>
Note 2
INTLVI
Note 2
LVIIF flag
LVIMD flag
(set by software)
Note 2
<8>
Cleared by software
L
<4>
Notes 1.
2.
The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1).
3.
If LVION is cleared (0) in a state below the LVI detection voltage, an INTLVI signal is generated and
LVIIF becomes 1.
Remark
<1> to <9> in Figure 25-7 above correspond to <1> to <9> in the description of When starting
operation in 25.4.2 (1) When detecting level of supply voltage (VDD).
697
(2) When detecting level of input voltage from external input pin (EXLVI)
When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from
external input pin (EXLVI)).
<3> Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value).
<4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<5> Use software to wait for an operation stabilization time (10 s (MAX.)).
<6> Confirm that input voltage from external input pin (EXLVI) detection voltage (VEXLVI = 1.21 V (TYP.)
when detecting the falling edge of EXLVI, or input voltage from external input pin (EXLVI) < detection
voltage (VEXLVI = 1.21 V (TYP.) when detecting the rising edge of EXLVI, at bit 0 (LVIF) of LVIM.
<7> Clear the interrupt request flag of LVI (LVIIF) to 0.
<8> Release the interrupt mask flag of LVI (LVIMK).
<9> Execute the EI instruction (when vector interrupts are used).
Figure 25-8 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in
this timing chart correspond to <1> to <8> above.
Caution Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
When stopping operation
Either of the following procedures must be executed.
698
Note 3
Note 3
Time
LVIMK flag
(set by software)
<1>
Note 1
LVISEL flag
(set by software)
LVION flag
(set by software)
<2>
<4>
<5> Wait time
LVIF flag
<6>
Note 2
INTLVI
Note 2
LVIIF flag
Note 2
LVIMD flag
(set by software) L
<7>
Cleared by software
<3>
Notes 1.
2.
The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1).
3.
If LVION is cleared (0) in a state below the LVI detection voltage, an INTLVI signal is generated and
LVIIF becomes 1.
Remark
<1> to <8> in Figure 25-8 above correspond to <1> to <8> in the description of When starting
operation in 25.4.2 (2) When detecting level of input voltage from external input pin (EXLVI).
699
700
Initialization
processing <1>
LVI reset
Setting LVI
Clearing WDT
Detection
voltage or higher
(LVIF = 0?)
No
Restarting timer H1
(TMHE1 = 0 TMHE1 = 1)
No
Yes
50 ms has passed?
(TMIFH1 = 1?)
Yes
Initialization
processing <2>
701
WDTRF of RESF
register = 1?
Yes
No
Reset processing by
watchdog timer
LVIRF of RESF
register = 1?
No
Yes
Power-on-clear/external
reset generated
Reset processing by
low-voltage detector
702
703
(3) 0084H/1084H
{ On-chip debug operation control
Disabling on-chip debug operation
Enabling on-chip debug operation and erasing data of the flash memory in case authentication of the onchip debug security ID fails
Enabling on-chip debug operation and not erasing data of the flash memory even in case authentication of
the on-chip debug security ID fails
Cautions 1. Be sure to set 00H (disabling on-chip debug operation) to 0084H for products not
equipped with the on-chip debug function (PD78F05xxA).
because 0084H and 1084H are switched during the boot operation.
2. To use the on-chip debug function with a product equipped with the on-chip debug
function (PD78F05xxDA), set 02H or 03H to 0084H. Set a value that is the same as that
of 0084H to 1084H because 0084H and 1084H are switched during the boot operation.
704
Address: 0080H/1080H
7
WINDOW1
WINDOW0
WDTON
WDCS2
WDCS1
WDCS0
LSROSC
WINDOW1
WINDOW0
25%
50%
75%
100%
WDTON
Counter operation disabled (counting stopped after reset), illegal access detection operation
disabled
Counter operation enabled (counting started after reset), illegal access detection operation enabled
WDCS2
WDCS1
WDCS0
LSROSC
17
Can be stopped by software (stopped when 1 is written to bit 1 (LSRSTOP) of RCM register)
Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the
boot swap operation.
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is
prohibited.
2. Setting WINDOW1 = WINDOW0 = 0 is prohibited when using the watchdog timer at 1.8 V VDD
< 2.7 V.
3. The watchdog timer continues its operation during self-programming and EEPROM
emulation of the flash memory. During processing, the interrupt acknowledge time is
delayed. Set the overflow time and window size taking this delay into consideration.
4. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the
watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (LSRSTOP) of
the internal oscillation mode register (RCM).
When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count clock is
supplied to 8-bit timer H1 even in the HALT/STOP mode.
5. Be sure to clear bit 7 to 0.
Remarks 1.
2.
705
Address: 0081H/1081H
7
POCMODE
POCMODE
Notes 1.
POCMODE can only be written by using a dedicated flash memory programmer. It cannot be set
during self-programming or boot swap operation during self-programming (at this time, 1.59 V POC
mode (default) is set). However, because the value of 1081H is copied to 0081H during the boot swap
operation, it is recommended to set a value that is the same as that of 0081H to 1081H when the boot
swap function is used.
2.
To change the setting for the POC mode, set the value to 0081H again after batch erasure (chip
erasure) of the flash memory. The setting cannot be changed after the memory of the specified block
is erased.
Note Be sure to set 00H to 0082H and 0083H, as these addresses are reserved areas. Also set 00H to 1082H
and 1083H because 0082H and 0083H are switched with 1082H and 1083H when the boot swap operation
is used.
Notes1, 2
Address: 0084H/1084H
Notes 1.
OCDEN1
OCDEN0
OCDEN1
OCDEN0
Operation disabled
Setting prohibited
Operation enabled. Does not erase data of the flash memory in case authentication
of the on-chip debug security ID fails.
Operation enabled. Erases data of the flash memory in case authentication of the
on-chip debug security ID fails.
Be sure to set 00H (on-chip debug operation disabled) to 0084H for products not equipped with the onchip debug function (PD78F05xxA). Also set 00H to 1084H because 0084H and 1084H are switched
during the boot swap operation.
2.
To use the on-chip debug function with a product equipped with the on-chip debug function
(PD78F05xxDA), set 02H or 03H to 0084H. Set a value that is the same as that of 0084H to 1084H
because 0084H and 1084H are switched during the boot swap operation.
Remark
For the on-chip debug security ID, see CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F05xxDA
ONLY).
706
Here is an example of description of the software for setting the option bytes.
OPT
CSEG
OPTION: DB
AT 0080H
30H
Remark
DB
00H
DB
00H
; Reserved area
DB
00H
; Reserved area
DB
00H
Referencing of the option byte is performed during reset processing. For the reset processing timing,
see CHAPTER 23 RESET FUNCTION.
707
The 78K0/Kx2 microcontrollers incorporates the flash memory to which a program can be written, erased, and
overwritten while mounted on the board.
Symbol
RAM2
RAM1
RAM0
ROM3
ROM2
ROM1
ROM0
RAM2
RAM1
RAM0
768 bytes
512 bytes
1024 bytes
IMS
R/W
Setting prohibited
ROM3
ROM2
ROM1
ROM0
8 KB
16 KB
24 KB
32 KB
48 KB
60 KB
Setting prohibited
Caution To set the memory size, set IMS and then IXS. Set the memory size so that the internal ROM and
internal expansion RAM areas do not overlap.
708
IMS Setting
PD78F0500A
42H
PD78F05x1A (x = 0 to 3)
04H
PD78F05x2A (x = 0 to 3)
C6H
C8H
PD78F05x4A (x = 1 to 4)
CCH
CFH
PD78F05x6A (x = 2 to 4)
CCH
PD78F05x7A, 78F05x7DA
Notes 1.
Note 1
Note 2
Note 2
(x = 2 to 4)
CCH
The internal ROM capacity and internal high-speed RAM capacity of the products with the on-chip
debug function can be debugged according to the debug target products. Set IMS according to the
debug target products.
The PD78F05x6A (x = 2 to 4) has internal ROMs of 96 KB, and the PD78F05x7A and 78F05x7DA
2.
(x = 2 to 4) have those of 128 KB. However, the set value of IMS of these devices is the same as
those of the 48 KB product because memory banks are used. For how to set the memory banks, see
4.3 Memory Bank Select Register (BANK).
Be sure to set each product to the values shown in Table 27-2 after a reset release.
The 78K0/KB2 is not provided with IXS register.
Figure 27-2. Format of Internal Expansion RAM Size Switching Register (IXS)
Address: FFF4H
R/W
Symbol
IXS
IXRAM4
IXRAM3
IXRAM2
IXRAM1
IXRAM0
IXRAM4
IXRAM3
IXRAM2
IXRAM1
IXRAM0
0 bytes
1024 bytes
2048 bytes
4096 bytes
6144 bytes
Setting prohibited
Caution To set memory size, set IMS and then IXS. Set memory size so that the internal ROM area and
internal expansion RAM area do not overlap.
709
PD78F05x2A (x = 1 to 3)
0CH
0CH
PD78F05x4A (x = 1 to 4)
0AH
08H
PD78F05x6A (x = 2 to 4)
04H
PD78F05x7A, 78F05x7DA
Note
IXS Setting
PD78F05x1A (x = 1 to 3)
Note
(x = 2 to 4)
00H
The internal expansion RAM capacity of the products with the on-chip debug function of 78K0/KC2,
78K0/KD2, 78K0/KE2, and 78K0/KF2 can be debugged according to the debug target products. Set IXS
according to the debug target products.
710
STATVE
VSS
XXXXX
XXXX YYYY
Axxxx
Bxxxxx
Cxxxxxx
XXX YYY
RS-232C
USB
RESET
Dedicated flash
memory programmer
CSI10/UART6
78K0/Kx2
microcontrollers
Host machine
A host machine that controls the dedicated flash memory programmer is necessary.
To interface between the dedicated flash memory programmer and the 78K0/Kx2 microcontrollers, CSI10 or
UART6 is used for manipulation such as writing and erasing. To write the flash memory off-board, a dedicated
program adapter (FA series) is necessary.
VSS/EVSS/AVSS
XXXXXX
XXXX
Bxxxxx
Cxxxxxx
STATVE
XXXXX
XXX YYY
XXXX YYYY
Axxxx
FLMD0
VDD/EVDD/AVREF
Dedicated flash
memory programmer
/RESET
RESET
SI/RxD
SO10
SO/TxD
SI10
SCK
SCK10
78K0/Kx2
microcontrollers
711
(2) UART6
Transfer rate: 115200 bps
Figure 27-5. Communication with Dedicated Flash memory programmer (UART6)
FLMD0
FLMD0
VDD
VDD/EVDD/AVREF
GND
XXX YYY
XXXXXX
VSS/EVSS/AVSS
RESET
/RESET
XXXX
STATVE
XXXXX
XXXX YYYY
Axxxx
Bxxxxx
Cxxxxxx
Dedicated flash
memory programmer
SI/RxD
TxD6
SO/TxD
RxD6
CLKNote
EXCLKNote
78K0/Kx2
microcontrollers
Note The above figure illustrates an example of wiring when using the clock output from the PG-FP5, FL-PR5,
PG-FP4 or FL-PR4.
When using the clock output from the PG-FPL3 or FP-LITE3, connect CLK to X1/P121, and connect its
inverted signal to X2/EXCLK/P122.
CLK
X1
X2
The dedicated flash memory programmer generates the following signals for the 78K0/Kx2 microcontrollers. For
details, refer to the users manual for the PG-FP5, FL-PR5, PG-FP4, FL-PR4, PG-FPL3, or FP-LITE3.
Table 27-3. Pin Connection
Dedicated Flash memory programmer
78K0/Kx2
Connection
microcontrollers
Signal Name
I/O
Pin Function
Pin Name
FLMD0
Output
Mode signal
FLMD0
VDD
I/O
Ground
Note 1
GND
CLK
Output
/RESET
Output
Reset signal
RESET
SI/RxD
Input
Receive signal
SO10/TxD6
SO/TxD
Output
Transmit signal
SI10/RxD6
SCK
Output
Transfer clock
SCK10
Notes 1.
2.
Remark
712
CSI10
Note 2
UART6
Note 1
Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used. When
using the clock output of the dedicated flash memory programmer, pin connection varies depending on the
type of the dedicated flash memory programmer used.
PG-FP5, FL-PR5, PG-FP4, FL-PR4: Connect CLK of the programmer to EXCLK/X2/P122.
PG-FPL3, FP-LITE3:
Connect CLK of the programmer to X1/P121, and connect its
inverted signal to X2/EXCLK/P122.
Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used.
: Be sure to connect the pin.
{: The pin does not have to be connected if the signal is generated on the target board.
: The pin does not have to be connected.
Users Manual U18598EJ1V0UD
For the pins not to be used when the dedicated program adapter (FA series) is used, perform the processing
described under the recommended connection of unused pins shown in Table 2-3 Pin I/O Circuit Types, or those
described in Table 27-4 Processing of Unused Pins When the Flash Memory Write Adapter Is Connected
(Required).
Table 27-4. Processing of Unused Pins When the Flash Memory Write Adapter Is Connected (Required)
Pin name
Pin processing
P00, P01
Notes 1, 5
P03 to P06
Notes 2, 5
P10, P11
Notes 3, 5
P14
Notes 4, 5
P16, P17
Notes 1, 5
P30 to P33
P60 to P63
P70 to P77
Note 1, 5
P120
P140 to P143
Notes 1.
These pins may be directly connected to EVSS, without using a resistor, when
design is performed so that operation is not switched to the normal operation
mode on the flash memory write adapter board during flash memory
programming.
2.
3.
Connect these pins with the programmer when communicating with the
dedicated flash memory programmer via serial communication by CSI10.
4.
Connect this pin with the programmer when communicating with the dedicated
5.
With products without an EVSS pin, connect them to VSS. With products without
713
Pins Used
CSI10
UART6
TxD6, RxD6
To connect the dedicated flash memory programmer to the pins of a serial interface that is connected to another
device on the board, care must be exercised so that signals do not collide or that the other device does not
malfunction.
714
Signal collision
Input pin
In the flash memory programming mode, the signal output by the device
collides with the signal sent from the dedicated flash programmer.
Therefore, isolate the signal of the other device.
Pin
Other device
Input pin
78K0/Kx2
microcontrollers
Pin
If the signal output by the dedicated flash memory programmer in the flash
memory programming mode affects the other device, isolate the signal of
the other device.
715
In the flash memory programming mode, the signal output by the reset
signal generator collides with the signal output by the dedicated flash
memory programmer. Therefore, isolate the signal of the reset signal
generator.
716
Connect CLK of the programmer and X1/P121, and connect its inverted
signal to X2/EXCLK/P122.
Cautions 1. Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used.
2. Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used.
3. For the product with an on-chip debug function (PD78F05xxDA), connect P31/INTP2/OCD1A
and P121/X1/OCD0A as follows when writing the flash memory with a flash memory
programmer.
P31/INTP2/OCD1A: Connect to EVSSNote via a resistor.
P121/X1/OCD0A:
717
No
End?
Yes
End
VDD
5.5 V
0V
VDD
RESET
0V
FLMD0 pulse
VDD
FLMD0
0V
Flash memory programming mode
Table 27-6. Relationship Between FLMD0 Pin and Operation Mode After Reset Release
FLMD0
0
VDD
718
Operation Mode
Normal operation mode
Flash memory programming mode
Users Manual U18598EJ1V0UD
Standard Setting
Port
UART-Ext-Osc
Speed
Note 1
Pins Used
Frequency
Note 3
115,200 bps
Note 2
2 to 20 MHz
Multiply Rate
1.0
TxD6, RxD6
UART-Ext-FP4CK
CSI-Internal-OSC
2.4 kHz to
2.5 MHz
SO10, SI10,
SCK10
Peripheral Number of
Clock
FLMD0
Pulses
fX
fEXCLK
fRH
Notes 1. Selection items for Standard settings on GUI of the flash memory programmer.
2. The possible setting range differs depending on the voltage. For details, refer to the chapter of electrical
specifications.
3. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART
communication, thoroughly evaluate the slew as well as the baud rate error.
Caution When UART6 is selected, the receive clock is calculated based on the reset command sent from the
dedicated flash memory programmer after the FLMD0 pulse has been received.
Remark
fX:
X1 clock
719
XXXX XXXXXX
Axxxx
Bxxxxx
XXXXX
Cxxxxxx
XXX YYY
XXXX YYYY
STATVE
Command
Response
78K0/Kx2
microcontrollers
Dedicated flash
memory programmer
The flash memory control commands of the 78K0/Kx2 microcontrollers are listed in the table below. All these
commands are issued from the programmer and the 78K0/Kx2 microcontrollers perform processing corresponding to
the respective commands.
Table 27-8. Flash Memory Control Commands
Classification
Verify
Command Name
Function
Compares the contents of a specified area of the flash memory with
Verify
Blank check
Chip Erase
Block Erase
Write
Programming
Getting information
Status
Silicon Signature
Gets 78K0/Kx2 information (such as the part number and flash memory
configuration).
Version Get
Checksum
Security
Security Set
Others
Reset
The 78K0/Kx2 microcontrollers return a response for the command issued by the dedicated flash memory
programmer. The response names sent from the 78K0/Kx2 microcontrollers are listed below.
Table 27-9. Response Names
Response Name
720
Function
ACK
Acknowledges command/data.
NAK
721
Executed Command
Batch Erase (Chip Erase)
Block Erase
Write
Note
Blocks cannot be
Can be performed
erased.
Can be performed.
Prohibition of writing
Cannot be performed.
erased.
written.
Note Confirm that no data has been written to the write area. Because data cannot be erased after batch erase
(chip erase) is prohibited, do not write data if the data has not been erased.
(2) During self programming
Valid Security
Executed Command
Block Erase
Write
Can be performed.
Table 27-11 shows how to perform security settings in each programming mode.
Table 27-11. Setting Security in Each Programming Mode
(1) On-board/off-board programming
Security
Security Setting
programmer, etc.
Prohibition of writing
command
Security Setting
Set by using information library.
Prohibition of writing
722
27.9 Processing Time for Each Command When PG-FP4 or PG-FP5 Is Used (Reference)
The following table shows the processing time for each command (reference) when the PG-FP4 or PG-FP5 is used
as a dedicated flash memory programmer.
Table 27-12. Processing Time for Each Command When PG-FP4 or PG-FP5 Is Used (Reference) (1/2)
(1) Products with internal ROMs of the 32 KB
Command of
Port: CSI-Internal-OSC
PG-FP4
clock (fRH)),
Frequency: 20 MHz
Signature
0.5 s (TYP.)
0.5 s (TYP.)
0.5 s (TYP.)
Blankcheck
0.5 s (TYP.)
0.5 s (TYP.)
0.5 s (TYP.)
Erase
0.5 s (TYP.)
0.5 s (TYP.)
0.5 s (TYP.)
Program
2.5 s (TYP.)
5 s (TYP.)
5 s (TYP.)
Verify
1.5 s (TYP.)
4 s (TYP.)
3.5 s (TYP.)
E.P.V
3.5 s (TYP.)
6 s (TYP.)
6 s (TYP.)
Checksum
0.5 s (TYP.)
0.5 s (TYP.)
0.5 s (TYP.)
Security
0.5 s (TYP.)
0.5 s (TYP.)
0.5 s (TYP.)
Port: CSI-Internal-OSC
PG-FP4
clock (fRH)),
Speed: 2.5 MHz
Frequency: 20 MHz
Signature
0.5 s (TYP.)
0.5 s (TYP.)
0.5 s (TYP.)
Blankcheck
1 s (TYP.)
1 s (TYP.)
1 s (TYP.)
Erase
1 s (TYP.)
1 s (TYP.)
1 s (TYP.)
Program
5 s (TYP.)
9 s (TYP.)
9 s (TYP.)
Verify
2 s (TYP.)
6.5 s (TYP.)
6.5 s (TYP.)
E.P.V
6 s (TYP.)
10.5 s (TYP.)
10.5 s (TYP.)
Checksum
0.5 s (TYP.)
1 s (TYP.)
1 s (TYP.)
Security
0.5 s (TYP.)
0.5 s (TYP.)
0.5 s (TYP.)
Caution When executing boot swapping, do not use the E.P.V. command with the dedicated flash
memory programmer.
723
Table 27-12. Processing Time for Each Command When PG-FP4 or PG-FP5 Is Used (Reference) (2/2)
(3) Products with internal ROMs of the 128 KB
Command of
Port: CSI-Internal-OSC
PG-FP4
clock (fRH)),
Speed: 2.5 MHz
Frequency: 20 MHz
Signature
0.5 s (TYP.)
0.5 s (TYP.)
Blankcheck
1 s (TYP.)
1 s (TYP.)
1 s (TYP.)
Erase
1.5 s (TYP.)
1.5 s (TYP.)
1.5 s (TYP.)
Program
9.5 s (TYP.)
18 s (TYP.)
18 s (TYP.)
Verify
4.5 s (TYP.)
13.5 s (TYP.)
13.5 s (TYP.)
E.P.V
11 s (TYP.)
19.5 s (TYP.)
19.5 s (TYP.)
Checksum
1 s (TYP.)
1 s (TYP.)
1 s (TYP.)
Security
0.5 s (TYP.)
0.5 s (TYP.)
0.5 s (TYP.)
Caution When executing boot swapping, do not use the E.P.V. command with the dedicated flash
memory programmer.
724
For details of the self-programming function and the self-programming library, refer to 78K0
Microcontrollers Self Programming Library Type01 Users Manual (U18274E).
Cautions 1. The self-programming function cannot be used when the CPU operates with the subsystem
clock.
2. Oscillation of the internal high-speed oscillator is started during self programming,
regardless of the setting of the RSTOP flag (bit 0 of the internal oscillation mode register
(RCM)). Oscillation of the internal high-speed oscillator cannot be stopped even if the STOP
instruction is executed.
3. Input a high level to the FLMD0 pin during self-programming.
4. Be sure to execute the DI instruction before starting self-programming.
The self-programming function checks the interrupt request flags (IF0L, IF0H, IF1L, and IF1H).
If an interrupt request is generated, self-programming is stopped.
5. Self-programming is also stopped by an interrupt request that is not masked even in the DI
status. To prevent this, mask the interrupt by using the interrupt mask flag registers (MK0L,
MK0H, MK1L, and MK1H).
6. Allocate the entry program for self-programming in the common area of 0000H to 7FFFH.
Figure 27-13. Operation Mode and Memory Map for Self-Programming (PD78F0547A)
FFFFH
FF00H
FEFFH
FB00H
FA F F H
FA 2 0 H
FA 1 F H
FA 0 0 H
F9FFH
F800H
F7FFH
Reserved
Buffer RAM
Reserved
Memory bank 4
Memory bank 2
Internal
expansion RAM
E000H
DFFFH
C000H
BFFFH
FFFFH
FF00H
FEFFH
FB00H
FA F F H
FA 2 0 H
FA 1 F H
FA 0 0 H
F9FFH
F800H
F7FFH
SFR
Internal highspeed RAM
Reserved
Flash memory
control
firmware ROM
Flash memory
(memory bank 0)
Disable
accessing
8000H
7FFFH
Memory bank 5
SFR
Internal highspeed RAM
Reserved
Buffer RAM
Reserved
Memory bank 2
Internal
expansion RAM
E000H
DFFFH
C000H
BFFFH
Reserved
Flash memory
control
firmware ROM
Disable
accessing
Enable
accessing
8000H
7FFFH
Memory bank 5
Memory bank 3
Flash memory
(common area)
Memory bank 1
0000H
Normal mode
Memory bank 4
Flash memory
(common area)
Memory bank 3
Memory bank 1
Instructions can be
fetched from common
area and firmware ROM.
Self-programming mode
725
The following figure illustrates a flow of rewriting the flash memory by using a self-programming library.
Figure 27-14. Flow of Self Programming (Rewriting Flash Memory)
Start of self programming
FlashStart
FlashEnv
CheckFLMD
FlashBlockBlankCheck
Normal completion?
No
Yes
FlashBlockErase
FlashWordWrite
FlashBlockVerify
Normal completion?
No
Yes
FlashBlockErase
FlashWordWrite
FlashBlockVerify
Normal completion?
No
Yes
Normal
completion
Error
FlashEnd
Remark
For details of the self-programming library, refer to 78K0 Microcontrollers Self Programming Library
Type01 Users Manual (U18274E).
726
The following table shows the processing time and interrupt response time for the self-programming library.
Table 27-13. Processing Time for Self Programming Library (1/3)
(1) When internal high-speed oscillation clock is used and entry RAM is located outside short direct
addressing range
Processing Time (s)
Library Name
Min.
Max.
Min.
4.0
4.5
4.0
Max.
4.5
1105.9
1106.6
1105.9
1106.6
905.7
906.1
904.9
905.3
12776.1
12778.3
12770.9
12772.6
26050.4
349971.3
26045.3
349965.6
1180.1 + 203 w
1184.3 + 2241 w
1172.9 + 203 w
1176.3 + 2241 w
25337.9
25340.2
25332.8
25334.5
4.0
4.5
4.0
4.5
1072.9
1075.2
1067.5
1069.1
1060.2
1062.6
1054.8
1056.6
1023.8
1028.2
1018.3
1022.1
70265.9
759995.0
70264.9
759994.0
1316.8 + 347 w
1320.9 + 2385 w
1309.0 + 347 w
1312.4 + 2385 w
(2) When internal high-speed oscillation clock is used and entry RAM is located in short direct addressing
range
Processing Time (s)
Library Name
Min.
Max.
Min.
4.0
4.5
4.0
4.5
Initialize library
449.5
450.2
449.5
450.2
249.3
249.7
248.6
248.9
Max.
12119.7
12121.9
12114.6
12116.3
25344.7
349266.4
25339.6
349260.8
445.8 + 203 w
449.9 + 2241 w
438.5 + 203 w
441.9 + 2241 w
24682.7
24684.9
24677.6
24679.3
4.0
4.5
4.0
4.5
417.6
419.8
412.1
413.8
405.0
407.4
399.5
401.3
367.4
371.8
361.9
365.8
69569.3
759297.3
69568.3
759296.2
795.1 + 347 w
799.3 + 2385 w
787.4 + 347 w
790.8 + 2385 w
Remarks 1. The above processing times are those when a write start address structure is located in the internal
high-speed RAM and during stabilized operation of the internal high-speed oscillator (RSTS = 1).
2. RSTS: Bit 7 of the internal oscillation mode register (RCM)
3. w: Number of words in write data (1 word = 4 bytes)
727
Library Name
Max.
Min.
Max.
34/fCPU
Initialize library
55/fCPU + 594
36/fCPU + 495
30/fCPU + 495
179/fCPU + 6429
136/fCPU + 6429
179/fCPU + 19713
179/fCPU + 268079
136/fCPU + 19713
136/fCPU + 268079
333/fCPU + 647 +
333/fCPU + 647 +
272/fCPU + 647 +
272/fCPU + 647 +
136 w
1647 w
136 w
1647 w
179/fCPU + 13284
136/fCPU + 13284
34/fCPU
180/fCPU + 581
134fCPU + 581
190/fCPU + 574
144/fCPU + 574
350/fCPU + 535
304/fCPU + 535
80/fCPU + 43181
80/fCPU + 572934
72/fCPU + 43181
72/fCPU + 572934
333/fCPU + 729 +
333/fCPU + 729 +
268/fCPU + 729 +
268/fCPU + 729 +
209 w
1722 w
209 w
1722 w
Remarks 1. The above processing times are those when a write start address structure is located in the internal
high-speed RAM and during stabilized operation of the internal high-speed oscillator (RSTS = 1).
2. RSTS: Bit 7 of the internal oscillation mode register (RCM)
3. fCPU: CPU operation clock frequency
4. w: Number of words in write data (1 word = 4 bytes)
728
Library Name
Max.
Min.
Max.
34/fCPU
Initialize library
55/fCPU + 272
36/fCPU + 173
30/fCPU + 173
179/fCPU + 6108
136/fCPU + 6108
179/fCPU + 19371
179/fCPU + 267738
136/fCPU + 19371
136/fCPU + 267738
333/fCPU + 247 +
333/fCPU + 247 +
272/fCPU + 247 +
272/fCPU + 247 +
136 w
1647 w
136 w
1647 w
179/fCPU+12964
136/fCPU+12964
34/fCPU
180/fCPU + 261
134/fCPU + 261
190/fCPU + 254
144/fCPU + 254
350/fCPU + 213
304/fCPU + 213
80/fCPU + 42839
80/fCPU + 572592
72/fCPU + 42839
72/fCPU + 572592
333/fCPU + 516 +
333/fCPU + 516 +
268/fCPU + 516 +
268/fCPU + 516 +
209 w
1722 w
209 w
1722 w
Remarks 1. The above processing times are those when a write start address structure is located in the internal
high-speed RAM and during stabilized operation of the internal high-speed oscillator (RSTS = 1).
2. RSTS: Bit 7 of the internal oscillation mode register (RCM)
3. fCPU: CPU operation clock frequency
4. w: Number of words in write data (1 word = 4 bytes)
729
Table 27-14. Interrupt Response Time for Self Programming Library (1/2)
(1) When internal high-speed oscillation clock is used
Interrupt Response Time (s (Max.))
Library Name
is outside short
is in short direct
is outside short
is in short direct
direct addressing
addressing range
direct addressing
addressing range
range
range
1100.9
431.9
1095.3
426.3
1452.9
783.9
1447.3
778.3
1247.2
579.2
1239.2
571.2
1125.9
455.9
1120.3
450.3
906.9
312.0
905.8
311.0
1215.2
547.2
1213.9
545.9
Remarks 1. The above interrupt response times are those during stabilized operation of the internal high-speed
oscillator (RSTS = 1).
2. RSTS: Bit 7 of the internal oscillation mode register (RCM)
(2) When high-speed system clock is used (normal model of C compiler)
Interrupt Response Time (s (Max.))
Library Name
RSTOP = 0, RSTS = 1
RSTOP = 1
is outside short
is in short direct
is outside short
is in short direct
direct addressing
addressing range
direct addressing
addressing range
range
range
179/fCPU + 567
179/fCPU + 246
179/fCPU + 1708
179/fCPU + 569
179/fCPU + 780
179/fCPU + 459
179/fCPU + 1921
179/fCPU + 782
333/fCPU + 763
333/fCPU + 443
333/fCPU + 1871
333/fCPU + 767
179/fCPU + 580
179/fCPU + 259
179/fCPU + 1721
179/fCPU + 582
80/fCPU + 456
80/fCPU + 200
80/fCPU + 1598
80/fCPU + 459
29/fCPU + 767
29/fCPU + 447
29/fCPU + 767
29/fCPU + 447
333/fCPU + 696
333/fCPU + 376
333/fCPU + 1838
333/fCPU + 700
Note
Note The longer value of the EEPROM write library interrupt response time becomes the Max. value, depending
on the value of fCPU.
Remarks 1. fCPU: CPU operation clock frequency
2. RSTOP: Bit 0 of the internal oscillation mode register (RCM)
3. RSTS: Bit 7 of the internal oscillation mode register (RCM)
730
Table 27-14. Interrupt Response Time for Self Programming Library (2/2)
(3) When high-speed system clock is used (static model of C compiler/assembler)
Interrupt Response Time (s (Max.))
Library Name
RSTOP = 0, RSTS = 1
RSTOP = 1
is outside short
is in short direct
is outside short
is in short direct
direct addressing
addressing range
direct addressing
addressing range
range
range
136/fCPU + 567
136/fCPU + 246
136/fCPU + 1708
136/fCPU + 569
136/fCPU + 780
136/fCPU + 459
136/fCPU + 1921
136/fCPU + 782
272/fCPU + 763
272/fCPU + 443
272/fCPU + 1871
272/fCPU + 767
136/fCPU + 580
136/fCPU + 259
136/fCPU + 1721
136/fCPU + 582
72/fCPU + 456
72/fCPU + 200
72/fCPU + 1598
72/fCPU + 459
19/fCPU + 767
19/fCPU + 447
19/fCPU + 767
19/fCPU + 447
268/fCPU + 696
268/fCPU + 376
268/fCPU + 1838
268/fCPU + 700
Note
Note The longer value of the EEPROM write library interrupt response time becomes the Max. value, depending
on the value of fCPU.
Remarks 1. fCPU: CPU operation clock frequency
2. RSTOP: Bit 0 of the internal oscillation mode register (RCM)
3. RSTS: Bit 7 of the internal oscillation mode register (RCM)
731
User program
Self programming
to boot cluster 1
User program
Executing boot
swapping by firmware
User program
2000H
User program
Boot program
(boot cluster 0)
Boot program
(boot cluster 0)
Boot program
(boot cluster 0)
1000H
0000H
Boot
Boot
Boot
XXXXH
Self programming
to boot cluster 0
User program
Executing boot
swapping by firmware
User program
2000H
1000H
0000H
Remark
732
Boot cluster 1 becomes 0000H to 0FFFH when a reset is generated after the boot flag has been set.
Boot
cluster 1
Boot
cluster 0
7
6
5
4
3
2
1
0
Program
Program
Program
Program
Boot program
Boot program
Boot program
Boot program
1000H
0000H
Erasing block 4
Erasing block 5
Erasing block 6
Erasing block 7
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Program
Program
Program
Boot program
Boot program
Boot program
Boot program
Program
Program
Boot program
Boot program
Boot program
Boot program
Program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Writing blocks 5 to 7
7 New boot program
6 New boot program
5 New boot program
4 New boot program
3 Boot program
2 Boot program
1 Boot program
0 Boot program
Boot swap
7
6
5
4
3
2
1
0
0000H
1000H
Erasing block 0
Erasing block 1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Erasing block 2
Erasing block 3
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Writing blocks 0 to 3
7
6
5
4
3
2
1
0
Boot swap
7
6
5
4
3
2
1
0
733
The PD78F05xxDA has an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when
this function is used, and product reliability therefore cannot be guaranteed. NEC Electronics is
not liable for problems occurring when the on-chip debug function is used.
Remark
VDD
VDD
VDD
1 k
(Recommended)
Reset circuit
Reset signal
RESET_INNote 1
10 k
(Recommended)
Target device
RESET
RESET_OUT
FLMD0
FLMD0
Note 2
VDD
VDD
X2 (DATA)Note 3
X2/OCD0B
GND
X1 (CLK)Note 3
X1/OCD0A
P31
GND
GND
R.F.U.
(Open)
R.F.U.
(Open)
Note 2
Notes 1. This connection is designed assuming that the reset signal is output from the N-ch open-drain buffer
(output resistance: 100 or less). For details, refer to QB-78K0MINI Users Manual (U17029E) or QBMINI2 Users Manual (U18371E).
2. Make pull-down resistor 470 or more (10 k: recommended).
3. Characters without parentheses represent the QB-78K0MINI name, and those within parenthesis the
QB-MINI2 name.
Cautions 1. Input the clock from the OCD0A/X1 pin during on-chip debugging.
2. Control the OCD0A/X1 and OCD0B/X2 pins by externally pulling down the OCD1A/P31 pin or
by using an external circuit using the P130 pin (that outputs a low level when the device is
reset).
734
Target connector
(10-pin)
VDD
VDD
VDD
3 to 10 k
(Recommended)
Note 2
VDD
1 k
(Recommended)
Reset circuit
Reset signal
RESET_INNote 1
10 k
Target device
(Recommended)
RESET
RESET_OUT
FLMD0
FLMD0
Note 3
VDD
VDD
X2 (DATA)Note 4
OCD1B/P32
GND
X1 (CLK)Note 4
OCD1A/P31
GND
GND
R.F.U.
(Open)
R.F.U.
Note 3
(Open)
Notes 1. This connection is designed assuming that the reset signal is output from the N-ch open-drain buffer
(output resistance: 100 or less). For details, refer to QB-78K0MINI Users Manual (U17029E) or QBMINI2 Users Manual (U18371E).
2. This is the processing of the pin when OCD1B/P32 is set as the input port (to prevent the pin from being
left opened when not connected to QB-78K0MINI or QB-MINI2).
3. Make pull-down resistor 470 or more (10 k: recommended).
4. Characters without parentheses represent the QB-78K0MINI name, and those within parenthesis the
QB-MINI2 name.
Connect the FLMD0 pin as follows when performing self programming by means of on-chip debugging.
Figure 28-3. Connection of FLMD0 Pin for Self Programming by Means of On-Chip Debugging
Target connector
Target device
Port
1 k (recommended)
FLMD0
FLMD0
10 k (recommended)
735
28FH
Pseudo RRM area
(256 bytes)
190H
18FH
FF7FH
Debug monitor area
(257 bytes)
8FH
8EH
85H
84H
F7F0H
Security ID area
(10 bytes)
Option byte area (1 byte)
03H
02H
00H
Note
With products not incorporated the internal expansion RAM (PD78F0503DA, 78F0513DA), it is not
necessary to secure this area.
Remark
Shaded reserved areas: Area used for the respective debug functions to be used
Other reserved areas:
736
This chapter lists each instruction set of the 78K0/Kx2 microcontrollers in table form. For details of each operation
and operation code, refer to the separate document 78K/0 Series Instructions Users Manual (U12326E).
Specification Method
rp
sfr
sfrp
Special function register symbol (16-bit manipulatable register even addresses only)
saddr
saddrp
addr16
Note
Note
addr5
word
byte
bit
RBn
RB0 to RB3
Note Addresses from FFD0H to FFDFH cannot be accessed with these operands.
Remark
For special function register symbols, see Table 3-7 Special Function Register List.
737
X:
X register
B:
B register
C:
C register
D:
D register
E:
E register
H:
H register
L:
L register
AX:
BC:
BC register pair
DE:
DE register pair
HL:
HL register pair
PC:
Program counter
SP:
Stack pointer
PSW:
CY:
Carry flag
AC:
Z:
Zero flag
RBS:
IE:
( ):
Inverted data
Cleared to 0
1:
Set to 1
R:
738
Mnemonic
MOV
transfer
XCH
Notes 1.
Operands
Clocks
Bytes
Note 2
Z AC CY
r, #byte
r byte
saddr, #byte
(saddr) byte
sfr, #byte
sfr byte
A, r
Note 3
Ar
r, A
Note 3
rA
A, saddr
A (saddr)
saddr, A
(saddr) A
A, sfr
A sfr
sfr, A
sfr A
A, !addr16
A (addr16)
!addr16, A
(addr16) A
PSW, #byte
PSW byte
A, PSW
A PSW
PSW, A
PSW A
A, [DE]
A (DE)
[DE], A
(DE) A
A, [HL]
A (HL)
[HL], A
(HL) A
A, [HL + byte]
A (HL + byte)
[HL + byte], A
(HL + byte) A
A, [HL + B]
A (HL + B)
[HL + B], A
(HL + B) A
A, [HL + C]
A (HL + C)
[HL + C], A
(HL + C) A
Ar
A, r
Note 3
Flag
Operation
Note 1
A, saddr
A (saddr)
A, sfr
A (sfr)
A, !addr16
10
A (addr16)
A, [DE]
A (DE)
A, [HL]
A (HL)
A, [HL + byte]
10
A (HL + byte)
A, [HL + B]
10
A (HL + B)
A, [HL + C]
10
A (HL + C)
When the internal high-speed RAM area is accessed or for an instruction with no data access
2.
3.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
739
Instruction
Group
Mnemonic
Operands
Clocks
Bytes
Note 1
16-bit data
MOVW
transfer
rp word
saddrp, #word
10
(saddrp) word
sfrp, #word
10
sfrp word
AX, saddrp
AX (saddrp)
saddrp, AX
(saddrp) AX
AX, sfrp
AX sfrp
sfrp, AX
sfrp AX
AX rp
AX, rp
Note 3
rp, AX
Note 3
rp AX
10
12
AX (addr16)
10
12
(addr16) AX
AX rp
A, CY A + byte
A, CY A + r
r, CY r + A
!addr16, AX
XCHW
AX, rp
ADD
A, #byte
operation
Note 3
saddr, #byte
A, r
Note 4
r, A
ADDC
A, saddr
A, CY A + (saddr)
A, !addr16
A, CY A + (addr16)
A, [HL]
A, CY A + (HL)
A, [HL + byte]
A, CY A + (HL + byte)
A, [HL + B]
A, CY A + (HL + B)
A, [HL + C]
A, CY A + (HL + C)
A, #byte
A, CY A + byte + CY
A, CY A + r + CY
r, CY r + A + CY
saddr, #byte
A, r
Note 4
r, A
Notes 1.
Z AC CY
Note 2
rp, #word
AX, !addr16
8-bit
Flag
Operation
A, saddr
A, CY A + (saddr) + CY
A, !addr16
A, CY A + (addr16) + C
A, [HL]
A, CY A + (HL) + CY
A, [HL + byte]
A, CY A + (HL + byte) + CY
A, [HL + B]
A, CY A + (HL + B) + CY
A, [HL + C]
A, CY A + (HL + C) + CY
When the internal high-speed RAM area is accessed or for an instruction with no data access
2.
3.
4.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
740
Instruction
Group
Mnemonic
Operands
Clocks
Bytes
Note 1
8-bit
SUB
operation
A, CY A byte
saddr, #byte
A, CY A r
r, A
r, CY r A
A, saddr
A, CY A (saddr)
Note 3
A, !addr16
A, CY A (addr16)
A, [HL]
A, CY A (HL)
A, [HL + byte]
A, CY A (HL + byte)
A, [HL + B]
A, CY A (HL + B)
A, [HL + C]
A, CY A (HL + C)
A, #byte
A, CY A byte CY
saddr, #byte
A, CY A r CY
r, A
r, CY r A CY
A, saddr
A, CY A (saddr) CY
A, !addr16
A, CY A (addr16) CY
A, [HL]
A, CY A (HL) CY
A, [HL + byte]
A, CY A (HL + byte) CY
A, r
AND
Note 3
A, [HL + B]
A, CY A (HL + B) CY
A, [HL + C]
A, CY A (HL + C) CY
A, #byte
A A byte
AAr
rrA
saddr, #byte
A, r
r, A
Notes 1.
Z AC CY
Note 2
A, #byte
A, r
SUBC
Flag
Operation
Note 3
A, saddr
A A (saddr)
A, !addr16
A A (addr16)
A, [HL]
A A (HL)
A, [HL + byte]
A A (HL + byte)
A, [HL + B]
A A (HL + B)
A, [HL + C]
A A (HL + C)
When the internal high-speed RAM area is accessed or for an instruction with no data access
2.
3.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
741
Instruction
Group
Mnemonic
Operands
Clocks
Bytes
Note 1
8-bit
OR
operation
A A byte
saddr, #byte
AAr
r, A
rrA
A, saddr
A A (saddr)
Note 3
A, !addr16
A A (addr16)
A, [HL]
A A (HL)
A, [HL + byte]
A A (HL + byte)
A, [HL + B]
A A (HL + B)
A, [HL + C]
A A (HL + C)
A, #byte
A A byte
saddr, #byte
AAr
r, A
rrA
A, saddr
A A (saddr)
A, !addr16
A A (addr16)
A, [HL]
A A (HL)
A, [HL + byte]
A A (HL + byte)
A, r
CMP
Note 3
A, [HL + B]
A A (HL + B)
A, [HL + C]
A A (HL + C)
A, #byte
A byte
(saddr) byte
Ar
rA
saddr, #byte
A, r
r, A
Notes 1.
Z AC CY
Note 2
A, #byte
A, r
XOR
Flag
Operation
Note 3
A, saddr
A (saddr)
A, !addr16
A (addr16)
A, [HL]
A (HL)
A, [HL + byte]
A (HL + byte)
A, [HL + B]
A (HL + B)
A, [HL + C]
A (HL + C)
When the internal high-speed RAM area is accessed or for an instruction with no data access
2.
3.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
742
Instruction
Group
Mnemonic
Operands
Clocks
Bytes
Flag
Operation
Note 1
Note 2
Z AC CY
16-bit
ADDW
AX, #word
AX, CY AX + word
operation
SUBW
AX, #word
AX, CY AX word
CMPW
AX, #word
AX word
Multiply/
MULU
16
AX A X
divide
DIVUW
25
AX (Quotient), C (Remainder) AX C
Increment/
INC
decrement
DEC
INCW
Rotate
rr+1
saddr
(saddr) (saddr) + 1
rr1
saddr
(saddr) (saddr) 1
rp
rp rp + 1
DECW
rp
rp rp 1
ROR
A, 1
ROL
A, 1
RORC
A, 1
ROLC
A, 1
ROR4
[HL]
10
12
A3 0 (HL)3 0, (HL)7 4 A3 0,
(HL)3 0 (HL)7 4
ROL4
[HL]
10
12
A3 0 (HL)7 4, (HL)3 0 A3 0,
(HL)7 4 (HL)3 0
BCD
ADJBA
adjustment
ADJBS
Bit
MOV1
manipulate
Notes 1.
2.
CY, saddr.bit
CY (saddr.bit)
CY, sfr.bit
CY sfr.bit
CY, A.bit
CY A.bit
CY, PSW.bit
CY PSW.bit
CY, [HL].bit
CY (HL).bit
saddr.bit, CY
(saddr.bit) CY
sfr.bit, CY
sfr.bit CY
A.bit, CY
A.bit CY
PSW.bit, CY
PSW.bit CY
[HL].bit, CY
(HL).bit CY
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
743
Instruction
Group
Mnemonic
Operands
Clocks
Bytes
Note 1
Bit
AND1
manipulate
OR1
XOR1
SET1
CLR1
Notes 1.
2.
Flag
Operation
Z AC CY
Note 2
CY, saddr.bit
CY CY (saddr.bit)
CY, sfr.bit
CY CY sfr.bit
CY, A.bit
CY CY A.bit
CY, PSW.bit
CY CY PSW.bit
CY, [HL].bit
CY CY (HL).bit
CY, saddr.bit
CY CY (saddr.bit)
CY, sfr.bit
CY CY sfr.bit
CY, A.bit
CY CY A.bit
CY, PSW.bit
CY CY PSW.bit
CY, [HL].bit
CY CY (HL).bit
CY, saddr.bit
CY CY (saddr.bit)
CY, sfr.bit
CY CY sfr.bit
CY, A.bit
CY CY A.bit
CY CY PSW.bit
CY, [HL].bit
CY CY (HL).bit
saddr.bit
(saddr.bit) 1
sfr.bit
sfr.bit 1
A.bit
A.bit 1
PSW.bit
PSW.bit 1
[HL].bit
(HL).bit 1
saddr.bit
(saddr.bit) 0
sfr.bit
sfr.bit 0
A.bit
A.bit 0
PSW.bit
PSW.bit 0
[HL].bit
(HL).bit 0
SET1
CY
CY 1
CLR1
CY
CY 0
NOT1
CY
CY CY
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
744
Instruction
Group
Call/return
Mnemonic
CALL
Operands
!addr16
Clocks
Bytes
3
Operation
Note 1
Note 2
Flag
Z AC CY
CALLF
!addr11
CALLT
[addr5]
BRK
RET
RETI
R R R
R R R
PUSH
manipulate
PSW
rp
1
1
(SP 1) PSW, SP SP 1
(SP 1) rpH, (SP 2) rpL,
SP SP 2
POP
PSW
PSW (SP), SP SP + 1
rp
SP, #word
10
SP word
SP, AX
SP AX
R R R
SP SP + 2
MOVW
AX, SP
AX SP
Unconditional BR
!addr16
PC addr16
branch
$addr16
PC PC + 2 + jdisp8
PCH A, PCL X
AX
Conditional BC
$addr16
PC PC + 2 + jdisp8 if CY = 1
branch
BNC
$addr16
PC PC + 2 + jdisp8 if CY = 0
BZ
$addr16
PC PC + 2 + jdisp8 if Z = 1
BNZ
$addr16
PC PC + 2 + jdisp8 if Z = 0
Notes 1.
2.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
745
Instruction
Group
Mnemonic
Operands
Clocks
Bytes
Note 1
Z AC CY
Note 2
Conditional BT
saddr.bit, $addr16
PC PC + 3 + jdisp8 if (saddr.bit) = 1
branch
sfr.bit, $addr16
11
PC PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr16
PC PC + 3 + jdisp8 if A.bit = 1
PSW.bit, $addr16
PC PC + 3 + jdisp8 if PSW.bit = 1
[HL].bit, $addr16
10
11
PC PC + 3 + jdisp8 if (HL).bit = 1
saddr.bit, $addr16
10
11
PC PC + 4 + jdisp8 if (saddr.bit) = 0
sfr.bit, $addr16
11
PC PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr16
PC PC + 3 + jdisp8 if A.bit = 0
BF
BTCLR
Flag
Operation
PSW.bit, $addr16
11
[HL].bit, $addr16
10
11
PC PC + 3 + jdisp8 if (HL).bit = 0
saddr.bit, $addr16
10
12
PC PC + 4 + jdisp8 if (saddr.bit) = 1
then reset (saddr.bit)
sfr.bit, $addr16
12
PC PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
A.bit, $addr16
PC PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PSW.bit, $addr16
12
PC PC + 4 + jdisp8 if PSW.bit = 1
10
12
PC PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
DBNZ
B, $addr16
B B 1, then
PC PC + 2 + jdisp8 if B 0
C, $addr16
C C 1, then
saddr, $addr16
10
PC PC + 2 + jdisp8 if C 0
PC PC + 3 + jdisp8 if (saddr) 0
CPU
SEL
RBS1, 0 n
control
NOP
No Operation
EI
IE 1 (Enable Interrupt)
DI
IE 0 (Disable Interrupt)
HALT
STOP
Notes 1.
2.
RBn
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
746
#byte
rNote
sfr
saddr
!addr16
PSW
[DE]
[HL]
None
[HL + B]
First Operand
A
[HL + C]
ADD
MOV
MOV
MOV
MOV
ADDC
XCH
XCH
XCH
XCH
SUB
ADD
ADD
ADD
SUBC
ADDC
ADDC ADDC
ADDC ADDC
AND
SUB
SUB
SUB
OR
SUBC
SUBC SUBC
SUBC SUBC
XOR
AND
AND
AND
AND
AND
CMP
OR
OR
OR
OR
OR
XOR
XOR
XOR
XOR
XOR
CMP
CMP
CMP
CMP
CMP
MOV
MOV
SUB
MOV
MOV
MOV
ROR
XCH
XCH
XCH
ROL
ADD
ADD
RORC
ROLC
SUB
MOV
INC
ADD
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
B, C
DBNZ
sfr
MOV
MOV
saddr
MOV
MOV
DBNZ
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
PSW
MOV
MOV
PUSH
MOV
POP
[DE]
MOV
[HL]
MOV
ROR4
ROL4
[HL + byte]
MOV
[HL + B]
[HL + C]
X
MULU
DIVUW
Note Except r = A
Users Manual U18598EJ1V0UD
747
#word
AX
rp
Note
sfrp
saddrp
!addr16
SP
None
First Operand
AX
ADDW
MOVW
SUBW
XCHW
MOVW
MOVW
MOVW
MOVW
CMPW
rp
MOVW
MOVW
Note
INCW
DECW
PUSH
POP
sfrp
MOVW
MOVW
saddrp
MOVW
MOVW
!addr16
SP
MOVW
MOVW
MOVW
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
First Operand
A.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
sfr.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
saddr.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
PSW.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
[HL].bit
MOV1
BT
SET1
BF
CLR1
BTCLR
CY
748
MOV1
MOV1
MOV1
MOV1
MOV1
SET1
AND1
AND1
AND1
AND1
AND1
CLR1
OR1
OR1
OR1
OR1
OR1
NOT1
XOR1
XOR1
XOR1
XOR1
XOR1
AX
!addr16
!addr11
[addr5]
$addr16
First Operand
Basic instruction
BR
CALL
CALLF
CALLT
BR
BR
BC
BNC
BZ
BNZ
Compound
BT
instruction
BF
BTCLR
DBNZ
749
The PD78F05xxDA has an on-chip debug function, which is provided for development and
evaluation.
Do not use the on-chip debug function in products designated for mass
production, because the guaranteed number of rewritable times of the flash memory may be
exceeded when this function is used, and product reliability therefore cannot be guaranteed.
NEC Electronics is not liable for problems occurring when the on-chip debug function is
used.
2.
78K0/KB2
78K0/KC2
30/36 Pins
Port 0
P00, P01
Port 1
P10 to P17
Port 2
P20 to P23
Port 3
P30 to P33
38 Pins
P20 to P25
Port 4
48 Pins
78K0/KF2
52 Pins
64 Pins
80 Pins
P00 to P03
P00 to P06
P20 to P27
P60, P61
Port 7
Port 12
P120 to P122
P40 to P43
P40 to P47
P50 to P53
P50 to P57
P60 to P63
P70, P71
P60 to P67
P70 to P73
P70 to P75
P70 to P77
P120 to P124
Port 13
P130
Port 14
P140
750
78K0/KE2
P40, P41
Port 5
Port 6
44 Pins
78K0/KD2
P140, P141
P140 to P145
Standard products
(2) Non-port functions
Port
78K0/KB2
78K0/KC2
30/36 Pins
38 Pins
44 Pins
48 Pins
78K0/KD2
78K0/KE2
78K0/KF2
52 Pins
64 Pins
80 Pins
Note 1
Note 1
AVSS
Power supply,
VDD, EVDD
ground
VSS, EVSS
Regulator
REGC
Reset
RESET
Clock
X1, X2,
oscillation
EXCLK
Writing to
FLMD0
AVREF, AVSS
flash memory
Interrupt
INTP0 to INTP5
Key interrupt
TM00
INTP0 to INTP6
KR0, KR1
KR0 to KR3
Timer
KR0 to KR7
TM01
Serial interface
INTP0 to INTP7
TM50
TI50, TO50
TM51
TI51, TO51
TMH0
TOH0
TMH1
TOH1
UART0
RxD0, TxD0
UART6
RxD6, TxD6
IIC0
SCL0, SDA0
CSI10
TI001
SCK11
Note 2
Note 2
, TI011
Note 2
, TO01
CSI11
SO11
Note 2
, SI11
Note 2
, SSI11
CSIA0
Note 2
Note 2
SCKA0, SIA0,
SOA0, BUSY0,
STB0
A/D converter
ANI0 to ANI3
ANI0 to ANI7
Clock output
PCL
Buzzer output
Low-voltage
ANI0 to ANI5
BUZ
EXLVI
detector (LVI)
On-chip debug OCD0A, OCD1A, OCD0B, OCD1B (mounted only onto PD78F05xxDA (product with on-chip debug function))
function
751
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
Absolute Maximum Ratings (TA = 25C) (1/2)
Parameter
Supply voltage
Symbol
Conditions
VDD
Input voltage
Unit
0.5 to +6.5
EVDD
0.5 to +6.5
VSS
0.5 to +0.3
EVSS
0.5 to +0.3
0.5 to VDD + 0.3
AVREF
Ratings
V
Note
AVSS
0.5 to +0.3
VIREGC
VI1
V
V
Note
V
V
VO
VAN
0.3 to +6.5
0.3 to VDD + 0.3
ANI0 to ANI7
V
Note
Note
V
V
Note
752
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
Absolute Maximum Ratings (TA = 25C) (2/2)
Parameter
Output current, high
Symbol
Ratings
Unit
10
mA
25
mA
55
mA
0.5
mA
mA
mA
mA
30
mA
60
mA
140
mA
mA
mA
mA
10
mA
TA
40 to +85
Tstg
65 to +150
IOH
Conditions
Per pin
Per pin
P20 to P27
P121 to P124
IOL
Per pin
Per pin
P20 to P27
P121 to P124
Cautions 1. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
2. The value of the current that can be run per pin must satisfy the value of the current per pin and
the total value of the currents of all pins.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
753
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
X1 Oscillator Characteristics
(TA = 40 to +85C, 1.8 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V)
Resonator
Recommended Circuit
X1 clock
Ceramic
resonator
Parameter
VSS X1
X2
Conditions
MIN.
MAX.
Unit
Note 2
20.0
MHz
Note 2
10.0
1.0
1.0
TYP.
oscillation
Note 1
frequency (fX)
C1
C2
1.8 V VDD < 2.7 V
X1 clock
Crystal
resonator
VSS X1
X2
1.0
1.0
1.0
5.0
Note 2
20.0
Note 2
10.0
MHz
oscillation
Note 1
frequency (fX)
C1
C2
1.8 V VDD < 2.7 V
1.0
5.0
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. It is 2.0 MHz (MIN.) when programming on the board via UART6.
Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the
above figures to avoid an adverse effect from wiring capacitance.
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. Since the CPU is started by the internal high-speed oscillation clock after a reset release, check
the X1 clock oscillation stabilization time using the oscillation stabilization time counter status
register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register
and oscillation stabilization time select register (OSTS) after sufficiently evaluating the
oscillation stabilization time with the resonator to be used.
754
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
Internal Oscillator Characteristics
(TA = 40 to +85C, 1.8 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V)
Resonator
Parameter
Conditions
RSTS = 1
Note
MIN.
TYP.
MAX.
Unit
7.6
8.0
8.4
MHz
7.6
8.0
10.4
MHz
RSTS = 0
2.48
5.6
9.86
MHz
216
240
264
kHz
192
240
264
kHz
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Remark
Recommended Circuit
VSS XT2
XT1
Conditions
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
Note 2
frequency (fXT)
Rd
C4
Parameter
C3
For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
755
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
DC Characteristics (1/4)
(TA = 40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V)
Parameter
Symbol
Note 1
IOH1
MAX.
Unit
Conditions
4.0 V VDD 5.5 V
3.0
mA
2.5
mA
1.0
mA
20.0
mA
10.0
mA
5.0
mA
30.0
mA
19.0
mA
10.0
mA
50.0
mA
29.0
mA
15.0
mA
AVREF = VDD
0.1
mA
MIN.
IOH2
0.1
mA
IOL1
8.5
mA
5.0
mA
2.0
mA
15.0
mA
5.0
mA
Note 2
TYP.
2.0
mA
20.0
mA
15.0
mA
9.0
mA
45.0
mA
35.0
mA
Note 3
IOL2
20.0
mA
65.0
mA
50.0
mA
29.0
mA
AVREF = VDD
0.4
mA
0.4
mA
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from VDD to an output
pin.
2. Value of current at which the device operation is guaranteed even if the current flows from an output pin to
GND.
3. Specification under conditions where the duty factor is 70% (time for which current is output is 0.7 t and
time for which current is not output is 0.3 t, where t is a specific time). The total output current of the pins
at a duty factor of other than 70% can be calculated by the following expression.
Where the duty factor of IOH is n%: Total output current of pins = (IOH 0.7)/(n 0.01)
<Example> Where the duty factor is 50%, IOH = 20.0 mA
Total output current of pins = (20.0 0.7)/(50 0.01) = 28.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
756
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
DC Characteristics (2/4)
(TA = 40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V)
Parameter
Input voltage, high
(products whose flash
memory is at least
Note 1
48 KB)
Conditions
MIN.
MAX.
Unit
VIH1
Symbol
0.7VDD
VDD
VIH2
0.8VDD
VDD
AVREF = VDD
TYP.
VIH3
P20 to P27
0.7AVREF
AVREF
VIH4
P60 to P63
0.7VDD
6.0
VIH1
0.7VDD
VDD
VIH2
0.8VDD
VDD
0.7AVREF
AVREF
0.7VDD
6.0
VIH3
P20 to P27
VIH4
P60 to P63
VIL1
0.3VDD
VIL2
0.2VDD
VIL3
P20 to P27
0.3AVREF
VIL1
0.3VDD
VIL2
0.2VDD
VIL3
P20 to P27
AVREF = VDD
0.3AVREF
VOH1
VDD 0.7
VDD 0.5
VDD 0.5
P20 to P27
AVREF = VDD,
IOH2 = 100 A
VDD 0.5
P121 to P124
IOH2 = 100 A
VDD 0.5
VOH2
AVREF = VDD
AVREF = VDD
Notes 1. Supported products: 78K0/KF2, 78K0/KD2 and 78K0/KE2 whose flash memory is at least 48 KB
2. Supported products: 78K0/KB2, 78K0/KC2, 78K0/KD2 and 78K0/KE2 whose flash memory is less than
32 KB
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
757
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
DC Characteristics (3/4)
(TA = 40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V)
Parameter
Output voltage, low
Symbol
VOL1
Conditions
P00 to P06, P10 to P17,
P30 to P33, P40 to P47,
P50 to P57, P64 to P67,
P70 to P77, P120, P130,
P140 to P145
MIN.
TYP.
MAX.
Unit
0.7
0.7
0.5
0.4
V
V
VOL2
P20 to P27
AVREF = VDD,
IOL2 = 0.4 mA
0.4
P121 to P124
IOL2 = 0.4 mA
0.4
VOL3
P60 to P63
2.0
0.4
0.6
0.4
0.4
VI = VDD
ILIH1
high
ILIH2
P20 to P27
VI = AVREF = VDD
ILIH3
P121 to 124
VI = VDD
OSC mode
20
VI = VSS
ILIL1
ILIL2
P20 to P27
ILIL3
P121 to 124
VI = VSS
OSC mode
20
RU
VI = VSS
10
100
VIL
0.2VDD
VIH
In self-programming mode
0.8VDD
VDD
Remark
758
20
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
DC Characteristics (4/4)
(TA = 40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V)
Parameter
Supply current
Symbol
Note 1
IDD1
Conditions
Note 2
Operating
fXH = 20 MHz
mode
VDD = 5.0 V
Notes 2, 3
fXH = 10 MHz
VDD = 5.0 V
Notes 2, 3
fXH = 10 MHz
VDD = 3.0 V
Notes 2, 3
fXH = 5 MHz
VDD = 3.0 V
Notes 2, 3
fXH = 5 MHz
VDD = 2.0 V
MIN.
TYP.
MAX.
Unit
3.2
5.5
mA
Resonator connection
4.5
6.9
mA
1.6
2.8
mA
Resonator connection
2.3
3.9
mA
1.5
2.7
mA
Resonator connection
2.2
3.2
mA
0.9
1.6
mA
Resonator connection
1.3
2.0
mA
0.7
1.4
mA
Resonator connection
1.0
1.6
mA
Note 4
1.4
2.5
mA
25
Resonator connection
15
30
0.8
2.6
mA
Note 5
VDD = 5.0 V
IDD2
Note 2
HALT
fXH = 20 MHz
mode
VDD = 5.0 V
Notes 2, 3
fXH = 10 MHz
VDD = 5.0 V
Notes 2, 3
fXH = 5 MHz
VDD = 3.0 V
Resonator connection
2.0
4.4
mA
0.4
1.3
mA
Resonator connection
1.0
2.4
mA
0.2
0.65
mA
Resonator connection
0.5
1.1
mA
Note 4
0.4
1.2
mA
3.0
22
Resonator connection
12
25
Note 5
VDD = 5.0 V
Note 6
IDD3
A/D converter
IADC
STOP
VDD = 5.0 V
20
mode
10
0.86
1.9
mA
10
18
Note 7
Note 8
operating current
Watchdog timer
IWDT
operating current
operation
Note 9
Remarks 1. fXH:
ILVI
High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
759
Standard products
Notes 1.
2.
Total current flowing into the internal power supply (VDD, EVDD), including the peripheral operation current
and the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. However, the
current flowing into the pull-up resistors and the output current of the port are not included.
Not including the operating current of the 8 MHz internal oscillator, 240 kHz internal oscillator, and XT1
oscillator, and the current flowing into the A/D converter, watchdog timer and LVI circuit.
3.
4.
Not including the operating current of the X1 oscillator, XT1 oscillator, and 240 kHz internal oscillator, and
the current flowing into the A/D converter, watchdog timer and LVI circuit.
5.
Not including the operating current of the X1 oscillator, 8 MHz internal oscillator, and 240 kHz internal
6.
Not including the operating current of the 240 kHz internal oscillator and XT1 oscillation, and the current
oscillator, and the current flowing into the A/D converter, watchdog timer and LVI circuit.
flowing into the A/D converter, watchdog timer and LVI circuit.
7.
Current flowing only to the A/D converter (AVREF). The current value of the 78K0/Kx2 microcontrollers is
8.
Current flowing only to the watchdog timer (including the operating current of the 240 kHz internal
the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
oscillator). The current value of the 78K0/Kx2 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT
when the watchdog timer operates.
9.
Current flowing only to the LVI circuit. The current value of the 78K0/KF2 is the sum of IDD1, IDD2 or IDD3
and ILVI when the LVI circuit operates.
760
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
AC Characteristics
(1) Basic operation
(TA = 40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V)
Parameter
Instruction cycle (minimum
instruction execution time)
Symbol
TCY
Conditions
Main system clock (fXP)
operation
MIN.
fPRS = fXH
(XSEL = 1)
0.1
32
0.2
32
32
125
Note 2
Note 1
0.4
114
122
20
MHz
10
MHz
MHz
fEXCLK
tEXCLKH,
tEXCLKL
Unit
fPRS
MAX.
TYP.
Note 3
7.6
8.4
MHz
7.6
10.4
MHz
Note 4
20.0
MHz
Note 4
10.0
MHz
5.0
MHz
1.0
1.0
1.0
24
ns
48
ns
96
ns
fEXCLKS
32
tEXCLKSH,
tEXCLKSL
12
tTIH0,
tTIL0
2/fsam +
Note 5
0.1
2/fsam +
Note 5
0.2
2/fsam +
Note 5
0.5
fTI5
tTIH5,
tTIL5
32.768
35
kHz
10
MHz
10
MHz
MHz
50
50
ns
100
ns
tINTH,
tINTL
ns
250
ns
10
Notes 1.
2.
3.
4.
5.
tRSL
761
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
TCY vs. VDD (Main System Clock Operation)
100
32
10
5.0
2.0
Guaranteed
operation range
1.0
0.4
0.2
0.1
0.01
0
1.0
2.0
1.8
3.0
4.0
2.7
Supply voltage VDD [V]
VIH
Test points
VIL
VIL
tEXCLKH
0.7VDD (MIN.)
0.3VDD (MAX.)
EXCLK
1/fEXCLKS
tEXCLKSL
0.7VDD (MIN.)
0.3VDD (MAX.)
EXCLKS
762
tEXCLKSH
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
TI Timing
tTIH0
tTIL0
1/fTI5
tTIL5
tTIH5
TI50, TI51
tINTL
INTP0 to INTP7
KR0 to KR7
RESET
763
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
(2) Serial interface
(TA = 40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V)
(a) UART6 (dedicated baud rate generator output)
Parameter
Symbol
Conditions
MIN.
TYP.
Transfer rate
MAX.
Unit
625
kbps
MAX.
Unit
625
kbps
Symbol
Conditions
MIN.
TYP.
Transfer rate
(c) IIC0
Parameter
Symbol
Conditions
Standard Mode
MIN.
MAX.
High-Speed Mode
MIN.
MAX.
Unit
fSCL
100
400
kHz
tSU: STA
4.7
0.6
tHD: STA
4.0
0.6
4.7
1.3
4.7
1.25
4.0
0.6
250
100
ns
Hold time
Note 1
tLOW
operation
Hold time when SCL0 = H
tHIGH
tSU: DAT
Note 2
tHD: DAT
fW = fXH/2 or fW =
DFC0 = 0
3.45
0.9
Note 4
Note 3
fEXSCL0 selected
1.00
DFC0 = 1
0.9
Note 5
Note 6
Note 7
1.125
fW = fRH/2
selected
DFC0 = 0
3.45
1.05
DFC0 = 1
1.184
Note 3
tSU: STO
4.0
0.6
tBUF
4.7
1.3
Notes 1.
2.
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
764
3.
fW indicates the IIC0 transfer clock selected by the IICCL and IICX0 registers.
4.
5.
6.
7.
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
(d) CSI1n (master mode, SCK1n... internal clock output)
Parameter
SCK1n cycle time
Symbol
tKCY1
tKH1,
Conditions
MIN.
ns
250
ns
500
ns
tKCY1/2
ns
15
tKSI1
tKSO1
ns
Note 1
tKCY1/2
50
Note 1
tKCY1/2
25
Unit
160
tSIK1
MAX.
tKL1
TYP.
ns
Note 1
55
ns
80
ns
170
ns
30
ns
Note 2
C = 50 pF
40
ns
MAX.
Unit
SO1n output
Notes 1.
2.
Symbol
Conditions
MIN.
TYP.
tKCY2
400
ns
tKH2,
tKCY2/2
ns
80
ns
50
ns
tKL2
SI1n setup time (to SCK1n)
tSIK2
tKSI2
tKSO2
Note
C = 50 pF
SO1n output
120
ns
120
ns
165
ns
n = 0, 1
765
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
(f) CSIA0 (master mode, SCKA0internal clock output)
Parameter
SCKA0 cycle time
Symbol
tKCY3
tKH3,
Conditions
MIN.
TYP.
MAX.
Unit
600
ns
1200
ns
1800
ns
tKCY3/2
ns
tKL3
50
2.7 V VDD < 4.0 V
tKCY3/2
ns
100
1.8 V VDD < 2.7 V
tKCY3/2
ns
200
SIA0 setup time (to SCKA0)
tSIK3
100
ns
200
ns
300
ns
tKSO3
SOA0 output
Note
C = 100 pF
200
ns
300
ns
400
ns
tKCY3/2
tSBD
ns
100
Strobe signal high-level width
tSBW
tKCY3
ns
30
2.7 V VDD < 4.0 V
tKCY3
ns
60
1.8 V VDD < 2.7 V
tKCY3
ns
120
Busy signal setup time (to
tBYS
100
200
ns
100
ns
tBYH
ns
tSPS
SCKA0
2tKCY3 +
ns
100
2.7 V VDD < 4.0 V
2tKCY3 +
ns
150
1.8 V VDD < 2.7 V
2tKCY3 +
200
Note C is the load capacitance of the SCKA0 and SOA0 output lines.
766
ns
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
(g) CSIA0 (slave mode, SCKA0external clock input)
Parameter
SCKA0 cycle time
Symbol
tKCY4
Conditions
MIN.
MAX.
600
ns
1200
ns
1800
ns
tKH4,
300
ns
tKL4
600
ns
900
ns
100
ns
2/fW +
ns
tSIK4
100
tKSO4
Note 2
C = 100 pF
SOA0 output
Note 1
2/fW +
100
Notes 1.
2.
tR4, tF4
ns
Note 1
2/fW +
300
ns
Note 1
2/fW +
200
Unit
TYP.
ns
Note 1
1000
ns
767
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
Serial Transfer Timing (1/2)
IIC0:
tLOW
SCL0
tHD: DAT
tHIGH
tHD: STA
tSU: STA
tHD: STA
tSU: STO
tSU: DAT
SDA0
tBUF
Stop
Start
condition condition
Restart
condition
CSI1n:
tKCYm
tKLm
tKHm
SCK1n
tSIKm
SI1n
tKSIm
Input data
tKSOm
SO1n
Remark
Output data
m = 1, 2
n = 0, 1
768
Stop
condition
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
Serial Transfer Timing (2/2)
CSIA0:
D2
SOA0
D2
SIA0
D1
D0
D1
D7
D0
D7
tKSI3, 4
tSIK3, 4
tKH3, 4
tKSO3, 4
tF4
SCKA0
tR4
tKL3, 4
tKCY3, 4
tSBD
tSBW
STB0
SCKA0
9Note
10Note
tBYS
10 + nNote
tBYH
1
tSPS
BUSY0
(active-high)
Note SCKA0 does not become low level here, but the timing is illustrated so that the timing specifications can be
shown.
769
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
A/D Converter Characteristics
(TA = 40 to +85C, 2.3 V AVREF VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V)
Parameter
Symbol
Resolution
Conditions
MIN.
TYP.
MAX.
Unit
10
bit
0.4
%FSR
0.6
%FSR
1.2
%FSR
RES
Notes 1, 2
Overall error
AINL
Conversion time
tCONV
Notes 1, 2
Zero-scale error
Full-scale error
EZS
Notes 1, 2
EFS
Note 1
ILE
Note 1
DLE
6.1
66.6
12.2
66.6
27
66.6
0.4
%FSR
0.6
%FSR
0.6
%FSR
0.4
%FSR
0.6
%FSR
0.6
%FSR
2.5
LSB
4.5
LSB
6.5
LSB
1.5
LSB
2.0
LSB
Notes 1.
2.
VAIN
AVSS
2.0
LSB
AVREF
Symbol
Detection voltage
VPOC
tPTH
tPW
Conditions
VDD: 0 V change inclination of VPOC
MIN.
TYP.
MAX.
Unit
1.44
1.59
1.74
0.5
V/ms
200
Time
770
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
Supply Voltage Rise Time (TA = 40 to +85C, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
tPUP1
(VDD: 0 V 1.8 V)
MAX.
Unit
3.6
ms
1.9
ms
tPUP2
Supply voltage
(VDD)
Supply voltage
(VDD)
1.8 V
1.8 V
VPOC
Time
Time
tPUP1
RESET pin
tPUP2
Symbol
VDDPOC
Conditions
POCMODE (option bye) = 1
MIN.
TYP.
MAX.
Unit
2.50
2.70
2.90
voltage
Remark
The operations of the POC circuit are as described below, depending on the POCMODE (option byte)
setting.
Option Byte Setting
POCMODE = 0
POC Mode
1.59 V mode operation
Operation
A reset state is retained until VPOC = 1.59 V (TYP.) is reached
after the power is turned on, and the reset is released when
VPOC is exceeded. After that, POC detection is performed at
VPOC, similarly as when the power was turned on.
The power supply voltage must be raised at a time of tPUP1 or
tPUP2 when POCMODE is 0.
POCMODE = 1
771
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
LVI Circuit Characteristics (TA = 40 to +85C, VPOC VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = 0 V)
Parameter
Detection
Symbol
voltage
Note 1
MIN.
TYP.
MAX.
Unit
VLVI0
4.14
4.24
4.34
VLVI1
3.99
4.09
4.19
VLVI2
3.83
3.93
4.03
VLVI3
3.68
3.78
3.88
VLVI4
3.52
3.62
3.72
VLVI5
3.37
3.47
3.57
VLVI6
3.22
3.32
3.42
VLVI7
3.06
3.16
3.26
VLVI8
2.91
3.01
3.11
VLVI9
2.75
2.85
2.95
VLVI10
2.60
2.70
2.80
VLVI11
2.45
2.55
2.65
VLVI12
2.29
2.39
2.49
VLVI13
2.14
2.24
2.34
VLVI14
1.98
2.08
2.18
VLVI15
1.83
1.93
2.03
1.11
1.21
1.31
EXLVI
Conditions
tLW
Note 2
200
tLWAIT
10
LVION 1
772
Time
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = 40 to +85C)
Parameter
Data retention supply voltage
Symbol
Conditions
VDDDR
MIN.
1.44
Note
TYP.
MAX.
Unit
5.5
Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC
reset is effected, but data is not retained when a POC reset is effected.
STOP mode
Operation mode
VDD
VDDDR
STOP instruction execution
773
Standard products
Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter.
Flash Memory Programming Characteristics
(TA = 40 to +85C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V)
Basic characteristics
Parameter
Symbol
TYP.
MAX.
Unit
4.5
11.0
mA
Teraca
20
200
ms
20
200
ms
10
100
Erase time
IDD
All block
Note 1
Twrwa
Cerwr
Conditions
MIN.
1 erase +
15 years
1000
Times
3 years
10000
Times
10 years
100
Times
the libraries
erase =
Note 3
1 rewrite
provided by
emulation libraries
provided by NEC
Notes 1.
Note 6
Characteristic of the flash memory. For the characteristic when a dedicated flash programmer, PG-FP4 or
PG-FP5, is used and the rewrite time during self programming, see Tables 27-12 and 27-13.
2.
The prewrite time before erasure and the erase verify time (writeback time) are not included.
3.
When a product is first written after shipment, erase write and write only are both taken as one
rewrite.
4.
The sample library specified by the 78K0/Kx2 Flash Memory Self Programming Users Manual
(Document No.: U17516E) is excluded.
5.
The sample program specified by the 78K0/Kx2 EEPROM Emulation Application Note (Document No.:
U17517E) is excluded.
6.
These include when the sample library specified by the 78K0/Kx2 Flash Memory Self Programming
Users Manual (Document No.: U17516E) and the sample program specified by the 78K0/Kx2 EEPROM
Emulation Application Note (Document No.: U17517E) are used.
774
78K0/KB2
78K0/KC2
30/36 Pins
Port 0
P00, P01
Port 1
P10 to P17
Port 2
P20 to P23
Port 3
P30 to P33
38 Pins
P20 to P25
Port 4
48 Pins
78K0/KE2
78K0/KF2
52 Pins
64 Pins
80 Pins
P00 to P03
P00 to P06
P20 to P27
P40, P41
Port 5
Port 6
44 Pins
78K0/KD2
P60, P61
Port 7
Port 12
P120 to P122
P40 to P43
P40 to P47
P50 to P53
P50 to P57
P60 to P63
P70, P71
P60 to P67
P70 to P73
P70 to P75
P70 to P77
P120 to P124
Port 13
P130
Port 14
P140
P140, P141
P140 to P145
775
78K0/KB2
78K0/KC2
30/36 Pins
38 Pins
44 Pins
48 Pins
78K0/KD2
78K0/KE2
78K0/KF2
52 Pins
64 Pins
80 Pins
Note 1
Note 1
AVSS
Power supply,
VDD, EVDD
ground
VSS, EVSS
Regulator
REGC
Reset
RESET
Clock
X1, X2,
oscillation
EXCLK
Writing to
FLMD0
AVREF, AVSS
flash memory
Interrupt
INTP0 to INTP5
Key interrupt
TM00
INTP0 to INTP6
KR0, KR1
Timer
KR0 to KR7
TM01
Serial interface
KR0 to KR3
INTP0 to INTP7
TM50
TI50, TO50
TM51
TI51, TO51
TMH0
TOH0
TMH1
TOH1
UART0
RxD0, TxD0
UART6
RxD6, TxD6
IIC0
SCL0, SDA0
CSI10
Note 2
TI001
, TI011
Note 2
Note 2
, TO01
CSI11
SCK11
SO11
Note 2
, SI11
Note 2
, SSI11
CSIA0
Note 2
Note 2
SCKA0, SIA0,
SOA0, BUSY0,
STB0
A/D converter
ANI0 to ANI3
ANI0 to ANI7
Clock output
PCL
Buzzer output
Low-voltage
ANI0 to ANI5
BUZ
EXLVI
detector (LVI)
776
Symbol
Conditions
VDD
Input voltage
Unit
0.5 to +6.5
EVDD
0.5 to +6.5
VSS
0.5 to +0.3
EVSS
0.5 to +0.3
0.5 to VDD + 0.3
AVREF
Ratings
V
Note
AVSS
0.5 to +0.3
VIREGC
VI1
V
V
Note
V
V
VO
VAN
0.3 to +6.5
0.3 to VDD + 0.3
ANI0 to ANI7
V
Note
Note
V
V
Note
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
777
Symbol
Ratings
Unit
10
mA
25
mA
55
mA
0.5
mA
mA
mA
mA
30
mA
60
mA
140
mA
mA
mA
mA
10
mA
TA
40 to +85
Tstg
65 to +150
IOH
Conditions
Per pin
Per pin
P20 to P27
P121 to P124
IOL
Per pin
Per pin
P20 to P27
P121 to P124
Cautions 1. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
2. The value of the current that can be run per pin must satisfy the value of the current per pin and
the total value of the currents of all pins.
Remark
778
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Recommended Circuit
X1 clock
Ceramic
resonator
Parameter
VSS X1
X2
Conditions
MIN.
MAX.
Unit
Note 2
20.0
MHz
Note 2
10.0
1.0
1.0
TYP.
oscillation
Note 1
frequency (fX)
C1
C2
1.8 V VDD < 2.7 V
X1 clock
Crystal
resonator
VSS X1
X2
1.0
1.0
1.0
5.0
Note 2
20.0
Note 2
10.0
MHz
oscillation
Note 1
frequency (fX)
C1
C2
1.8 V VDD < 2.7 V
1.0
5.0
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. It is 2.0 MHz (MIN.) when programming on the board via UART6.
Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the
above figures to avoid an adverse effect from wiring capacitance.
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. Since the CPU is started by the internal high-speed oscillation clock after a reset release, check
the X1 clock oscillation stabilization time using the oscillation stabilization time counter status
register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register
and oscillation stabilization time select register (OSTS) after sufficiently evaluating the
oscillation stabilization time with the resonator to be used.
Remark
For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
779
Parameter
Conditions
RSTS = 1
Note
MIN.
TYP.
MAX.
Unit
7.6
8.0
8.4
MHz
7.6
8.0
10.4
MHz
RSTS = 0
2.48
5.6
9.86
MHz
216
240
264
kHz
192
240
264
kHz
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Remark
Recommended Circuit
VSS XT2
XT1
Conditions
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
Note 2
frequency (fXT)
Rd
C4
Parameter
C3
For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
780
Symbol
Note 1
IOH1
MAX.
Unit
Conditions
4.0 V VDD 5.5 V
3.0
mA
2.5
mA
1.0
mA
12.0
mA
7.0
mA
5.0
mA
18.0
mA
15.0
mA
10.0
mA
23.0
mA
20.0
mA
15.0
mA
AVREF = VDD
0.1
mA
Note 3
MIN.
IOH2
0.1
mA
IOL1
8.5
mA
5.0
mA
2.0
mA
15.0
mA
5.0
mA
Note 2
TYP.
2.0
mA
20.0
mA
15.0
mA
9.0
mA
45.0
mA
35.0
mA
Note 3
IOL2
20.0
mA
65.0
mA
50.0
mA
29.0
mA
AVREF = VDD
0.4
mA
0.4
mA
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from VDD to an output
pin.
2. Value of current at which the device operation is guaranteed even if the current flows from an output pin to
GND.
3. Specification under conditions where the duty factor is 70% (time for which current is output is 0.7 t and
time for which current is not output is 0.3 t, where t is a specific time). The total output current of the pins
at a duty factor of other than 70% can be calculated by the following expression.
Where the duty factor of IOH is n%: Total output current of pins = (IOH 0.7)/(n 0.01)
<Example> Where the duty factor is 50%, IOH = 20.0 mA
Total output current of pins = (20.0 0.7)/(50 0.01) = 28.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Users Manual U18598EJ1V0UD
781
Conditions
MIN.
MAX.
Unit
VIH1
Symbol
0.7VDD
VDD
VIH2
0.8VDD
VDD
AVREF = VDD
TYP.
VIH3
P20 to P27
0.7AVREF
AVREF
VIH4
P60 to P63
0.7VDD
6.0
VIH1
0.7VDD
VDD
VIH2
0.8VDD
VDD
0.7AVREF
AVREF
0.7VDD
6.0
VIH3
P20 to P27
VIH4
P60 to P63
VIL1
0.3VDD
VIL2
0.2VDD
VIL3
P20 to P27
0.3AVREF
VIL1
0.3VDD
VIL2
0.2VDD
VIL3
P20 to P27
AVREF = VDD
0.3AVREF
VOH1
VDD 0.7
VDD 0.5
VDD 0.5
P20 to P27
AVREF = VDD,
IOH2 = 100 A
VDD 0.5
P121 to P124
IOH2 = 100 A
VDD 0.5
VOH2
AVREF = VDD
AVREF = VDD
Notes 1. Supported products: 78K0/KF2, 78K0/KD2 and 78K0/KE2 whose flash memory is at least 48 KB
2. Supported products: 78K0/KB2, 78K0/KC2, 78K0/KD2 and 78K0/KE2 whose flash memory is less than
32 KB
Remark
782
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Symbol
VOL1
Conditions
P00 to P06, P10 to P17,
P30 to P33, P40 to P47,
P50 to P57, P64 to P67,
P70 to P77, P120, P130,
P140 to P145
MIN.
TYP.
MAX.
Unit
0.7
0.7
0.5
0.4
V
V
VOL2
P20 to P27
AVREF = VDD,
IOL2 = 0.4 mA
0.4
P121 to P124
IOL2 = 0.4 mA
0.4
VOL3
P60 to P63
2.0
0.4
0.6
0.4
0.4
VI = VDD
ILIH1
high
ILIH2
P20 to P27
VI = AVREF = VDD
ILIH3
P121 to 124
VI =
VDD
OSC mode
20
VI = VSS
P20 to P27
ILIL3
P121 to 124
VI =
VSS
OSC mode
20
Pull-up resistor
RU
VI = VSS
10
100
VIL
0.2VDD
VIH
In self-programming mode
0.8VDD
VDD
Remark
20
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
783
Symbol
Note 1
IDD1
Conditions
Note 2
Operating
fXH = 20 MHz
mode
VDD = 5.0 V
Notes 2, 3
fXH = 10 MHz
VDD = 5.0 V
Notes 2, 3
fXH = 10 MHz
VDD = 3.0 V
Notes 2, 3
fXH = 5 MHz
VDD = 3.0 V
Notes 2, 3
fXH = 5 MHz
VDD = 2.0 V
MIN.
TYP.
MAX.
Unit
3.2
5.5
mA
Resonator connection
4.5
6.9
mA
1.6
2.8
mA
Resonator connection
2.3
3.9
mA
1.5
2.7
mA
Resonator connection
2.2
3.2
mA
0.9
1.6
mA
Resonator connection
1.3
2.0
mA
0.7
1.4
mA
Resonator connection
1.0
1.6
mA
Note 4
1.4
2.5
mA
30
Resonator connection
15
35
0.8
2.6
mA
Note 5
VDD = 5.0 V
IDD2
Note 2
HALT
fXH = 20 MHz
mode
VDD = 5.0 V
Notes 2, 3
fXH = 10 MHz
VDD = 5.0 V
Notes 2, 3
fXH = 5 MHz
VDD = 3.0 V
Resonator connection
2.0
4.4
mA
0.4
1.3
mA
Resonator connection
1.0
2.4
mA
0.2
0.65
mA
Resonator connection
0.5
1.1
mA
Note 4
0.4
1.2
mA
3.0
27
Resonator connection
12
32
Note 5
VDD = 5.0 V
Note 6
IDD3
A/D converter
IADC
STOP
VDD = 5.0 V
20
mode
10
0.86
1.9
mA
10
18
Note 7
Note 8
operating current
Watchdog timer
IWDT
operating current
operation
Note 9
Remarks 1. fXH:
ILVI
High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
784
2.
Total current flowing into the internal power supply (VDD, EVDD), including the peripheral operation current
and the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. However, the
current flowing into the pull-up resistors and the output current of the port are not included.
Not including the operating current of the 8 MHz internal oscillator, 240 kHz internal oscillator, and XT1
oscillator, and the current flowing into the A/D converter, watchdog timer and LVI circuit.
3.
4.
Not including the operating current of the X1 oscillator, XT1 oscillator, and 240 kHz internal oscillator, and
the current flowing into the A/D converter, watchdog timer and LVI circuit.
5.
Not including the operating current of the X1 oscillation, 8 MHz internal oscillator and 240 kHz internal
6.
Not including the operating current of the 240 kHz internal oscillator and XT1 oscillation, and the current
oscillator, and the current flowing into the A/D converter, watchdog timer and LVI circuit.
flowing into the A/D converter, watchdog timer and LVI circuit.
7.
Current flowing only to the A/D converter (AVREF). The current value of the 78K0/Kx2 microcontrollers is
8.
Current flowing only to the watchdog timer (including the operating current of the 240 kHz internal
the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
oscillator). The current value of the 78K0/Kx2 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT
when the watchdog timer operates.
9.
Current flowing only to the LVI circuit. The current value of the 78K0/Kx2 microcontrollers is the sum of
IDD1, IDD2 or IDD3 and ILVI when the LVI circuit operates.
785
AC Characteristics
(1) Basic operation
(TA = 40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V)
Parameter
Instruction cycle (minimum
instruction execution time)
Symbol
TCY
Conditions
Main system clock (fXP)
operation
MIN.
0.1
32
0.2
32
32
125
Note 1
0.4
Note 2
114
122
fPRS = fXH
(XSEL = 1)
20
MHz
10
MHz
MHz
fPRS = fRH
(XSEL = 0)
fEXCLK
tEXCLKH,
tEXCLKL
Unit
fPRS
MAX.
TYP.
Note 3
7.6
8.4
MHz
7.6
10.4
MHz
Note 4
20.0
MHz
Note 4
10.0
MHz
5.0
MHz
1.0
1.0
1.0
24
ns
48
ns
96
ns
fEXCLKS
32
tEXCLKSH,
tEXCLKSL
12
tTIH0,
tTIL0
2/fsam +
Note 5
0.1
2/fsam +
Note 5
0.2
2/fsam +
Note 5
0.5
fTI5
tTIH5,
tTIL5
32.768
35
kHz
10
MHz
10
MHz
MHz
50
50
ns
100
ns
tINTH,
tINTL
ns
250
ns
10
Notes 1.
2.
3.
4.
5.
786
tRSL
32
10
5.0
2.0
Guaranteed
operation range
1.0
0.4
0.2
0.1
0.01
0
1.0
2.0
1.8
3.0
4.0
2.7
Supply voltage VDD [V]
VIH
Test points
VIL
VIL
tEXCLKH
0.8VDD (MIN.)
0.2VDD (MAX.)
EXCLK
1/fEXCLKS
tEXCLKSL
tEXCLKSH
0.8VDD (MIN.)
0.2VDD (MAX.)
EXCLKS
787
tTIL0
1/fTI5
tTIL5
tTIH5
TI50, TI51
tINTL
INTP0 to INTP7
KR0 to KR7
RESET
788
Symbol
Conditions
MIN.
TYP.
Transfer rate
MAX.
Unit
625
kbps
MAX.
Unit
625
kbps
Symbol
Conditions
MIN.
TYP.
Transfer rate
(c) IIC0
Parameter
Symbol
Conditions
Standard Mode
fSCL
Hold time
tLOW
tHIGH
tSU:DAT
tHD:DAT
Note 2
MAX.
100
400
kHz
0.6
4.0
0.6
4.7
1.3
4.7
1.25
4.0
0.6
250
100
ns
fW = fXH/2 or
DFC0 = 0
fW = fEXSCL0 selected
(transmission)
MIN.
tHD:STA
MAX.
Unit
4.7
MIN.
High-Speed Mode
3.45
0.9
Note 4
Note 3
1.00
DFC0 = 1
0.9
Note 6
1.125
N
fW = fRH/2 selected
Note 3
Note 5
Note 7
DFC0 = 0
3.45
1.05
DFC0 = 1
1.184
tSU:STO
4.0
0.6
tBUF
4.7
1.3
Notes 1.
2.
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
3.
fW indicates the IIC0 transfer clock selected by the IICCL and IICX0 registers.
4.
5.
6.
7.
789
Symbol
tKCY1
tKH1,
Conditions
MIN.
TYP.
MAX.
Unit
200
ns
400
ns
600
ns
tKCY1/2
ns
Note 1
tKL1
20
2.7 V VDD < 4.0 V
tKCY1/2
ns
Note 1
30
1.8 V VDD < 2.7 V
tKCY1/2
ns
Note 1
60
SI1n setup time (to SCK1n)
tSIK1
tKSI1
tKSO1
70
ns
100
ns
190
ns
30
ns
Note 2
C = 50 pF
40
ns
MAX.
Unit
SO1n output
Notes 1.
2.
Symbol
Conditions
MIN.
TYP.
tKCY2
400
ns
tKH2,
tKCY2/2
ns
tKL2
SI1n setup time (to SCK1n)
tSIK2
80
ns
tKSI2
50
ns
tKSO2
SO1n output
C = 50
Note
pF
120
ns
120
ns
180
ns
790
n = 0, 1
Symbol
tKCY3
tKH3,
Conditions
MIN.
TYP.
MAX.
Unit
600
ns
1200
ns
1800
ns
tKCY3/2
ns
tKL3
50
2.7 V VDD < 4.0 V
tKCY3/2
ns
100
1.8 V VDD < 2.7 V
tKCY3/2
ns
200
SIA0 setup time (to SCKA0)
tSIK3
100
ns
200
ns
300
ns
tKSO3
SOA0 output
Note
C = 100 pF
200
ns
300
ns
400
ns
tKCY3/2
tSBD
ns
100
Strobe signal high-level width
tSBW
tKCY3
ns
30
2.7 V VDD < 4.0 V
tKCY3
ns
60
1.8 V VDD < 2.7 V
tKCY3
ns
120
Busy signal setup time (to
tBYS
100
ns
200
ns
100
ns
tBYH
tSPS
SCKA0
2tKCY3 +
ns
100
2.7 V VDD < 4.0 V
2tKCY3
ns
150
1.8 V VDD < 2.7 V
2tKCY3
ns
200
Note C is the load capacitance of the SCKA0 and SOA0 output lines.
791
Symbol
Conditions
MIN.
MAX.
600
ns
1200
ns
1800
ns
tKH4,
300
ns
tKL4
600
ns
900
ns
100
ns
2/fW +
ns
tSIK4
100
tKSO4
Note 2
C = 100 pF
SOA0 output
Note 1
2/fW +
100
Notes 1.
2.
792
tR4, tF4
ns
Note 1
1000
ns
Note 1
2/fW +
300
ns
Note 1
2/fW +
200
Unit
tKCY4
TYP.
ns
tHD:DAT
tHIGH
tHD:STA
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
SDA0
tBUF
Stop
Start
condition condition
Restart
condition
Stop
condition
CSI1n:
tKCYm
tKLm
tKHm
SCK1n
tSIKm
SI1n
tKSIm
Input data
tKSOm
SO1n
Remark
Output data
m = 1, 2
n = 0, 1
793
D2
SOA0
D2
SIA0
D1
D0
D1
D7
D0
D7
tKSI3, 4
tSIK3, 4
tKH3, 4
tKSO3, 4
tF4
SCKA0
tR4
tKL3, 4
tKCY3, 4
tSBD
tSBW
STB0
SCKA0
9Note
10Note
tBYS
10 + nNote
tBYH
1
tSPS
BUSY0
(active-high)
Note SCKA0 does not become low level here, but the timing is illustrated so that the timing specifications can be
shown.
794
Symbol
Resolution
Conditions
MIN.
TYP.
MAX.
Unit
10
bit
0.4
%FSR
0.6
%FSR
1.2
%FSR
RES
Notes 1, 2
Overall error
AINL
Conversion time
tCONV
Notes 1, 2
Zero-scale error
Full-scale error
EZS
Notes 1, 2
EFS
Note 1
ILE
Note 1
DLE
6.1
66.6
12.2
66.6
27
66.6
0.4
%FSR
0.6
%FSR
0.6
%FSR
0.4
%FSR
0.6
%FSR
0.6
%FSR
2.5
LSB
4.5
LSB
6.5
LSB
1.5
LSB
2.0
LSB
Notes 1.
2.
VAIN
AVSS
2.0
LSB
AVREF
Symbol
Detection voltage
VPOC
tPTH
tPW
Conditions
VDD: 0 V change inclination of VPOC
MIN.
TYP.
MAX.
Unit
1.44
1.59
1.74
0.5
V/ms
200
Time
Users Manual U18598EJ1V0UD
795
Symbol
Conditions
MIN.
TYP.
tPUP1
(VDD: 0 V 1.8 V)
MAX.
Unit
3.6
ms
1.9
ms
tPUP2
Supply voltage
(VDD)
Supply voltage
(VDD)
1.8 V
1.8 V
VPOC
Time
Time
tPUP1
RESET pin
tPUP2
Symbol
VDDPOC
Conditions
POCMODE (option bye) = 1
MIN.
TYP.
MAX.
Unit
2.50
2.70
2.90
voltage
Remark
The operations of the POC circuit are as described below, depending on the POCMODE (option byte)
setting.
Option Byte Setting
POCMODE = 0
POC Mode
1.59 V mode operation
Operation
A reset state is retained until VPOC = 1.59 V (TYP.) is reached
after the power is turned on, and the reset is released when
VPOC is exceeded. After that, POC detection is performed at
VPOC, similarly as when the power was turned on.
The power supply voltage must be raised at a time of tPUP1 or
tPUP2 when POCMODE is 0.
POCMODE = 1
796
Symbol
voltage
Note 1
MIN.
TYP.
MAX.
Unit
VLVI0
4.14
4.24
4.34
VLVI1
3.99
4.09
4.19
VLVI2
3.83
3.93
4.03
VLVI3
3.68
3.78
3.88
VLVI4
3.52
3.62
3.72
VLVI5
3.37
3.47
3.57
VLVI6
3.22
3.32
3.42
VLVI7
3.06
3.16
3.26
VLVI8
2.91
3.01
3.11
VLVI9
2.75
2.85
2.95
VLVI10
2.60
2.70
2.80
VLVI11
2.45
2.55
2.65
VLVI12
2.29
2.39
2.49
VLVI13
2.14
2.24
2.34
VLVI14
1.98
2.08
2.18
VLVI15
1.83
1.93
2.03
1.11
1.21
1.31
EXLVI
Conditions
tLW
Note 2
200
tLWAIT
10
LVION 1
Time
797
Symbol
Conditions
VDDDR
MIN.
1.44
Note
TYP.
MAX.
Unit
5.5
Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC
reset is effected, but data is not retained when a POC reset is effected.
STOP mode
Data retention mode
VDD
VDDDR
STOP instruction execution
798
Operation mode
Symbol
TYP.
MAX.
Unit
4.5
11.0
mA
Teraca
20
200
ms
20
200
ms
10
100
Erase time
IDD
All block
Note 1
Twrwa
Cerwr
Conditions
MIN.
1 erase +
15 years
1000
Times
3 years
10000
Times
10 years
100
Times
the libraries
erase =
Note 3
1 rewrite
provided by
emulation libraries
provided by NEC
Notes 1.
Note 6
Characteristic of the flash memory. For the characteristic when a dedicated flash programmer, PG-FP4 or
PG-FP5, is used and the rewrite time during self programming, see Tables 27-12 and 27-13.
2.
The prewrite time before erasure and the erase verify time (writeback time) are not included.
3.
When a product is first written after shipment, erase write and write only are both taken as one
rewrite.
4.
The sample library specified by the 78K0/Kx2 Flash Memory Self Programming Users Manual
(Document No.: U17516E) is excluded.
5.
The sample program specified by the 78K0/Kx2 EEPROM Emulation Application Note (Document No.:
U17517E) is excluded.
6.
These include when the sample library specified by the 78K0/Kx2 Flash Memory Self Programming
Users Manual (Document No.: U17516E) and the sample program specified by the 78K0/Kx2 EEPROM
Emulation Application Note (Document No.: U17517E) are used.
799
32.1 78K0/KB2
PD78F0500AMC-CAB-AX, 78F0501AMC-CAB-AX, 78F0502AMC-CAB-AX, 78F0503AMC-CAB-AX,
78F0503DAMC-CAB-AX, 78F0500AMC(A)-CAB-AX, 78F0501AMC(A)-CAB-AX, 78F0502AMC(A)-CAB-AX,
78F0503AMC(A)-CAB-AX
16
P
1
15
F
G
J
S
E
D
K
(UNIT:mm)
M M
ITEM
A
B
NOTE
Each lead centerline is located within 0.13 mm of its
true position (T.P.) at maximum material condition.
0.65 (T.P.)
0.22 +0.10
0.05
0.100.05
1.300.10
1.20
8.100.20
6.100.10
1.000.20
0.15 +0.05
0.01
0.50
0.13
0.10
3 +5
3
0.25(T.P.)
0.600.15
9.700.10
0.30
800
DIMENSIONS
0.25 MAX.
0.15 MAX.
P30MC-65-CAB
32x b
S AB
A
ZE
w S A
ZD
6
5
4
E
2.90
1
D
F E
y1
D C B A
E
2.90
w S B
INDEX MARK
A
y
DETAIL OF C PART
S
DETAIL OF D PART
DETAIL OF E PART
R0.170.05
0.700.05
0.550.05 R0.120.05
0.75
0.55
R0.170.05
0.700.05
R0.120.05 0.550.05
0.75
0.55
b
(Land pad)
0.340.05
(Aperture of
solder resist)
0.55
0.75
0.550.05
0.700.05
0.55
0.75
0.550.05
0.700.05
R0.2750.05
R0.350.05
(UNIT:mm)
ITEM
D
DIMENSIONS
4.000.10
4.000.10
0.20
0.50
0.910.07
0.240.05
0.05
0.08
y1
0.20
ZD
0.75
ZE
0.75
P36FC-50-AA3-2
801
32.2 78K0/KC2
PD78F0511AMC-GAA-AX, 78F0512AMC-GAA-AX, 78F0513AMC-GAA-AX, 78F0513DAMC-GAA-AX
20
P
1
19
F
G
J
S
E
D
K
(UNIT:mm)
M M
ITEM
A
B
NOTE
Each lead centerline is located within 0.10 mm of its
true position (T.P.) at maximum material condition.
0.65 (T.P.)
0.30 +0.10
0.05
0.1250.075
2.00 MAX.
1.700.10
8.100.20
6.100.10
1.000.20
0.15 +0.10
0.05
0.50
0.10
0.10
3 +5
3
0.25(T.P.)
0.600.15
12.300.10
0.30
802
DIMENSIONS
0.25 MAX.
0.15 MAX.
P38MC-65-GAA
HD
detail of lead end
L1
33
A3
23
22
34
L
Lp
HE
(UNIT:mm)
44
12
ITEM
D
11
1
ZE
ZD
b
S
A
A1
NOTE
Each lead centerline is located within 0.20 mm of
its true position at maximum material condition.
10.000.20
HD
12.000.20
HE
12.000.20
1.60 MAX.
A1
0.100.05
A2
1.400.05
A3
A2
DIMENSIONS
10.000.20
0.25
0.35 +0.08
0.04
0.125 +0.075
0.025
0.50
Lp
0.600.15
L1
1.000.20
+5
3 3
0.80
0.20
0.10
ZD
1.00
ZE
1.00
P44GB-80-GAF
803
36
A3
25
37
24
L
Lp
L1
HE
(UNIT:mm)
13
48
1
12
ZE
e
ZD
b
A
A2
A1
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
804
DIMENSIONS
7.000.20
7.000.20
HD
9.000.20
HE
9.000.20
1.60 MAX.
A1
0.100.05
A2
1.400.05
A3
0.25
+0.07
0.20 0.03
ITEM
D
0.125 +0.075
0.025
0.50
Lp
0.600.15
L1
1.000.20
+5
3 3
0.50
0.08
0.08
ZD
0.75
ZE
0.75
P48GA-50-GAM
32.3 78K0/KD2
PD78F0521AGB-GAG-AX, 78F0522AGB-GAG-AX, 78F0523AGB-GAG-AX, 78F0524AGB-GAG-AX,
78F0525AGB-GAG-AX, 78F0526AGB-GAG-AX, 78F0527AGB-GAG-AX, 78F0527DAGB-GAG-AX,
78F0521AGB(A)-GAG-AX, 78F0522AGB(A)-GAG-AX, 78F0523AGB(A)-GAG-AX, 78F0524AGB(A)-GAG-AX,
78F0525AGB(A)-GAG-AX, 78F0526AGB(A)-GAG-AX, 78F0527AGB(A)-GAG-AX
HD
detail of lead end
L1
39
40
27
26
A3
c
HE
Lp
(UNIT:mm)
52
14
13
ZE
e
b
ZD
S
A
A2
S
A1
NOTE
Each lead centerline is located within 0.13mm of
its true position at maximum material condition.
ITEM
D
DIMENSIONS
10.000.20
10.000.20
HD
12.000.20
HE
12.000.20
1.60 MAX.
A1
0.100.05
A2
1.400.05
A3
0.25
0.30 +0.08
0.04
0.125 +0.075
0.025
0.50
Lp
0.600.15
L1
1.000.20
3 +5
3
0.65
0.13
0.10
ZD
1.10
ZE
1.10
P52GB-65-GAG
805
32.4 78K0/KE2
PD78F0531AGB-GAH-AX, 78F0532AGB-GAH-AX, 78F0533AGB-GAH-AX, 78F0534AGB-GAH-AX,
78F0535AGB-GAH-AX, 78F0536AGB-GAH-AX, 78F0537AGB-GAH-AX, 78F0537DAGB-GAH-AX,
78F0531AGB(A)-GAH-AX, 78F0532AGB(A)-GAH-AX, 78F0533AGB(A)-GAH-AX, 78F0534AGB(A)-GAH-AX,
78F0535AGB(A)-GAH-AX, 78F0536AGB(A)-GAH-AX, 78F0537AGB(A)-GAH-AX
48
A3
33
49
32
L
Lp
L1
HE
(UNIT:mm)
17
64
1
16
ZE
e
ZD
b
S
A
A2
A1
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
806
ITEM
D
DIMENSIONS
10.000.20
10.000.20
HD
12.000.20
HE
12.000.20
1.60 MAX.
A1
0.100.05
A2
1.400.05
A3
0.25
+0.07
0.20 0.03
0.125 +0.075
0.025
0.50
Lp
0.600.15
L1
1.000.20
3 +5
3
0.50
0.08
0.08
ZD
1.25
ZE
1.25
P64GB-50-GAH
A3
48
49
33
32
L
Lp
HE
L1
(UNIT:mm)
64
ITEM
D
17
16
ZE
e
ZD
b
S
A
A1
NOTE
Each lead centerline is located within 0.20 mm of
its true position at maximum material condition.
14.000.20
HD
17.200.20
HE
17.200.20
1.70 MAX.
A1
0.1250.075
A2
1.400.05
A3
A2
DIMENSIONS
14.000.20
0.25
0.35 +0.08
0.04
0.125 +0.075
0.025
0.80
Lp
0.8860.15
L1
1.600.20
+5
3 3
0.80
0.20
0.10
ZD
1.00
ZE
1.00
P64GC-80-GAL
807
33
49
32
A3
c
L
Lp
HE
L1
(UNIT:mm)
64
17
1
16
ZE
e
ZD
b
S
A
A1
NOTE
Each lead centerline is located within 0.13 mm of
its true position at maximum material condition.
808
DIMENSIONS
12.000.20
12.000.20
HD
14.000.20
HE
14.000.20
1.60 MAX.
A1
0.100.05
A2
1.400.05
A3
A2
ITEM
D
0.25
0.30 +0.08
0.04
0.125 +0.75
0.25
0.50
Lp
0.600.15
L1
1.000.20
3 +5
3
0.65
0.13
0.10
ZD
ZE
1.125
1.125
P64GK-65-GAJ
48
A3
33
49
32
L
Lp
L1
HE
(UNIT:mm)
64
17
1
16
ZE
e
ZD
ITEM
D
DIMENSIONS
7.000.20
7.000.20
HD
9.000.20
HE
9.000.20
1.20 MAX.
A1
0.100.05
A2
1.000.05
A3
0.25
+0.07
0.16 0.03
S
A2
A1
NOTE
Each lead centerline is located within 0.07mm of
its true position at maximum material condition.
0.125 +0.075
0.025
0.50
Lp
0.600.15
L1
1.000.20
+5
3 3
0.40
0.07
0.08
ZD
0.50
ZE
0.50
P64GA-40-HAB
809
60x b
S AB
A
ZE
w S A
ZD
8
7
6
5
3.90
4
3
2
1
B
E
C
D
H G F E D C B A
y1
3.90
w S B
INDEX MARK
A
S
y
DETAIL OF C PART
S
DETAIL OF D PART
DETAIL OF E PART
R0.170.05
0.700.05
0.550.05 R0.120.05
0.75
0.55
R0.170.05
0.700.05
R0.120.05 0.550.05
0.75
0.55
b
(Land pad)
0.340.05
(Aperture of
solder resist)
810
0.55
0.75
0.550.05
0.700.05
0.55
0.75
0.550.05
0.700.05
R0.2750.05
R0.350.05
(UNIT:mm)
ITEM
D
DIMENSIONS
5.000.10
5.000.10
0.20
0.50
0.910.07
0.240.05
0.05
0.08
y1
0.20
ZD
0.75
ZE
0.75
P64FC-50-AA1-1
32.5 78K0/KF2
PD78F0544AGC-GAD-AX, 78F0545AGC-GAD-AX, 78F0546AGC-GAD-AX, 78F0547AGC-GAD-AX,
78F0547DAGC-GAD-AX, 78F0544AGC(A)-GAD-AX, 78F0545AGC(A)-GAD-AX, 78F0546AGC(A)-GAD-AX,
78F0547AGC(A)-GAD-AX
60
61
A3
41
40
L
Lp
HE
L1
(UNIT:mm)
80
1
21
20
ZE
e
ZD
b
S
A
A2
S
A1
NOTE
Each lead centerline is located within 0.13 mm of
its true position at maximum material condition.
ITEM
D
DIMENSIONS
14.000.20
14.000.20
HD
17.200.20
HE
17.200.20
1.70 MAX.
A1
0.1250.075
A2
1.400.05
A3
0.25
+0.08
0.30 0.04
0.125 +0.075
0.025
0.80
Lp
0.8860.15
L1
1.600.20
3 +5
3
0.65
0.13
0.10
ZD
ZE
0.825
0.825
P80GC-65-GAD
811
60
A3
41
c
61
40
L
Lp
L1
HE
(UNIT:mm)
21
80
1
20
ZE
e
ZD
b
A2
S
A1
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
812
DIMENSIONS
12.000.20
12.000.20
HD
14.000.20
HE
14.000.20
1.60 MAX.
A1
0.100.05
A2
1.400.05
A3
0.25
+0.07
0.20 0.03
ITEM
D
0.125 +0.075
0.025
0.50
Lp
0.600.15
L1
1.000.20
3 +5
3
0.50
0.08
0.08
ZD
1.25
ZE
1.25
P80GK-50-GAK
These products should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, please contact an NEC Electronics
sales representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Remark
Evaluation of the soldering conditions for the 38-pin products of 78K0/KC2 is incomplete because these
products are under development.
Table 33-1. Surface Mounting Type Soldering Conditions
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher),
Note
Note
IR60-207-3
Pin temperature: 350C max., Time: 3 seconds max. (per pin row)
After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
Cautions 1.
2.
Do not use different soldering methods together (except for partial heating).
The PD78F05xxDA has an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when
this function is used, and product reliability therefore cannot be guaranteed. NEC Electronics is
not liable for problems occurring when the on-chip debug function is used.
813
814
Register
Access
Hardware
Serial interface
ASIS0
Read
1 clock (fixed)
ASIS6
Read
1 clock (fixed)
IICS0
Read
1 clock (fixed)
ADM
Write
ADS
Write
ADPC
Write
ADCR
Read
UART0
Serial interface
UART6
Serial interface
IIC0
A/D converter
The above number of clocks is when the same source clock is selected for fCPU and fPRS. The number of wait
clocks can be calculated by the following expression and under the following conditions.
<Calculating number of wait clocks>
2 fCPU
+1
Number of wait clocks =
fAD
* Fraction is truncated if the number of wait clocks 0.5 and rounded up if the number of wait clocks > 0.5.
fAD:
fCPU:
fPRS:
fXP:
Caution When the peripheral hardware clock (fPRS) is stopped, do not access the registers listed above
using an access method in which a wait request is issued.
Remark The clock is the CPU clock (fCPU).
815
Table 34-2. RAM Accesses That Generate Wait and Number of CPU Wait Clocks (78K0/KF2 only)
Area
Buffer RAM
Access
Write
1 to 81 clocks
5 fCPU
+1
fW
* Fraction is truncated if the number of wait clocks multiplied by (1/fCPU) is equal or lower than tCPUL and rounded up if higher than
tCPUL.
fW:
Frequency of base clock selected by CKS00 bit of CSIS0 register (CKS00 = 0: fPRS, CKS00 = 1: fPRS/2)
Note No waits are generated when five CSIA0 operating clocks or more are inserted between writing to the RAM
from the CSIA0 and writing to the buffer RAM from the CPU.
816
The following development tools are available for the development of systems that employ the 78K0/Kx2
microcontrollers.
Figure A-1 shows the development tool configuration.
Support for PC98-NX series
Unless otherwise specified, products supported by IBM PC/ATTM compatibles are compatible with PC98-NX
series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles.
WindowsTM
Unless otherwise specified, Windows means the following OSs.
Windows 98
Windows NTTM
Windows 2000
Windows XP
817
Debugging software
Integrated debuggerNote 4
C compiler package
System simulator
Device fileNote 1
C library source fileNote 2
Control software
Project manager
(Windows only)Note 3
Host machine
(PC or EWS)
USB interface cableNote 4
Power supply unitNote 4
QB-78K0KX2Note 4
Flash memory
write environment
Flash memory
programmerNote 4
Emulation probe
Flash memory
write adapter
Flash memory
Target system
Notes 1.
Download the device file for 78K0/Kx2 microcontrollers (DF780547) from the download site for
development tools (http://www.necel.com/micro/ods/eng/index.html).
2.
3.
4.
The QB-78K0KX2 is supplied with the integrated debugger ID78K0-QB, a USB interface cable, a
power supply unit, the on-chip debug emulator QB-MINI2, connection cables (10-pin and 16-pin
cables), and the 78K0-OCD board. Any other products are sold separately.
Download the software for operating the QB-MINI2 from the download site for development tools
(http://www.necel.com/micro/ods/eng/index.html) when using the QB-MINI2.
818
Debugging software
Integrated debuggerNote 4
C compiler package
System simulator
Device fileNote 1
C library source fileNote 2
Control software
Project manager
(Windows only)Note 3
Host machine
(PC or EWS)
USB interface cableNote 4
QB-78K0MININote 4
Flash memory
write environment
Flash memory
programmer
Connection cableNote 4
Flash memory
write adapter
Flash memory
Target connector
Target system
Notes 1.
Download the device file for 78K0/Kx2 microcontrollers (DF780547) from the download site for
development tools (http://www.necel.com/micro/ods/eng/index.html).
2.
3.
4.
On-chip debug emulator QB-78K0MINI is supplied with integrated debugger ID78K0-QB, USB
interface cable, and connection cable. Any other products are sold separately.
819
Debugging software
Integrated debuggerNote 1
C compiler package
System simulator
Device fileNote 1
C library source fileNote 2
Control software
Project manager
(Windows only)Note 3
Host machine
(PC or EWS)
USB interface cableNote 4
QB-MINI2Note 4
QB-MINI2Note 4
Connection cable
78K0-OCD boardNote 4
(16-pin cable)Note 4
Connection cable
(10-pin/16-pin cable)Note 4
Target connector
Target system
Notes 1.
Download the device file for 78K0/Kx2 microcontrollers (DF780547) and the integrated debugger
(ID78K0-QB) from the download site for development tools
(http://www.necel.com/micro/ods/eng/index.html).
2.
3.
4.
On-chip debug emulator QB-MINI2 is supplied with USB interface cable, connection cables (10-pin
cable and 16-pin cable), and 78K0-OCD board. Any other products are sold separately. In addition,
download the software for operating the QB-MINI2 from the download site for development tools
(http://www.necel.com/micro/ods/eng/index.html).
820
Development tools (software) common to the 78K0 microcontrollers are combined in this
package.
package
Remark
in the part number differs depending on the host machine and OS used.
SSP78K0
Host Machine
OS
AB17
PC-9800 series,
BB17
Supply Medium
CD-ROM
This assembler converts programs written in mnemonics into object codes executable
Assembler package
with a microcontroller.
This assembler is also provided with functions capable of automatically creating symbol
tables and branch instruction optimization.
This assembler should be used in combination with a device file (DF780547).
<Precaution when using RA78K0 in PC environment>
This assembler package is a DOS-based application. It can also be used in Windows,
however, by using the Project Manager (included in assembler package) on Windows.
Part number: SRA78K0
CC78K0
This compiler converts programs written in C language into object codes executable with
C compiler package
a microcontroller.
This compiler should be used in combination with an assembler package and device file.
<Precaution when using CC78K0 in PC environment>
This C compiler package is a DOS-based application. It can also be used in Windows,
however, by using the Project Manager (included in assembler package) on Windows.
Part number: SCC78K0
Note 1
DF780547
Device file
This device file should be used in combination with a tool (RA78K0, CC78K0, SM+ for
78K0/KX2, and ID78K0-QB).
The corresponding OS and host machine differ depending on the tool to be used.
Part number: SDF780547
CC78K0-L
Note 2
This is a source file of the functions that configure the object library included in the C
compiler package.
This file is required to match the object library included in the C compiler package to the
users specifications.
Part number: SCC78K0-L
Notes 1.
The DF780547 can be used in common with the RA78K0, CC78K0, SM+ for 78K0/Kx2, and ID78K0QB. Download the DF780547 from the download site for development tools
(http://www.necel.com/micro/ods/eng/index.html).
2.
821
Remark
in the part number differs depending on the host machine and OS used.
SRA78K0
SCC78K0
SCC78K0-L
Host Machine
AB17
PC-9800 series,
BB17
3P17
3K17
TM
SPARCstation
OS
TM
Supply Medium
CD-ROM
TM
SunOS
TM
TM
Solaris
(Rel. 10.10)
(Rel. 4.1.4)
(Rel. 2.5.1)
SDF780547
Host Machine
OS
AB13
PC-9800 series,
BB13
Supply Medium
3.5-inch 2HD FD
This is control software designed to enable efficient user program development in the
Project manager
822
Note 1
, FP-LITE3
Note 2
Flash memory programming adapter used connected to the flash memory programmer
Notes 1.
2.
memory.
for use.
Phase-out
The part numbers of the flash memory programming adapter and the packages of the target device are
described below.
Package
78K0/KB2
FA-30MC-5A4-A,
FA-78F0503MC-5A4-MX
78K0/KC2
FA-78F0503FC-AA3-MX
Under development
FA-78F0515GA-8EU-MX
FA-78F0513GB-UES-MX,
FA-44GB-8ES-A
78K0/KD2
78K0/KE2
FA-52GB-8ET-A,
FA-78F0527GB-UET-MX
FA-64GB-8EU-A,
FA-78F0537GB-UEU-MX
FA-64GC-8BS-A,
FA-78F0537GC-UBS-MX
FA-64GK-9ET-A,
FA-78F0537GK-UET-MX
78K0/KF2
FA-78F0537GA-8EV-MX
FA-78F0537FC-AA1-MX
FA-80GC-8BT-A,
FA-78F0547GC-UBT-MX
FA-80GK-9EU-A,
FA-78F0547GK-8EU-MX
Remarks 1. FL-PR5, FL-PR4, FP-LITE3, and FA-xxxx are products of Naito Densei Machida Mfg. Co., Ltd.
TEL: +81-42-750-4172 Naito Densei Machida Mfg. Co., Ltd.
2. Use the latest version of the flash memory programming adapter.
823
A.4.2 When using on-chip debug emulator with programming function QB-MINI2
QB-MINI2
memory. It is available also as on-chip debug emulator which serves to debug hardware
programming function
and software when developing application systems using the 78K0/Kx2 microcontrollers.
When using this as flash memory programmer, it should be used in combination with a
connection cable (16-pin cable) and a USB interface cable that is used to connect the
host machine.
Remarks 1. The QB-MINI2 is supplied with a USB interface cable and connection cables (10-pin cable and 16pin cable), and the 78K0-OCD board. A connection cable (10-pin cable) and the 78K0-OCD board
are used only when using the on-chip debug function.
2. Download the software for operating the QB-MINI2 from the download site for development tools
(http://www.necel.com/micro/ods/eng/index.html).
This in-circuit emulator serves to debug hardware and software when developing application
systems using the 78K0/Kx2 microcontrollers. It supports to the integrated debugger (ID78K0QB). This emulator should be used in combination with a power supply unit and emulation probe,
and the USB is used to connect this emulator to the host machine.
QB-144-CA-01
Check pin adapter
This check pin adapter is used in waveform monitoring using the oscilloscope, etc.
QB-80-EP-01T
Emulation probe
This emulation probe is flexible type and used to connect the in-circuit emulator and target
system.
Note
This exchange adapter is used to perform pin conversion from the in-circuit emulator to target
connector.
Note
This space adapter is used to adjust the height between the target system and in-circuit emulator.
Note
This YQ connector is used to connect the target connector and exchange adapter.
Note
This mount adapter is used to mount the target device with socket.
Note
QB-xxxx-EA-xxx
Exchange adapter
QB-xxxx-YS-xxx
Space adapter
QB-xxxx-YQ-xxx
YQ connector
QB-xxxx-HQ-xxx
Mount adapter
QB-xxxx-NQ-xxx ,
Target connector
824
Note The part numbers of the exchange adapter, space adapter, YQ connector, mount adapter, and target
connector and the packages of the target device are described below.
Package
Exchange
Space Adapter
YQ Connector
Mount Adapter
Adapter
78K0/KB2
Target
Connector
QB-30MC-
QB-30MC-
QB-30MC-
QB-30MC-
(MC-5A4 and
EA-02T
YS-01T
YQ-01T
HQ-01T
NQ-01T
QB-36FC-
None
None
None
QB-36FC-
(FC-AA3 type)
EA-01T
MC-CAB types)
78K0/KC2
78K0/KD2
78K0/KE2
78K0/KF2
NQ-01T
QB-38MCNote
QB-38MCNote
QB-38MCNote
QB-38MCNote
(MC-GAA type)
EA-01T
YQ-01T
YQ-01T
HQ-01T
NQ-01T
QB-44GB-
QB-44GB-
QB-44GB-
QB-44GB-
QB-44GB-
(GB-GAF type)
EA-03T
YS-01T
YQ-01T
HQ-01T
NQ-01T
QB-48GA-
QB-48GA-
QB-48GA-
QB-48GA-
QB-48GA-
(GA-GAM type)
EA-02T
YS-01T
YQ-01T
HQ-01T
NQ-01T
QB-52GB-
QB-52GB-
QB-52GB-
QB-52GB-
QB-52GB-
(GB-GAG type)
EA-02T
YS-01T
YQ-01T
HQ-01T
NQ-01T
QB-64GB-
QB-64GB-
QB-64GB-
QB-64GB-
QB-64GB-
(GB-GAH type)
EA-04T
YS-01T
YQ-01T
HQ-01T
NQ-01T
QB-64GC-
QB-64GC-
QB-64GC-
QB-64GC-
QB-64GC-
(GC-GAL type)
EA-03T
YS-01T
YQ-01T
HQ-01T
NQ-01T
QB-64GK-
QB-64GK-
QB-64GK-
QB-64GK-
QB-64GK-
(GK-GAJ type)
EA-04T
YS-01T
YQ-01T
HQ-01T
NQ-01T
QB-64GA-
QB-64GA-
QB-64GA-
QB-64GA-
QB-64GA-
(GA-9EV type)
EA-01T
YS-01T
YQ-01T
HQ-01T
NQ-01T
QB-64FC-
None
None
None
QB-64FC-
(FC-AA1 type)
EA-01T
QB-80GC-
QB-80GC-
QB-80GC-
QB-80GC-
QB-80GC-
(GC-GAD type)
EA-01T
YS-01T
YQ-01T
HQ-01T
NQ-01T
QB-80GK-
QB-80GK-
QB-80GK-
QB-80GK-
QB-80GK-
(GK-GAK type)
EA-01T
YS-01T
YQ-01T
HQ-01T
NQ-01T
NQ-01T
825
Remarks 1. The QB-78K0KX2 is supplied with the integrated debugger ID78K0-QB, a USB interface cable, a
power supply unit, the on-chip debug emulator QB-MINI2, connection cables (10-pin and 16-pin
cables), and the 78K0-OCD board.
Download the software for operating the QB-MINI2 from the download site for development tools
(http://www.necel.com/micro/ods/eng/index.html) when using the QB-MINI2.
2. The packed contents of QB-78K0KX2 differ depending on the part number, as follows.
Packed Contents In-Circuit Emulator
Emulation Probe
Exchange Adapter
YQ Connector
Target Connector
QB-30MC-YQ-01T
QB-30MC-NQ-01T
Part Number
QB-78K0KX2
QB-78K0KX2-ZZZ
None
QB-80-EP-01T
QB-78K0KX2-T30MC
QB-78K0KX2-T36FC
QB-30MC-EA-02T
QB-36FC-EA-01T
Note
Note
None
QB-38MC-YQ-01T
QB-36FC-NQ-01T
Note
QB-38MC-NQ-01T
Note
QB-78K0KX2-T38MC
QB-38MC-EA-01T
QB-78K0KX2-T44GB
QB-44GB-EA-03T
QB-44GB-YQ-01T
QB-44GB-NQ-01T
QB-78K0KX2-T48GA
QB-48GA-EA-02T
QB-48GA-YQ-01T
QB-48GA-NQ-01T
QB-78K0KX2-T52GB
QB-52GB-EA-02T
QB-52GB-YQ-01T
QB-52GB-NQ-01T
QB-78K0KX2-T64GB
QB-64GB-EA-04T
QB-64GB-YQ-01T
QB-64GB-NQ-01T
QB-78K0KX2-T64GC
QB-64GC-EA-03T
QB-64GC-YQ-01T
QB-64GC-NQ-01T
QB-78K0KX2-T64GK
QB-64GK-EA-04T
QB-64GK-YQ-01T
QB-64GK-NQ-01T
QB-78K0KX2-T64GA
QB-64GA-EA-01T
QB-64GA-YQ-01T
QB-64GA-NQ-01T
QB-78K0KX2-T64FC
QB-64FC-EA-01T
None
QB-64FC-NQ-01T
QB-78K0KX2-T80GC
QB-80GC-EA-01T
QB-80GC-YQ-01T
QB-80GC-NQ-01T
QB-78K0KX2-T80GK
QB-80GK-EA-01T
QB-80GK-YQ-01T
QB-80GK-NQ-01T
This on-chip debug emulator serves to debug hardware and software when developing
application systems using the 78K0/Kx2. It supports the integrated debugger (ID78K0-QB). This
emulator should be used in combination with a connection cable and a USB interface cable that is
used to connect the host machine.
Target connector
specifications
Remark
The QB-78K0MINI is supplied with a USB interface cable, connection cables, and the integrated
debugger ID78K0-QB.
826
A.5.3 When using on-chip debug emulator with programming function QB-MINI2
QB-MINI2
This on-chip debug emulator serves to debug hardware and software when developing
programming function
programmer dedicated to microcontrollers with on-chip flash memory. When using this
as on-chip debug emulator, it should be used in combination with a connection cable (10pin cable or 16-pin cable), a USB interface cable that is used to connect the host
machine, and the 78K0-OCD board.
Remarks 1. The QB-MINI2 is supplied with a USB interface cable and connection cables (10-pin cable and 16pin cable), and the 78K0-OCD board. A connection cable (10-pin cable) and the 78K0-OCD board
are used only when using the on-chip debug function.
2. Download the software for operating the QB-MINI2 from the download site for development tools
(http://www.necel.com/micro/ods/eng/index.html).
System simulator
It is used to perform debugging at the C source level or assembler level while simulating
the operation of the target system on a host machine.
Use of SM+ for 78K0/Kx2 allows the execution of application logical testing and
performance testing on an independent basis from hardware development, thereby
providing higher development efficiency and software quality.
SM+ for 78K0/KX2 should be used in combination with the device file (DF780547).
Part number: SSM780547-B
ID78K0-QB
This debugger supports the in-circuit emulators for the 78K0 microcontrollers. The
Integrated debugger
Remark
in the part number differs depending on the host machine and OS used.
SSM780547-B
SID78K0-QB
Host Machine
OS
AB17
PC-9800 series,
BB17
Supply Medium
CD-ROM
827
This chapter shows areas on the target system where component mounting is prohibited and areas where there
are component mounting height restrictions when the QB-78K0KX2 is used.
12.5
13.375
11.5
10
10
12.5
17.375
Note
828
11.5
Note
Height can be adjusted by using space adapters (each adds 2.4 mm)
3.5
3.5
4
21.8
15
13.375
9.85
10
9.85
10
15
17.375
Note
Height can be adjusted by using space adapters (each adds 2.4 mm)
829
15
10
15
13.375
17.375
Note
Note
10
9.5
9.5
Height can be adjusted by using space adapters (each adds 2.4 mm)
15
13.375
9.85
10
10
15
17.375
Note
Note Height can be adjusted by using space adapters (each adds 2.4 mm)
830
9.85
3.5
3.5
4
21.8
: Exchange adapter area (connector part): Components up to 2.45 mm in height can be mounted
: Exchange adapter area (probe part):
15
13.375
9.5
10
9.5
10
15
17.375
Note
Note Height can be adjusted by using space adapters (each adds 2.4 mm)
831
15
10
15
13.375
17.375
Note
10
10.5
10.5
Note
Height can be adjusted by using space adapters (each adds 2.4 mm)
15
11.85
10
10
15
13.375
17.375
Note
Note
832
11.85
Height can be adjusted by using space adapters (each adds 2.4 mm)
Users Manual U18598EJ1V0UD
15
10.5
10
10.5
10
15
13.375
17.375
Note
Note
Height can be adjusted by using space adapters (each adds 2.4 mm)
15
12.05
10
12.05
10
15
13.375
17.375
Note
Note
Height can be adjusted by using space adapters (each adds 2.4 mm)
Users Manual U18598EJ1V0UD
833
15
10.5
10
10
15
13.375
17.375
Note
Note
834
10.5
Height can be adjusted by using space adapters (each adds 2.4 mm)
C.1 Register Index (In Alphabetical Order with Respect to Register Names)
[A]
A/D converter mode register (ADM)............................................................................................................................400
A/D port configuration register (ADPC) ...............................................................................................................209, 406
Analog input channel specification register (ADS) ......................................................................................................405
Asynchronous serial interface control register 6 (ASICL6)..........................................................................................453
Asynchronous serial interface operation mode register 0 (ASIM0) .............................................................................423
Asynchronous serial interface operation mode register 6 (ASIM6) .............................................................................447
Asynchronous serial interface reception error status register 0 (ASIS0).....................................................................425
Asynchronous serial interface reception error status register 6 (ASIS6).....................................................................449
Asynchronous serial interface transmission status register 6 (ASIF6) ........................................................................450
Automatic data transfer address count register 0 (ADTC0) ........................................................................................510
Automatic data transfer address point specification register 0 (ADTP0) .....................................................................508
Automatic data transfer interval specification register 0 (ADTI0) ................................................................................509
[B]
Baud rate generator control register 0 (BRGC0).........................................................................................................426
Baud rate generator control register 6 (BRGC6).........................................................................................................452
[C]
Capture/compare control register 00 (CRC00)............................................................................................................269
Capture/compare control register 01 (CRC01)............................................................................................................269
Clock operation mode select register (OSCCTL) ........................................................................................................219
Clock output selection register (CKS) .........................................................................................................................392
Clock selection register 6 (CKSR6).............................................................................................................................450
[D]
Divisor selection register 0 (BRGCA0)........................................................................................................................507
[E]
8-bit A/D conversion result register (ADCRH) .............................................................................................................404
8-bit timer compare register 50 (CR50).......................................................................................................................336
8-bit timer compare register 51 (CR51).......................................................................................................................336
8-bit timer counter 50 (TM50)......................................................................................................................................336
8-bit timer counter 51 (TM51)......................................................................................................................................336
8-bit timer H carrier control register 1 (TMCYC1)........................................................................................................360
8-bit timer H compare register 00 (CMP00) ................................................................................................................355
8-bit timer H compare register 01 (CMP01) ................................................................................................................355
8-bit timer H compare register 10 (CMP10) ................................................................................................................355
8-bit timer H compare register 11 (CMP11) ................................................................................................................355
8-bit timer H mode register 0 (TMHMD0) ....................................................................................................................356
8-bit timer H mode register 1 (TMHMD1) ....................................................................................................................356
8-bit timer mode control register 50 (TMC50) .............................................................................................................340
8-bit timer mode control register 51 (TMC51) .............................................................................................................340
Users Manual U18598EJ1V0UD
835
836
837
838
C.2 Register Index (In Alphabetical Order with Respect to Register Symbol)
[A]
ADCR:
ADCRH:
ADM:
ADPC:
ADS:
ADTC0:
ADTI0:
ADTP0:
ASICL6:
ASIF6:
ASIM0:
ASIM6:
ASIS0:
ASIS6:
[B]
BANK:
BRGC0:
BRGC6:
BRGCA0:
[C]
CKS:
CKSR6:
CMP00:
CMP01:
CMP10:
CMP11:
CR000:
CR001:
CR010:
CR011:
CR50:
CR51:
CRC00:
CRC01:
CSIC10:
CSIC11:
CSIM10:
CSIM11:
CSIMA0:
CSIS0:
CSIT0:
839
[D]
DMUC0:
[E]
EGN:
EGP:
[I]
IF0H:
IF0L:
IF1H:
IF1L:
IIC0:
IICC0:
IICCL0:
IICF0:
IICS0:
IICX0:
IMS:
ISC:
IXS:
[K]
KRM:
[L]
LVIM:
LVIS:
[M]
MCM:
MDA0H:
MDA0L:
MDB0:
MK0H:
MK0L:
MK1H:
MK1L:
MOC:
[O]
OSCCTL:
OSTC:
OSTS:
[P]
P0:
P1:
P2:
840
P3:
P4:
P5:
P6:
P7:
P12:
P13:
P14:
PCC:
PM0:
PM1:
Port mode register 1........................................................................................ 195, 342, 361, 427, 455, 485
PM2:
PM3:
PM4:
PM5:
PM6:
PM7:
PM12:
PM14:
PR0H:
PR0L:
PR1H:
PR1L:
PRM00:
PRM01:
PU0:
PU1:
PU3:
PU4:
PU5:
PU6:
PU7:
PU12:
PU14:
[R]
RCM:
RESF:
RXB0:
RXB6:
RXS0:
RXS6:
[S]
SDR0:
SIO10:
841
SIO11:
SIOA0:
SOTB10:
SOTB11:
SVA0:
[T]
TCL50:
TCL51:
TM00:
TM01:
TM50:
TM51:
TMC00:
TMC01:
TMC50:
TMC51:
TMCYC1:
TOC01:
TXB6:
TXS0:
TXS6:
[W]
WDTE:
WTM:
842
Hard
Chapter
Chapter 1
Chapter 2
Hard Classification
(1/28)
Function
Details of
Function
Cautions
Page
pp. 35,
37 to 40
AVSS, EVSS
pp. 36,
41 to 43
EVDD
pp. 36,
41 to 43
REGC
pp. 35
to 43
ANI0/P20 to
ANIn/P2n
ANI0/P20 to ANIn/P2n are set in the analog input mode after release of reset.
pp. 35
to 43
ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset.
p. 74
p. 74
P31/INTP2/
OCD1A
p. 75
Process the P31/INTP2/OCD1A pin of the products mounted with the on-chip
debug function (PD78F05xxDA) as follows, when it is not used when it is
connected to a flash memory programmer or an on-chip debug emulator (see the
table on p.75).
p. 79
P121/X1/OCD0A Process the P121/X1/OCD0A pin of the products mounted with the on-chip
debug function (PD78F05xxDA) as follows, when it is not used when it is
connected to a flash memory programmer or an on-chip debug emulator (see the
table on p.79).
Soft
Chapter 3
REGC pin
Memory
space
Keep the wiring length as short as possible for the broken-line part in the above
figure.
p. 82
p. 88
IMS, IXS: Internal Regardless of the internal memory capacity, the initial values of the internal
memory size
memory size switching register (IMS) and internal expansion RAM size switching
switching register, register (IXS) of all products in the 78K0/Kx2 microcontrollers are fixed (IMS =
internal expansion CFH, IXS = 0CH). Therefore, set the value corresponding to each product as
RAM size
indicated below.
switching register To set the memory size, set IMS and then IXS. Set the memory size so that the p. 88
internal ROM and internal expansion RAM areas do not overlap.
Memory bank
p. 105
p. 105
p. 105
p. 105
SFR: Special
Do not access addresses to which SFRs are not assigned.
function register
p. 107
SP: Stack
pointer
p. 117
843
Soft
Chapter
Chapter 4
Chapter 5
Soft Classification
(2/28)
Function
Memory
bank
switching
function
(PD78F
05x6A,
78F05x7A,
78F05x7DA
(x = 2 to 4)
only)
Port
function
Details of
Function
Cautions
Page
BANK: Memory
bank select
register
Be sure to change the value of the BANK register in the common area (0000H to p. 141
7FFFH).
If the value of the BANK register is changed in the bank area (8000H to BFFFH),
an inadvertent program loop occurs in the CPU. Therefore, never change the
value of the BANK register in the bank area.
Memory bank
p. 142
Branching and accessing cannot be directly executed between different memory p. 142
banks. Execute branching or accessing between different memory banks via the
common area.
P02/SO11,
P04/SCK11
p. 142
p. 142
To use P02/SO11 and P04/SCK11 as general-purpose ports, set serial operation p. 155
mode register 11 (CSIM11) and serial clock selection register 11 (CSIC11) to the
default status (00H).
p. 166
Port 2
Make the AVREF pin the same potential as the VDD pin when port 2 is used as a
digital port.
p. 172
For the 38-pin products of 78K0/KC2, be sure to set bits 6 and 7 of PM2 to 1,
and bits 6 and 7 of P2 to 0.
p. 173
p. 174
P31/INTP2/
OCD1A
Soft
p. 174
Process the P31/INTP2/OCD1A pin of the products mounted with the on-chip
debug function (PD78F05xxDA) as follows, when it is not used when it is
connected to a flash memory programmer or an on-chip debug emulator (see the
table on p.174).
Port 4
For the 38-pin products of 78K0/KC2, be sure to set bits 0 and 1 of PM4 and P4
to 0.
p. 178
Port 7
For the 38-pin products of 78K0/KC2, be sure to set bits 2 and 3 of PM7 and P7
to 0.
p. 185
P121/X1/OCD0A,
P122/X2/EXCLK/
OCD0B,
P123/XT1,
P124/XT2/EXCLKS
When using the P121 to P124 pins to connect a resonator for the main system
p. 186
clock (X1, X2) or subsystem clock (XT1, XT2), or to input an external clock for
the main system clock (EXCLK) or subsystem clock (EXCLKS), the X1 oscillation
mode, XT1 oscillation mode, or external clock input mode must be set by using
the clock operation mode select register (OSCCTL) (for details, see 6.3 (1)
Clock operation mode select register (OSCCTL) and (3) Setting of operation
mode for subsystem clock pin). The reset value of OSCCTL is 00H (all of the
P121 to P124 pins are I/O port pins). At this time, setting of the PM121 to
PM124 and P121 to P124 pins is not necessary.
p. 187
Process the P121/X1/OCD0A pin of the products mounted with the on-chip
debug function (PD78F05xxDA) as follows, when it is not used when it is
connected to a flash memory programmer or an on-chip debug emulator (see the
table on p.187).
Port mode
registers
Be sure to set bits 2 to 7 of PM0, bits 4 to 7 of PM2, bits 4 to 7 of PM3, bits 2 to 7 p. 195
of PM6, bits 3 to 7 of PM12 to 1. (78K0/KB2)
p. 196
For the 38-pin products, be sure to set bits 2 to 7 of PM0, bits 6 and 7 of PM2,
bits 4 to 7 of PM3, bits 2 to 7 of PM4, bits 4 to 7 of PM6, bits 4 to 7 of PM7, and
bits 5 to 7 of PM12 to 1. Also, be sure to set bits 0 and 1 of PM4, and bits 2
and 3 of PM7 to 0.
For the 44-pin products, be sure to set bits 2 to 7 of PM0, bits 4 to 7 of PM3, bits
2 to 7 of PM4, bits 4 to 7 of PM6, bits 4 to 7 of PM7, and bits 5 to 7 of PM12 to
1.
For the 48-pin products, be sure to set bits 2 to 7 of PM0, bits 4 to 7 of PM3, bits
2 to 7 of PM4, bits 4 to 7 of PM6, bits 6 and 7 of PM7, bits 5 to 7 of PM12, and
bits 1 to 7 of PM14 to 1. (78K0/KC2)
844
Chapter 5
Chapter
Soft Classification
(3/28)
Function
Port
function
Details of
Function
Port mode
registers
Cautions
Page
Be sure to set bits 4 to 7 of PM0, bits 4 to 7 of PM3, bits 2 to 7 of PM4, bits 4 to 7 p. 197
of PM6, bits 5 to 7 of PM12, and bits 1 to 7 of PM14 to 1. (78K0/KD2)
Be sure to set bit 7 of PM0, bits 4 to 7 of PM3, bits 4 to 7 of PM4, bits 4 to 7 of
PM5, bits 4 to 7 of PM6, bits 5 to 7 of PM12, and bits 2 to 7 of PM14 to 1.
(78K0/KE2)
p. 198
Be sure to set bit 7 of PM0, bits 4 to 7 of PM3, bits 5 to 7 of PM12, and bits 6 and p. 199
7 of PM14 to 1. (78K0/KF2)
Port register
(78K0/KC2)
For the 38-pin products, be sure to set bits 6 and 7 of P2, bits 0 and 1 of P4, and p. 201
bits 2 and 3 of P7 to 0.
ADPC: A/D port Set the channel used for A/D conversion to the input mode by using port mode
configuration
register 2 (PM2).
register
If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC
when the peripheral hardware clock is stopped. For details, see CHAPTER 34
CAUTIONS FOR WAIT.
Chapter 6
Soft
1-bit
manipulation
instruction for
port register n
(Pn)
Clock
generator
OSCCTL: Clock Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency
operation mode exceeds 10 MHz.
select register
Set AMPH before setting the peripheral functions after a reset release. The
value of AMPH can be changed only once after a reset release. When the highspeed system clock (X1 oscillation) is selected as the CPU clock, supply of the
CPU clock is stopped for 4.06 to 16.12 s after AMPH is set to 1. When the
high-speed system clock (external clock input) is selected as the CPU clock,
supply of the CPU clock is stopped for the duration of 160 external clocks after
AMPH is set to 1.
p. 210
p. 210
p. 214
pp. 220,
221
pp. 220,
221
If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is pp. 220,
stopped for 4.06 to 16.12 s after the STOP mode is released when the internal 221
high-speed oscillation clock is selected as the CPU clock, or for the duration of
160 external clocks when the high-speed system clock (external clock input) is
selected as the CPU clock. When the high-speed system clock (X1 oscillation) is
selected as the CPU clock, the oscillation stabilization time is counted after the
STOP mode is released.
To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7
pp. 220,
(MSTOP) of the main OSC control register (MOC) is 1 (the X1 oscillator stops or 221
the external clock from the EXCLK pin is disabled).
Be sure to clear bits 1 to 5 to 0. (78K0/KB2)
Be sure to clear bits 1 to 3 to 0. (78K0/KC2 to 78K0/KF2)
PCC: Processor Be sure to clear bits 3 to 7 to 0. (78K0/KB2)
clock control
Be sure to clear bits 3 and 7 to 0. (78K0/KC2 to 78K0/KF2)
register
The peripheral hardware clock (fPRS) is not divided when the division ratio of the
PCC is set.
p. 220
p. 221
p. 222
p. 223
pp. 222,
223
Confirm that bit 5 (CLS) of the processor clock control register (PCC) is 0 (CPU is p. 224
operating with main system clock) when changing the current values of
XTSTART, EXCLKS, and OSCSELS.
845
Chapter 6
Chapter
Soft Classification
(4/28)
Function
Clock
generator
Details of
Function
Cautions
RCM: Internal
When setting RSTOP to 1, be sure to confirm that the CPU operates with a clock
oscillation mode other than the internal high-speed oscillation clock. Specifically, set under either
register
of the following conditions.
<1> 78K0/KB2
When MCS = 1 (when CPU operates with the high-speed system clock)
<2> 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2
When MCS = 1 (when CPU operates with the high-speed system clock)
When CLS = 1 (when CPU operates with the subsystem clock)
In addition, stop peripheral hardware that is operating on the internal high-speed
oscillation clock before setting RSTOP to 1.
Page
p. 225
MOC: Main OSC When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock p. 226
control register other than the high-speed system clock. Specifically, set under either of the
following conditions.
<1> 78K0/KB2
When MCS = 0 (when CPU operates with the internal high-speed
oscillation clock)
<2> 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2
When MCS = 0 (when CPU operates with the internal high-speed
oscillation clock)
When CLS = 1 (when CPU operates with the subsystem clock)
In addition, stop peripheral hardware that is operating on the high-speed system
clock before setting MSTOP to 1.
Do not clear MSTOP to 0 while bit 6 (OSCSEL) of the clock operation mode select p. 226
register (OSCCTL) is 0 (I/O port mode).
Soft Hard
Soft
Hard
p. 226
The peripheral hardware cannot operate when the peripheral hardware clock is
stopped. To resume the operation of the peripheral hardware after the peripheral
hardware clock has been stopped, initialize the peripheral hardware.
846
MCM: Main
clock mode
register
OSTC:
Oscillation
stabilization time
counter status
register
p. 227
Do not rewrite MCM0 when the CPU clock operates with the subsystem clock.
p. 227
A clock other than fPRS is supplied to the following peripheral functions regardless p. 227
of the setting of XSEL and MCM0.
Watchdog timer (operates with internal low-speed oscillation clock)
7
9
When fRL, fRL/2 , or fRL/2 is selected as the count clock for 8-bit timer H1
(operates with internal low-speed oscillation clock)
Peripheral hardware selects the external clock as the clock source
(Except when the external count clock of TM0n (n = 0, 1) is selected (TI00n pin
valid edge))
After the above time has elapsed, the bits are set to 1 in order from MOST11 and p. 228
remain 1.
The oscillation stabilization time counter counts up to the oscillation stabilization p. 228
time set by OSTS. If the STOP mode is entered and then released while the
internal high-speed oscillation clock is being used as the CPU clock, set the
oscillation stabilization time as follows.
Desired OSTC oscillation stabilization time Oscillation stabilization time set by
OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
The X1 clock oscillation stabilization wait time does not include the time until clock p. 228
oscillation starts (a below).
OSTS:
Oscillation
stabilization time
select register
To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
before executing the STOP instruction.
p. 229
Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
p. 229
Chapter
Classification
OSTS:
Oscillation
stabilization time
select register
Cautions
Page
The oscillation stabilization time counter counts up to the oscillation stabilization p. 229
time set by OSTS. If the STOP mode is entered and then released while the
internal high-speed oscillation clock is being used as the CPU clock, set the
oscillation stabilization time as follows.
Desired OSTC oscillation stabilization time Oscillation stabilization time set by
OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
The X1 clock oscillation stabilization wait time does not include the time until clock p. 229
oscillation starts (a below).
X1/XT1
oscillator
Clock
generator
operation
when
power
supply
voltage is
turned on
Soft
Chapter 6
Clock
generator
Details of
Function
Hard
Function
Soft
(5/28)
p. 231
When using the X1 oscillator and XT1 oscillator, wire as follows in the area
enclosed by the broken lines in the Figures 6-12 and 6-13 to avoid an adverse
effect from wiring capacitance.
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines. Do not route the wiring near
a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as
VSS. Do not ground the capacitor to a ground pattern through which a high
current flows.
Do not fetch signals from the oscillator.
Note that the XT1 oscillator is designed as a low-amplitude circuit for reducing
power consumption.
When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase
with XT1, resulting in malfunctioning.
p. 232
It is not necessary to wait for the oscillation stabilization time when an external
clock input from the EXCLK and EXCLKS pins is used.
pp. 236,
237
p. 237
Do not change the value of EXCLK and OSCSEL while the external main systerm p. 238
clock is operating.
p. 238
Set the external main system clock after the supply voltage has reached the
operable voltage of the clock to be used (see CHAPTER 30 ELECTRICAL
SPECIFICATIONS (STANDARD PRODUCTS) and CHAPTER 31 ELECTRICAL
SPECIFICATIONS ((A) GRADE PRODUCTS)).
Main system
clock
If the high-speed system clock is selected as the main system clock, a clock other p. 239
than the high-speed system clock cannot be set as the peripheral hardware clock.
High-speed
system clock
p. 240
p. 242
847
Soft
Chapter 6
Chapter
Classification
(6/28)
Function
Details of
Function
Controlling XT1/P123,
subsystem XT2/EXCLKS/
clock
P124
External clock
from peripheral
hardware pins
Cautions
Page
The XT1/P123 and XT2/EXCLKS/P124 pins are in the I/O port mode after a reset p. 243
release.
p. 243
Do not start the peripheral hardware operation with the external clock from
peripheral hardware pins when the internal high-speed oscillation clock and highspeed system clock are stopped while the CPU operates with the subsystem
clock, or when in the STOP mode.
XT1 clock,
Do not change the value of XTSTART, EXCLKS, and OSCSELS while the
external
subsystem clock is operating.
subsystem clock
p. 243
Subsystem clock Be sure to confirm that CLS = 0 when clearing OSCSELS to 0. In addition, stop
the watch timer if it is operating on the subsystem clock.
p. 244
The subsystem clock oscillation cannot be stopped using the STOP instruction.
p. 244
If Internal low-speed oscillator cannot be stopped is selected by the option byte, p. 245
Controlling Internal lowspeed oscillation oscillation of the internal low-speed oscillation clock cannot be controlled.
internal
low-speed clock
oscillation
clock
CPU clock
pp. 249,
Set the clock after the supply voltage has reached the operable voltage of the
250, 252
clock to be set (see CHAPTER 30 ELECTRICAL SPECIFICATIONS
(STANDARD PRODUCTS) and CHAPTER 31 ELECTRICAL SPECIFICATIONS
((A) GRADE PRODUCTS)).
p. 255
Selection of the main system clock cycle division factor (PCC0 to PCC2) and
switchover from the main system clock to the subsystem clock (changing CSS
from 0 to 1) should not be set simultaneously.
Simultaneous setting is possible, however, for selection of the main system clock
cycle division factor (PCC0 to PCC2) and switchover from the subsystem clock to
the main system clock (changing CSS from 1 to 0).
Hard
Soft
Chapter 7
When switching the internal high-speed oscillation clock to the high-speed system p. 256
clock, bit 2 (XSEL) of MCM must be set to 1 in advance. The value of XSEL can
be changed only once after a reset release.
848
16-bit
timer/event
counters
00, 01
Do not rewrite MCM0 when the CPU clock operates with the subsystem clock.
p. 256
The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin
at the same time, and the valid edge of TI011 and timer output (TO01) cannot be
used for the P06 pin at the same time. Select either of the functions.
p. 261
If clearing of bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control
register 0n (TMC0n) to 00 and input of the capture trigger conflict, then the
captured data is undefined.
p. 261
To change the mode from the capture mode to the comparison mode, first clear
the TMC0n3 and TMC0n2 bits to 00, and then change the setting. A value that
has been once captured remains stored in CR00n unless the device is reset. If
the mode has been changed to the comparison mode, be sure to set a
comparison value.
p. 261
TM0n: 16-bit
Even if TM0n is read, the value is not captured by CR01n.
timer counter 0n
p. 262
CR00n, CR01n:
16-bit timer
capture/compare
registers 00n,
01n
CR00n does not perform the capture operation when it is set in the comparison
mode, even if a capture trigger is input to it.
p. 263
CR01n does not perform the capture operation when it is set in the comparison
mode, even if a capture trigger is input to it.
p. 263
To capture the count value of the TM0n register to the CR00n register by using
p. 265
the phase reverse to that input to the TI00n pin, the interrupt request signal
(INTTM00n) is not generated after the value has been captured. If the valid edge
is detected on the TI01n pin during this operation, the capture operation is not
performed but the INTTM00n signal is generated as an external interrupt signal.
To not use the external interrupt, mask the INTTM00n signal.
Cautions
Page
TMC0n: 16-bit
16-bit timer/event counter 0n starts operation at the moment TMC0n2 and
p. 266
timer mode
TMC0n3 are set to values other than 00 (operation stop mode), respectively. Set
control register 0n TMC0n2 and TMC0n3 to 00 to stop the operation.
CRC0n: Capture/ To ensure that the capture operation is performed properly, the capture trigger
compare control requires a pulse two cycles longer than the count clock selected by prescaler
register 0n
mode register 0n (PRM0n).
pp. 269,
270
TOC0n: 16-bit
Be sure to set TOC0n using the following procedure.
timer output
<1> Set TOC0n4 and TOC0n1 to 1.
control register 0n <2> Set only TOE0n to 1.
<3> Set either of LVS0n or LVR0n to 1.
p. 271
PRM0n: Prescaler Do not apply the following setting when setting the PRM0n1 and PRM0n0 bits to p. 274
mode register 0n 11 (to specify the valid edge of the TI00n pin as a count clock).
Clear & start mode entered by the TI00n pin valid edge
Setting the TI00n pin as a capture trigger
Soft
Hard
If the operation of the 16-bit timer/event counter 0n is enabled when the TI00n or p. 274
TI01n pin is at high level and when the valid edge of the TI00n or TI01n pin is
specified to be the rising edge or both edges, the high level of the TI00n or TI01n
pin is detected as a rising edge. Note this when the TI00n or TI01n pin is pulled
up. However, the rising edge is not detected when the timer operation has been
once stopped and then is enabled again.
The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin p. 274
at the same time, and the valid edge of TI011 and timer output (TO01) cannot be
used for the P06 pin at the same time. Select either of the functions.
Clear & start
mode entered by
TI00n pin valid
edge input
Do not set the count clock as the valid edge of the TI00n pin (PRM0n1 and
PRM0n0 = 11). When PRM0n1 and PRM0n0 = 11, TM0n is cleared.
PPG output
To change the duty factor (value of CR01n) during operation, see 7.5.1 Rewriting p. 310
CR01n during TM0n operation.
Set values to CR00n and CR01n such that the condition 0000H CR01n <
CR00n FFFFH is satisfied.
One-shot pulse
output
p. 288
p. 312
Do not input the trigger again (setting OSPT0n to 1 or detecting the valid edge of p. 314
the TI00n pin) while the one-shot pulse is output. To output the one-shot pulse
again, generate the trigger after the current one-shot pulse output has completed.
To use only the setting of OSPT0n to 1 as the trigger of one-shot pulse output, do p. 314
not change the level of the TI00n pin or its alternate function port pin. Otherwise,
the pulse will be unexpectedly output.
LVS0n, LVRn0
p. 316
Be sure to set LVS0n and LVR0n following steps <1>, <2>, and <3> above.
Step <2> can be performed after <1> and before <3>.
p. 328
Hard
Chapter
Classification
Soft
Details of
Function
Timer start errors An error of up to one clock may occur in the time required for a match signal to
be generated after timer start. This is because counting TM0n is started
asynchronously to the count pulse.
Soft
Chapter 7
16-bit
timer/event
counters
00, 01
Hard
Function
Soft
(7/28)
CR00n, CR01n:
16-bit timer
capture/compare
registers 00n, 01n
p. 329
p. 329
Set a value other than 0000H to CR00n and CR01n in clear & start mode entered p. 329
upon a match between TM0n and CR00n (TM0n cannot count one pulse when it
is used as an external event counter).
When the valid edge is input to the TI00n/TI01n pin and the reverse phase of the p. 330
TI00n pin is detected while CR00n/CR01n is read, CR01n performs a capture
operation but the read value of CR00n/CR01n is not guaranteed. At this time, an
interrupt signal (INTTM00n/INTTM01n) is generated when the valid edge of the
TI00n/TI01n pin is detected (the interrupt signal is not generated when the
reverse-phase edge of the TI00n pin is detected).
When the count value is captured because the valid edge of the TI00n/TI01n pin
was detected, read the value of CR00n/CR01n after INTTM00n/INTTM01n is
generated.
849
Chapter
Classification
Chapter 7
Page
CR00n, CR01n: The values of CR00n and CR01n are not guaranteed after 16-bit timer/event
counter 0n stops.
16-bit timer
capture/compare
registers 00n,
01n
p. 330
ES0n0, ES0n1
Set the valid edge of the TI00n pin while the timer operation is stopped (TMC0n3
and TMC0n2 = 00). Set the valid edge by using ES0n0 and ES0n1.
p. 330
Re-triggering
one-shot pulse
Make sure that the trigger is not generated while an active level is being output in p. 330
the one-shot pulse output mode. Be sure to input the next trigger after the current
active level is output.
OVF0n
The OVF0n flag is set to 1 in the following case, as well as when TM0n overflows. p. 331
Select the clear & start mode entered upon a match between TM0n and CR00n.
Set CR00n to FFFFH.
When TM0n matches CR00n and TM0n is cleared from FFFFH to 0000H
Even if the OVF0n flag is cleared to 0 after TM0n overflows and before the next
count clock is counted (before the value of TM0n becomes 0001H), it is set to 1
again and clearing is invalid.
p. 331
One-shot pulse
output
One-shot pulse output operates correctly in the free-running timer mode or the
clear & start mode entered by the TI00n pin valid edge. The one-shot pulse
cannot be output in the clear & start mode entered upon a match between TM0n
and CR00n.
p. 331
TI00n
When the valid edge of TI00n is specified as the count clock, the capture register
for which TI00n is specified as a trigger does not operate correctly.
p. 332
TI00n, TI01n
To accurately capture the count value, the pulse input to the TI00n and TI01n pins p. 332
as a capture trigger must be wider than two count clocks selected by PRM0n (see
Figure 7-9).
INTTM00n,
INTTM01n
The capture operation is performed at the falling edge of the count clock but the
interrupt signals (INTTM00n and INTTM01n) are generated at the rising edge of
the next count clock (see Figure 7-9).
CRC0n1 = 1
p. 332
When the count value of the TM0n register is captured to the CR00n register in
the phase reverse to the signal input to the TI00n pin, the interrupt signal
(INTTM00n) is not generated after the count value is captured. If the valid edge is
detected on the TI01n pin during this operation, the capture operation is not
performed but the INTTM00n signal is generated as an external interrupt signal.
Mask the INTTM00n signal when the external interrupt is not used.
p. 332
Specifying valid If the operation of the 16-bit timer/event counter 0n is enabled after reset and
edge after reset while the TI00n or TI01n pin is at high level and when the rising edge or both the
edges are specified as the valid edge of the TI00n or TI01n pin, then the high level
of the TI00n or TI01n pin is detected as the rising edge. Note this when the TI00n
or TI01n pin is pulled up. However, the rising edge is not detected when the
operation is once stopped and then enabled again.
Hard
850
Cautions
Soft
16-bit
timer/event
counters
00, 01
Details of
Function
Hard
Soft
(8/28)
Function
p. 332
Sampling clock
for eliminating
noise
The sampling clock for eliminating noise differs depending on whether the valid
edge of TI00n is used as the count clock or capture trigger. In the former case,
the sampling clock is fixed to fPRS. In the latter, the count clock selected by
PRM0n is used for sampling.
When the signal input to the TI00n pin is sampled and the valid level is detected
two times in a row, the valid edge is detected. Therefore, noise having a short
pulse width can be eliminated (see Figure 7-9).
p. 332
TI00n/TI01n
The signal input to the TI00n/TI01n pin is not acknowledged while the timer is
stopped, regardless of the operation mode of the CPU.
p. 332
Reading of
TM0n
TM0n can be read without stopping the actual counter, because the count values
captured to the buffer are fixed when it is read. The buffer, however, may not be
updated when it is read immediately before the counter counts up, because the
buffer is updated at the timing the counter counts up.
p. 333
Soft Classification
Chapter 8
Chapter
(9/28)
Function
Details of Function
8-bit
CR5n: 8-bit timer
timer/event compare register 5n
counters
50, 51
Cautions
Page
In the mode in which clear & start occurs on a match of TM5n and CR5n
(TMC5n6 = 0), do not write other values to CR5n during operation.
p. 336
In PWM mode, make the CR5n rewrite period 3 count clocks of the count
clock (clock selected by TCL5n) or more.
p. 336
TCL50: Timer clock When rewriting TCL50 to other data, stop the timer operation beforehand.
selection register 50 Be sure to clear bits 3 to 7 to 0.
p. 338
TCL51: Timer clock When rewriting TCL51 to other data, stop the timer operation beforehand.
selection register 51 Be sure to clear bits 3 to 7 to 0.
p. 339
TMC5n: 8-bit timer The settings of LVS5n and LVR5n are valid in other than PWM mode.
mode control
Perform <1> to <4> below in the following order, not at the same time.
register 5n (TMC5n) <1> Set TMC5n1, TMC5n6:
Operation mode setting
<2> Set TOE5n to enable output:
Timer output enable
<3> Set LVS5n, LVR5n (see Caution 1): Timer F/F setting
<4> Set TCE5n
Interval timer
p. 338
p. 339
p. 341
p. 341
p. 341
p. 341
p. 343
p. 346
PWM output
p. 347
In PWM mode, make the CR5n rewrite period 3 count clocks of the count
clock (clock selected by TCL5n) or more.
Soft
Chapter 9
When reading from CR5n between <1> and <2> in Figure 8-15, the value read p. 350
differs from the actual value (read value: M, actual value of CR5n: N).
Timer start error
An error of up to one clock may occur in the time required for a match signal to p. 351
be generated after timer start. This is because 8-bit timer counters 50 and 51
(TM50, TM51) are started asynchronously to the count clock.
Reading of TM5n
p. 351
TM5n can be read without stopping the actual counter, because the count
values captured to the buffer are fixed when it is read. The buffer, however,
may not be updated when it is read immediately before the counter counts up,
because the buffer is updated at the timing the counter counts up.
8-bit timers CMP0n: 8-bit timer CMP0n cannot be rewritten during timer count operation. CMP0n can be
H0, H1
H comparer register refreshed (the same value is written) during timer count operation.
0n (CMP0n)
p. 355
CMP1n: 8-bit timer In the PWM output mode and carrier generator mode, be sure to set CMP1n
H compare register when starting the timer count operation (TMHEn = 1) after the timer count
1n (CMP1n)
operation was stopped (TMHEn = 0) (be sure to set again even if setting the
same value to CMP1n).
p. 355
TMHMD0: 8-bit
timer H mode
register 0
p. 358
TMHMD1: 8-bit
timer H mode
register 1
In the PWM output mode, be sure to set the 8-bit timer H compare register 10 p. 358
(CMP10) when starting the timer count operation (TMHE0 = 1) after the timer
count operation was stopped (TMHE0 = 0) (be sure to set again even if setting
the same value to CMP10).
The actual TOH0/P15 pin output is determined depending on PM15 and P15,
besides TOH0 output.
p. 358
p. 360
In the PWM output mode and carrier generator mode, be sure to set the 8-bit p. 360
timer H compare register 11 (CMP11) when starting the timer count operation
(TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be
sure to set again even if setting the same value to CMP11).
851
Classification
Soft
Details of
Function
Cautions
Page
8-bit
TMHMD1: 8-bit When the carrier generator mode is used, set so that the count clock frequency of
p. 360
timers H0, timer H mode
TMH1 becomes more than 6 times the count clock frequency of TM51.
H1
register 1
The actual TOH1/INTP5/P16 pin output is determined depending on PM16 and P16, p. 360
besides TOH1 output.
TMCYC1: 8-bit
timer H carrier
register 1
Do not rewrite RMC1 when TMHE = 1. However, TMCYC1 can be refreshed (the
same value is written).
p. 360
PWM output
The set value of the CMP1n register can be changed while the timer counter is
operating. However, this takes a duration of three operating clocks (signal selected
by the CKSn2 to CKSn0 bits of the TMHMDn register) from when the value of the
CMP1n register is changed until the value is transferred to the register.
p. 366
Soft
Hard
Chapter 9
Chapter
(10/28)
Function
Be sure to set the CMP1n register when starting the timer count operation (TMHEn = p. 366
1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again
even if setting the same value to the CMP1n register).
Make sure that the CMP1n register setting value (M) and CMP0n register setting
value (N) are within the following range.
00H CMP1n (M) < CMP0n (N) FFH
Carrier
Do not rewrite the NRZB1 bit again until at least the second clock after it has been
generator (8-bit rewritten, or else the transfer from the NRZB1 bit to the NRZ1 bit is not guaranteed.
timer H1 only) When the 8-bit timer/event counter 51 is used in the carrier generator mode, an
interrupt is generated at the timing of <1>. When the 8-bit timer/event counter 51 is
used in a mode other than the carrier generator mode, the timing of the interrupt
generation differs.
p. 366
p. 372
p. 372
Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = p. 374
1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again
even if setting the same value to the CMP11 register).
Set so that the count clock frequency of TMH1 becomes more than 6 times the count p. 374
clock frequency of TM51.
Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH.
p. 374
p. 374
The set value of the CMP11 register can be changed while the timer counter is
operating. However, it takes the duration of three operating clocks (signal selected
by the CKS12 to CKS10 bits of the TMHMD1 register) since the value of the CMP11
register has been changed until the value is transferred to the register.
Soft
Hard
Soft
Chapter 11
Chapter 10
Be sure to set the RMC1 bit before the count operation is started.
Watch
timer
WTM: Watch
Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to
timer operation WTM7) of WTM) during watch timer operation.
mode register
Interrupt
request
p. 374
p. 381
When operation of the watch timer and 5-bit counter is enabled by the watch timer
p. 383
mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1),
the interval until the first interrupt request signal (INTWT) is generated after the
register is set does not exactly match the specification made with bits 2 and 3
(WTM2, WTM3) of WTM. Subsequently, however, the INTWT signal is generated at
the specified intervals.
Watchdog WDTE:
If a value other than ACH is written to WDTE, an internal reset signal is generated. If p. 386
timer
Watchdog timer the source clock to the watchdog timer is stopped, however, an internal reset signal
enable register is generated when the source clock to the watchdog timer resumes operation.
Operation
control
p. 386
The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)).
p. 386
The first writing to WDTE after a reset release clears the watchdog timer, if it is made p. 387
before the overflow time regardless of the timing of the writing, and the watchdog
timer starts counting again.
If the watchdog timer is cleared by writing ACH to WDTE, the actual overflow time p. 387
may be different from the overflow time set by the option byte by up to 2/fRL seconds.
852
Soft Classification
Chapter 11
Chapter
(11/28)
Function
Watchdog
timer
Details of
Function
Operation
control
Cautions
The watchdog timer can be cleared immediately before the count value
overflows (FFFFH).
Page
p. 387
p. 388
The operation of the watchdog timer in the HALT and STOP modes differs as
follows depending on the set value of bit 0 (LSROSC) of the option byte (see
Table on p. 388).
If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP
mode is released. At this time, the counter is not cleared to 0 but starts
counting from the value at which it was stopped.
If oscillation of the internal low-speed oscillator is stopped by setting LSRSTOP
(bit 1 of the internal oscillation mode register (RCM) = 1) when LSROSC = 0,
the watchdog timer stops operating. At this time, the counter is not cleared to 0.
Setting overflow
time of
watchdog timer,
Setting window
open period of
watchdog time
Chapter 12
Soft
Chapter 13
Soft
Setting window
open period of
watchdog timer
pp. 388,
The watchdog timer continues its operation during self-programming and
389
EEPROM emulation of the flash memory. During processing, the interrupt
acknowledge time is delayed. Set the overflow time and window size taking this
delay into consideration.
Setting WINDOW1 = WINDOW0 = 0 is prohibited when using the watchdog
timer at 1.8 V VDD < 2.7 V.
p. 389
The first writing to WDTE after a reset release clears the watchdog timer, if it is
made before the overflow time regardless of the timing of the writing, and the
watchdog timer starts counting again.
p. 389
Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0).
pp. 393,
395
Set BCS1 and BCS0 when the buzzer output operation is stopped (BZOE = 0).
p. 395
When data is read from ADCR and ADCRH, a wait cycle is generated. Do not
p. 399
read data from ADCR and ADCRH when the peripheral hardware clock (fPRS) is
stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT.
ADM: A/D
A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and
converter mode LV0 to values other than the identical data.
register
If data is written to ADM, a wait cycle is generated. Do not write data to ADM
when the peripheral hardware clock (fPRS) is stopped. For details, see
CHAPTER 34 CAUTIONS FOR WAIT.
A/D conversion
timer selection
ADCR: 10-bit
A/D conversion
register
pp. 388,
389
p. 401
p. 401
p. 402
The above conversion time does not include clock frequency errors. Select
conversion time, taking clock frequency errors into consideration.
p. 402
p. 402
p. 403
When writing to the A/D converter mode register (ADM), analog input channel
specification register (ADS), and A/D port configuration register (ADPC), the
contents of ADCR may become undefined. Read the conversion result
following conversion completion before writing to ADM, ADS, and ADPC. Using
timing other than the above may cause an incorrect conversion result to be
read.
If data is read from ADCR, a wait cycle is generated. Do not read data from
ADCR when the peripheral hardware clock (fPRS) is stopped. For details, see
CHAPTER 34 CAUTIONS FOR WAIT.
p. 403
853
Soft Classification
Chapter 13
Chapter
(12/28)
Function
A/D
converter
Details of
Function
ADCRH: 8-bit
A/D conversion
register
ADS: Analog
input channel
specification
register
Cautions
Page
p. 404
When writing to the A/D converter mode register (ADM), analog input channel
specification register (ADS), and A/D port configuration register (ADPC), the
contents of ADCRH may become undefined. Read the conversion result following
conversion completion before writing to ADM, ADS, and ADPC. Using timing
other than the above may cause an incorrect conversion result to be read.
If data is read from ADCRH, a wait cycle is generated. Do not read data from
ADCRH when the peripheral hardware clock (fPRS) is stopped. For details, see
CHAPTER 34 CAUTIONS FOR WAIT.
p. 404
p. 405
If data is written to ADS, a wait cycle is generated. Do not write data to ADS when p. 405
the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 34
CAUTIONS FOR WAIT.
ADS: Analog
input channel
specification
register,
ADPC: A/D port
configuration
register (ADPC)
Set a channel to be used for A/D conversion in the input mode by using port mode pp. 405,
register 2 (PM2).
406
If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC
when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER
34 CAUTIONS FOR WAIT.
p. 406
Port mode
register 2 (PM2)
For the 38-pin products of 78K0/KC2, be sure to set bits 6 and 7 of PM2 to 1,
and bits 6 and 7 of P2 to 0.
p. 407
p. 408
p. 412
p. 412
<1> can be omitted. However, ignore data of the first conversion after <5> in this p. 412
case.
The period from <6> to <9> differs from the conversion time set using bits 5 to 1
(FR2 to FR0, LV1, LV0) of ADM. The period from <8> to <9> is the conversion
time set using FR2 to FR0, LV1, and LV0.
p. 412
854
Hard
Input range of
ANI0 to ANI7
Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AVREF
or higher and AVSS or lower (even in the range of absolute maximum ratings) is
input to an analog input channel, the converted value of that channel becomes
undefined. In addition, the converted values of the other channels may also be
affected.
p. 415
Soft
Operating current The A/D converter stops operating in the STOP mode. At this time, the operating p. 415
in STOP mode
current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D
converter mode register (ADM) to 0. To restart from the standby status, clear bit 0
(ADIF) of interrupt request flag register 1L (IF1L) to 0 and start operation.
Conflicting
operations
If conflict occurs between A/D conversion result register (ADCR, ADCRH) write
and ADCR or ADCRH read by instruction upon the end of conversion, ADCR or
ADCRH read has priority. After the read operation, the new conversion result is
written to ADCR or ADCRH.
p. 415
If conflict occurs between ADCR or ADCRH write and A/D converter mode
register (ADM) write, analog input channel specification register (ADS), or A/D
port configuration register (ADPC) write upon the end of conversion, ADM, ADS,
or ADPC write has priority. ADCR or ADCRH write is not performed, nor is the
conversion end interrupt signal (INTAD) generated.
p. 415
Hard Classification
Details of
Function
Cautions
Page
p. 415
A/D
Noise
To maintain the 10-bit resolution, attention must be paid to noise input to the
converter countermeasures AVREF pin and pins ANI0 to ANI7.
Connect a capacitor with a low equivalent resistance and a good frequency
response to the power supply.
The higher the output impedance of the analog input source, the greater the
influence. To reduce the noise, connecting external C as shown in Figure 1320 is recommended.
Do not switch these pins with other pins during conversion.
The accuracy is improved if the HALT mode is set immediately after the start of
conversion.
ANI0/P20 to
ANI7/P27
The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to
P27).
When A/D conversion is performed with any of ANI0 to ANI7 selected, do not
access P20 to P27 while conversion is in progress; otherwise the conversion
resolution may be degraded. It is recommended to select pins used as P20 to
P27 starting with the ANI0/P20 that is the furthest from AVREF.
p. 416
If a digital pulse is applied to the pins adjacent to the pins currently used for A/D p. 416
conversion, the expected value of the A/D conversion may not be obtained due to
coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin
undergoing A/D conversion.
p. 416
Input impedance This A/D converter charges a sampling capacitor for sampling during sampling
of ANI0 to ANI7 time.
pins
Therefore, only a leakage current flows when sampling is not in progress, and a
current that charges the capacitor flows during sampling. Consequently, the input
impedance fluctuates depending on whether sampling is in progress, and on the
other states.
To make sure that sampling is effective, however, it is recommended to keep the
output impedance of the analog input source to within 10 k, and to connect a
capacitor of about 100 pF to the ANI0 to ANI7 pins (see Figure 13-20).
AVREF pin input
impedance
Soft
Chapter 13
Chapter
(13/28)
Function
A series resistor string of several tens of k is connected between the AVREF and p. 416
AVSS pins.
Therefore, if the output impedance of the reference voltage source is high, this will
result in a series connection to the series resistor string between the AVREF and
AVSS pins, resulting in a large reference voltage error.
Interrupt request The interrupt request flag (ADIF) is not cleared even if the analog input channel
p. 417
flag (ADIF)
specification register (ADS) is changed. Therefore, if an analog input pin is
changed during A/D conversion, the A/D conversion result and ADIF for the prechange analog input may be set just before the ADS rewrite. Caution is therefore
required since, at this time, when ADIF is read immediately after the ADS rewrite,
ADIF is set despite the fact A/D conversion for the post-change analog input has
not ended. When A/D conversion is stopped and then resumed, clear ADIF
before the A/D conversion operation is resumed.
Conversion
results just after
A/D conversion
start
The first A/D conversion value immediately after A/D conversion starts may not
p. 417
fall within the rating range if the ADCS bit is set to 1 within 1 s after the ADCE bit
was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures
such as polling the A/D conversion end interrupt request (INTAD) and removing
the first conversion result.
A/D conversion
result register
(ADCR, ADCRH)
read operation
When a write operation is performed to the A/D converter mode register (ADM),
analog input channel specification register (ADS), and A/D port configuration
register (ADPC), the contents of ADCR and ADCRH may become undefined.
Read the conversion result following conversion completion before writing to
ADM, ADS, and ADPC. Using a timing other than the above may cause an
incorrect conversion result to be read.
p. 417
855
Chapter
Chapter 14
Soft Classification
(14/28)
Function
Serial
interface
UART0
Details of
Function
UART mode
Cautions
If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode),
normal operation continues. If clock supply to serial interface UART0 is stopped
(e.g., in the STOP mode), each register stops operating, and holds the value
immediately before clock supply was stopped. The TXD0 pin also holds the value
immediately before clock supply was stopped and outputs it. However, the
operation is not guaranteed after clock supply is resumed. Therefore, reset the
circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0.
Page
p. 419
Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to p. 419
start communication.
p. 419
TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To
enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks
of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set
within two clocks of base clock, the transmission circuit or reception circuit may not
be initialized.
Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1.
pp. 419,
422
TXS0: Transmit Do not write the next transmit data to TXS0 before the transmission completion
shift register 0
interrupt signal (INTST0) is generated.
p. 422
ASIM0:
Asynchronous
serial interface
operation mode
register 0
To start the transmission, set POWER0 to 1 and then set TXE0 to 1. To stop the
transmission, clear TXE0 to 0, and then clear POWER0 to 0.
p. 424
To start the reception, set POWER0 to 1 and then set RXE0 to 1. To stop the
reception, clear RXE0 to 0, and then clear POWER0 to 0.
p. 424
Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0
pin. If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input,
reception is started.
p. 424
p. 424
TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To
enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks
of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set
within two clocks of base clock, the transmission circuit or reception circuit may not
be initialized.
Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1.
p. 424
Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits. p. 424
Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always
performed with number of stop bits = 1, and therefore, is not affected by the set
value of the SL0 bit.
ASIS0:
Asynchronous
serial interface
reception error
status register 0
p. 424
p. 424
The operation of the PE0 bit differs depending on the set values of the PS01 and
PS00 bits of asynchronous serial interface operation mode register 0 (ASIM0)
p. 425
Only the first bit of the receive data is checked as the stop bit, regardless of the
number of stop bits.
p. 425
If an overrun error occurs, the next receive data is not written to receive buffer
register 0 (RXB0) but discarded.
p. 425
If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0 p. 425
when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER
34 CAUTIONS FOR WAIT.
Hard
BRGC0: Baud
Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when
rate generator
rewriting the MDL04 to MDL00 bits.
control register 0 Make sure that bit 7 (POWER0) of the ASIM0 register = 0 when rewriting the
TPS01 and TPS00 bits.
856
The baud rate value is the output clock of the 5-bit counter divided by 2.
p. 427
p. 427
p. 427
Chapter
Chapter 14
Soft Classification
(15/28)
Function
Serial
interface
UART0
Details of
Function
Cautions
Page
POWER0,
TXE0, RXE0:
Bits 7, 6, 5 of
ASIM0
Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation stop
mode.
To start the communication, set POWER0 to 1, and then set TXE0 or RXE0 to 1.
p. 428
UART mode
Take relationship with the other party of communication when setting the port
mode register and port register.
p. 429
UART
transmission
After transmit data is written to TXS0, do not write the next transmit data before the p. 432
transmission completion interrupt signal (INTST0) is generated.
UART reception If a reception error occurs, read asynchronous serial interface reception error
status register 0 (ASIS0) and then read receive buffer register 0 (RXB0) to clear
the error flag.
Otherwise, an overrun error will occur when the next data is received, and the
reception error status will persist.
Error of baud
rate
p. 433
Reception is always performed with the number of stop bits = 1. The second
stop bit is ignored.
p. 433
Keep the baud rate error during transmission to within the permissible error range
at the reception destination.
p. 436
Make sure that the baud rate error during reception satisfies the range shown in (4) p. 436
Permissible baud rate range during reception.
Soft
Chapter 15
Permissible
Make sure that the baud rate error during reception is within the permissible error
baud rate range range, by using the calculation expression shown below.
during reception
Serial
interface
UART6
UART mode
p. 438
The TXD6 output inversion function inverts only the transmission side and not the p. 440
reception side. To use this function, the reception side must be ready for reception
of inverted data.
If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode),
normal operation continues. If clock supply to serial interface UART6 is stopped
(e.g., in the STOP mode), each register stops operating, and holds the value
immediately before clock supply was stopped. The TXD6 pin also holds the value
immediately before clock supply was stopped and outputs it. However, the
operation is not guaranteed after clock supply is resumed. Therefore, reset the
circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0.
p. 440
Set POWER6 = 1 and then set TXE6 = 1 (transmission) or RXE6 = 1 (reception) to p. 440
start communication.
p. 440
TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6. To
enable transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks
of the base clock after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is
set within two clocks of the base clock, the transmission circuit or reception circuit
may not be initialized.
Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1.
p. 440
p. 440
If data is continuously transmitted, the communication timing from the stop bit to
the next start bit is extended two operating clocks of the macro. However, this
does not affect the result of communication because the reception side initializes
the timing when it has detected a start bit. Do not use the continuous transmission
function if the interface is used in LIN communication operation.
TXB6: Transmit Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface
buffer register 6 transmission status register 6 (ASIF6) is 1.
p. 446
Do not refresh (write the same value to) TXB6 by software during a communication p. 446
operation (when bits 7 and 6 (POWER6, TXE6) of asynchronous serial interface
operation mode register 6 (ASIM6) are 1 or when bits 7 and 5 (POWER6, RXE6)
of ASIM6 are 1).
Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1.
p. 446
857
Soft Classification
Chapter 15
Chapter
(16/28)
Function
Serial
interface
UART6
Details of
Function
ASIM6:
Asynchronous
serial interface
operation mode
register 6
Cautions
To start the transmission, set POWER6 to 1 and then set TXE6 to 1. To stop the
transmission, clear TXE6 to 0, and then clear POWER6 to 0.
p. 448
To start the reception, set POWER6 to 1 and then set RXE6 to 1. To stop the
reception, clear RXE6 to 0, and then clear POWER6 to 0.
p. 448
Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RXD6
p. 448
pin. If POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception
is started.
TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6. To
enable transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks
of the base clock after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is
set within two clocks of the base clock, the transmission circuit or reception circuit
may not be initialized.
ASIS6:
Asynchronous
serial interface
reception error
status register 6
Page
p. 448
Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1.
p. 448
Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.
p. 448
Fix the PS61 and PS60 bits to 0 when used in LIN communication operation.
p. 448
Clear TXE6 to 0 before rewriting the SL6 bit. Reception is always performed with
the number of stop bits = 1, and therefore, is not affected by the set value of the
SL6 bit.
p. 448
p. 448
The operation of the PE6 bit differs depending on the set values of the PS61 and
PS60 bits of asynchronous serial interface operation mode register 6 (ASIM6).
p. 449
For the stop bit of the receive data, only the first bit is checked regardless of the
number of stop bits.
p. 449
If an overrun error occurs, the next receive data is not written to receive buffer
register 6 (RXB6) but discarded.
p. 449
Soft Hard
If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6 p. 449
when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER 34
CAUTIONS FOR WAIT.
ASIF6:
Asynchronous
serial interface
transmission
status register 6
p. 450
To transmit data continuously, write the first transmit data (first byte) to the TXB6
register. Be sure to check that the TXBF6 flag is 0. If so, write the next transmit
data (second byte) to the TXB6 register. If data is written to the TXB6 register while
the TXBF6 flag is 1, the transmit data cannot be guaranteed.
CKSR6: Clock
selection
register 6
p. 451
BRGC6: Baud
Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when
rate generator
rewriting the MDL67 to MDL60 bits.
control register 6 The baud rate is the output clock of the 8-bit counter divided by 2.
p. 452
ASICL6:
Asynchronous
serial interface
control register 6
p. 452
p. 453
ASICL6 can be refreshed (the same value is written) by software during a
communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits
7 and 5 (POWER6, RXE6) of ASIM6 = 1). However, do not set both SBRT6 and
SBTT6 to 1 by a refresh operation during SBF reception (SBRT6 = 1) or SBF
transmission (until INTST6 occurs since SBTT6 has been set (1)), because it may
re-trigger SBF reception or SBF transmission.
In the case of an SBF reception error, the mode returns to the SBF reception mode. p. 454
The status of the SBRF6 flag is held (1).
Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of
ASIM6 = 1. After setting the SBRT6 bit to 1, do not clear it to 0 before SBF
reception is completed (before an interrupt request signal is generated).
858
p. 454
Chapter
Chapter 15
Soft Classification
(17/28)
Function
Details of Function
Serial
ASICL6:
interface Asynchronous serial
UART6 interface control
register 6
Cautions
Page
The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to p. 454
0 after SBF reception has been correctly completed.
Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6
p. 454
(TXE6) of ASIM6 = 1. After setting the SBTT6 bit to 1, do not clear it to 0 before
SBF transmission is completed (before an interrupt request signal is generated).
The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to p. 454
0 at the end of SBF transmission
Do not set the SBRT6 bit to 1 during reception, and do not set the SBTT6 bit to p. 454
1 during transmission.
Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0. p. 454
POWER6, TXE6,
RXE6: Bits 7, 6, 5 of
ASIM6
Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to stop the operation.
To start the communication, set POWER6 to 1, and then set TXE6 or RXE6 to
1.
p. 456
UART mode
Take relationship with the other party of communication when setting the port
mode register and port register.
p. 457
Fix the PS61 and PS60 bits to 0 when the device is used in LIN communication p. 460
operation.
Continuous
transmission
p. 462
The TXBF6 and TXSF6 flags of the ASIF6 register change from 10 to 11,
and to 01 during continuous transmission. To check the status, therefore, do
not use a combination of the TXBF6 and TXSF6 flags for judgment. Read only
the TXBF6 flag when executing continuous transmission.
When the device is use in LIN communication operation, the continuous
transmission function cannot be used. Make sure that asynchronous serial
interface transmission status register 6 (ASIF6) is 00H before writing transmit
data to transmit buffer register 6 (TXB6).
p. 462
p. 462
To transmit data continuously, write the first transmit data (first byte) to the
TXB6 register. Be sure to check that the TXBF6 flag is 0. If so, write the next
transmit data (second byte) to the TXB6 register. If data is written to the TXB6
register while the TXBF6 flag is 1, the transmit data cannot be guaranteed.
Normal reception
p. 462
p. 462
If a reception error occurs, read ASIS6 and then RXB6 to clear the error flag.
Otherwise, an overrun error will occur when the next data is received, and the
reception error status will persist.
p. 466
Reception is always performed with the number of stop bits = 1. The second
stop bit is ignored.
p. 466
p. 466
Keep the baud rate error during transmission to within the permissible error
range at the reception destination.
p. 473
Make sure that the baud rate error during reception satisfies the range shown in p. 473
(4) Permissible baud rate range during reception.
Soft
Chapter 16
Permissible baud rate Make sure that the baud rate error during reception is within the permissible
range during reception error range, by using the calculation expression shown below.
SOTB1n: Transmit
Serial
interface buffer register 1n
CSI10,
CSI11
p. 474
p. 479
p. 479
859
Soft
Chapter
Chapter 16
Classification
(18/28)
Function
Details of Function
Serial
SIO1n: Serial I/O shift
interface register 1n
CSI10,
CSI11
p. 480
p. 483
p. 483
p. 485
To use P02/SO11 and P04/SCK11 as general-purpose ports, set CSIC11 in the p. 485
default status (00H).
The phase type of the data clock is type 1 after reset.
p. 485
3-wire serial I/O mode Take relationship with the other party of communication when setting the port
mode register and port register.
p. 487
Communication
operation
Do not access the control register and data register when CSOT1n = 1 (during
serial communication).
p. 490
When using serial interface CSI11, wait for the duration of at least one clock
before the clock operation is started to change the level of the SSI11 pin in the
slave mode; otherwise, malfunctioning may occur.
p. 490
If a value is written to TRMD1n, DAP1n, and DIR1n, the output value of SO1n
changes.
p. 498
Serial
SIOA0: Serial I/O shift A communication operation is started by writing to SIOA0. Consequently, when p. 502
interface register 0
transmission is disabled (bit 3 (TXEA0) of CSIMA0 = 0), write dummy data to
CSIA0
the SIOA0 register to start the communication operation, and then perform a
receive operation.
Do not write data to SIOA0 while the automatic transmit/receive function is
operating.
CSIMA0:
When CSIAE0 = 0, the buffer RAM cannot be accessed.
Serial operation mode When CSIAE0 is changed from 1 to 0, the registers and bits mentioned in Note
specification register 0 above are asynchronously initialized. To set CSIAE0 = 1 again, be sure to reset the initialized registers.
860
p. 479
In the slave mode, reception is started when data is read from SIO11 with a low p. 479
level input to the SSI11 pin. For details on the reception operation, see 16.4.2
(2) Communication operation.
Be sure to clear bit 5 to 0.
SO1n output
Soft
Page
CSIM10: Serial
operation mode
register 10
Chapter 17
Cautions
p. 502
p. 503
p. 503
p. 503
p. 504
p. 506
p. 506
After automatic data transfer is stopped, the data address when the transfer
stopped is stored in automatic data transfer address count register 0 (ADTC0).
However, since no function to restart automatic data transfer is incorporated,
when transfer is stopped by setting ATSTP0 = 1, start automatic data transfer
by setting ATSTA0 to 1 after re-setting the registers.
p. 506
During transfer (TSF0 = 1), rewriting serial operation mode specification register p. 505
0 (CSIMA0), serial status register 0 (CSIS0), divisor selection register 0
(BRGCA0), automatic data transfer address point specification register 0
(ADTP0), automatic data transfer interval specification register 0 (ADTI0), and
serial I/O shift register 0 (SIOA0) are prohibited. However, these registers can
be read and re-written to the same value. In addition, the buffer RAM can be
rewritten during transfer.
Chapter
Chapter 17
Soft Classification
(19/28)
Function
Serial
interface
CSIA0
Details of Function
Cautions
Page
p. 508
Because the setting of bit 5 (STBE0) and bit 4 (BUSYE0) of serial status register p. 509
ADTI0: Automatic
data transfer interval 0 (CSIS0) takes priority over the ADTI0 setting, the interval time based on the
specification register setting of STBE0 and BUSYE0 is generated even when ADTI0 is cleared to 00H.
0
3-wire serial I/O
mode
Take relationship with the other party of communication when setting the port
mode register and port register.
1-byte transmission/ The SOA0 pin becomes low level by an SIOA0 write.
reception
p. 512
p. 514
Communication start If CSIAE0 is set to 1 after data is written to SIOA0, communication does not start. p. 516
3-wire serial I/O
mode with automatic
transmit/receive
function
Automatic
transmission/
reception mode
A wait state may be generated when data is written to the buffer RAM. For
details, see CHAPTER 34 CAUTIONS FOR WAIT.
p. 517
Take the relationship with the other communicating party into consideration when p. 519
setting the port mode register and port register.
Because, in the automatic transmission/reception mode, the automatic
transmit/receive function writes/reads data to/from the internal buffer RAM after
1-byte transmission/reception, an interval is inserted until the next
transmission/reception. As the buffer RAM write/read is performed at the same
time as CPU processing, the interval is dependent upon the value of automatic
data transfer interval specification register 0 (ADTI0) and the set values of bits 5
and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic
transmit/receive interval time).
p. 521
If an access to the buffer RAM by the CPU conflicts with an access to the buffer p. 521
RAM by serial interface CSIA0 during the interval period, the interval time
specified by automatic data transfer interval specification register 0 (ADTI0) may
be extended.
Automatic
transmission
p. 526
If an access to the buffer RAM by the CPU conflicts with an access to the buffer p. 526
RAM by serial interface CSIA0 during the interval period, the interval time
specified by automatic data transfer interval specification register 0 (ADTI0) may
be extended.
p. 528
Repeat transmission Because, in the repeat transmission mode, a read is performed on the buffer
RAM after the transmission of one byte, the interval is included in the period up
mode
to the next transmission. As the buffer RAM read is performed at the same time
as CPU processing, the interval is dependent upon automatic data transfer
interval specification register 0 (ADTI0) and the set values of bits 5 and 4
(STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic
transmit/receive interval time).
If an access to the buffer RAM by the CPU conflicts with an access to the buffer p. 528
RAM by serial interface CSIA0 during the interval period, the interval time
specified by automatic data transfer interval specification register 0 (ADTI0) may
be extended.
861
Chapter
Chapter 17
Soft Classification
(20/28)
Function
Serial
interface
CSIA0
Details of Function
Automatic
transmission/
reception suspension
and restart
Cautions
Page
p. 531
Busy control cannot be used simultaneously with the interval time control
function of automatic data transfer interval specification register 0 (ADTI0).
Soft
Chapter 18
Busy & strobe control When TSF0 is cleared, the SOA0 pin goes low.
option
Serial
interface
IIC0
p. 534
IIC0: IIC shift register Do not write data to IIC0 during data transfer.
0
Write or read IIC0 only during the wait period. Accessing IIC0 in a
communication state other than during the wait period is prohibited. When the
device serves as the master, however, IIC0 can be written only once after the
communication trigger bit (STT0) is set to 1.
IICC0: IIC control
register 0
p. 537
p. 540
p. 540
The start condition is detected immediately after I C is enabled to operate (IICE0 p. 544
= 1) while the SCL0 line is at high level and the SDA0 line is at low level.
2
Immediately after enabling I C to operate (IICE0 = 1), set LREL0 (1) by using a 1bit memory manipulation instruction.
When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set to 1
during the ninth clock and wait is canceled, after which TRC0 is cleared and the
SDA0 line is set to high impedance.
p. 547
If data is read from IICS0, a wait cycle is generated. Do not read data from IICS0 p. 548
when the peripheral hardware clock (fPRS) is stopped. For details, see CHAPTER
34 CAUTIONS FOR WAIT.
p. 551
As the bus release status (IICBSY = 0) is recognized regardless of the actual bus p. 551
status when STCEN = 1, when generating the first start condition (STT0 = 1), it is
necessary to verify that no third party communications are in progress in order to
prevent such communications from being destroyed.
Write to IICRSV only when the operation is stopped (IICE0 = 0).
862
p. 532
p. 551
Selection clock
setting
Determine the transfer clock frequency of I C by using CLX0, SMC0, CL01, and p. 554
CL00 before enabling the operation (by setting bit 7 (IICE0) of IIC control register
0 (IICC0) to 1). To change the transfer clock frequency, clear IICE0 once to 0.
When
STCEN = 0
p. 571
Immediately after I C operation is enabled (IICE0 = 1), the bus communication
status (IICBSY (bit 6 of IICF0) = 1) is recognized regardless of the actual bus
status. When changing from a mode in which no stop condition has been
detected to a master device communication mode, first generate a stop condition
to release the bus, then perform master device communication.
When using multiple masters, it is not possible to perform master device
communication when the bus has not been released (when a stop condition has
not been detected).
Use the following sequence for generating a stop condition.
Set IIC clock selection register 0 (IICCL0).
Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1.
Set bit 0 (SPT0) of IICC0 to 1.
When
STCEN = 1
Immediately after I C operation is enabled (IICE0 = 1), the bus released status
(IICBSY = 0) is recognized regardless of the actual bus status. To generate the
first start condition (STT0 (bit 1 of IIC control register 0 (IICC0)) = 1), it is
necessary to confirm that the bus has been released, so as to not disturb other
communications.
p. 571
Chapter
Chapter 18
Soft Classification
(21/28)
Function
Serial
interface
IIC0
Details of Function
Cautions
Page
If other I C
If I C operation is enabled and the device participates in communication already p. 571
2
communications are in progress when the SDA0 pin is low and the SCL0 pin is high, the macro of I C
already in progress recognizes that the SDA0 pin has gone low (detects a start condition). If the
value on the bus at this time can be recognized as an extension code, ACK is
2
returned, but this interferes with other I C communications. To avoid this, start
2
I C in the following sequence.
Clear bit 4 (SPIE0) of IICC0 to 0 to disable generation of an interrupt request
signal (INTIIC0) when the stop condition is detected.
2
Set bit 7 (IICE0) of IICC0 to 1 to enable the operation of I C.
Wait for detection of the start condition.
Set bit 6 (LREL0) of IICC0 to 1 before ACK is returned (4 to 80 clocks after
setting IICE0 to 1), to forcibly disable detection.
Transfer clock
frequency setting
Determine the transfer clock frequency by using SMC0, CL01, CL00 (bits 3, 1,
p. 571
and 0 of IICL0), and CLX0 (bit 0 of IICX0) before enabling the operation (IICE0 =
1). To change the transfer clock frequency, clear IICE0 to 0 once.
STT0, SPT0:
Setting STT0 and SPT0 (bits 1 and 0 of IICC0) again after they are set and
Bits 1, 0 of IIC control before they are cleared to 0 is prohibited.
register 0 (IICC0)
p. 572
Soft
Chapter 19
Transmission reserve When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt p. 572
request is generated when the stop condition is detected. Transfer is started
when communication data is written to IIC0 after the interrupt request is
generated. Unless the interrupt is generated when the stop condition is
detected, the device stops in the wait state because the interrupt request is not
generated when communication is started. However, it is not necessary to set
SPIE0 to 1 when MSTS0 (bit 7 of IICS0) is detected by software.
Multiplier/
divider
SDR0: Remainder
data register 0
MDA0H, MDA0L:
Multiplication/
division data register
A0
p. 608
The value read from SDR0 during operation processing (while bit 7 (DMUE) of
multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed.
p. 610
SDR0 is reset when the operation is started (when DMUE is set to 1).
p. 610
p. 610
Do not change the value of MDA0 during operation processing (while bit 7
(DMUE) of multiplier/divider control register 0 (DMUC0) is 1). Even in this case,
the operation is executed, but the result is undefined.
p. 610
The value read from MDA0 during operation processing (while DMUE is 1) is not p. 610
guaranteed.
MDB0: Multiplication/ Do not change the value of MDB0 during operation processing (while bit 7
division data register (DMUE) of multiplier/divider control register 0 (DMUC0) is 1). Even in this case,
B0
the operation is executed, but the result is undefined.
DMUC0:
Multiplier/divider
control register 0
p. 611
Do not clear MDB0 to 0000H in the division mode. If set, undefined operation
results are stored in MDA0 and SDR0.
p. 611
p. 612
Do not change the value of DMUSEL0 during operation processing (while DMUE p. 612
is 1). If it is changed, undefined operation results are stored in
multiplication/division data register A0 (MDA0) and remainder data register 0
(SDR0).
If DMUE is cleared to 0 during operation processing (while DMUE is 1), the
operation processing is stopped. To execute the operation again, set
multiplication/division data register A0 (MDA0), multiplication/division data
register B0 (MDB0), and multiplier/divider control register 0 (DMUC0), and start
the operation (by setting DMUE to 1).
p. 612
863
Chapter
Chapter 20
Soft Classification
(22/28)
Function
Interrupt
function
Details of
Function
1F0L, 1F0L,
1F1L, 1F1H:
Interrupt request
flag registers
MK0L, MK0H,
MK1L, MK1H:
Interrupt mask
flag registers
PR0L, PR0H,
PR1L, PR1H:
Priority
specification flag
registers
864
Cautions
When operating a timer, serial interface, or A/D converter after standby release,
operate it once after clearing the interrupt request flag. An interrupt request flag
may be set by noise.
Page
p. 624
When manipulating a flag of the interrupt request flag register, use a 1-bit memory p. 624
manipulation instruction (CLR1). When describing in C language, use a bit
manipulation instruction such as IF0L.0 = 0; or _asm(clr1 IF0L, 0); because the
compiled assembler must be a 1-bit memory manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation
instruction such as IF0L &= 0xfe; and compiled, it becomes the assembler of three
instructions.
mov a, IF0L
and a, #0FEH
mov IF0L, a
In this case, even if the request flag of another bit of the same interrupt request flag
register (IF0L) is set to 1 at the timing between mov a, IF0L and mov IF0L, a, the
flag is cleared to 0 at mov IF0L, a. Therefore, care must be exercised when using
an 8-bit memory manipulation instruction in C language.
Be sure to clear bits 2, 4 to 7 of IF1L and bits 1 to 7 of IF1H to 0. (78K0/KB2)
p. 625
Be sure to clear bits 6 and 7 of IF1L to 0 in the 38-pin and 44-pin products.
Be sure to clear bit 7 of IF1L to 0 in the 48-pin products.
Be sure to clear bits 1 to 7 of IF1H to 0. (78K0/KC2)
p. 626
p. 627
p. 628
p. 629
p. 630
Be sure to set bits 6 and 7 of MK1L to 1 in the 38-pin and 44-pin products.
Be sure to set bit 7 of MK1L to 1 in the 48-pin products.
Be sure to set bits 1 to 7 of MK1H to 1. (78K0/KC2)
p. 631
p. 632
p. 633
p. 634
p. 635
Be sure to set bits 6 and 7 of PR1L to 1 in the 38-pin and 44-pin products.
Be sure to set bit 7 of PR1L to 1 in the 48-pin products.
Be sure to set bits 1 to 7 of PR1H to 1. (78K0/KC2)
p. 636
p. 637
p. 638
p. 639
Chapter
Chapter 20
Soft Classification
(23/28)
Function
Interrupt
function
Details of
Function
EGP, EGN:
External interrupt
rising edge,
falling edge
enable registers
Cautions
Be sure to clear bits 6 and 7 of EGP and EGN to 0 in the 38-pin and 44-pin products p. 640
of 78K0/KC2 and 78K0/KB2.
Be sure to clear bit 7 of EGP and EGN to 0 in the 48-pin products of 78K0/KC2 and
78K0/KD2.
Select the port mode by clearing EGPn and EGNn to 0 because an edge may be
detected when the external interrupt function is switched to the port function.
Software
Do not use the RETI instruction for restoring from the software interrupt.
interrupt request
Soft
Soft
Chapter 22
Key
interrupt
function
Standby
function
p. 641
p. 645
p. 649
The BRK instruction is not one of the above-listed interrupt request hold
instructions. However, the software interrupt activated by executing the BRK
instruction causes the IE flag to be cleared. Therefore, even if a maskable interrupt
request is generated during execution of the BRK instruction, the interrupt request is
not acknowledged.
KRM: Key return If any of the KRMn bits used is set to 1, set bit n (PU7n) of the corresponding pullmode register
up resistor register 7 (PU7) to 1.
p. 652
If KRM is changed, the interrupt request flag may be set. Therefore, disable
interrupts and then change the KRM register. Clear the interrupt request flag and
enable interrupts.
p. 652
The bits not used in the key interrupt mode can be used as normal ports.
p. 652
For the 38-pin products of 78K0/KC2, be sure to set bits 2 to 7 of KRM to 0. For
the 44-pin and 48-pin products of 78K0/KC2, be sure to set bits 4 to 7 of KRM to
0.
p. 652
Standby function The STOP mode can be used only when the CPU is operating on the main system p. 653
clock. The subsystem clock oscillation cannot be stopped. The HALT mode can be
used when the CPU is operating on either the main system clock or the subsystem
clock.
When shifting to the STOP mode, be sure to stop the peripheral hardware operation p. 653
operating with main system clock before executing STOP instruction.
The following sequence is recommended for operating current reduction of the A/D p. 653
converter when the standby function is used: First clear bit 7 (ADCS) and bit 0
(ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion
operation, and then execute the STOP instruction.
OSTC:
Oscillation
stabilization time
counter status
register
Soft Hard
Chapter 21
BRK instruction
Page
OSTS:
Oscillation
stabilization time
select register
After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
p. 655
p. 655
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (a below).
p. 655
To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
before executing the STOP instruction.
p. 656
Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
p. 656
p. 656
865
Chapter
Chapter 22
Standby
function
Soft
Hard Classification
(24/28)
Function
Details of
Function
Cautions
Page
The X1 clock oscillation stabilization wait time does not include the time until clock p. 656
OSTS:
oscillation starts (a below).
Oscillation
stabilization time
select register
STOP mode
Because the interrupt request signal is used to clear the standby mode, if there is
an interrupt source with the interrupt request flag set and the interrupt mask flag
reset, the standby mode is immediately cleared if set. Thus, the STOP mode is
reset to the HALT mode immediately after execution of the STOP instruction and
the system returns to the operating mode as soon as the wait time set using the
oscillation stabilization time select register (OSTS) has elapsed.
p. 661
To use the peripheral hardware that stops operation in the STOP mode, and the
peripheral hardware for which the clock that stops oscillating in the STOP mode
after the STOP mode is released, restart the peripheral hardware.
p. 663
p. 663
To shorten oscillation stabilization time after the STOP mode is released when the p. 663
CPU operates with the high-speed system clock (X1 oscillation), switch the CPU
clock to the internal highspeed oscillation clock before the execution of the STOP
instruction using the following procedure.
<1> Set RSTOP to 0 (starting oscillation of the internal high-speed oscillator)
<2> Set MCM0 to 0 (switching the CPU from X1 oscillation to internal high-speed
oscillation) <3> Check that MCS is 0 (checking the CPU clock) <4> Check that
RSTS is 1 (checking internal high-speed oscillation operation) <5> Execute the
STOP instruction
Before changing the CPU clock from the internal high-speed oscillation clock to the
high-speed system clock (X1 oscillation) after the STOP mode is released, check
the oscillation stabilization time with the oscillation stabilization time counter status
register (OSTC).
Hard
Reset
function
866
Soft
Chapter 24
Soft
Chapter 23
p. 663
If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is
stopped for 4.06 to 16.12 s after the STOP mode is released when the internal
high-speed oscillation clock is selected as the CPU clock, or for the duration of 160
external clocks when the high-speed system clock (external clock input) is selected
as the CPU clock.
Power-onclear circuit
For an external reset, input a low level for 10 s or more to the RESET pin.
p. 668
During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock,
and internal low-speed oscillation clock stop oscillating. External main system
clock input and external subsystem clock input become invalid.
p. 668
When the STOP mode is released by a reset, the STOP mode contents are held
during reset input. However, the port pins become high-impedance, except for
P130, which is set to low-level output.
p. 668
Block diagram of An LVI circuit internal reset does not reset the LVI circuit.
reset function
p. 669
Watchdog timer A watchdog timer internal reset resets the watchdog timer.
overflow
p. 671
RESF: Reset
control flag
register
p. 678
If an internal reset signal is generated in the POC circuit, the reset control flag
register (RESF) is cleared to 00H.
p. 679
Set the low-voltage detector by software after the reset status is released
(see CHAPTER 25 LOW-VOLTAGE DETECTOR).
pp. 681,
682
Soft Classification
Soft
Poweron-clear
circuit
Lowvoltage
detector
Details of
Function
Cautions
Page
In 2.7 V/1.59 V
POC mode
A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply p. 682
voltage reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7
V (TYP.) within 1.93 ms, the power supply oscillation stabilization time of 0 to 5.39
ms is automatically generated before reset processing.
Cautions for
power-on-clear
circuit
In a system where the supply voltage (VDD) fluctuates for a certain period in the
vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset
and released from the reset status. In this case, the time from release of reset to
the start of the operation of the microcontroller can be arbitrarily set by taking the
following action.
Soft Hard
Chapter 25
Chapter 24
Chapter
(25/28)
Function
p. 683
p. 687
Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
p. 687
When using LVI as an interrupt, if LVION is cleared (0) in a state below the LVI
detection voltage, an INTLVI signal is generated and LVIIF becomes 1.
p. 687
Soft
Chapter 26
Soft
Hard
When used as
reset (When
detecting level of
input voltage
from external
input pin
(EXLVI))
p. 690
If supply voltage (VDD) detection voltage (VLVI) when LVIMD is set to 1, an internal p. 690
reset signal is not generated.
<1> must always be executed. When LVIMK = 0, an interrupt may occur
immediately after the processing in <3>.
p. 693
If input voltage from external input pin (EXLVI) detection voltage (VEXLVI = 1.21 V
(TYP.)) when LVIMD is set to 1, an internal reset signal is not generated.
p. 693
Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
p. 693
Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
When used as
interrupt (When
detecting level of
input voltage
from external
input pin
(EXLVI))
p. 698
p. 700
Cautions for low- In a system where the supply voltage (VDD) fluctuates for a certain period in the
voltage detector vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on
how the low-voltage detector is used.
(1) When used as reset
The system may be repeatedly reset and released from the reset status.
In this case, the time from release of reset to the start of the operation of the
microcontroller can be arbitrarily set by taking action (1) below.
(2) When used as interrupt
Interrupt requests may be frequently generated. Take (b) of action (2) below.
Option
byte
0082H, 0083H/
1082H, 1083H
Be sure to set 00H to 0082H and 0083H (0082H/1082H and 0083H/1083H when
the boot swap function is used).
0080H/1080H
Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H p. 703
are switched during the boot swap operation.
p. 703
867
Chapter
Chapter 26
Soft Classification
(26/28)
Function
Option
byte
Details of
Function
Cautions
Page
0081H/1081H
POCMODE can only be written by using a dedicated flash memory programmer. It p. 703
cannot be set during self-programming or boot swap operation during selfprogramming (at this time, 1.59 V POC mode (default) is set). However, because
the value of 1081H is copied to 0081H during the boot swap operation, it is
recommended to set a value that is the same as that of 0081H to 1081H when the
boot swap function is used.
0084H/1084H
Be sure to set 00H (disabling on-chip debug operation) to 0084H for products not
equipped with the on-chip debug function (PD78F05xxA). Also set 00H to 1084H
because 0084H and 1084H are switched during the boot swap operation.
p. 704
To use the on-chip debug function with a product equipped with the on-chip debug p. 704
function (PD78F05xxDA), set 02H or 03H to 0084H. Set a value that is the same
as that of 0084H to 1084H because 0084H and 1084H are switched during the boot
swap operation.
0080H/1080H
Soft
Chapter 27
0081H/1081H
Flash
IMS: Internal
memory memory size
switching
register,
IXS: internal
expansion RAM
size switching
register
Operation clock
p. 705
p. 706
Be sure to set each product to the values shown in Table 27-1 after a reset release. p. 708
Be sure to set each product to the values shown in Table 27-2 after a reset release. p. 709
The 78K0/KB2 is not provided with IXS register.
p. 709
To set the memory size, set IMS and then IXS. Set the memory size so that the
internal ROM and internal expansion RAM areas do not overlap.
pp. 708,
709
Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used. p. 717
Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when
UART6 is used.
p. 717
Processing of X1, For the product with an on-chip debug function (PD78F05xxDA), connect
p. 717
P31 pins
P31/INTP2/OCD1A and P121/X1/OCD0A as follows when writing the flash memory
with a flash memory programmer.
P31/INTP2/OCD1A: Connect to EVSS via a resistor.
P121/X1/OCD0A: Connect to VSS via a resistor.
Hard
Selecting
communication
mode
When UART6 is selected, the receive clock is calculated based on the reset
command sent from the dedicated flash memory programmer after the FLMD0
pulse has been received.
Security Settings After the security setting for the batch erase is set, erasure cannot be performed for p. 721
the device. In addition, even if a write command is executed, data different from
that which has already been written to the flash memory cannot be written, because
the erase command is disabled.
If a security setting that rewrites boot cluster 0 has been applied, boot cluster 0 of
that device will not be rewritten.
868
p. 719
p. 721
Hard Classification
Flash
memory
Details of
Function
Cautions
Page
E.P.V.
command
usage
When executing boot swapping, do not use the E.P.V. command with the dedicated pp. 723,
flash memory programmer.
724, 732
Flash memory
programming
by selfprogramming
The self-programming function cannot be used when the CPU operates with the
subsystem clock.
p. 725
p. 725
Soft
Chapter 27
Chapter
(27/28)
Function
p. 725
p. 725
Self-programming is also stopped by an interrupt request that is not masked even in p. 725
the DI status. To prevent this, mask the interrupt by using the interrupt mask flag
registers (MK0L, MK0H, MK1L, and MK1H).
Hard
Chapter 28
Allocate the entry program for self-programming in the common area of 0000H to
7FFFH.
p. 734
On-chip PD78F05xxDA The PD78F05xxDA has an on-chip debug function, which is provided for
debug
development and evaluation. Do not use the on-chip debug function in products
function
designated for mass production, because the guaranteed number of rewritable times
(PD78F
of the flash memory may be exceeded when this function is used, and product
reliability therefore cannot be guaranteed. NEC Electronics is not liable for problems
05xxDA
occurring when the on-chip debug function is used.
only)
Hard
When
OCD0A/X1 and
OCD0B/X2 are
used
Chapter 30, 31
p. 725
Input the clock from the OCD0A/X1 pin during on-chip debugging.
p. 734
Control the OCD0A/X1 and OCD0B/X2 pins by externally pulling down the
p. 734
OCD1A/P31 pin or by using an external circuit using the P130 pin (that outputs a low
level when the device is reset).
p. 750
Electrical PD78F05xxDA The PD78F05xxDA has an on-chip debug function, which is provided for
specificat
development and evaluation. Do not use the on-chip debug function in products
ions
designated for mass production, because the guaranteed number of rewritable times
of the flash memory may be exceeded when this function is used, and product
reliability therefore cannot be guaranteed. NEC Electronics is not liable for problems
occurring when the on-chip debug function is used.
pp. 750,
752 to 759,
761 to 775,
777 to 784,
786 to 799
Absolute
maximum
ratings
Product quality may suffer if the absolute maximum rating is exceeded even
momentarily for any parameter. That is, the absolute maximum ratings are rated
values at which the product is on the verge of suffering physical damage, and
therefore the product must be used under conditions that ensure that the absolute
maximum ratings are not exceeded.
Value of the
current
The value of the current that can be run per pin must satisfy the value of the current pp. 753,
per pin and the total value of the currents of all pins.
778
pp. 752,
753, 777,
778
869
Hard Classification
Chapter 30, 31
Chapter
(28/28)
Function
Electrical
specifications
Details of
Function
Cautions
Page
pp. 754,
X1 oscillator
When using the X1 oscillator, wire as follows in the area enclosed by the
779
characteristics broken lines in the above figures to avoid an adverse effect from wiring
capacitance.
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating
current flows.
Always make the ground point of the oscillator capacitor the same potential
as VSS.
Do not ground the capacitor to a ground pattern through which a high current
flows.
Do not fetch signals from the oscillator.
pp. 754,
Since the CPU is started by the internal high-speed oscillation clock after a
779
reset release, check the X1 clock oscillation stabilization time using the
oscillation stabilization time counter status register (OSTC) by the user.
Determine the oscillation stabilization time of the OSTC register and oscillation
stabilization time select register (OSTS) after sufficiently evaluating the
oscillation stabilization time with the resonator to be used.
pp. 755,
XT1 oscillator When using the XT1 oscillator, wire as follows in the area enclosed by the
780
characteristics broken lines in the above figure to avoid an adverse effect from wiring
capacitance
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating
current flows.
Always make the ground point of the oscillator capacitor the same potential
as VSS.
Do not ground the capacitor to a ground pattern through which a high current
flows.
Do not fetch signals from the oscillator.
Hard
Chapter 33
pp. 755,
The XT1 oscillator is designed as a low-amplitude circuit for reducing power
780
consumption, and is more prone to malfunction due to noise than the X1
oscillator. Particular care is therefore required with the wiring method when the
XT1 clock is used.
Recommended
soldering
conditions
Do not use different soldering methods together (except for partial heating).
PD78F05xxDA The PD78F05xxDA has an on-chip debug function, which is provided for
p. 813
p. 813
870
Soft
Chapter 34
When the peripheral hardware clock (fPRS) is stopped, do not access the
registers listed above using an access method in which a wait request is
issued.
p. 815
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