Paper ID: 23

Title: A Single-Channel Voltage-Scalable (0.9V-8GS/s 0.8V-7.3GS/s 0.6V-4.5GS/s) >38.7dB SNDR 8b Time-Domain ADC Featuring Voltage-
Shrink Sampling and Asynchronous Pipelined Successive-Approximation in 28nm CMOS

Abstract: Time-domain ADC is gaining interest for its inherent technology scalability recently. In this work, we present a single-channel voltage-
scalable 8b TDADC in 28nm CMOS, achieving (39.9dB, 41.0dB, 39.5dB) SNDR with Nyquist input at (0.6V, 0.8V, 0.9V) supply and consumes
(20.35mW, 61.43mW, 85.33mW) and 0.011mm2 at (4.5GS/s, 7.3GS/s, 8GS/s), leading to the Walden FoM of (56.2fJ/conv.-step, 91.7fJ/conv.-step,
144.1fJ/conv.-step), demonstrating technology-oriented superiority at high frequency scenes.
Subcommittee First Choice: Data Converters
Subcommittee Second Choice: Undecided

Submission Demographics

This paper is being submitted from University

Are you interested in participating in the Demonstration Session at ISSCC? No

Double-Blind Review Process

1. Have you read the Author Instructions and FAQ which outline the double-blind review submission requirements? Yes
I have read the Author Instructions and FAQ.
2. Is your manuscript fully anonymized to hide author and affiliation identities, including PDF metadata, logos on die photos, logos on
printed circuit board photos, etc.? Yes
my manuscript is fully anonymized to hide author and affiliation identities.
3. Did you cite all relevant prior work (including your own) in the third person? Yes
I have cited all relevant prior work in the third person.
4. Did you upload as Supporting Material any work of yours that is related to this submission and has been sent to another
Conference/Journal, but has not been published yet? Did you cite this work in anonymized format according to the Author Instructions?
Failure to adhere to this process may result in removal from accepted paper list even after acceptance. Yes
any work of ours which is related to this submission and has been sent to another Conference/Journal
but has not been published yet
has been uploaded as Supporting Material and has been cited in anonymized format.
5. Please check the following to show you have read and understood:
I understand that, if accepted, I will need to submit an updated version of my paper with author and affiliation data included and references
unblinded.
I understand that, if accepted, my paper will be edited by a Technical Editor who will ensure that my paper is compliant with the ISSCC editorial
guidelines.

Technology

CMOS

Originality

New design and/or architecture

New design methodology
Fastest published

Design Status

Chip testing complete, measured data supporting submitted paper

Submission Highlights

The proposed time-domain ADC is the first presented 8GS/s single channel 8b ADC with voltage scaling down to 0.6V (4.5GS/s) and a rail-to-rail
full-scale input.

Introduction
1. Have you clearly highlighted what is the novelty in the reported circuit or architecture? Is the target application clearly described? Yes
2. Have you explained how your circuit or architecture advances the state of the art? If your work is part of a large system, have you
explained how your particular design advances the state-of-the-art as part of that system? Yes
3. Have you compared your results against representative examples from the recent literature? Please clarify and explain using a table, if
possible. Yes
4. Have you included performance in the form of recognized standard metrics (such as PVT sensitivity, area, noise, reliability metrics,
etc)? Yes
5. For power consumption and area measurements, have you clearly stated what blocks or functions are included (or omitted) in the
calculations? Yes
6. The ISSCC committee considers the quality of the referenced citations when judging your paper, does your reference list provide
adequate coverage of the related work (prior work by others and your own work) including papers from previous ISSCC where
applicable? Yes
7. Has your text been reviewed for correct use of grammar, punctuation, and spelling? Yes
9. ISSCC reviews circuit performance based on actual measured results (rather than simulation)-- Are the results clearly stated as
measured or simulated? Yes
10. What is the abstraction level of the primary innovation? Transistor/circuit topology level
Other. Please explain
11. Does your innovation cut across different subcommittees? No
Please list all subcommittees in which your innovation cuts across.

Data Converters

1. We ask that you provide the following measured data in the submitted paper (or in the supplemental material). If you chose not to
provide the data below, please explain why they are not appropriate to document your work.

● Nyquist ADC: SNR, SFDR, SNDR vs. Fin and Fclock; nominal (by design) input sampling capacitance (or resistance) driven by external

signal source; input voltage/current range; output spectrum.

● Oversampling ADC: SNR, SFDR, SNDR vs. Fin and Fclock; OSR; nominal (by design) input sampling capacitance (or input resistance)

driven by external signal source; input voltage/current range; output spectrum.

● Nyquist DAC: SNR (NSD preferred), SFDR (IMD preferred) vs. Fin and Fclock; output current/voltage range; output spectrum; load (e.g. off-

chip 50).
● Oversampling DAC: SNR, SFDR, SNDR vs. Fin and Fclock; OSR; output current/voltage range; output spectrum; load (e.g. 10k ||30pF).
N/A.
2. In what process technology was your device fabricated/measured (e.g. 65nm CMOS)?
28nm CMOS
3. What are the supply and reference voltages used in your device? Please list all voltages and the corresponding sub-blocks (e.g.
reference=0.2V/0.8V, analog=1V, digital=1.8V, analog switches=1.8V).
IO(DC) : 2.5V. Switches/analog/digital: from 0.6V to 0.9V.
4. What is the power dissipation breakdown of your device (e.g. total=12mW: references=2mW, analog=5mW, digital=3mW,
calibration=2mW)? Please be clear about on-chip or off-chip voltage references, and provide power in either case.
At 0.6V, total = 20.53mW, VTC = 1.54mW, TDC = 14.7mW, clock = 1.6mW, delay buffers bank/digital error correction/decimation = 2.51mW. At
0.9V, total = 85.33mW, VTC = 6.3mW, TDC = 61.9mW, clock = 6.63mW, delay buffers bank/digital error correction/decimation = 10.5mW.
5. If any calibration is applied, please identify whether it is on-chip or off-chip.
Off-chip foreground calibration.

Undecided

N/A
A Single-Channel Voltage-Scalable (0.9V-8GS/s 0.8V-7.3GS/s 0.6V-4.5GS/s) >38.7dB SNDR 8b Time-Domain ADC
Featuring Voltage-Shrink Sampling and Asynchronous Pipelined Successive-Approximation in 28nm CMOS
(Placeholder1)
(Placeholder2)
As an emerging architecture targeting ultra-high bandwidth wirelines, time-domain ADC (TDADC) is gaining interest for

its inherent technology scalability and compact silicon area. Although the delay unit used as the reference varies

dramatically at different operating conditions, the PVT-robust of the quantization can be achieved by implementing an

interpolation-based two-stage TDC with the same course/fine topology [1]. However, the speed limit and scaling capacity

of TDADC remain to be explored, which are significant to highlight its technology-oriented superiority other than the

voltage-domain comparatives in high-speed scenarios. Variants (Vernier delay, dynamic delay, passive pulse shrinking,

interpolation) of flash-based TDC [1-4] are widely implemented in TDADC to achieve sub-gate time resolution and mitigate

the speed/resolution trade-off. But the conversion speed of Flash-based TDC is confined by the whole delay line, thus

limiting the maximum achievable frequency (Fig. 1). Two-step quantization is usually used in the Flash-based TDC to

boost the frequency, which inevitably raises the circuit complexity without conquering the frequency reduction [1-5].

Asynchronous pipelined TDC has once been reported in [8] to alleviate the speed/resolution restriction further. But the

time amplifier deployed is PVT-sensitive and not applicable to voltage scaling, and the asynchronous clock generation is

not close considered, resulting in frequency penalty. In addition, the VTCs in previous work [1-7] don’t support a rail-to-

rail full-scale input as abstracted in Fig. 1, which will lead to the deterioration of noise performance and refrain the TDADC

from voltage scaling at high speed. Co-design of VTC and TDC is also insufficient in the reported arts, leading to wasted

effort overoptimizing each sub-block and increasing the cost for TDADC linearity improvement.

In this work, we present a single-channel voltage-scalable (0.9V-8GS/s 0.8V-7.3GS/s 0.6V-4.5GS/s) 8b TDADC by

leveraging several techniques. Namely: 1) Concurrent voltage-shrink sampling and voltage-step generation in the voltage-

to-time conversion, enabling the VTC to support a rail-to-rail full-scale input with linear conversion. 2) An asynchronous

pipelined successive-approximation (APSA) TDC with Vernier reference delay, breaking through the speed limitation

results from the long delay chain and alleviating the resolution/speed trade-off prominently. 3) Co-optimization of the VTC

and TDC, improving the linearity across the 0.6V-0.9V supply band. The prototype achieves (39.9dB, 41.0dB, 39.5dB)
SNDR with the Nyquist input at (0.6V, 0.8V, 0.9V) supply and consuming (20.35mW, 61.43mW, 85.33mW) power and

0.011mm2 area at (4.5GS/s, 7.3GS/s, 8GS/s), leading to the Walden FoM of (56.2fJ/conv.-step, 91.7fJ/conv.-step,

144.1fJ/conv.-step).

Figure 1 shows the block diagram of the proposed TDADC, which consists of a clock pulse generator, a voltage-shrink

sampling VTC, and an APSA TDC. Two bootstrapped switches are cascaded in VTC to achieve voltage-shrink sampling.

The voltage-to-time conversion is accomplished with the current source pulling up the voltage of transition node X. APSA

TDC then quantizes the time-domain signal out of the VTC utilizing successive approximation (SA). Asynchronous

pipelined clocks are generated inside the phase detector (PD) to implement the pipeline logic, breaking the speed limit

due to the inter-stage delay of SA. Vernier delays are deployed in each stage to achieve sub-gate fine time resolution.

Since each stage is implemented with the same structure, the TDC is PVT-robust. Stage 5 and 4 (8 LSB) are repeated as

1bit redundancy to alleviate the time residue offset due to the delay mismatch. A clock derived from the clock pulse

generator is used for last synchronization and decimation. As illustrated in Fig. 1, the maximum achievable frequency of

TDADC is mainly defined by the time resolution T , given the resolution N and the minimum waveform width T for

propagating (subject to technology). The design starts from resolving the resolution T for approximating the speed

limit. With intensive simulation, T is chosen as 370fs (typical) at 0.9V, reaching a max 8GHz clock and covering PD

time offset and the accumulated jitter of timing signal at LSB stage, also guaranteeing the performance with reference

delay mismatch and PD metastability.

Figure 2 presents the VTC behavioral model, illustrating the operation process. In phase 1, when CK is low, switch S1,

S3, S4 are turned on. The input signal is tracked and sampled by capacitor C1. Switch S3, S4 reset both plates of capacitor

C2 to ground. In phase 2, when CK is high, switch S2 and S5 are turned on. The voltage at node Y changes immediately

due to the charge redistribution between C1 and C2, followed adjacently by the voltage stepping at node X because of

the charge conservation (AC resistance of the cascaded current source approaches infinity in this instant). Afterward, the

voltage at node X is pulled up to VDD. Then different rising edges generate owing to the different initial stepping voltage

at node X (according to input), completing the voltage-time conversion. The concurrent voltage-shrink sampling and
voltage-step generation can be described intuitively using the waveforms shown in Fig. 2. The conversion range mismatch

between VTC and TDC with varying PVT is compensated by calibrating the VTC’s conversion gain with the tunable

charging current.

The timing diagram of APSA TDC is illustrated in Fig. 3. Each bit generated in every comparison during SA is captured by

the asynchronous clock CKN with T -T larger than the DFF setup time. The overall data acquisition is achieved with

the presented DFFs bank. A customized NAND gate is deployed in PD for clock generation, leading to a predetermined

timing interval among adjacent CKNs (ΔT) and enabling the pipelined operation along with the SA structure. Since T >

T (3σ limits), the PD is time-offset calibration-free. The comparator metastability is an essential speed-limiting

factor for all types of ADC. But there is an intrinsic gain in metastability performance for the time comparator due to the Y-

X axis transition, as illustrated with the error rate equation in Fig. 3. The TDADC BER is determined by only 1 PD in the

SA architecture, which is set lower than 10-11 (post-simulation) at 0.6V-0.9V supply with the allocated delay T .

TDADC is essentially a cross-domain converter, as shown in Fig. 4. Co-design of the VTC and TDC with inverse

conversion curves can improve the ADC linearity while reducing the linearity requirement of each block. The embedded

binary search algorithm in APSA TDC enables a practical co-design methodology as presented in the flowchart. By

modeling the delay elements of each SA stage, time delay coefficients ΔT , ΔT are used to find the optimal conversion

curve of the TDC. LMS adaptive algorithm is deployed to converge the co-design flow, which is also implemented for the

off-chip foreground calibration of the measured ADC by tuning the effective radix W(i). The mismatch of |ΔT | (3σ

limits) is set to <2T by optimizing the buffer size and chain length in each stage, ensuring the calibration efficiency.

The TDADC fabricated in a 28nm CMOS occupies an active area of 0.011mm2 in Fig. 7. The compact size possesses the

ADC an advantage in time-interleaved implementation. The implemented ~60fF input capacitor enables a >10GHz

bandwidth (0.6V-0.9V). Adjusting bias voltage V (Fig. 1) removes the VTC offset and aligns the VTC/TDC conversion

range gap at different supplies. LMS adaptive foreground calibration is performed once under each power supply,

calibrating the reference delay variation. Measured dynamic performance is summarized in Fig. 5, presenting 53.2dB-

56.6dB SFDR across 0.6V-0.9V. The Walden FoM of the proposed TDADC is improved from 144.1fJ/conv.-step at (0.9V,
8GS/s) to 56.2fJ/conv.-step at (0.6V, 4.5GS/s), achieving optimized energy efficiency through voltage scaling as presented

in Fig. 6 (top-right). The power consumption when supply voltage from 0.9V down to 0.6V follows P ∝ fVDD ,

demonstrating the TDADC only consumes dynamic power and is highly digitized. The performance comparison in Fig. 6

shows that the ADC achieves a maximum 8GS/s and SNDR >38.7dB (up to 10GHz input), supporting a rail-to-rail full-

scale input. Our design is the first presented 8GS/s single channel 8b ADC with voltage scaling down to 0.6V (4.5GS/s)

in favor of extensive applications driven by energy-efficient high-speed demand.

(Placeholder3)
References
(1)
[1] M. Zhang, et al., "16.2 a 4× interleaved 10GS/s 8b time-domain ADC with 16× interpolation-
based inter-stage gain achieving> 37.5 dB SNDR at 18GHz input," ISSCC, pp. 252-254, Feb.
2020.
(2)
[2] M. Hassanpourghadi and M. S.-W. Chen, “A 2-way 7.3-bit 10 GS/s Time-Based Folding ADC
with Passive Pulse-Shrinking Cells,” IEEE CICC, pp. 1-2, Apr. 2019.
(3)
[3] K. Ohhata, “A 2.3-mW, 1-GHz, 8-Bit Fully Time-Based Two-Step ADC Using a High-
Linearity Dynamic VTC,” IEEE JSSC, vol. 54, no. 7, pp. 2038-2048, Jul. 2019.
(4)
[4] G. Erfan et al., "10.8 A 4-element 500MHz-modulated-BW 40mW 6b 1GS/s analog-time-to-
digital-converter-enabled spatial signal processor in 65nm CMOS." ISSCC, pp. 186-188, Feb.
2020.
(5)
[5] Y. Lyu, and Filip Tavernier, "A 4-GS/s 39.9-dB SNDR 11.7-mW hybrid voltage–time two-step
ADC with feed-forward ring oscillator-based TDCs," IEEE JSSC, vol. 55, no. 7, pp. 1807-1818, Jul.
2020.
(6)
[6] S. Zhu et al., “A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder
Number System in 65-nm CMOS,” IEEE JSSC, vol. 53, no. 4, pp. 1172-1183, Apr. 2018.
(7)
[7] Yi. Il-Min et al., "A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time
Converter and Pipelined TDC in 65-nm CMOS." IEEE JSSC, vol. 56, no. 2, pp. 465-475, Feb.
2021.
(8)
[8] J. Kim et al., “A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital
Converter With on-Chip Digital Background Calibration in 0.13-μm CMOS,” IEEE JSSC, vol. 48,
no. 2, pp. 516-526, Feb. 2013.
 Asynchronous
𝐓𝐝 + 𝐓𝐅𝐒 /𝟐 𝐓𝐝 + 𝐓𝐅𝐒 /𝟐 Pipelined SA TDC

MUX

MUX
Clock Pulse
Generator 𝐕𝐛 VTC 𝐓𝐝 𝐓𝐝
50Ω I PD PD ... ... PD
𝐓𝐝 𝐓𝐝

MUX

MUX
X 𝐓𝐝 + 𝐓𝐅𝐒 /𝟐 𝐓𝐝 + 𝐓𝐅𝐒 /𝟐
BS BS Stage8 B8 & CK8 Stage7 B7 & CK7 Stage0 B0 & CK0
Delay Buffers Bank ( x9 x8 x7 x6 x5 x4 x3 x2 x1)
60fF 9b sampled data 9 asynchronous clocks
Asynchronous Pipelined DFFs
& Digital Error Correction (DEC)
synchronous clock
& Decimation
8b output

Speed limit Voltage scalability Traditional VTCs

𝐓𝐂𝐊
clock 1 input sampled as the initial voltage
pulse SNR VDD VDD SNR 𝐕𝐈𝐍 𝐕𝐈𝐍 < 𝐕𝐃𝐃 − 𝐕𝐓𝐇
VTC noise
𝐕𝐓𝐇
𝐓𝐅𝐒 /𝟐 𝐓𝐏
voltage-domain time-domain 2 input controlling discharge
technology
𝟏 𝟏 𝟏 𝐕𝐏 |𝐕𝐏 − 𝐕𝐍 | << 𝐕𝐃𝐃
𝐅𝐦𝐚𝐱 = < = PD offset delay mismatch 𝐕𝐍
𝐓𝐂𝐊 𝐓𝐅𝐒 /𝟐 + 𝐓𝐏 𝟐𝐍−𝟏 𝐓𝐋𝐒𝐁 + 𝐓𝐏 (linear discharge)
elementary block jitter
Initial 𝐓𝐋𝐒𝐁 Flash-based TDC
𝟏 propagate
𝐅𝐦𝐚𝐱 < N bits
𝐓𝐝 + 𝐦𝐚𝐫𝐠𝐢𝐧
𝟏 T T ... T
𝐓𝐋𝐒𝐁
𝐓𝐏
time resolution
minimum width for propagating
𝐅𝐦𝐚𝐱 < ? 𝐓𝐝 + 𝐦𝐚𝐫𝐠𝐢𝐧 B1 B2 B3
𝐅𝐦𝐚𝐱 =
𝟏
(𝟐𝐍 − 𝟏)ⅹ𝐓 BM
𝐓𝐝 time allocated for PD metastability T2B decoder
𝐓𝐅𝐒 TDC full-scale input N bits

Fig. 1: Block diagram of the proposed ADC (top). Speed limit and voltage scalability of TDADC,
and abstract models of traditional VTCs and Flash-based TDC.
 Phase 1 CK=0
VTC Behavioral Model CK

VDD
Pulse S4
I S1

CK S5 X OUT S3

Phase 2 CK=VDD VDD

S4 𝐓𝐎𝐔𝐓
I
𝐕𝐈𝐍 S1 S2 C2
Y
CK S5
C1 C3
S3 S2

input output X charge conservation

shrunken input (virtual )
𝐕𝐗 = 𝛂𝐕𝐈𝐍
linear 𝐂𝟏 𝐂 𝟐
charging 𝛂=
𝐕𝐗 𝐓𝐎𝐔𝐓 𝐂𝟏 (𝐂𝟐 + 𝐂𝟑 ) + 𝐂𝟐 𝐂𝟑
region
linear charging Conversion
𝛂𝐈 Gain
𝚫𝐓 = 𝐕𝐈𝐍
sample charge redistribution voltage step, pull-up 𝐂𝟏 //𝐂𝟐 + 𝐂𝟑

Fig. 2: Behavioral model of the proposed voltage-shrink sampling VTC and the operation process.
The VTC conversion gain with a tunable charging current (bottom-right).
APSA TDC Timing Diagram (no showing redundancy) B8 B7 B6 B5 B4 B3 B2 B1 B0
𝐓𝐈𝐍 CK8 CK7 CK6 CK5 CK4 CK3 CK2 CK1 CK0
VTC D D D D D D D D D
𝚫𝐓 Q Q Q Q Q Q Q Q Q
B7 1 0 CK7 CK6 CK5 CK4 CK3 CK2 CK1 CK0
D D D D D D D D
CK7 Q Q Q Q Q Q Q Q
> 𝐬𝐞𝐭𝐮𝐩𝐃𝐅𝐅 1
CK6 CK5 CK4 CK3 CK2 CK1 CK0
OUT7 D D D D D D D
Q Q Q Q Q Q Q
B6 1 0

CK6 .. .. .. .. .. ..
OUT6
11
. CK1 . CK0 . . . .
.. .. .. D D DFFs bank
Q Q
𝚫𝐓 > 𝐝𝐞𝐥𝐚𝐲𝐃𝐅𝐅 + 𝐬𝐞𝐭𝐮𝐩𝐃𝐅𝐅
𝐓𝐏𝐃 − 𝐓𝐂𝐊 > 𝐬𝐞𝐭𝐮𝐩𝐃𝐅𝐅
𝚫𝐓 = 𝐓𝐂𝐊(𝐧−𝟏) − 𝐓𝐂𝐊(𝐧) = 𝐝 {
𝐓 + 𝐓𝐌𝐔𝐗 + 𝟐𝐢−𝟏 𝐓𝐋𝐒𝐁
𝐓𝐝 + 𝐓𝐌𝐔𝐗 D
CK0

Q
PD: phase detector & asynchrnous clock
VDD removed for MSB 𝐂𝐊 𝐕𝐓𝐂
ON OP
Synchronous DFFs
PD time offset:
IP OP P N P Mux_P
𝐓𝐋𝐒𝐁 > 𝐓𝐎𝐅𝐅𝐒𝐄𝐓 (3σ limits) => calibration free
IN ON N SR_latch PD metastability:
0.9V
Mux_N TT, 27

Error Rate Perror

𝟐𝐕𝐥𝐨𝐠𝐢𝐜 −𝐓𝐝 1E-8
0.8V
0.7V
𝐏𝐞𝐫𝐫𝐨𝐫 = 𝐞 𝛕
OP ON 𝐓𝐏𝐃 𝐀 𝐕 ⅹ𝐓𝐋𝐒𝐁 ⅹ𝐒𝐥𝐞𝐰𝐑𝐚𝐭𝐞 1E-11
0.6V

1E-12

𝛕: 𝐏𝐃 𝐫𝐞𝐠𝐞𝐧𝐞𝐫𝐚𝐭𝐢𝐨𝐧 𝐭𝐢𝐦𝐞 𝐜𝐨𝐧𝐬𝐭𝐚𝐧𝐭

1E-16
NAND 𝐀𝐕 = 𝟏: 𝐠𝐚𝐢𝐧 𝐛𝐞𝐟𝐨𝐫𝐞 𝐏𝐃
𝐕𝐥𝐨𝐠𝐢𝐜 = 𝐕𝐃𝐃 ∶ 𝐯𝐚𝐥𝐢𝐝 𝐨𝐮𝐭𝐩𝐮𝐭 𝐯𝐨𝐥𝐭𝐚𝐠𝐞 𝐥𝐞𝐯𝐞𝐥 1E-20
0.8 1 1.2 1.4
Delay (X100ps)
𝐓𝐂𝐊 data
𝐓𝐝
balance IP/IN
clock Benefit for time comparator 132ps 96ps 78ps 67ps

Fig. 3: Timing diagram of the proposed APSA TDC and the implemented DFFs bank for data
synchronization (top). Schematic of the implemented PD with time-offset calibration-free (bottom-
left) and the PD metastability analysis (bottom-right).
 Cross-domain conversion Linearity optimization & calibration
𝚫𝐓𝐢𝐏 𝚫𝐓𝐍

time difference
∑𝟕𝐢=𝟎 𝐖(𝐢)ⅹ 𝐃 − 𝐢𝐢 𝐃𝐢

digital code

digital code
𝐓𝐈𝐍 𝟐𝐢 𝐢 𝟐
VTC + TDC = ADC
𝐃𝐎𝐔𝐓 =
𝐓𝐅𝐒
=
𝐓𝐅𝐒
(𝐃𝐎𝐔𝐓 𝛜(−𝟏, 𝟏) 𝐖(𝐢) = 𝟐𝐢 )
=ƒ(x) =ƒ-1(x)
analog voltage time difference analog voltage (LMS adaptive)

Stage delay with Vernier reference

𝐓𝐢𝐏 𝐓𝐌𝐔𝐗,𝐏 Initial Initial
𝚫𝐓𝐢𝐏 = 𝚫𝐓𝐢𝐍 = 𝟐𝐢−𝟏 𝐓𝐋𝐒𝐁 𝐖(𝐢) = 𝟐𝐢
𝐂+ 𝐂𝐢𝐏
1 ADC
𝚫𝐓𝐢𝐏 , 𝚫𝐓𝐢𝐍 𝐖(𝐢) (sinewave)
IP OP VTC
0 (spice)
𝐏
𝐓𝐈𝐍 𝐂
𝐓𝐝𝐏 TDC (verilogA) 𝐃𝐎𝐔𝐓 =
𝐢
𝐖(𝐢)𝐃(𝐢)𝐀𝐃𝐂

𝐃𝐢 , 𝐃𝐢 = (𝟏, 𝟎) 𝐨𝐫 (𝟎, 𝟏) 𝚫𝐓𝐢𝐏 = 𝐓𝐢𝐏 −𝐓𝐝𝐍

PD Amplitude
𝐓𝐏𝐃,𝐎𝐅𝐅𝐒𝐄𝐓 𝚫𝐓𝐢𝐍 = 𝐓𝐢𝐍 − 𝐓𝐝𝐏 INL/DNL No Phase
THD/SFDR +
+-
𝐍
𝐓𝐈𝐍 𝐓𝐢𝐍 Offset
? estimation
𝐂 + 𝐂𝐢𝐍
0 Yes (FFT)
IN ON
1 𝚫𝐓𝐢𝐏 , 𝚫𝐓𝐢𝐍 𝐂𝐢𝐏 , 𝐂𝐢𝐍 error
𝐂 𝐓𝐌𝐔𝐗,𝐍
𝐓𝐝𝐍 ADC verification
No
converges
(spice) ?
|(𝐓𝐎𝐏 − 𝐓𝐈𝐏 ) − (𝐓𝐎𝐍 − 𝐓𝐈𝐍 )| = 𝚫𝐓𝐢 Yes
𝐝𝐮𝐞 𝐭𝐨 𝐓𝐌𝐔𝐗,𝐏 , 𝐓𝐌𝐔𝐗,𝐍 , 𝚫𝐓𝐢𝐏 , 𝚫𝐓𝐢𝐍 Design closure Calibration done
|𝚫𝐓𝐢 − 𝟐(𝐢−𝟏) 𝐓𝐋𝐒𝐁 | ≠ 𝟎 => 𝐦𝐢𝐬𝐦𝐚𝐭𝐜𝐡

Fig. 4: Linearity improvement for cross-domain conversion (top-left). Delay model of the
quantization stage in APSA TDC with Vernier reference delay (bottom-left) and co-design of
VTC/TDC for linearity optimization and off-chip foreground calibration (right).
 w/o, Cal w/o, Cal

Magnitude [dBFS]
Magnitude [dBFS]
0 0.9V 8GS/s fin= 117.3096MHz 0 0.9V 8GS/s -THD= 50.0dB
-20 SFDR= 54.9dB -THD= 51.6dB -20 fin=3.96191GHz SNDR=39.5dB
-40 SNDR=40.8dB ENOB=6.49bit
-40 SFDR= 53.2dB ENOB=6.21bit

-60 -60
-80 -80
0 5 10 15 0 5 10 15
Frequency [MHz] w/o, Cal Frequency [MHz] w/o, Cal
Magnitude [dBFS]

Magnitude [dBFS]
0 0.8V 7.3GS/s fin= 27.6245MHz 0 0.8V 7.3GS/s -THD= 54.4dB
-20 SFDR= 56.0dB -THD= 54.1dB -20 fin=3.61525GHz SNDR=41.0dB
ENOB=6.52bit
-40 SNDR=41.8dB ENOB=6.65bit -40 SFDR= 56.6dB
-60 -60
-80 -80
0 4 8 12 0 4 8 12
Frequency [MHz] w/o, Cal Frequency [MHz] w/o, Cal

Magnitude [dBFS]
Magnitude [dBFS]

0 0.6V 4.5GS/s fin= 32.4097MHz 0 0.6V 4.5GS/s -THD= 51.5dB

-20 SFDR= 56.6dB -THD= 52.7dB -20 fin=2.23737GHz SNDR=39.9dB
-40 SNDR=40.4dB ENOB=6.42bit -40 SFDR= 54.2dB ENOB=6.33bit

-60 -60
-80 -80
0 2 4 6 8 0 2 4 6 8
Frequency [MHz] Frequency [MHz]

Fig. 5: Measured 8192-point output spectrum at (0.9V, 8GS/s), (0.8V, 7.3GS/s), (0.6V, 4.5GS/s)
with (blue) and without (red) calibration (decimated by 255x).
 160
80 measured measured with voltage scaling

[fJ/conv.-step]
Power [mW]
measured at 0.9V

FOMWalden
60 ∝ 𝒇𝑽𝑫𝑫𝟐 120
0.9V
0.8V
40 80
0.7V
0.6V optimal range
20 40
[0.6V 4.5GS/s] [0.7V 6.0GS/s] [0.8V 7.3GS/s] [0.9V 8.0GS/s] [4.5GS/s] [6.0GS/s] [7.3GS/s] [8.0GS/s]

[1] S. Zhu [7] [3] [5] Z. Zheng

This work
ISSCC20 VLSI17 JSSC21 JSSC 19 JSSC20 ISSCC20
Hybrid Dynamic
Architecture Time-Domain (TD)
(CDAC+TD) Pipeline
Technology 28nm 65 65 65 65 28 28
Channels 1 4 1 1 1 1 1
Resolution (bits) 8 8 7.93 7 8 7 6
Area (mm2) 0.011 0.095 0.08 0.011 0.007 0.017 0.017
Supply (V) 0.9 0.8 0.6 1 1.2/1.3 1 1 1 0.9
Input Range (Vpp,diff ) 1.8 1.6 1.2 0.9 1.2 1.6 0.8 <0.81 N/A
fs (GS/s) 8 7.3 4.5 10 2 4 1 4 3.3
39.5 41.0 39.9 40.1
SNDR (dB) @ Nyquist 40.7 34.58 44.4 39.9 34.2
(38.8 @9.77G2) (40.5 @9.87G2) (39.1 @9.75G2) (37.6 @18.1G)

54.2 56.6 53.2 52.8

SFDR (dB) @ Nyquist 48.4 45.7 59.7 47.8 45.5
(52.1 @9.77G2) (53.0 @9.87G2) (51.1 @9.75G2) (46.7 @18.1G)

Power (mW) 85.33 61.43 20.35 50.8 21 11.3 2.3 11.7 5.5
FOMWalden (fJ/conv.-step)
144.1 91.7 56.2 61.5 119 64.5 18.7 39.3 40.0
@Nyquist
FOMScehreier (dB)
146.6 148.8 150.4 150.0 150.6 147.1 157.3 152.2 148.9
@Nyquist
1
Estimated from simulation .
2
Maximum input frequency is limited by balun deployed for measurement.

Fig. 6: Measured power consumption versus (voltage, speed) and measured Walden FoM
with/without voltage scaling (top). Performance summary and state-of-the-art comparison
(bottom).
 37 um

Clock VTC

311 um
Buffers

APSA
DFFs bank TDC
&DEC
&Decimation

Fig. 7: Die micrograph.

 60 60

55 55

50 50

[dB]
[dB]
SFDR
SFDR -THD
45 0.9V 8GS/s -THD 45 0.8V 7.3GS/s SNDR
SNDR
40 40

0 2 4 6 8 10 0 2 4 6 8 10
Input Frequency [GHz] Input Frequency [GHz]

60 60

55 55

50 50
[dB]

[dB]
SFDR
SFDR
45 0.6V 4.5GS/s -THD
SNDR 45 0.6V 4.5GS/s -THD
SNDR

40 40

0 2 4 6 8 10 -30 -15 0 15 30 45 60 75 90
Input Frequency [GHz] Ambient Temperature [℃]

Fig. S1: Measured SFDR/-THD/SNDR versus input frequency at (0.9V 8GS/s) (0.8V 7.3GS/s)
(0.6V 4.5GS/s). Measured SFDR/-THD/SNDR versus ambient temperature at (0.6V 4.5GS/s).
 Clock 1.6mW Clock 4.79mW

Others
Others 2.51mW 7.61mW

VTC 1.54mW VTC 4.62mW

TDC 14.7mW TDC 44.41mW
0.6V 4.5GS/s 0.8V 7.3GS/s

Clock 6.63mW
Supply Speed Power FOMW
Others 10.5mW
(V) (GS/s) (mW) (fJ/conv.-step)
@ Nyq.
0.9 8 85.33 144.1
0.8 7.3 61.43 91.7
0.6 4.5 20.35 56.2
TDC 61.9mW VTC 6.3mW
0.9V 8GS/s

Fig. S2: Power breakdowns and Walden FoM summary at (0.6V, 4.5GS/s), (0.8V, 7.3GS/s), (0.9V,
8GS/s). Others include delay buffers bank, digital error correction, and decimation.
 PC
(Matlab)
Temperature chamber
Keysight E8257D 11612V K69
Signal Generator Bias-Tee
BAL-0010 Balun
Input
PCB
damping ..10..
..00..

DUT
..11..
..01..
Phase Locked ..11..
..10..
..00..
11612V K69 ..10..
Bias-Tee LT3045 LDOs
BAL-0010 Balun
Keysight 16821A
Logic Analyzer
Clock
Keysight E8267D
Signal Generator

Keysight N6705B Power Source

Fig. S3: Measurement setup.