TDF8553J: 1. General Description

TDF8553J
I2C-bus controlled 4 × 50 Watt power amplifier and multiple

voltage regulator
Rev. 01 — 3 December 2008 Objective data sheet
1. General description
1.1 Amplifiers
The TDF8553 has a complementary quad audio power amplifier that uses BCDMOS
technology. It contains four amplifiers configured in Bridge Tied Load (BTL) to drive
speakers for front and rear left and right channels. The I2C-bus allows diagnostic
information of each amplifier and its speaker to be read separately. Both front and both
rear channel amplifiers can be configured independently in line driver mode with a gain of
20 dB (differential output) or amplifier mode with a gain of 26 dB (BTL output).
1.2 Voltage regulators

The TDF8553 has a multiple output voltage regulator with two power switches.
The voltage regulator contains the following:
• Four switchable regulators and two standby regulators

• Two power switches with loss-of-ground protection and surge protection
• Second supply pin to reduce dissipation by means of an external DC-to-DC converter
2. Features
n Amplifiers
u I2C-bus control
u Can drive a 2 Ω load with a battery voltage of up to 16 V and a 4 Ω load with a
battery voltage of up to 18 V
u DC load detection, open, short and present
u AC load (tweeter) detection
u Programmable clip detect; 1 % or 4 %
u Programmable thermal protection pre-warning
u Independent short-circuit protection per channel
u Selectable line driver (20 dB) and amplifier mode (26 dB)
u Loss-of-ground and open VP safe
u All outputs protected from short-circuit to ground, to VP or across the load
u All pins protected from short-circuit to ground
u Soft thermal-clipping to prevent audio holes
u Low battery detection
NXP Semiconductors TDF8553J
4 × 50 Watt power amplifier and multiple voltage regulator
n Voltage regulators
u I2C-bus control
u Good stability for any regulator with almost any output capacitor value
u Six voltage regulators (microcontroller, display, audio processor, tuner, bus,
mechanical digital and drive)
u Selectable output voltages for regulators 1, 4 and 5
u Low dropout voltage PNP output stages
u High supply voltage ripple rejection
u Low noise for all regulators
u Two power switches (antenna switch and amplifier switch)
u Standby regulators 2 and 6 (microcontroller and bus supply) operational during
load dump and thermal shut-down
u Low standby quiescent current (only regulators 2 and 6 operational)
u Second supply pin for connecting optional external DC-to-DC converter to reduce
internal dissipation
u Backup functionality for regulator 2
n Protection
u If connection to the battery voltage is reversed, all regulator voltages will be zero
u Able to withstand output voltages up to 18 V (supply line may be short-circuited)
u Thermal protection to avoid thermal breakdown
u Load-dump protection
u Regulator outputs protected from DC short-circuit to ground or to supply voltage
u All regulators protected by foldback current limiting
u Power switches protected from loss-of-ground and surge conditions
3. Applications
n Boost amplifier and voltage regulator for car radios and CD/MD players
4. Quick reference data

Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
Amplifiers
VP(oper) operating supply voltage RL = 4 Ω 8 14.4 18 V
Iq(tot) total quiescent current no load - 280 400 mA
Po(max) maximum output power RL = 4 Ω; VP = 14.4 V; VIN = 2 V RMS square wave 44 46 - W
RL = 4 Ω; VP = 15.2 V; VIN = 2 V RMS square wave 49 52 - W
RL = 2 Ω; VP = 14.4 V; VIN = 2 V RMS square wave 83 87 - W
THD total harmonic distortion Po = 1 W to 12 W; f = 1 kHz; RL = 4 Ω - 0.01 0.1 %
Vn(o) output noise voltage filter 20 Hz to 22 kHz; RS = 600 Ω
line driver mode - 25 35 µV
amplifier mode - 50 70 µV
TDF8553J_1 © NXP B.V. 2008. All rights reserved.
Objective data sheet Rev. 01 — 3 December 2008 2 of 47

Table 1. Quick reference data …continued

Voltage regulators
VP supply voltage regulators 1, 3, 4 and 5 on; switches 1 and 2 on 10 14.4 18 V
jump starts for t ≤ 10 minutes - - 30 V
load dump protection for t ≤ 50 ms and tr ≥ 2.5 ms - - 50 V
Vth(dis) disable threshold regulator 1, 3, 4 and 5 on; switches 1 and 2 on 18.1 22 - V
voltage
VDCDC DC-to-DC converter 4.75 5.0 VP V
voltage
Iq(tot) total quiescent current standby mode; VP = 14.4 V - 180 250 µA
VO(reg) regulator output voltage regulator 1; 0.5 mA ≤ IO ≤ 400 mA; 10 V ≤ VP ≤ 18 V;
selectable via I2C-bus
IB2[D3:D2] = 01 7.9 8.3 8.7 V
IB2[D3:D2] = 10 8.1 8.6 9.1 V
IB2[D3:D2] = 11 4.75 5.0 5.25 V
regulator 2; 0.5 mA ≤ IO ≤ 350 mA; 10 V ≤ VP ≤ 18 V 3.1 3.3 3.5 V
regulator 3; 0.5 mA ≤ IO ≤ 500 mA; 5 V ≤ VDCDC ≤ 18 V 3.1 3.3 3.5 V
regulator 4; 0.5 mA ≤ IO ≤ 800 mA; 10 V ≤ VP ≤ 18 V;
selectable via I2C-bus
IB2[D7:D5] = 001 4.75 5.0 5.25 V
IB2[D7:D5] = 010 5.7 6.0 6.3 V
IB2[D7:D5] = 011 6.6 7.0 7.4 V
IB2[D7:D5] = 100 8.1 8.6 9.1 V
IB2[D7:D5] = 101 7.6 8.0 8.4 V
regulator 5; 0.5 mA ≤ IO ≤ 400 mA; selectable via
I2C-bus
10 V ≤ VP ≤ 18 V; IB1[D7:D4] = 0001 5.7 6.0 6.3 V
10 V ≤ VP ≤ 18 V; IB1[D7:D4] = 0010 6.65 7.0 7.37 V
10 V ≤ VP ≤ 18 V; IB1[D7:D4] = 0011 7.8 8.2 8.6 V
10.5 V ≤ VP ≤ 18 V; IB1[D7:D4] = 0100 8.55 9.0 9.45 V
11 V ≤ VP ≤ 18 V; IB1[D7:D4] = 0101 9.0 9.5 10.0 V
11.5 V ≤ VP ≤ 18 V; IB1[D7:D4] = 0110 9.5 10.0 10.5 V
13 V ≤ VP ≤ 18 V; IB1[D7:D4] = 0111 9.9 10.4 10.9 V
14.2 V ≤ VP ≤ 18 V; IB1[D7:D4] = 1000 11.8 12.5 13.2 V
12.5 V ≤ VP ≤ 18 V; IB1[D7:D4] = 1001 VP − 1 VP − 0.5 - V
10 V ≤ VP ≤ 18 V; IB1[D7:D4] = 1010 4.75 5.0 5.25 V
10 V ≤ VP ≤ 18 V; IB1[D7:D4] = 1011 3.1 3.3 3.5 V
regulator 6; 0.5 mA ≤ IO ≤ 100 mA; 10 V ≤ VP ≤ 18 V 4.75 5.0 5.25 V
Power switches
Vdo dropout voltage switch 1; IO = 400 mA - 0.6 1.1 V
switch 2; IO = 400 mA - 0.6 1.1 V

5. Ordering information
Table 2. Ordering information
Type number Package
Name Description Version
TDF8553J DBS37P plastic DIL-bent-SIL power package; 37 leads (lead length 6.8 mm) SOT725-1

6. Block diagram
28
REGULATOR 6 REG6
36 37
BUCAP REGULATOR 2 REG2
TEMPERATURE &
BACKUP REFERENCE LOAD DUMP
SWITCH VOLTAGE PROTECTION VOLTAGE
REGULATOR
35
VP REGULATOR 1 30
REG1
VDCDC 26
REGULATOR 3 31
REG3
REGULATOR 4 33
ENABLE REG4
LOGIC
REGULATOR 5 34
REG5
SWITCH 1
29
SW1
SWITCH 2
27
SW2
32
GND
20
2 VP1
SDA 6
4 TDF8553J VP2
SCL 25
DIAG
22 I2C-BUS
STB STANDBY/ MUTE CLIP DETECT/ DIAGNOSTIC
INTERFACE
11 MUTE 9
IN1 26 dB/ OUT1+
20 dB 7
OUT1−
PROTECTION/
DIAGNOSTIC
15 MUTE 17
IN2 26 dB/ OUT2+
20 dB 19
OUT2−
PROTECTION/
DIAGNOSTIC
12 MUTE 5
IN3 26 dB/ OUT3+
20 dB 3
OUT3−
PROTECTION/
DIAGNOSTIC
14 MUTE 21
IN4 26 dB/ OUT4+
20 dB 23
VP OUT4−
PROTECTION/
DIAGNOSTIC
TEMPERATURE & LOAD

DUMP PROTECTION
AMPLIFIER
10 13 16 8 1 18 24
SVR SGND PGND1 PGND3 coa070

ACGND PGND2/TAB PGND4
Fig 1. Block diagram

7. Pinning information
7.1 Pinning
PGND2/TAB 1
SDA 2
OUT3− 3
SCL 4
OUT3+ 5
VP2 6
OUT1− 7
PGND1 8
OUT1+ 9
SVR 10
IN1 11
IN3 12
SGND 13
IN4 14
IN2 15
ACGND 16
OUT2+ 17
PGND3 18
OUT2− 19 TDF8553
VP1 20
OUT4+ 21
STB 22
OUT4− 23
PGND4 24
DIAG 25
VDCDC 26
SW2 27
REG6 28
SW1 29
REG1 30
REG3 31
GND 32
REG4 33
REG5 34
VP 35
BUCAP 36
REG2 37
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Fig 2. Pin configuration

7.2 Pin description

Table 3. Pin description
Symbol Pin Description
PGND/TAB 1 power ground 2 and connection for heatsink
SDA 2 I2C-bus data input and output
OUT3− 3 channel 3 negative output
SCL 4 I2C-bus clock input
OUT3+ 5 channel 3 positive output
VP2 6 power supply voltage 2 to amplifiers
PGND1 8 power ground 1
SVR 10 half supply voltage filter capacitor
IN1 11 channel 1 input
SGND 13 signal ground
ACGND 16 AC ground
VP1 20 power supply voltage 1 to amplifiers
STB 22 standby, operating or mute mode select input
DIAG 25 diagnostic and clip detection output, active LOW
VDCDC 26 power supply voltage from optional DC-to-DC converter
SW2 27 antenna switch; supplies unregulated power to car aerial motor
REG6 28 regulator 6 output; supply for bus controller
SW1 29 amplifier switch; supplies unregulated power to amplifier(s)
REG1 30 regulator 1 output; supply for audio part of radio and CD player
REG3 31 regulator 3 output; supply for signal processor part (mechanical
digital) of CD player
GND 32 combined voltage regulator, power and signal ground
REG4 33 regulator 4 output; supply for mechanical part (mechanical drive)
of CD player
REG5 34 regulator 5 output; supply for display part of radio and CD player
VP 35 power supply to voltage regulators
BUCAP 36 connection for backup capacitor
REG2 37 regulator 2 output; supply voltage to microcontroller

8. Functional description
The TDF8553 is a multiple voltage regulator combined with four independent audio power
amplifiers configured in bridge tied load, with diagnostic capability. All regulator output
voltages except regulators 2 and 6 can be controlled via the I2C-bus.
The amplifier diagnostic functions give information about output offset, load, or
short-circuit. Diagnostic functions are controlled via the I2C-bus. The TDF8553 is
protected against short-circuit, over-temperature, open ground and open VP connections.
If a short-circuit occurs at the output of a single amplifier, that channel shuts down, and
the other channels continue to operate normally. The channel that has a short-circuit can
be switched off by the microcontroller via the appropriate enable bit of the I2C-bus to
prevent any noise generated by the fault condition from being heard.
8.1 Start-up
At power on, regulators 2 and 6 will reach their final voltage when the backup capacitor
voltage exceeds 5.5 V independently of the voltage on pin STB. When pin STB is LOW,
the total quiescent current is low, and the I2C-bus lines are high impedance.
When pin STB is HIGH, the I2C-bus is biased on and then the TDF8553 performs a
power-on reset. When bit D0 of instruction byte IB1 is set, the amplifier is activated, bit D7
of data byte DB2 (power-on reset occurred) is reset, and pin DIAG is no longer held LOW.
8.2 Start-up and shut-down timing

See Figure 12.
A capacitor connected to pin SVR enables smooth start-up and shut-down, preventing the
amplifier from producing audible clicks at switch-on or switch-off. The start-up and
shut-down times can be extended by increasing the capacitor value.
If the amplifier is shut down using pin STB, the amplifier is muted, the regulators and
switches are switched off, and the capacitor connected to pin SVR discharges. The
low-current standby mode is activated 2 seconds after pin STB goes LOW.
8.3 Power-on reset and supply voltage spikes

See Figure 13 and Figure 14.
If the supply voltage drops too low to guarantee the integrity of the data in the I2C-bus
latches, the power-on reset cycle will start. All latches will be set to a predefined state,
pin DIAG will be pulled LOW to indicate that a power-on reset has occurred, and bit D7 of
data byte DB2 is also set for the same reason. When D0 of instruction byte IB1 is set, the
power-on flag resets, pin DIAG is released and the amplifier will then enter its start-up
cycle.
8.4 Diagnostic output

Pin DIAG indicates clipping, thermal protection pre-warning of amplifier and voltage
regulator sections, short-circuit protection, and low and high battery voltage. Pin DIAG is
an open-drain output, is active LOW, and must be connected to an external voltage via an

external pull-up resistor. If a failure occurs, pin DIAG remains LOW during the failure and
no clipping information is available. The microcontroller can read the failure information
via the I2C-bus.
8.5 Amplifiers
8.5.1 Muting
A hard mute and a soft mute can both be performed via the I2C-bus. A hard mute mutes
the amplifier within 0.5 ms. A soft mute mutes the amplifier within 20 ms and is less
audible. A hard mute is also activated if a voltage of 8 V is applied to pin STB.
8.5.2 Temperature protection

If the average junction temperature rises to a temperature value that has been set via the
I2C-bus, a thermal protection pre-warning is activated making pin DIAG LOW. If the
temperature continues to rise, all four channels will be muted to reduce the output power
(soft thermal clipping). The value at which the temperature mute control activates is fixed;
only the temperature at which the thermal protection pre-warning signal occurs can be
specified by bit D4 in instruction byte IB3. If implementing the temperature mute control
does not reduce the average junction temperature, all the power stages will be switched
off (muted) at the absolute maximum temperature Tj(max).
8.5.3 Offset detection

Offset detection can only be performed when there is no input signal to the amplifiers, for
instance when the external digital signal processor is muted after a start-up. The output
voltage of each channel is measured and compared with a reference voltage. If the output
voltage of a channel is greater than the reference voltage, bit D2 of the associated data
byte is set and read by the microcontroller during a read instruction. Note that the value of
this bit is only meaningful when there is no input signal and the amplifier is not muted.
Offset detection is always enabled.
8.5.4 Speaker protection

If one side of a speaker is connected to ground, a missing current protection is
implemented to prevent damage to the speaker. A fault condition is detected in a channel
when there is a mismatch between the power current in the high side and the power
current in the low side; during a fault condition the channel will be switched off.
The load status of each channel can be read via the I2C-bus: short to ground (one side of
the speaker connected to ground), short to VP (one side of the speaker connected to VP),
and shorted load.
8.5.5 Line driver mode

An amplifier can be used as a line driver by switching it to low gain mode. In normal mode,
the gain between single-ended input and differential output (across the load) is 26 dB. In
low-gain mode the gain between single-ended input and differential output is 20 dB.

8.5.6 Input and AC ground capacitor values

The negative inputs to all four amplifier channels are combined at pin ACGND. To obtain
the best performance of supply voltage ripple rejection and unwanted audible noise, the
value of the capacitor connected to pin ACGND must be as close as possible to 4 times
the value of the input capacitor connected to the positive input of each channel.
8.5.7 Load detection
8.5.7.1 DC-load detection

When DC-load detection is enabled, during the start-up cycle, a DC-offset is applied
slowly to the amplifier outputs, and the output currents are measured. If the output current
of an amplifier rises above a certain level, it is assumed that there is a load of less than
6 Ω and bit D5 is reset in the associated data byte register to indicate that a load is
detected.
Because the offset is measured during the amplifier start-up cycle, detection is inaudible
and can be performed every time the amplifier is switched on.
8.5.7.2 AC-load detection

AC-load detection can be used to detect that AC-coupled speakers are connected
correctly during assembly. This requires at least 3 periods of a 19 kHz sine wave to be
applied to the amplifier inputs. The amplifier produces a peak output voltage which also
generates a peak output current through the AC-coupled speaker. The 19 kHz sine wave
is also audible during the test. If the amplifier detects three current peaks that are greater
than 550 mA, the AC-load detection bit is set. Three current peaks are counted to avoid
false AC-load detection which can occur if the input signal is switched on and off. The
peak current counter can be reset by setting bit D1 of instruction byte IB1 to logic 0.
To guarantee AC-load detection, an amplifier current of more than 550 mA is required.
AC-load detection will never occur with a current of less than 150 mA.
Figure 3 shows which AC loads are detected at different output voltages. For example, if a
load is detected at an output voltage of 2.5 V peak, the load is less than 4 Ω. If no load is
detected, the output impedance is more than 14 Ω.

001aai691
102
no load present (1)

ZL
(Ω)
undefined (2)
10
load present
1
0 2.5 5 7.5 10
VoM (V)
(1) IoM = < 150 mA.

(2) IoM = > 550 mA.
Fig 3. Tolerance of AC-load detection as a function of output voltage
8.5.7.3 Load detection procedure
1. At start-up, enable the AC or DC-load detection by setting D1 of instruction byte IB1 to

logic 1.
2. After 250 ms the DC load is detected and the mute is released. This is inaudible and
can be implemented each time the IC is powered on.
3. When the amplifier start-up cycle is completed (after 1.5 s), apply an AC signal to the
input, and DC-load bits D5 of each data byte should be read and stored by the
microcontroller.
4. After at least 3 periods of the input signal, the load status can be checked by reading
AC-detect bits D4 of each data byte.
The AC-load peak current counter can be reset by setting bit D1 of instruction
byte IB1 to logic 0 and then to logic 1. Note that this will also reset the DC-load
detection bits D5 in each data byte.
8.5.8 Low headroom protection

The normal DC output voltage of the amplifier is set to half the supply voltage and is
related to the voltage on pin SVR. An external capacitor is connected to pin SVR to
suppress power supply ripple. If the supply voltage drops (at vehicle engine start), the DC
output voltage will follow slowly due to the affect of the SVR capacitor.
The headroom voltage is the voltage required for correct operation of the amplifier and is
defined as the voltage difference between the level of the DC output voltage before the VP
voltage drop and the level of VP after the voltage drop (see Figure 4).
At a certain supply voltage drop, the headroom voltage will be insufficient for correct
operation of the amplifier. To prevent unwanted audible noises at the output, the
headroom protection mode will be activated (see Figure 4). This protection discharges the
capacitors connected to pins SVR and ACGND to increase the headroom voltage.

V
(V) vehicle engine start
VP
14
headroom voltage
SVR voltage
8.4
7
amplifier
DC output voltage
t (s)
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Fig 4. Amplifier output during supply voltage drop
8.6 Voltage regulators

The voltage regulator section contains:
• Four switchable regulators and two standby regulators

• Two power switches with loss-of-ground and surge protection
• Second supply pin to reduce dissipation by means of an external DC-to-DC converter
• Backup functionality for regulator 2
The TDF8553 uses low dropout voltage regulators for use in low voltage applications.
All of the voltage regulators except for the standby regulators can be controlled via the
I2C-bus. The voltage regulator section of this device has two power switches which are
capable of delivering unregulated continuous current, and has several fail-safe protection
modes. It conforms to peak transient tests and protects against continuous high voltage
(24 V), short-circuits and thermal stress. Standby regulators 2 and 6 will try to maintain
output for as long as possible even if a thermal shut-down or any other fault condition
occurs. During overvoltage stress conditions, all outputs except regulators 2 and 6 will
switch off and the device will be able to supply a minimum current for an indefinite amount
of time sufficient for powering the memory of a microcontroller and bus controller
functionality. Provision is made for an external reserve supply capacitor to be connected
to pin BUCAP which can store enough energy to allow regulator 2 to supply a
microcontroller for a period long enough for it to prepare for a loss-of-voltage.
8.6.1 Standby regulator outputs

Standby outputs (regulators 2 and 6) are used for the microcontroller and bus controller
supply. These regulators will not shut down with the switched regulators and cannot be
controlled by the I2C-bus. The standby regulators will not shut down during load dump
transients or by high temperature protection.
8.6.2 Backup capacitor

The backup capacitor (Cbackup) is used as a backup supply for the regulator 2 output when
the battery supply voltage (VP) cannot support the regulator 2 voltage.

8.6.3 Backup function

The backup function is implemented by a switch function, which behaves like an ideal
diode between pins VP and BUCAP; the forward voltage of this ideal diode depends on
the current flowing through it. The backup function supplies regulator 2 during brief
periods when no supply voltage is present on pin VP. It requires an external capacitor to
be connected to pin BUCAP and ground. When the supply voltage is present on pin VP
this capacitor will be charged to a level of VP − 0.3 V. When the supply voltage is absent
from pin VP, this charge can then be used to supply regulator 2 for a brief period (tbackup)
calculated using the formula:
V P – ( V REG2 – 0.5 )
t backup = C backup × R L ×  -----------------------------------------------
 V REG2 
Example: VP = 14.4 V, VREG2 (voltage on pin REG2) = 3.3 V, RL = 1 kΩ and
Cbackup = 100 µF provides a tbackup of 321 ms.
When an overvoltage condition occurs, the voltage on pin BUCAP is limited to

approximately 24 V; see Figure 5.
V
(V)
VP
VBUCAP
VREG2
t (s)
tbackup out of regulation
001aai693
V P – ( V REG2 – 0.5 )
t backup = C backup ×  ------------------------------------------------
 I load 
Fig 5. Backup capacitor function
8.6.4 Power switches

There are two power switches that provide an unregulated DC voltage output for
amplifiers and an aerial motor respectively. The switches have internal protection for
over-temperature conditions and are activated by setting bits D2 and D3 of instruction
byte IB1 to logic 1.
In the ON state, the switches have a low impedance to the battery voltage. When the
battery voltage is higher than 22 V, the switches are switched off. When the battery
voltage is below 22 V the switches are set to their original condition.
The power switches have built-in surge protection to be able to absorb energy from
switching inductive or capacitive external loads. This surge protection is implemented in
such a way that in case no supply (VP) is present the supply line will not be charged from
a possible external source connected to a power switch output.

8.6.5 External DC-to-DC converter

The VDCDC supply pin can be connected to an external DC-to-DC down converter
(VO ≥ 5 V) to reduce the dissipation in regulator 3. If no external DC-to-DC converter is
used, the VDCDC pin must be connected to VP.
8.6.6 Protection
All regulator and switch outputs are fully protected by foldback current limiting against load
dumps and short-circuits; see Figure 6. During a load dump all regulator outputs, except
the output of regulators 2 and 6, will go low.
The power switches can withstand ‘loss-of-ground’. This means that if pin GND becomes
disconnected, the switch is protected by automatically connecting its outputs to ground.
8.6.7 Temperature protection

If the junction temperature of a regulator becomes too high, the amplifier(s) are switched
off to prevent unwanted noise signals being audible. A regulator junction temperature that
is too high is indicated by pin DIAG going LOW and is also indicated by setting bit D6 in
data byte DB2.
If the junction temperature of the regulator continues to rise and reaches the maximum
temperature protection level, all regulators and switches will be disabled except
regulators 2 and 6.
VREGn
IOS IOlim IREGn
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Fig 6. Foldback current protection
8.7 I2C-bus specification
0 = write
1 = read
MSB LSB
1 1 0 1 1 0 0 R/W
mdb516
Fig 7. Address byte

If address byte bit R/W = 0, the TDF8553 expects 3 instruction bytes: IB1, IB2 and IB3;
see Table 1 to Table 6.
After a power-on, all instruction bits are set to zero.
If address byte bit R/W = 1, the TDF8553 will send 4 data bytes to the microcontroller:
DB1, DB2, DB3 and DB4; see Table 7 to Table 10.
SDA SDA
SCL SCL
S P
START condition STOP condition

mba608
Fig 8. Definition of start and stop conditions
SDA
SCL
data line change

stable; of data
data valid allowed mba607
Fig 9. Bit transfer

I2C-bus WRITE
SCL 1 2 7 8 9 1 2 7 8 9
SDA MSB MSB − 1 LSB + 1 ACK MSB MSB − 1 LSB + 1 LSB ACK
S ADDRESS W A WRITE DATA A P
To stop the transfer, after the last acknowledge (A)

a stop condition (P) must be generated
I2C-bus READ
SCL 1 2 7 8 9 1 2 7 8 9
SDA MSB MSB − 1 LSB + 1 ACK MSB MSB − 1 LSB + 1 LSB ACK
S ADDRESS R A READ DATA A P
To stop the transfer, the last byte must not be acknowledged

: generated by master (microcontroller) and a stop condition (P) must be generated
: generated by slave (TDF8553)
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S : start
P : stop
A : acknowledge
R/W : read / write
Fig 10. I2C-bus read and write modes
Table 4. Instruction byte IB1 bit description

Bit Symbol Description
7 D7 regulator 5 output voltage control; see Table 5
6 D6
5 D5
4 D4
3 D3 SW2 control
0 = SW2 off
1 = SW2 on
2 D2 SW1 control
0 = SW1 off
1 = SW1 on
1 D1 AC-load or DC-load detection switch
0 = AC-load or DC-load detection off; resets DC-load detection bits
and AC-load detection peak current counter
1 = AC-load or DC-load detection on

Table 4. Instruction byte IB1 bit description …continued

0 D0 amplifier start enable (clear power-on reset flag D7 of DB2)
0 = amplifier off; pin DIAG remains LOW
1 = amplifier on; when power-on occurs, bit D7 of DB2 is reset and
pin DIAG is released
Table 5. Regulator 5 (display) output voltage control

Bit Output (V)
D7 D6 D5 D4
0 0 0 0 0 (off)
0 0 0 1 6.0
0 0 1 0 7.0
0 0 1 1 8.2
0 1 0 0 9.0
0 1 0 1 9.5
0 1 1 0 10.0
0 1 1 1 10.4
1 0 0 0 12.5
1 0 0 1 ≤ VP − 1 (switch)
1 0 1 0 5.0
1 0 1 1 3.3

6 D6
5 D5
4 D4 regulator 3 (mechanical digital) control
0 = regulator 3 off
1 = regulator 3 on
2 D2
1 D1 soft mute all amplifier channels (mute delay 20 ms)
0 = mute off
1 = mute on
0 D0 hard mute all amplifier channels (mute delay 0.4 ms)
0 = mute off
1 = mute on

Table 7. Regulator 4 (mechanical drive) output voltage control

Bit Output (V)
D7 D6 D5
0 0 0 0 (off)
0 0 1 5
0 1 0 6
0 1 1 7
1 0 0 8.6
1 0 1 8.0
Table 8. Regulator 1 (audio) output voltage control

Bit Output (V)
D3 D2
0 0 0 (off)
0 1 8.3
1 0 8.6
1 1 5.0

7 D7 clip detection level
0 = 4 % detection level
1 = 1 % detection level
6 D6 amplifier channels 1 and 2 gain select
0 = 26 dB gain (normal mode)
1 = 20 dB gain (line-driver mode)
5 D5 amplifier channels 3 and 4 gain select
0 = 26 dB gain (normal mode)
1 = 20 dB gain (line-driver mode)
4 D4 amplifier thermal protection pre-warning
0 = warning at 145 °C
1 = warning at 122 °C
3 D3 disable channel 1
0 = enable channel 1
1 = disable channel 1

Table 9. Instruction byte IB3 bit description …continued

Table 10. Instruction byte DB1 bit description

7 D7 amplifier thermal protection pre-warning
0 = no warning
1 = junction temperature above pre-warning level
6 D6 amplifier maximum thermal protection
0 = junction temperature below 175 °C
1 = junction temperature above 175 °C
5 D5 channel 4 DC load detection
0 = DC load detected
1 = no DC load detected
4 D4 channel 4 AC load detection
0 = no AC load detected
1 = AC load detected
3 D3 channel 4 load short-circuit
0 = normal load
1 = short-circuit load
2 D2 channel 4 output offset
0 = no output offset
1 = output offset
1 D1 channel 4 VP short-circuit
0 = no short-circuit to VP
1 = short-circuit to VP
0 D0 channel 4 short-circuit to ground
0 = no short-circuit to ground
1 = short-circuit to ground
Table 11. Data byte DB2 bit description

7 D7 Power-on reset occurred or amplifier status
0 = amplifier on
1 = POR has occurred; amplifier off
6 D6 regulator thermal protection pre-warning
0 = no warning
1 = regulator temperature too high; amplifier off

Table 11. Data byte DB2 bit description …continued

0 = normal load
1 = output offset

7 D7 -
6 D6 -
0 = normal load
1 = output offset


7 D7 -
6 D6 -
4 D4 channel 1 AC load detected
0 = normal load
1 = output offset
1 D1 channel 1 short-circuit to VP
9. Limiting values
Table 14. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VP supply voltage operating - 18 V
not operating −1 +50 V
jump starts for t ≤ 10 - 30 V
minutes
load dump protection for 0 50 V
t ≤ 50 ms and tr ≥ 2.5 ms
VSDA voltage on pin SDA operating 0 7 V
VSCL voltage on pin SCL operating 0 7 V
VI input voltage pins INn, SVR, ACGND, 0 13 V
DIAG, operating
VSTB voltage on pin STB operating 0 24 V
IOSM non-repetitive peak output current - 10 A
IORM repetitive peak output current - 6 A
VP(sc) short-circuit supply voltage across output pin loads - 18 V
and to ground or supply
(AC and DC)

Table 14. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VP(r) reverse supply voltage voltage regulator only - −18 V
Ptot total power dissipation Tcase = 70 °C - 80 W
Tj junction temperature - 150 °C
Tstg storage temperature −55 +150 °C
Tamb ambient temperature −40 +85 °C
Vesd electrostatic discharge voltage [1] - 2000 V
[2] - 200 V
[1] Human body model: Rs = 1.5 kΩ; C = 100 pF; all pins have passed all tests to 2500 V to guarantee 2000 V, according to class II.
[2] Machine model: Rs = 10 Ω; C = 200 pF; L = 0.75 mH; all pins have passed all tests to 250 V to guarantee 200 V, according to class II.
10. Thermal characteristics

Table 15. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction in free air 40 K/W
to ambient
Rth(j-c) thermal resistance from junction see Figure 11 0.75 K/W
to case
Virtual junction
Amplifier Voltage regulator
0.5 K/W 1 K/W
0.2 K/W
Case mdb514
Fig 11. Equivalent thermal resistance network
10.1 Quality specification

In accordance with “General Quality Specification for Integrated Circuits SNW-FQ-611D”.

11. Characteristics
Table 16. Characteristics
Tamb = 25 °C; VDCDC; VP = 14.4 V; RL = 4 Ω; measured in the test circuit Figure 26; unless otherwise specified.
Amplifier section
Supply voltage behavior
VP(oper) operating supply voltage RL = 4 Ω 8 14.4 18 V
RL = 2 Ω 8 14.4 16 V
Iq(tot) total quiescent current no load - 280 400 mA
Istb standby current - 10 50 µA
VO output voltage DC - 7.2 - V
VP(low)(mute) low supply voltage mute 6.5 7 8 V
Vhr headroom voltage when headroom protection is - 1.4 - V
activated; see Figure 4
VPOR power-on reset voltage see Figure 13 - 5.5 - V
VO(offset) output offset voltage mute mode and power on −100 0 +100 mV
Mode select (pin STB)
VSTB voltage on pin STB standby mode - - 1.3 V
operating mode 2.5 - 5.5 V
mute mode 8 - VP V
II input current VSTB = 5 V - 4 25 µA
Start-up, shut-down and mute timing
twake wake-up time from standby before first - 300 500 µs
I2C-bus transmission is
recognized; via pin STB; see
Figure 12
td(mute_off) mute off delay time via I2C-bus (IB1 bit D0); - 250 - ms
CSVR = 22 µF; see Figure 12
td(mute-on) delay time from mute to on soft mute; via I2C-bus 10 25 40 ms
(IB2 bit D1 = 1 to 0)
hard mute; via I2C-bus 10 25 40 ms
(IB2 bit D0 = 1 to 0)
via pin STB; 10 25 40 ms
VSTB = 8 V to 4 V
td(on-mute) delay time from on to mute soft mute; via I2C-bus 10 25 40 ms
(IB2 bit D1 = 0 to 1)
hard mute; via I2C-bus - 0.4 1 ms
(IB2 bit D0 = 0 to 1)
via pin STB; - 0.4 1 ms
VSTB = 4 V to 8 V
I2C-bus interface
VIL LOW-level input voltage on pins SCL and SDA - - 1.5 V
VIH HIGH-level input voltage on pins SCL and SDA 2.3 - 5.5 V
VOL LOW-level output voltage on pin SDA; Iload = 3 mA - - 0.4 V
fSCL SCL clock frequency - - 400 kHz

Table 16. Characteristics …continued

Amplifier diagnostics
VOL(DIAG_N) LOW-level output voltage on pin DIAG fault condition (pin LOW); - - 0.8 V
IDIAG_N = 200 µA
VO(offset) output offset voltage ±1.5 ±2 ±2.5 V
THDclip total harmonic distortion clip detection IB3 bit D7 = 0 - 4 - %
level IB3 bit D7 = 1 - 1 - %
Tj(AV)(pwarn) pre-warning average junction IB3 bit D4 = 0 135 145 155 °C
temperature IB3 bit D4 = 1 112 122 132 °C
Tj(AV)(mute) mute average junction temperature VIN = 0.05 V; −3 dB muting 150 160 170 °C
Tj(AV)(off) average junction temperature for off all outputs switched off 165 175 185 °C
ZL load impedance DC load detected - - 6 Ω
no DC load detected 500 - - Ω
Idet(load) load detection current AC load detected 550 - - mA
no AC load detected - - 150 mA
Amplifier
Po output power RL = 4 Ω; VP = 14.4 V; 20 21 - W
THD = 0.5 %
RL = 4 Ω; VP = 14.4 V; 27 28 - W
THD = 10 %
RL = 2 Ω; VP = 14.4 V; 37 41 - W
THD = 0.5 %
RL = 2 Ω; VP = 14.4 V; 51 55 - W
THD = 10 %
Po(max) maximum output power RL = 4 Ω; VP = 14.4 V; 44 46 - W
VIN = 2 V RMS square wave
RL = 4 Ω; VP = 15.2 V; 49 52 - W
RL = 2 Ω; VP = 14.4 V; 83 87 - W
THD total harmonic distortion Po = 1 W to 12 W; f = 1 kHz; - 0.01 0.1 %
RL = 4 Ω
Po = 1 W to 12 W; f = 10 kHz - 0.2 0.5 %
Po = 4 W; f = 1 kHz - 0.01 0.03 %
line driver mode; - 0.01 0.03 %
Vo = 2 V (RMS); f = 1 kHz;
RL = 600 Ω
αcs channel separation f = 1 Hz to 10 kHz; 50 60 - dB
RS = 600 Ω
Po = 4 W; f = 1 kHz - 80 - dB
SVRR supply voltage rejection ratio f = 100 Hz to 10 kHz; 55 70 - dB
RS = 600 Ω
CMRR common mode rejection ratio amplifier mode; 40 70 - dB
Vcm = 0.3 V (p-p);
f = 1 kHz to 3 kHz; RS = 0 Ω


Vcm(max)(rms) maximum common mode voltage (rms f = 1 kHz - - 0.6 V
value)
Vn(o) output noise voltage filter 20 Hz to 22 kHz;
RS = 600 Ω
line driver mode - 25 35 µV
amplifier mode - 50 70 µV
Gv(amp) voltage gain amplifier mode single-ended in to differential 25 26 27 dB
out
Gv(ld) voltage gain line driver mode single-ended in to differential 19 20 21 dB
out
Zi input impedance Cin = 220 nF 55 70 - kΩ
αmute mute attenuation VO(on)/Vo(mute) 80 90 - dB
Vo(mute) mute output voltage Vi = 1 V (RMS) - 70 - µV
Bp power bandwidth −1 dB; THD = 1 % - 20 - kHz
Voltage regulator section
VP supply voltage regulator 1, 3, 4 and 5 on; 10.0 14.4 18 V
switches 1 and 2 on
standby regulator 2 in 5.0 - 50 V
regulation
standby regulator 6 in 6.0 - 50 V
regulation
Vth(dis) disable threshold voltage regulator 1, 3, 4 and 5 on; 18.1 22 - V
switches 1 and 2 on
VDCDC DC-to-DC converter voltage 4.75 5.0 VP V
Iq(tot) total quiescent current standby mode [1] - 180 250 µA
Regulator 1 (pin REG1) audio supply; IO = 5 mA unless otherwise specified
VO(reg) regulator output voltage 0.5 mA ≤ IO ≤ 400 mA;
10 V < VP < 18 V
IB2[D3:D2] = 01 7.9 8.3 8.7 V
IB2[D3:D2] = 10 8.1 8.6 9.1 V
IB2[D3:D2] = 11 4.75 5.0 5.25 V
SVRR supply voltage rejection ratio fripple = 120 Hz; 50 60 - dB
Vripple = 2 V (p-p)
Vdo dropout voltage VP = 7 V; IB2[D3:D2] = 01 [3]
IO = 300 mA - 0.5 0.8 V

IO = 400 mA - 0.7 1.2 V
IO output current VO ≥ 4 V [4] 400 700 - mA
IOS output short-circuit current RL ≤ 0.5 Ω [5] 100 200 - mA
Line regulation
∆VO output voltage variation 10 V ≤ VP ≤ 18 V - - 50 mV
Load regulation
∆VO output voltage variation 5 mA ≤ IO ≤ 400 mA - - 100 mV


Regulator 2 (pin REG2) microprocessor supply; IO = 5 mA unless otherwise specified
VO(reg) regulator output voltage 0.5 mA ≤ IO ≤ 350 mA; 3.1 3.3 3.5 V
10 V ≤ VP ≤ 18 V
Vripple = 2 V (p-p)
Vdo dropout voltage VBUCAP = 4.75 V [6][8]
IO = 350 mA - 1.45 2.0 V

IO output current VO ≥ 2.8 V [4] 350 1000 - mA
Line regulation
∆VO output voltage variation 10 V ≤ VP ≤ 18 V - 3 50 mV
Load regulation
∆VO output voltage variation 0.5 mA ≤ IO ≤ 350 mA - - 100 mV
Regulator 3 (pin REG3) mechanical digital supply; IO = 5 mA unless otherwise specified
VO(reg) regulator output voltage 10 V ≤ VP ≤ 18 V; 3.1 3.3 3.5 V
0.5 mA ≤ IO ≤ 500 mA;
5 V ≤ VDCDC ≤ 18 V
Vripple = 2 V (p-p)
Vdo dropout voltage VDCDC = 4.75 V; IO = 500 mA [2][8] - 1.45 2.0 V
Line regulation
∆VO output voltage variation 5 V ≤ VDCDC ≤ 18 V - 3 50 mV
Load regulation
Regulator 4 (pin REG4) mechanical drive supply; IO = 5 mA unless otherwise specified
VO(reg) regulator output voltage 10 V ≤ VP ≤ 18 V;
0.5 mA ≤ IO ≤ 800 mA
IB2[D7:D5] = 001 4.75 5.0 5.25 V
IB2[D7:D5] = 010 5.7 6.0 6.3 V
IB2[D7:D5] = 011 6.6 7.0 7.4 V
IB2[D7:D5] = 100 8.1 8.6 9.1 V
IB2[D7:D5] = 101 7.6 8.0 8.4 V
Vripple = 2 V (p-p)
IO = 500 mA - 0.5 0.8 V

IO = 800 mA - 0.7 1.2 V
IOM peak output current T ≤ 3 s; VO = 4 V 1 1.5 - A
IO output current VO ≥ 4 V; T ≤ 100 ms; [4] 1.5 2 - A
VP ≥ 11.5 V


Line regulation
Load regulation
Regulator 5 (pin REG5) display supply; IO = 5 mA unless otherwise specified
VO(reg) regulator output voltage 0.5 mA ≤ IO ≤ 400 mA
10 V ≤ VP ≤ 18 V; 5.7 6.0 6.3 V
IB1[D7:D4] = 0001
10 V ≤ VP ≤ 18 V; 6.65 7.0 7.37 V
IB1[D7:D4] = 0010
10 V ≤ VP ≤ 18 V; 7.8 8.2 8.6 V
IB1[D7:D4] = 0011
10.5 V ≤ VP ≤ 18 V; 8.55 9.0 9.45 V
IB1[D7:D4] = 0100
11 V ≤ VP ≤ 18 V; 9.0 9.5 10.0 V
IB1[D7:D4] = 0101
11.5 V ≤ VP ≤ 18 V; 9.5 10.0 10.5 V
IB1[D7:D4] = 0110
13 V ≤ VP ≤ 18 V; 9.9 10.4 10.9 V
IB1[D7:D4] = 0111
14.2 V ≤ VP ≤ 18 V; 11.8 12.5 13.2 V
IB1[D7:D4] = 1000
12.5 V ≤ VP ≤ 18 V; VP − 1 VP − 0.5 - V
IB1[D7:D4] = 1001
10 V ≤ VP ≤ 18 V; 4.75 5.0 5.25 V
IB1[D7:D4] = 1010
10 V ≤ VP ≤ 18 V; 3.1 3.3 3.5 V
IB1[D7:D4] = 1011
Vripple = 2 V (p-p)
IO = 300 mA - 0.5 0.8 V

IO = 400 mA - 0.7 1.2 V
Line regulation
Load regulation
Regulator 6 (pin REG6) bus control supply; IO = 5 mA unless otherwise specified
VO(reg) regulator output voltage 0.5 mA ≤ IO ≤ 100 mA; 4.75 5.0 5.25 V
10 V ≤ VP ≤ 18 V


Vripple = 2 V (p-p)
Vdo dropout voltage VP = 4.75 V; IO = 100 mA [3] - 0.4 0.8 V
IO output current VO > 4.0 V [4] 150 350 - mA
IOS output short-circuit current RL < 0.5 Ω [5] 50 125 - mA
Line regulation
Load regulation
Power switch 1 (pin SW1) antenna
Vdo dropout voltage IO = 300 mA - 0.6 0.8 V
IO = 400 mA - 0.6 1.1 V
IO output current VO ≥ 8.5 V [4] 0.5 1 - A
IOS output short-circuit current RL ≤ 0.5 Ω [5] - 250 - mA
IL leakage current VO = 18 V; VP = 0 V [7] - 25 250 µA
Power switch 2 (pin SW2) amplifier
Vdo dropout voltage IO = 300 mA - 0.6 0.8 V
IO = 400 mA - 0.6 1.1 V
IO output current VO ≥ 8.5 V [4] 0.5 1 - A
IOS output short-circuit current RL ≤ 0.5 Ω [5] - 250 - mA
IL leakage current VO = 18 V; VP = 0 V [7] - 25 250 µA
Backup switch
Ibu backup current (DC) VBUCAP ≥ 6 V 0.4 1.5 - A
VCL clamping voltage VP = 30 V; IO(reg2) = 100 mA - 24 28 V
Vdo dropout voltage IO = 500 mA; (VP − VBUCAP) - 0.8 1.2 V
[1] The quiescent current is measured in standby mode when RL = ∞.

[2] The dropout voltage of regulator 3 is the voltage difference between VDCDC and VO(reg).
[3] The dropout voltage of a regulator is the voltage difference between VP and VO(reg).
[4] At current limit, VO(reg) is held constant; see Figure 6.
[5] The foldback current protection limits the dissipation power at short-circuit; see Figure 6.
[6] The dropout voltage of regulator 2 is the voltage difference between VBUCAP and VO(reg).
[7] Unbiased switch-supply IL is measured in supply line VP.
[8] Regulator output still in regulation at applied test voltage, therefore the actual dropout voltage can not be measured.

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Objective data sheet
TDF8553J_1
NXP Semiconductors
VP
DIAG
VREG3
Regulator switched off

Amplifier status when amplifier is
DB2 bit D7 completely muted
IB1 bit D0
IB2 bit D4
twake
Rev. 01 — 3 December 2008
STB

SVR
td(mute-off)
Soft
mute
Amplifier Soft
output mute
001aai697
Fig 12. Start-up and shut-down timing
TDF8553J
© NXP B.V. 2008. All rights reserved.
29 of 47
VO Headroom protection activated:

(V) 1) fast mute
VP
2) discharge of SVR
14.4
Low VP mute activated
8.8
Output
Headroom voltage voltage
8.6
7.2
Low VP mute released
SVR voltage
3.5
DIAG
DB2 bit D7
VREG3
001aai694
Fig 13. Low supply voltage behavior at VP > 5.5 V

VO
(V)
VP
Low VP mute activated
14.4
POR activated
8.8
8.6
7.2
5.5
3.5
SVR voltage
DIAG
DB2 bit D7 POR has occurred
VREG3
001aai695
Fig 14. Low supply voltage behavior at VP < 5.5 V

mrc345
102
THD
(%)
10
(1)
10−1
10−2 (2)
(3)
10−3
10−2 10−1 1 10 102
Po (W)
(1) f = 10 kHz.
(2) f = 1 kHz.
(3) f = 100 Hz.
VP = 14.4 V.
RL = 4 Ω.
Fig 15. Total harmonic distortion as a function of output power
mrc344
10
THD
(%)
10−1
10−2 (1)
(2)
10−3
10−2 10−1 1 10 102
f (kHz)
(1) Po = 1 W.
(2) Po = 10 W.
VP = 14.4 V.
RL = 4 Ω.
Fig 16. Total harmonic distortion as a function of frequency

mrc329
1
THD
(%)
10−1
10−2
10−3
10-1 1 10 102
Vo (rms)
VP = 14.4 V.
RL = 600 Ω.
f = 1 kHz.
Fig 17. Total harmonic distortion as a function of output voltage in balanced line driver
mode
mrc330
30
Po (1)
(W)
28
26
(2)
24
22
(3)
20
10−2 10−1 1 10 102
f (kHz)
(1) THD = 10 %.
(2) THD = 5 %.
(3) THD = 0.5 %.
VP = 14.4 V.
Fig 18. Output power as a function of frequency; RL = 4 Ω

mrc335
60
Po
(W)
(1)
55
(2)
50
45
(3)
40
35
10−2 10−1 1 10 102
f (kHz)
(1) THD = 10 %.
(2) THD = 5 %.
(3) THD = 0.5 %.
VP = 14.4 V.
Fig 19. Output power as a function of frequency; RL = 2 Ω
001aaa283
100
Po
(W)
80
60
(1)
40
(2)
(3)
20
0
8 10 12 14 16 18 20
VP (V)
(1) Maximum power.

(2) THD = 10 %.
(3) THD = 0.5 %.
f = 1 kHz.
Fig 20. Output power as a function of supply voltage; RL = 4 Ω

001aai696
100
Po
(W)
80
(1)
60
(2)
40
(3)
20
0
8 10 12 14 16 18 20
VP (V)
(1) Maximum power.

(2) THD = 10 %.
(3) THD = 0.5 %.
f = 1 kHz.
Fig 21. Output power as a function of supply voltage; RL = 2 Ω
mrc333
80
SVRR
(dB)
76
72
(1)
68
(2)
64
60
10−1 1 10
f (kHz)
(1) Operating mode.

(2) Mute mode.
VP = 14.4 V.
RL = 4 Ω.
Vripple = 2 V (p-p).
RS = 600 Ω.
Fig 22. Supply voltage rejection ratio as a function of frequency

mrc351
100
αcs
(dB)
90
80
70
60
50
10−2 10−1 1 10 102
f (kHz)
VP = 14.4 V.
RL = 4 Ω.
Po = 4 W.
RS = 600 Ω.
Fig 23. Channel separation
mrc342
50
Ptot
(W)
40
30
20
10
0
0 10 20 30
Po (W)
VP = 14.4 V.
RL = 4 Ω.
f = 1 kHz.
Fig 24. Amplifier power dissipation as a function of output power; all channels driven

mrc343
100
η
(%)
80
60
40
20
0
0 8 16 24 32 40
Po (W)
VP = 14.4 V.
RL = 4 Ω.
f = 1 kHz.
Fig 25. Amplifier efficiency as a function of output power; all channels driven

12. Application information
28 REG6
REGULATOR 6 bus controller
10 µF 100 nF
(50 V)
BUCAP 37 REG2
REGULATOR 2 microcontroller
1000 µF 36 10 µF
220 nF 100 nF
(16 V) (50 V)
TEMPERATURE &
BACKUP REFERENCE LOAD DUMP
SWITCH VOLTAGE PROTECTION VOLTAGE
REGULATOR
VP 35
14.4 V REGULATOR 1 30 REG1
audio
220 µF 220 nF 10 µF
(16 V) 100 nF
(50 V)
VDCDC REGULATOR 3 31 REG3 mechanical

26 digital
14.4 V/5 V
10 µF
(1) 100 nF
(50 V)
REGULATOR 4 33 REG4 mechanical

ENABLE drive
LOGIC 10 µF
100 nF
(50 V)
REGULATOR 5 34 REG5
display
10 µF
100 nF
(50 V)
SWITCH 1
29 SW1
amplifiers
10 µF
100 nF
(50 V)
SWITCH 2
27 SW2 aerial
motor
10 µF
100 nF
(50 V)
32 GND
20 VP1
2 14.4 V
SDA TDF8553J 6 VP2
4
SCL 25 DIAG 10 kΩ
STB
22
STANDBY/ MUTE I2C-BUS
CLIP DETECT/ DIAGNOSTIC 220 (1) 220 2200 µF
INTERFACE
nF nF (16 V)
microcontroller
RS 9 OUT1+
IN1 11 MUTE
26 dB/
470 nF 20 dB 7 OUT1−
PROTECTION/
DIAGNOSTIC
RS 17 OUT2+
IN2 15 MUTE
26 dB/
470 nF 20 dB 19 OUT2−
PROTECTION/
DIAGNOSTIC
RS 5 OUT3+
IN3 12 MUTE
26 dB/
470 nF 20 dB 3 OUT3−
PROTECTION/
DIAGNOSTIC
RS 21 OUT4+
IN4 14 MUTE
26 dB/
470 nF 20 dB 23 OUT4−
VP
PROTECTION/
DIAGNOSTIC
TEMPERATURE & LOAD

DUMP PROTECTION
AMPLIFIER
10 13 16 8 1 18 24
SVR SGND ACGND PGND1 PGND2/TAB PGND3 PGND4
2.2 µF
22 µF
(4 × 470 nF)
coa071
(1) See Section 12.1.

The value of ACGND capacitor must be close to 4 × the value of capacitor connected to the positive input of each channel; for
EMC reasons a 10 nF capacitor can be connected between each amplifier output and ground.
Fig 26. Test and application diagram of TDF8553J

12.1 Supply decoupling

See Figure 26.
The high frequency 220 nF decoupling capacitors connected to power supply voltage
pins 6 and 20 should be located as close as possible to these pins.
It is important to use good quality capacitors. These capacitors should be able to

suppress high voltage peaks that can occur on the power supply if several audio channels
are accidentally shorted to the power supply simultaneously, due to the activation of
current protection. Good results have been achieved using 0805 case-size capacitors
(X7R material, 220 nF) located close to power supply voltage pins 6 and 20.
If a DC-to-DC converter is used to supply regulator 3, the recommendations of the

converter manufacturer relating to decoupling must be followed.
001aai763
Fig 27. Printed-circuit board layout of test and application circuit showing top copper layer viewed from top

001aai762
Fig 28. Printed-circuit board layout of test and application circuit showing bottom copper layer viewed from top
001aai764
Fig 29. Printed-circuit board layout of test and application circuit showing components and top copper layout
viewed from top

001aai765
Fig 30. Printed-circuit board layout of test and application circuit showing bottom copper layout and bottom
components viewed from bottom
12.2 Beep input circuit

Beep input circuit to amplify the beep signal from the microcontroller to all 4 amplifiers
(gain = 0 dB). Note that this circuit will not affect amplifier performance.
TDF8553J
ACGND
2.2 µF
1.7 kΩ 0.22 µF
From
microcontroller
100 Ω 47 pF
001aai677
Fig 31. Application diagram for beep input
12.3 Noise
The outputs of regulators 1 to 6 are designed to give very low noise with good stability.
The noise output voltage depends on output capacitor Co. Table 17 shows the affect of the
output capacitor on the noise figure.

Table 17. Regulator noise figures

Regulator Noise figure (µV) [1]
Co = 10 µF Co = 47 µF Co = 100 µF
1 225 180 145
2 700 600 390
3 100 85 65
4 235 205 175
5 315 285 225
6 710 550 340
[1] Measured in the frequency range 20 Hz to 80 kHz; at IO(reg) = 10 mA
12.4 Stability
The regulators are made stable by connecting capacitors to the regulator outputs. The
stability can be guaranteed with almost any output capacitor if its Electric Series
Resistance (ESR) stays below the ESR curve shown in Figure 32. If an electrolytic
capacitor is used, its behavior with temperature can cause oscillations at extremely low
temperature. Oscillation problems can be avoided by adding a 47 nF capacitor in parallel
with the electrolytic capacitor. The following example describes how to select the value of
output capacitor.
12.4.1 Example regulator 2

Regulator 2 is stabilized with an electrolytic output capacitor of 10 µF which has an ESR
of 4 Ω. At Tamb = −30 °C the capacitor value decreases to 3 µF and its ESR increases to
28 Ω which is above the maximum allowed as shown in Figure 32, and which will make
the regulator unstable. To avoid problems with stability at low temperatures, the
recommended solution is to use tantalum capacitors. Either use a tantalum capacitor of
10 µF, or an electrolytic capacitor with a higher value.
20
ESR
(Ω)
15
maximum ESR
10
5 stable region
0
0.1 1 10 100 mgl912
C (µF)
Fig 32. Curve for selecting the value of output capacitors for regulators 1 to 6

13. Package outline
DBS37P: plastic DIL-bent-SIL power package; 37 leads (lead length 6.8 mm) SOT725-1
non-concave
x Dh
Eh
view B: mounting base side
d A2
j E
A
L4
L3
L
L2
1 37
Z e1 w M
bp Q c v M
e e2
m
0 10 20 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A A2 bp c D(1) d Dh E(1) e e1 e2 Eh j L L2 L3 L4 m Q v w x Z(1)
4.65 0.60 0.5 42.2 37.8 15.9 8 3.4 3.9 1.15 22.9 2.1 3.30
mm 19 12 2 1 4 6.8 4 0.6 0.25 0.03
4.35 0.45 0.3 41.7 37.4 15.5 3.1 3.1 0.85 22.1 1.8 2.65
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
01-11-14
SOT725-1 --- --- ---
02-11-22
Fig 33. Package outline SOT725-1 (DBS37P)


14. Soldering of through-hole mount packages
14.1 Introduction to soldering through-hole mount packages

This text gives a very brief insight into wave, dip and manual soldering.
Wave soldering is the preferred method for mounting of through-hole mount IC packages
on a printed-circuit board.
14.2 Soldering by dipping or by solder wave

Driven by legislation and environmental forces the worldwide use of lead-free solder
pastes is increasing. Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb
or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic
body must not exceed the specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.
14.3 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is
less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is
between 300 °C and 400 °C, contact may be up to 5 seconds.
14.4 Package related soldering information

Table 18. Suitability of through-hole mount IC packages for dipping and wave soldering
Package Soldering method
Dipping Wave
CPGA, HCPGA - suitable
DBS, DIP, HDIP, RDBS, SDIP, SIL suitable suitable[1]
PMFP[2] - not suitable
[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit
board.
[2] For PMFP packages hot bar soldering or manual soldering is suitable.

15. Abbreviations
Table 19. Abbreviations
Acronym Description
BCDMOS Bipolar CMOS DMOS MOS
CMOS Complementary Metal-Oxide Semiconductor
DMOS Double-Diffused Metal-Oxide Semiconductor
EMC ElectroMagnetic Compatibility
MOS Metal-Oxide Semiconductor
POR Power-On Reset
16. Revision history

Table 20. Revision history
Document ID Release date Data sheet status Change notice Supersedes
TDF8553J_1 20081203 Objective data sheet - -

17. Legal information
17.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in Applications — Applications that are described herein for any of these
modifications or additions. NXP Semiconductors does not give any products are for illustrative purposes only. NXP Semiconductors makes no
representations or warranties as to the accuracy or completeness of representation or warranty that such applications will be suitable for the
information included herein and shall have no liability for the consequences of specified use without further testing or modification.
use of such information. Limiting values — Stress above one or more limiting values (as defined in
Short data sheet — A short data sheet is an extract from a full data sheet the Absolute Maximum Ratings System of IEC 60134) may cause permanent
with the same product type number(s) and title. A short data sheet is intended damage to the device. Limiting values are stress ratings only and operation of
for quick reference only and should not be relied upon to contain detailed and the device at these or any other conditions above those given in the
full information. For detailed and full information see the relevant full data Characteristics sections of this document is not implied. Exposure to limiting
sheet, which is available on request via the local NXP Semiconductors sales values for extended periods may affect device reliability.
office. In case of any inconsistency or conflict with the short data sheet, the Terms and conditions of sale — NXP Semiconductors products are sold
full data sheet shall prevail. subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
17.3 Disclaimers explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
General — Information in this document is believed to be accurate and terms and conditions, the latter will prevail.
reliable. However, NXP Semiconductors does not give any representations or
No offer to sell or license — Nothing in this document may be interpreted
warranties, expressed or implied, as to the accuracy or completeness of such
or construed as an offer to sell products that is open for acceptance or the
information and shall have no liability for the consequences of use of such
grant, conveyance or implication of any license under any copyrights, patents
information.
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
Quick reference data — The Quick reference data is an extract of the
changes to information published in this document, including without
product data given in the Limiting values and Characteristics sections of this
limitation specifications and product descriptions, at any time and without
document, and as such is not complete, exhaustive or legally binding.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed, 17.4 Trademarks
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or Notice: All referenced brands, product names, service names and trademarks
malfunction of an NXP Semiconductors product can reasonably be expected are the property of their respective owners.
to result in personal injury, death or severe property or environmental I2C-bus — logo is a trademark of NXP B.V.
18. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]

19. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 12.4.1 Example regulator 2 . . . . . . . . . . . . . . . . . . . . 42
1.1 Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 43
1.2 Voltage regulators. . . . . . . . . . . . . . . . . . . . . . . 1 14 Soldering of through-hole mount packages . 44
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 14.1 Introduction to soldering through-hole mount
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 14.2 Soldering by dipping or by solder wave . . . . . 44
5 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 14.3 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 44
14.4 Package related soldering information . . . . . . 44
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 45
7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6
16 Revision history . . . . . . . . . . . . . . . . . . . . . . . 45
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 17 Legal information . . . . . . . . . . . . . . . . . . . . . . 46
8 Functional description . . . . . . . . . . . . . . . . . . . 8 17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 46
17.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.1 Start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2 Start-up and shut-down timing . . . . . . . . . . . . . 8
17.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.3 Power-on reset and supply voltage spikes . . . . 8
8.4 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . 8 18 Contact information . . . . . . . . . . . . . . . . . . . . 46
8.5 Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.5.1 Muting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
8.5.2 Temperature protection. . . . . . . . . . . . . . . . . . . 9
8.5.3 Offset detection. . . . . . . . . . . . . . . . . . . . . . . . . 9
8.5.4 Speaker protection . . . . . . . . . . . . . . . . . . . . . . 9
8.5.5 Line driver mode . . . . . . . . . . . . . . . . . . . . . . . . 9
8.5.6 Input and AC ground capacitor values . . . . . . 10
8.5.7 Load detection . . . . . . . . . . . . . . . . . . . . . . . . 10
8.5.7.1 DC-load detection . . . . . . . . . . . . . . . . . . . . . . 10
8.5.7.2 AC-load detection . . . . . . . . . . . . . . . . . . . . . . 10
8.5.7.3 Load detection procedure . . . . . . . . . . . . . . . . 11
8.5.8 Low headroom protection . . . . . . . . . . . . . . . . 11
8.6 Voltage regulators. . . . . . . . . . . . . . . . . . . . . . 12
8.6.1 Standby regulator outputs. . . . . . . . . . . . . . . . 12
8.6.2 Backup capacitor . . . . . . . . . . . . . . . . . . . . . . 12
8.6.3 Backup function . . . . . . . . . . . . . . . . . . . . . . . 13
8.6.4 Power switches . . . . . . . . . . . . . . . . . . . . . . . . 13
8.6.5 External DC-to-DC converter . . . . . . . . . . . . . 14
8.6.6 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.6.7 Temperature protection. . . . . . . . . . . . . . . . . . 14
8.7 I2C-bus specification . . . . . . . . . . . . . . . . . . . . 14
9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 21
10 Thermal characteristics. . . . . . . . . . . . . . . . . . 22
10.1 Quality specification . . . . . . . . . . . . . . . . . . . . 22
11 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 23
12 Application information. . . . . . . . . . . . . . . . . . 38
12.1 Supply decoupling . . . . . . . . . . . . . . . . . . . . . 39
12.2 Beep input circuit . . . . . . . . . . . . . . . . . . . . . . 41
12.3 Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12.4 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 3 December 2008
Document identifier: TDF8553J_1

TDF8553J: 1. General Description

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TDF8553J

I2C-bus controlled 4 × 50 Watt power amplifier and multiple

1.2 Voltage regulators

The voltage regulator contains the following:

• Four switchable regulators and two standby regulators

4. Quick reference data

TDF8553J_1 © NXP B.V. 2008. All rights reserved.

Objective data sheet Rev. 01 — 3 December 2008 2 of 47

Table 1. Quick reference data …continued

TDF8553J_1 © NXP B.V. 2008. All rights reserved.

Objective data sheet Rev. 01 — 3 December 2008 3 of 47

TDF8553J_1 © NXP B.V. 2008. All rights reserved.

Objective data sheet Rev. 01 — 3 December 2008 4 of 47

TEMPERATURE & LOAD

SVR SGND PGND1 PGND3 coa070

Fig 1. Block diagram

TDF8553J_1 © NXP B.V. 2008. All rights reserved.

Objective data sheet Rev. 01 — 3 December 2008 5 of 47

Fig 2. Pin configuration

TDF8553J_1 © NXP B.V. 2008. All rights reserved.

Objective data sheet Rev. 01 — 3 December 2008 6 of 47

7.2 Pin description

TDF8553J_1 © NXP B.V. 2008. All rights reserved.

Objective data sheet Rev. 01 — 3 December 2008 7 of 47

8.2 Start-up and shut-down timing

8.3 Power-on reset and supply voltage spikes

8.4 Diagnostic output

TDF8553J_1 © NXP B.V. 2008. All rights reserved.

Objective data sheet Rev. 01 — 3 December 2008 8 of 47

8.5.2 Temperature protection

8.5.3 Offset detection

8.5.4 Speaker protection

8.5.5 Line driver mode

TDF8553J_1 © NXP B.V. 2008. All rights reserved.

Objective data sheet Rev. 01 — 3 December 2008 9 of 47

8.5.6 Input and AC ground capacitor values

8.5.7 Load detection

8.5.7.1 DC-load detection

8.5.7.2 AC-load detection

TDF8553J_1 © NXP B.V. 2008. All rights reserved.

Objective data sheet Rev. 01 — 3 December 2008 10 of 47

no load present (1)

(1) IoM = < 150 mA.

8.5.7.3 Load detection procedure

1. At start-up, enable the AC or DC-load detection by setting D1 of instruction byte IB1 to

8.5.8 Low headroom protection

TDF8553J_1 © NXP B.V. 2008. All rights reserved.

Objective data sheet Rev. 01 — 3 December 2008 11 of 47

Fig 4. Amplifier output during supply voltage drop

8.6 Voltage regulators

• Four switchable regulators and two standby regulators

8.6.1 Standby regulator outputs

8.6.2 Backup capacitor

TDF8553J_1 © NXP B.V. 2008. All rights reserved.

Objective data sheet Rev. 01 — 3 December 2008 12 of 47

8.6.3 Backup function

When an overvoltage condition occurs, the voltage on pin BUCAP is limited to

Fig 5. Backup capacitor function

8.6.4 Power switches