Lecture # 01 Dr. Rehan Hafiz <[email protected].

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 Course Website for ADSD Fall 2009
2

MOODLE
&
http://sites.google.com/site/ADSDFall2009/

Lectures: Tuesday @ 5:30-6:20 pm, Thursday @ 5:30-7:20 pm

Contact: By appointment/Email, Office:218-Faculty Block

Research opportunities

Ongoing Projects

Introduction
 Introduction - Mine
4

Expertise

Digital system design for complex algorithms

Optical Tomography, Computer Vision & Image Processing

Activities

Group Director : Vision Imaging & Signal Processing Research
Group (VISPRO)

Co-author & Team lead in a 36 Million ICT R&D:
 Design and Verification of Low-Power, High-Speed IP Suite for
Universal Serial Bus (USB 3.0)

PhD, The University of Manchester: Reconfigurable
signal processing techniques for optical tomography
 Research Opportunities
VISpro
VISpro
Vision Image & Signal Processing Research Group
5

System Design Research Group

Multi-View Imaging (MVI)

Digital Image Calibration For Multi-Projector
System (DICMS)

Object tracking – (Reconfigurable SIFT)
 & FPGA Implementations of these

Orange Tree
Solution
Research Opportunities
VISpro
VISpro -- Multi-View Imaging (MVI)

MVI: Videos acquired from multiple video sources

Enormous video data Enormous information 
Enormous applications

Multimedia/ Surveillance/ Inspection

Immersive Multimedia Applications

Sports/ Cricket Match

Video Conferencing

Research Theme Camera-1 Camera-2

Real Time Panoramic View Generation

I(x,y
I( x,y)
x,y) I`(x,y
I`(x,y)
x,y)

Real Time View Point Generation T(x,y
T(x,y)
x,y)
Overlapping
region
 Research Opportunities
USB-
USB-3.0
Design of low power USB host & device controller
7

Design of low power USB host & device controller

USB 3.0 “4.8 Gb/s” as compared to 480 Mb/s

SEECS & Whizz Silicon (Silicon Valley, USA)

Research Theme

Low Power System Design for FPGAs

& also, Reconfigurable processors
 Introduction-Aims
8

Name

Area of interest

Where u see yourself
in future

Industry ?

Academia ?

Research ?

Development ?

Any where else ?

What you expect to learn ?

ADSD Fall 2009
Course Outline
 Textbook
10

(Cil.) Advanced Digital Design

with the Verilog HDL, M D.
Ciletti

(Stv) Advanced FPGA Design,
Steve Kilts
 Reference Books
11

Verilog HDL, Samir Palnitkar

Synthesis of Arithmetic Circuits
 ADSD-Fall-2009 ---- Course outline
12

Introduction
Architectures for Arithmetic

Digital design methodology (Cil.) Processors (Cil.)

Initial Assessment of students
Adders, Multipliers, Dividers

Combinational & Sequential Logic
Coordinate Rotation Digital Computer
(CORDIC Algorithm)
(Cil.)

Common structures
Reconfigurable Processors

HDL review
Advanced FPGA Design Concepts

Synthesis (Stv.)

Design & Synthesis of Datapath
Architecting Speed
controllers (Cil.)
Architecting Area

Architecting Power

Micro-Architecture

Clock Domains

Pipelined & Timeshared
Reset Circuits
Architectures
Coding for synthesis

Fixed point & Floating point
Synthesis Optimization
Arithmetic
Timing Analysis
 Distribution
13

Quizzes 10%

Assignment 10%

Research Project-I 5%

Research Project-II 5%

Mid 30%

Final 40%
14

Class Ethics
 Class Ethics &.. Other stuff
15

Attendance

Respect for all & classroom discipline

Quizzes

Anytime

“Never cheat”

Better fail NOW or else will fail somewhere LATER in life

Hard work “always” pays….

Assignments

References (IEEE Indexing [1],[2],…)

Plagiarism

No copying
 PLAGIARISM

Adapted from What is Plagiarism PowerPoint

16 http://mciu.org/~spjvweb/plagiarism.ppt
17
Questions….
19

Assessment
Status quo – Where we stand?
 Short Quiz
1 You are familiar with VHDL or Verilog ?
2 Have you done fixed point arithmetic for FPGA?
3 Have you ever implemented a register file or a RAM using HDL ?

4 Are you familiar with truncating/rounding errors associated with fixed point
arithmetic ?
5 Are you familiar with Multiplier for Fixed Point Arithmetic ?

6 Have you studied Time Shared Architectures?

7 Have you ever implemented a pipelined Architectures?
8 Have you studied Wallace Trees
9 Have you studied CORDIC
10 Have you studied datapath & control part partitioning?

11 Have you ever designed a micro architecture?

12 Are you familiar with coding techniques that result in a low power FPGA based
system design?
13 Have you studied Optimizing Speed of a Digital System

14 Have you studied Optimizing Area of a Digital System

15 Have you studied Handling different Clock Domains

Lecture # 01 Dr. Rehan Hafiz <[email protected]>
 Digital Design Methodology
22

From concept to reality

A long tiring process
 Design Methodology: Big Picture
MRDMarketing Arch.Spec. Design
Requirement (Macro Specification DesignPartition
23
Document Architecture) MicroArchitecture

Design DesignEntry
Functional
Integration& Simulation
Verification HDL
Verification

Synthesize& Post synthesis Test Generation

Presynthesis
Map Gate-Level Design & Fault
Sign-Off
Netlist Verification Generation

VerifyPhysical& ClockTrees
DesignSign-Off Extract Parasitic ElectricalDesign
Rules Cell Routing
 Design Methodology
Marketing Requirement Architecture Specification
Document (MRD) Macro Architecture

A list of desirable features
Architecture at a very high and
abstract level

Studies

Usually a transaction level

Customer’s expectations
model (TLM)

Competing Products

Defines communicating

Add-ons
processes

Market opportunities

Events may not be defined

Time to market

Projects revenue estimates

Profit Margins

Evaluation
 Sample
Architecture
25
Architectural Spec : Another Example….
 Design Methodology
Design Specification or
Design Partition
Micro Architecture

Written statement of
FUs defined by their
functionality, timing, area, behavior
power, testability, fault
coverage, etc.
Interacting functional units

Functional specification
Control vs. datapath
methods: separation

State Transition Graphs
Interconnection structures

Timing Charts within datapath

Algorithm State Machines (like
Top-down design method
flowcharts)

Exploiting hierarchy

Design Reuse
 Design Methodology
Simulation and Functional
Design Entry/ HDL
28
Verification

HDL
Simulation vs. Formal

Higher productivity than Methods
schematic based gate level
implementation
Test Plan Development

Easier to Debug, Modify & Update
What to test & how ?

De-burdens gate level
E.g: Instruction set for a range of
optimizations data

Allows this stage to be technology
independent (e.g., FPGA LUTs or

Testbench Development
ASIC standard cell libraries)
Testing of independent modules

Behavioral descriptions
Test Execution and Model
Verification

Meets Specification ?
 Design Methodology
Design Integration and
Pre synthesis sign-off
Verification
29

Integrate
Full functionality

Demonstrated

Bugs lurking in the

Make sure that the behavior
interface behavior specification meets the
among modules design specification

The Testbench

I/O interfacing with top
level module

Monitor port & bus
activity across module
bounderies
 Design Methodology
Gate-Level Synthesis and Post-synthesis Design
Technology Mapping
30
Validation

Synthesize the design from
Comparing Synthesized gate-
the behavior description level description to the

Optimized Boolean verified behavioral model
description

Map onto target technology
A testbench that instantiates
both models & drive them via

Optimizations
common stimulus

Minimize logic

Reduce area

Reduce power

Balance speed vs. other
resources consumed

Produces netlist of standard
cells or database to configure
target FPGA
 Design Methodology
Post synthesis Timing
ASIC Specific
Verification
31

Are the timing
Test Generation and Fault

specifications met? Simulation

Are the speeds adequate
Placement and Routing
on the critical paths?
Clock distribution trees to
minimize skew

Re-synthesis may be

Physical and Electrical
required to achieve Design Rule Check
timing goals

Determining Parastics

Resize transistors

Extract geometric

Modify architecture
information

Choose a different target
device or technology
Questions….