Deep dive in foundry process

design kits (PDKs)

Amit Kumar (Principal Hardware Engineer)
Microsoft, Mountain View, CA

James Bae (Sr. Manager)

Intel, Austin, TX
Abstract
A Process Design Kit (PDK) serves as the fundamental building block for integrated circuit (IC) design, playing a crucial role in transforming chip designs
into silicon reality. In this exploration, we delve into the intricate world of PDKs, examining their development, quality assurance processes, and
multifaceted applications.

PDK Overview: A PDK encompasses a collection of files that meticulously describe the specifics of a semiconductor process. These files serve as essential
inputs for Electronic Design Automation (EDA) tools during chip design. Clients engage with a foundry's PDKs before production to ensure that their chip
designs align with the foundry's capabilities and intended functionality.

PDK Components and Usage: We dissect each part of the PDK and explore its role in IC design. From technology files defining design rules to
parameterized cells (PCells) customizing transistors, PDKs provide critical guidance. PDKs act as the vital link between design and fabrication, enabling
seamless communication between designers and foundries.

Semiconductor Process Variations: We investigate different semiconductor processes such as FinFET, SOI, GAA/Back metal, and Silicon photonics. Each
process has unique requirements, and PDKs tailor their contents accordingly. The respective PDKs support these technologies by providing essential
information for successful chip fabrication.

EDA Tool Ecosystem and PDK Integration: We briefly explore the EDA tool landscape, discussing tools used at various design stages. These tools rely on
accurate PDK data to generate layouts, verify designs, and simulate performance. Standardized interfaces across diverse technology platforms enhance
PDK usability.

Effective PDK Utilization: Tips and tricks for maximizing PDK features and utilities are shared. Designers can leverage these insights to streamline their
workflows and achieve optimal results. Case Studies and Impact: We delve into real-world case studies, examining how new devices and metal stack
enablement influence different PDK components. By understanding these impacts, designers can make informed decisions during the design process.
About Speakers
Amit Kumar (Principal Hardware Engineer, Microsoft)
• 21+ Years in the field of PDK development & qualification, CAD & design methodology, Physical Design, Physical
Verification and flow development, automation, people management, and program/project management.
• Mainly focus on 3DIC methodologies, Physical Verification, CAD flows and Reliability analysis (ESD & EMIR).
• Certified ISO 26262 – Automotive – Functional Safety Engineer and Senior Member of IEEE & Member of IEEE
standards association.
• Published 15+ paper/presentation at leading conference and university.
• Previously worked at GlobalFoundries, Xilinx, and Synopsys(Virage Logic)

James Bae (Senior Engineering Manager, Intel)

• James Bae has 20+ years of Design Engineering, Design methodologies, Customer Engagement, Business
Engagement and Engineering Resource Management His expertise are in building best in class templates libraries,
extraction, simulation methodologies as a part of Design Enablement. James recently led the team of 20+ engineers
to enable industry 1st electromagnetic solutions including 1st Intel 18A power via and GAA structure.
• James is actively engaging in conferences/EDA/SRC as ongoing presenter/contributor/reviewer and published 10+
technical papers/presentations. He also worked as Principal Member of Technical Staff at GLOBALFOUNDRIES, to
grow GlobalFoundries Corporate AE team focused on customer engagement and PDK/IP solutions.
Agenda
• Semiconductor ecosystem
• Design House, Foundry, EDA vendors, OSATs, IPs
• Introduction to Fabrication, Foundry technologies & application
• Foundry process design
• PDK collaterals & its usage
• PDK collaterals and EDA tools
• PDK development and QA flow
• Understanding process design kits components, checks and flow
• DM, DRC, LVS, ERC, ESD/PERC, DFM, FILL, Antenna, Electromigration and IR Drop, High Voltage checks
• Parasitic Extraction and Model-PEX boundary
• Understanding spice model and simulation
• Understanding 3DIC Flow and its requirements
• Case Study: Skywater 130 PDK (Open source PDK) and its components
• Digital design flow and related PDK enablement
• Summary
Abbreviation and common terms
• PDK: Process Design Kits
• IP: Intellectual Property
• EDA: Electronics Design Automation
• OSAT: Outsources Semiconductor Assembly And Test
• FDSOI: Fully Depletion Silicon On Insulator
• GAA: Gate All Around
• EMIR: Electromigration and IR (Voltage) Drop
• 3DIC : Three Dimensional Integrated Circuits
• SOC: System On Chip
• RF/MMWave : Radio Frequency / Milli-meter wave
• DRC: Design Rule Checking / DM: Design Manual
• ESD: Electro-static discharge
• PEX: Parasitic extraction
Semiconductor Ecosystem
• Semiconductor Chip Foundries (Pure Play)
• Companies that manufacture chips in fabs for other customers
• Fabless Chip Companies
• Design chip and send to foundries for manufacturing
• Integrated Device Manufacturers
• Design and manufacture their own chips, also manufacture for other fabless companies
• Wafer Fab Equipment
• Provide equipment's/machines for chip manufactures
• Chip Material Companies
• Companies that provide all materials for chip manufacturing
• Example: Gases used in manufacturing, wafers, photomasks, slurries and photoresists
• EDA Companies
• Companies provide specialized software used by designers for every step of chip design
• IP Cores Companies
• Companies build their chip and sell/license to other companies
• Soft and Hard IPs
Source: www.semiwiki.com
Foundry Technologies & applications
Gate All Around (GAA) AI Accelerator, GPU, CPU
Logic Design
Advanced

Back Metal Support Back metal routing & mini-tsv

FinFet Vertical Transistor architecture (CPU/GPU)
Silicon-On-Insulator (SOI) Fully depletion silicon on insulator (IOT, Battery operated devices)
CMOS Bulk High-K High K di-electric technologies (45nm – 28nm)
Gate-First/Gate-Last Tech. Gate-First & Gate Last CMOS technologies
Image Sensor Tech. Front/Back side illumination (Image Sensors, HDR camera)
Technology
Specialty

BCD/BCD-Lite Bipolar CMOS-DMOS (Industrial Power mgmt., High V devices)

RF / MMW RF & MMWave 5G RF transceiver, automotive radar sensors
SiGe (Silicon Germanium) Storage devices, setup box, wireless headsets
MEMs Technology Micro electromechanical systems (gyroscope, pressure gauges)
Silicon Photonics Datacenter Applications (photo diodes, transformers, waveguides)
 Product Definition
Planning and
Budgeting

Design
Design Integration

RTL Design

RTL Verification

Logic Synthesis

Gate Level Netlist

Physical Synthesis

Layout (GDS)

Synthesis & Verification Layout Verification

Mask Generation
OPC\DRC Check
Fabrication

Wafer

Function Wafer
Testing

Reliability Test

Dicing \ Sorting

Packaging
Packing

Assembly
Semiconductor Product design – Full Flow

PCB Assembly

System Assembly
System
Integration

System Testing
Semiconductor Fabrication
Introduction of Fabrication Steps
• Building Silicon Wafer
• Cutting and processing uniform thickness wafers by polishing and apply smooth layer of silicon dioxide
• IC Imprinting
• Apply patterns using photomasks to imprint transistors and other devices using photolithography process
• Etching Process
• Etching process use gas and liquid etchant to selectively remove part of deposited material until desired
pattern is available on wafer
• Dry and wet etching processes are used
• Thin-film Process
• Depositing very think layers of materials using chemical vapors deposition (CVD) process to achieve
desired electrical properties
• Applicable for conducting layer and insulating layers depositions
• Interconnect Process
• Build metal and via interconnect to enable signal connection from top metal to devices
• Copper and aluminum are used for interconnects
• Electrical Die Sorting Process
• Perform electrical die sorting test to ensure quality of chip to achieve high yield
• Packaging & Testing
• Wafers are cut into individual chips with diamond cutter and package each chip on lead frame and
connecting its pins with package pins
• Perform various tests (voltage, electrical and temperature) on packaged chips
Process Design Kits Introduction
• Process design kits (PDK) are set of files that contain process related
information which model any fabrication process to design an integrated Semiconductor Foundry
circuits using the electronics design automation (EDA) tools.
Technology
• Designer use PDK to preform planning, design, verification, simulation FAB
before fabricating at Foundry Development
• PDKs are building block for any integrated circuit design and interface Process Design Kits
between Foundry and design house
• Quality of PDK enable first-pass silicon success and help achieve
predictable performance of final product Sales / Application Engineering
• PDK Contains
• Design Environment and device libraries
• Technology data including techfiles
• Verification / Signoff runset
• Reference Flow with recommended setting and demo kits Technology or CAD
• Simulation models
• Standard cell libraries, abstracted views and device characterization Design Team
libraries
• Documentation including design manual
Design Company
• Support major EDA tools, runsets, flows
PDK collaterals & EDA tools
DRC

LVS
Synthesis, Clock Tree EM & IR
RTL Design DFM Timing Analysis
Floorplan Synthesis, PnR Analsys

FillGen Post Layout

Early ESD
Schematic Pre-layout ESD & Latchup Parasitic Simulation Tnx EM & IR
Check Layout Design
Design Simulation Check Extraction + Aging Analysis
(Schematic) Antenna
Simulation
Design, Verification, Signoff

Parasitic
Pcell Library Spice Models FillGen Design for Layout vs
Design Aid Design Manual Extraction
(Schematic / Manufacturing Schematic & EMIR Techfiles
(LDE) & DRC runsets Techfiles /
Layout) APR Techfiles / Standard Cell Lib* (DFM) LVS-EXT
EMX
Process Design Kits Components

Virtuoso Antenna Calibre Extraction EMIR

Hspice (SNPS), Calibre DRC Calibre LVS
Custom(CDNS), Calibre FillGen, Calibre PERC/PERC- StarRC (SNPS), Voltus/Voltus-
Spectre (CDNS) (Siemens), (Siemens),
Compiler(SNPS) Pagasus (Siemens), LDL (Siemens), xACT (Siemens), Fi (CDNS),
Pagasus Pagasus
(CDNS), Pagasus ICV (SNPS) XRC (CDNS) Redhawk-
(CDNS), ICV (CDNS), ICV
Fusion Compiler (SNPS), Innovus ICV (SNPS) (CDNS), ICV SC/Totem
(SNPS) (SNPS)
(CDNS) (SNPS) PrimeTime (SNPS) (Ansys/SNPS)
EDA Tools
How to build Brand New PDKs
- Market Study
- Application Specific
- Customer Input & Testchip’s &
Request Technology Shuttle’s PDK Product
- Business Decision Development (Customer + Development Development
- Ecosystem Internal )
- Foundry Tooling
- Geo-political

Testchip’s to generate silicon PDK develop initial Pcell/verification

TD define device list, Feedback based on
data for devices, its for Testchip, PDK development
metals stacks, device actual silicon
parameters, metals stacks, based on testchip data/results (new
types and device performance,
device performance, model- rules, devices, parameters, design &
parameters product operation
hardware reports verification flows
PDK Development & QA Flow
1-2 Months 3-6 Months (depend on technology & SOW items) 1-2 Months

Device List Design Manual Design Env Documentation PDK - QA

Metal Stacks Component Rel
Layer/MetalStacks Metal Stacks QA based on SOW
Notes
Device Spec’s Design Rules Device Spec’s PDK Docs & Flows Full PDK QA

RELEASE
Testchip Results Truth Tables Signoff Standard Cell Lib Documentation QA
Silicon Reports ESD Rules / Limits Metal Stacks Library dev QA Regression
Feature Request EM Limits Cross tool QA
Device Spec’s Technology LEF
Technology Special Flows &
Scaling Reference Design Models & PEX Reference Flow QA
methodologies
Design Manual
• Design manual is document that capture all the semiconductor process and process design
kit related information required to setup, usage and deploy different flows
• Used by PDK development and QA team
• Used by Design team to understand rules and technology related information
• What design manual includes:
• PDK Contents / Directory structure
• Instruction for installation of Process design kits
• Technology overview and related information
• Metallization options with pitch/spacing details Design manual contents from
• Device truth table with details about all the CAD layers Cadence GPDK 90nm
• Special Flows
• Layout Design rules for conductors (metal and vias)
• Layout design rules for devices
• Layout design rules and guidelines for ESD and Latchup
• Reliability related rules
• Model and model parameters
• Rules and guidelines for dummy pattern and metal fill
• Guideline for digital and analog flows
Source: Cadence Generic PDK 90nm
Parametrized Cells (Pcells)
• A pcell is a Parameterized Cell View
• A graphical element
• Usually a layout cell, but it could be a
schematic symbol or a schematic circuit
• A program which when executed creates a
graphical element
• Usually, a pcell is a single device (resistor,
FET, inductor, waveguide, etc.)
• Rather than a single fixed layout, it allows user
to specify parameters

Source: www.cadence.com
Design Rule Check (DRC) DRC Checks

• DRC Rules are setup of parameters and associated checks ensure design/mask Spacing Spacing
correctness
(Double Layer) (Single Layer)
• Designer use Foundry DRC runset + EDA Tools to validate their layout designs M2 M2
M1
• Single layer, double layers and multi layer complex rules
• Types of Rules Width
• Spacing, width and enclosure rules
• Antenna rules, High voltage rules M2
• ESD and Latchup rules
• Poly and Metal Fill Density rules
Enclosure V1
Sample DRC Rules in Foundry Runset
Rule_1 { @ Width of metal2 should be greater than 1um
INTERNAL M2 < 1
}

Foundry DRC EDA Tools (e.g.

Foundry Design runset Siemens – Results
Process Manual Design Calibre, Synopsys
(Layout) ICV)
Layout vs Schematic (LVS)
LVS Checks
• LVS ensure schematic vs layout equivalency
• Popular EDA tools for LVS
• Siemens – Calibre, Synopsys – ICV, Cadence – Pegasus

• LVS runset includes

• Layer and datatypes definitions
• Device definition with device types and pin order
• Device properties calculation (include L, W, LOD, Stress and other complex properties)
• Device merging, reduction and filtering
Merging & Merging &
Sample LVS runset Reduction Reduction
// Device <device_type><subtype> <seed> <gate> <source> <drain> <bulk> <swap list> <aux_layers> <prop cal>
DEVICE MP(pfet_lvt) lvspfet_seed pgate(g) pfet_sd(s) pfet_sd(d) [s d] <poly>
Property [ ] Layout Schematic
Netlist Netlist

Foundry LVS runset EDA Tools Compare

Foundry Design (e.g. Siemens Results
Design (layout) (Summary +
Process Manual – Calibre, DB)
Synopsys ICV) Verification Results
Design (schematic)
Electrostatic Discharge (ESD)
ESD Models
Characteristics HBM MM CDM
ESD Library
Equivalent 0.5-1.0∝H + 200pF in Field plate to chip
1.5k + 100pF in series
Circuit series capacitance only
ESD Diode/BJT
One pin only (Discharge
Simulates Between ANY two pins Between ANY two pins ESD N+/P+ STI diode
Pin) ESD Vertical NPN Bipolar Transistor
Esd EG n+/pwell poly-bound diode
Discharge Exponential Decay Time Const = 11-16 MHz damped ~1 Ghz damped ESD EZ vertical PNP/NPN poly-bound
diode
Waveform 150ns Oscillation Oscillation Single and Double Diode (STI)
RC Clamp
Lowest Current and Voltage,
On-Chip stress Intermediate Current, Highest Current, Voltage
longest duration ESD FETs
characteristics Voltage and duration and shortest duration
I(HBM)=V(HBM)/1500 Ohms
SG/EG ESD NFET (pcell ESDNFET)
Thermal failures: MOSFET Junction damage, ESDNSH(pcell ESDNFET)
Failure Gate oxide damage and ESDNDRES (pcell ESDNFET)
snapback, Interconnect fusing, Interconnect fusing, gate thin/thick gate nfet_esd (pcell ESDNFET)
Mechanisms interconnect dam
gate oxide damage oxide damage

• Design team used to do custom ESD solution, but trends are moving into Foundry to support more compilated solutions due to time-to-market
• Ansys Totem Pathfinder
• Siemens Calibre PERC Sch/LDL
• Synopsys ICV PERC Sch/LDL
• Cadence Pegasus PERC Sch
Programmable Electric Rule Checking (PERC-LDL)
Current density flow: Point-to-point resistance check flow:
• Foundry provide current density limits based on conductor, • Foundry provide required minimum resistance for ESD paths
via’s and sizes of conductors
• EDA tool extract resistance and compare against Foundry limit
• Different CD limit supported for various CDM/HBM limits
• EDA tool extract W/L of conductor and check against foundry • Support full R-extraction & Resistance approximation
current limits
PERC Checks & Foundry Implementation
• Netlist Checks (Topology)
• Based on schematic netlist
• Check ESD discharge path, ESD devices, Sizes of ESD devices based on device Foundry runset
properties Netlist (Sch) (Rules)

• Layout / Netlist Checks (Topology & Geometry) Programmable Electric

• Based on layout netlist Rule checker (PERC)
• Check ESD discharge path, ESD devices, Sizes of ESD devices based on device
properties extracted by LVS deck Results

• Check ESD device sizes based on layout PERC : Electrical

• Current Density & Point-to-Point Checks
• Extract Current discharge path from layout based on rules
• Extract Full path or non-full path
• Full Path Example: I/O PAD  HBM Diode  VDD  Power Clamp  VSS Netlist (Sch) Netlist (layout)
Foundry runset
(Rules)
• Non-Full Path Example: I/O PAD  HBM Diode OR VDD  Power Clamp
• R-only Extraction Programmable Electric Rule
checker (PERC/PERC-LDL)
• PERC Matrix solver
• Check resistance between source and sink Results

• Check Current Density between source and sink PERC : Electrical + Geometrical
• Extract and write violation path as oasis (optional)
Antenna Effect
M2
• Antenna effect in semiconductor is also called plasma-induced gate
oxide damage during the fabrication process M1 M1
• Antenna Effects are cause by fabrication steps: Gate Gate
SRC DRN SRC DRN
• Contact Etch, sputter etch before metal deposit, oxide/metal deposition,
resist removal Fig 1: Antenna Effect Illustration
• Checking Methodology: --------- ---------------
M1 M1
• If there is a large area of poly or metal, and if it connects ONLY to gates --------- ---------------
of transistors (not to source or drain or any other active material) then Gate Gate
SRC DRN SRC DRN
these ions will travel through the transistors. If the ratio of the poly or
metal layers to the area of the transistors is too large, the transistors will
be destroyed
Fig 2: Gate damage due to charges
• Sample command used in runset (Calibre): NET AREA RATIO -+-+-+-+-+-+-+-+
M2
• How to avoid Antenna Effect
-+-+-+-- -+-+-+-+-+-
• Using metal jumper (It can increase delay in nets) M1 M1
• Using Antenna diodes (It can increase area) -+-+-+-- -+-+-+-+-+-
• Cutting poly layer using poly cut layer SRC Gate DRN SRC Gate DRN

Fig 3 : Diffusion damage due to charges

Latch Up
• Latchup is high current state in which PNP and NPN transistors rise to the
establishment of low resistance conducting path between VDD (Supply)
and GND (ground).
• What cause latch
• Positive or negative voltage spike on input/output
• ESD events
• Ionization radiation & high-power microwave interference
• Prevention
• Insulating oxide trenches preventing parasitic SCR
• Guard ring should be used to collect current
• Lightly doped epitaxial layer on heavily doped substrate
• Reducing Rsub (substrate resistance) and reducing Rwell (Well Resistance)
• Foundry Runsets / Rules:
• Checks if P-type and N-type guard rings are available in design around IO devices
• Rule checks if wells and property taped
• Spacing between P and N type devices with respective guard rings
• Checks to check spacing between I/O devices (with guard rings) to internal
devices (without guard rings)
Electromigration and IR Drop (EMIR)
• Electromigration is the gradual displacement of metal atoms when the
current density is high enough to cause a drift of metal ions in the
direction of the electron flow
• The amount of drift depends on the
• Nature of the conductor
• Crystal size
• Interface and grain-boundary chemistry
• Magnitude of forces
• Temperature
• Mechanical stress
• EM checking tools calculate current and compare this current with
Foundry specified current limits
• All metal layers and via’s have a finite amount of resistance and Voltage
drops due to the resistance of metals and wires. This drop is called IR
drop
EMIR Analysis and EM Techfiles development
Cadence – Voltus / Voltus - Fi
Idc and Irms Limits EM Techfiles (per SHE
for Conductors and Doc +
metal stack parameter
Vias Reference QA
Mapping files for (overlap +
Kits
Test structure layers/devices spacing)
Idc and Irms Limits
on Testchips
for RM devices EM Techfiles (per SHE
Doc +
metal stack/percorner) parameter
Idc and Irms Limits Reference QA
Mapping files for (overlap +
(Automotive & Self Kits
layers/devices spacing)
Heating Effects)
Ansys – Redhawk / Totem

Input design Simulation EM Report

LVS Parasitic Heatmap +
(Schematic (EM + DB
(PEX=True) Extraction EM Fixing
+ Layout options) Generation
Derating implementation for EM-ICT Different Lc (Critical length), which is
used in short line length calculations,
can be defined as variable and later
can be used in equations directly

Equations (Idc, Irms, and Ipeak are

defined for each conductors and vias

Equations (Temp, POH and CDF) are

defined for each conductors; “Tlife”,
“Tj”, and “cdf_percentage” is defined
in user run template. This will allow
the user to run EMIR analysis for non-
default conditions and derating will
be applied accordingly for each
conductors

Equations are defined for different

W/L (including short line length)
condition, Each equation uses
previously defined applicable
Inline support for Min/max allow the user to check CDF is supported as equation which allows user to
variables
various conditions with correct current limits (example: defined directly in techfile and CDF derating can be
derated current should not exceed “Irms” for conductors; applied along with Time/Temperature derating. NO NEED
this can be easily implemented with min/max equations) TO CREATE SEPARATE EM-ICT FILE FOR EACH CDF VALUE Irms and Ipeak can be defined using
variables

*Values shown are NOT actual and shown here for demonstration purpose only

28
EM – Current direction for short lines and vias
electrons flow down electrons flow up
Via n gets short line boost for metal n (e.g. M1) Via n gets short line boost for metal n+1 (e.g. M2)

Electron Flow (e-) Via n+1 Electron Flow (e-) Via n+1
Higher (e.g. V2) (e.g. V2)
electron VOID
density
Via n
Via n (e.g. V1)
(e.g. V1) Copper conductor
: n+1 (e.g. M2) –
Copper conductor Short line
Copper conductor : n+1 (e.g. M2) - Copper conductor
: n (e.g. M1) – Any length : n (e.g. M1) –
Short line VOID Any length

29
EM – Current direction for via’s implementation

Tabular definition for

Current direction max “Idc” current
for short line via’s limit based on
are defined in current directions
design manual
Maximum Idc is
Default condition applied based on
via Idc is derated current direction, Lc,
with Time, and top/bottom
Temperature and metal width
CDF conditions
*Values shown are NOT actual and shown here for demonstration purpose only

30
EMIR – Self Heating for FinFet & Photonics

31
PDK Implementation for EM-Self Heating Effect

• SHE and non-SHE config files

• PEX-EMIR templates
• Documentation and Reference Flow

*Values shown are NOT actual and shown here for demonstration purpose only

32
 High Voltage / Multi voltage domain checks
• SoC usually have multiple power domain and high voltage
Source Netlist
• These checks enable DRC checking based on voltage on NetA NetB NetC
nets Device Topology
1.2v 1.8v 1.2v
• Voltage-aware DRC enable effective DRC checking recognition recognition
• Foundry support different spacing limits based on Voltage
• Voltage difference Propagation
• Metal – Metal spacing 0.0v 0.8v 0.0v
Layout vs netlist
• It enable physical and electrical analysis for nets cross-reference
1.8v 1.8v
Automated nets
annotations
Net voltage assignment – propagation order:
Voltage-aware DRC
Supply on net Supply on net Supply on net
based on Supply on net
based on voltage based on priority
connection with based voltage
high OR low high OR low
device devices PERC based Voltage-aware DRC Flow
markers markers
Additional Checks / Utilities
• Checks for Illegal layers in design
• Its checks if designer is not using any extra/foundry reserved layer in design by mistake
• Unintentional extra layer cause design change, design discrepancy
• Check for layer to mask mapping
• Utility to convert design layer to equivalent mask required
• Metal Fill Utility
• To achieve uniform metal density and thickness during chemical mechanical policing (CMP). Foundry provide fill utility
which can be run on physical database before sending it to foundry for fabrication
• Fill support all Front end and back
• Floorplan based checks
• Floorplan based checks can be run in digital design flow after the floorplan stage
• DFM (Design for Manufacturability) Checks
• DFM checks are like DRC but more focus on manufacturability and reliability.
• It include techniques and best practices to improve overall manufacturing process and final product
• Electrical rule checking
• Electrical rules are checking for wrong/missing connection, well connection and more
What is 3DIC & why we need ?
Cost Modularization
• 3DIC allow vertical stacking of chips
• Special connects: TSV or Hybrid bonding
• Widely used for networking, graphics and AI accelerator chips
• Reduced Cost & Footprint
• Lower Yield problem
• Parallel development and testing Yield Heterogeneous Integ.

• Higher Bandwidth
• Allows larger number of vertical vias between layers
• Allows wide bandwidth buses
• Lower Power Consumption
Bandwidth (Memory) Size (Reticle)
• Smaller Package sizes
• Power hungry logic can on be one IC (on latest node)
• Vertical stacking for shorter and faster interconnects
• Heterogeneous Integration
• Flexibility to use different processes and technology nodes
2.5D & 3D IC Flow & Challenges
Foundry/OSAT SIPI/Reliability
Analog
Analog designer
designer Digital
Digital designer
designer Packaging
Packaging designer
designer Signoff Engineers
Interface Engineer

System Designer Inputs ASIC / IPs

I/O connection spec Interposer Verilog Golden bump/pad xls Routing Spec

Chip Design Intent

Soc_top Verilog Power Config Interposer floorplan
(Blocks, Ips)

Foundry / OSAT Bump locations

Tech LEF with TSV and
backside layer
Package
Bump LEF (ubump, C4 3DIC
bumps)
Physical verification
(DRC/LVS) runsets

PEX techfiles

EMIR Techfiles & Package bump locations

mapping files

Finished
System Digital Analog and Early
Packaging Integration Signoff Design for Part
Design/ Design Mixed Signal Analysis
Flow Flow Flow Test Flow testing
Planning Flow Flow Flow
Flow
3DIC Stacking and Physical Verification
• 3DIC Checks
• Port and text related checks are generated on the fly vdd1
vdd2
• User can enable or disable checks
• TEXT & PORT Checks Figure1: Multiple Texts

• Floating Text -> Check floating texts

• Additional Ports -> Additional ports in layout and missing in source
• Missing Ports -> Additional ports in source but missing in layout
• Multiple Text -> Bump which contains more then one unique texts Figure2: Missing Text

• Missing Text -> Bumps that don’t have any attached text
• Un-connected Ports vdd3
Figure3: Floating Text
• Floating ports in source and layout netlist
3DIC Analysis – Reliability & Thermal
• EMIR co-simulation for 3DIC chip-package-system
• Per pin 3D heatmap Die1 – Metal Layers (Tech1)

• System level Dynamic IR drop heatmap ubumps

SOC3 Die2 – Metal Layers (Tech2)
• 3D thermal heatmap HBM
SOC1 SOC2
HBM TSV (Top die – Interposer)
• Extract power network of chip – interposer – package ubumps
Interposer Interposer (Tech3)
(includes coupling effects) RDL Layers (Die to Die
• Includes Package/PCB thermal modeling Package - Substrate Connections)
Embedded Dcap’s
• Thermal induced stress analysis (handle different TSV (RDL – Interposer)

coefficient of thermal expansion (CTE)) C4 Bumps

Package Routing Layers

Power Delivery Interposer

Package C4 bump Ubump Die2 Ubump/TSV Die1
Network (PDN) (TSV/RDL)

Signal Route
Interposer Interposer
(Driver – Die1 TSV Memory (HBM) Die2 Die2
Receiver)
(RDL/TSV) (RDL/TSV)

38
PDK Customization and best practices
• Foundry expect tape-in design clean on Foundry provided PDK checks using qualified EDA tool versions
• User’s can write custom rules and develop custom techfiles for additional coverage
• Use setting based on your product lifetime, operating conditions and application space.
• User’s can request waiver from Foundry if violation are marginal
• Identify which rules/flows are mandatory OR optional for tapeout
• Review Foundry tape-in checklist in advance to understand requirements
• Setup split checks to enable parallelism and quick turnout
• Enable or disable type of rule checking based on project milestone
• E.g. Don’t run ESD unless design is short clean
• Identify high cost (resource/time) rules and optimize it locally
• Add any custom devices + customer specific layers
Digital Design – Standard Cell Libraries

Source: Skywater open source 130 pdk

Standard Cell Libraries - collaterals
Cell Library:
- Contains various views for each cells
- Example: symbol, Verilog,, lef, oasis,
spice netlist, .lib for various
corner/temp/voltage, ccsnoise, cdl

Models:
Verilog simulation models

Technology LEF:
It contains technology related
information including conductor, via,
dimensions, parasitic and rules

Timing Libraries:
Timing libraries/arc for different
operating conditions
Source: Skywater open source 130 pdk
Metal Stack Development
• Metal Stack (metallization options) provide
set of metals/vias to connect devices to
bumps
• Metals are categories in different sets with
variable pitch, spacing, width
requirements.
• Some technology support top-layer as
aluminum and lower metals of copper
material
• SOC with higher transistor density
requires metals stack with more
conductors
Source: Skywater open source 130 pdk
Device (NFET & ESD NMOS FET)
•NFET 1.8V ESD NMOS FET
•Model name: nfet_01v8; Cell Name: nfet_01v8 •Cell Name: sky130_fd_pr__nfet_01v8
•Operating Voltages where SPICE models are valid •Model Name:
•VDS = 0 to 1.95V
•VGS = 0 to 1.95V sky130_fd_pr__esd_nfet_01v8, sky130_fd_pr__esd_nfet_g5v0d1
•VBS = + 0.3 to -1.95V 0v5, sky130_fd_pr__esd_nfet_g5v0d10v5_nv

Operating Voltages where SPICE models are valid

•V = 0 to 11.0V (sky130_fd_pr__nfet_g5v0d10v5*), 0 to 1.95V (sky130_fd_pr__nfet_01v8*)
DS

•V = 0 to 5.0V (sky130_fd_pr__nfet_g5v0d10v5*), 0 to 1.95V (sky130_fd_pr__nfet_01v8*)

GS

•V = 0 to -5.5V, (sky130_fd_pr__nfet_g5v0d10v5), +0.3 to -5.5V

BS

(sky130_fd_pr__nfet_05v0_nvt), 0 to -1.95V (sky130_fd_pr__nfet_01v8*)

Source: Skywater open source 130 pdk

Content of Open Source PDK (Skywater 130)

Source: Skywater open source 130 pdk

CMOS Bulk Process

• Planner technology
• pmos are in n-well and nmos
are p-substrate
• Economical process till
32nm/28nm
• Fewer mask means lower cost
High-k Metal Gate Process

• From 65nm->45->32nm->28nm sizing happened

at all levels
• GOX (Gate-Oxide) thinning lead to explosion of
gate leakage
• Historically SiO2 was used for gate oxide, started
32nm/28nm foundry moved to High-k materials
• Most Fab use HfSiON (Nitride hafnium silicates)
FinFet Technologies
• Higher transconductance (current out
per voltage in)
• Lower apparent input capacitance for
the same gain (faster switching speed)
• Less wafer area per transistor to get
high gain, as fin height can be adjusted
• I-V curves get flatter, lower dynamic
power consumption, better on/off
characteristics)
• Complex to manufacture, reliability
challenges
Silicon on Insulator (SOI) Technologies
• SOI (Silicon on Insulator) Lower leakage
than bulk
• Fully depleted channel  Lower leakage
currents
• Lower doping effort  Less Vth variation
across chip
• Body-biasing capability
• Better isolation between devices
• Very small WPE effect
• Reduced junction capacitances
• Short channel effects improvement (Xj ,
Back Bias Tdep)
• Idle for IOT applications
Voltage

Source: https://globalfoundries.com & https://semiwiki.com

Intel 20A/18A (GAA/Ribbon Fets Technology)
Biggest Innovation since FinFET
• Introduces RibbonFET and PowerVia:
• Biggest innovation since Intel introduced FinFETs to HVM in
2011.
• Gate-All-Around (GAA) transistor improves density and
performance versus FinFET. PowerVia

• Optimized ribbon stack delivers superior performance per watt

and minimum supply voltage (Vmin).
• PowerVia is Intel’s unique industry-first implementation of
backside power delivery architecture that improves standard cell
utilization by 5-10% and performance by greater than 5%2.
• Well-suited for High Performance Computing (HPC) and mobile
applications.

RibbonFET
Source: www.intel.com & https://semiwiki.com
Understanding Parasitic extractions
• The contribution of interconnect to signal delay is greater than
the cell contribution at process nodes 0.13um and below
• •About 80% of the overall path delay is attributed to interconnect
• •Accurate knowledge of the interconnect parasitic is a must for
high performance chip design
• Still R &C Driven extraction
Pre-layout vs post layout simulation
• A pcell is a “parameterized” cell used to represent a device in custom design
• Extraction uses gray-box/black-box concept to handle parasitics against model
PEX flows (LVS->PEX->Models)
•Extraction Requirements
• No DRC errors; LVS cleanness; No open/shorts; Check soft-connect, floating wells
• EMIR Flow requires additional info

Data Preparation
Schematic netlist Generation CDL GDS/OAS
Layout data Generation

Nxtrgrd(Synopsys)
calibre_starrc_map Synopsys StarRC
Cadence Quantus
Siemens xACT
Generate Hierarchical Cell List Hierarchical cell list
lvs.svrf

Calibre LVS
Siemens Calibre* RCX LVS SPF OA Extracted SPEF
Data Generation for extraction view

CCI
CCI query Circuit simulation, noise analysis, timing
Parasitic Extraction with StarRC
analysis, reliability tools

In typical design house team is using hierarchical LVS to speed up the physical verification as design size is huge
EDA Vendors and their tools
Technology Files:
nxtgrd + VCF (StarRCXT)
qrcTechFile + qrcViaRModelFile (QRC)

Designs
(testcases)

Extracted netlist or
oa-extracted view
Req: successful LVS: Extraction
ICV runst + ICV
Calibre runset + Calibre Simulation:
Auxiliary files Model files + Spectre
Model files + Hspice (as needed)
Extraction tools:
StarRCXT
QRC
3D Field solvers
• FinFet, GAA structure is based
on 3D Transistors
• More items are covered in
Extraction tools
• Model vs PEX boundary
• StarQTF, Quantus Field Solver
 What is device Model
• What is a Compact Model
• An efficient analytical
mathematical representation of a physical
device that can be easily written in a circuit
analysis framework. Compact Model

• Compact Models Should

• Contain the essential physics to accurately
model real data.
• Be common across a single device
type technologies (MOSFET, Diode,
MRAM, etc.) Technology/Process Development

• Be straightforward to extract parameters

• Computationally efficient
IC Design
 Model Corner vs Monte Carlo
Full Monte Carlo Full Monte Carlo

SS FFG
0.35 800
FS SF

Iddset of pfet [mA]

0.3 700
FSG SSG SFG FFG
TT TT
Vt of pfet

0.25 600

SFG FSG
0.2 500
FFG SSG
SF Local Monte Carlo FS Local Monte Carlo
(a.k.a mismatch) (a.k.a mismatch)
FF 0.25 0.3 0.35 0.4 SS 500 600 700 800
Vt of nfet[V] Idsat of nfet [mA]

An example plot of each corner location compared to Monte Carlo circles

Type of Analysis
• DC/AC/Transient – Basic Simulation
• Noise/SP – Mostly Small Signal
• PSS/Pnoise – Large Signal

DC
Transient
Pnoise
Model Maturity
Model Maturity 0.1 0.3 0.5 0.9 1.0 1.1 and after
Model vs Si Paper Model Limited Nominal Corner Learning is Most Si learning is Fab is ready to Adding additional
done done HVM range

List of devices Minimal Fets, Cap Feature added Customer Input Customer Input RF, mmWave Adding additional
such as thick gates received receive devices are Feature such as
considered LDMOS, MRAM,
more BEOLs

Performance Based on previous 50-60% 70% 80- 90% > 90% 100%
generation

IP Basic Std Cell

Customer Only Test chip for Anker Customer Lead Customers Limited Production Open to general Open to general
Readiness development is open customers customers
EDA Tool Breadth Usually one major 1 additional flow is EDA tool breadth is All tool breadth Customer specific
flow added considered flow is added
Aging Mechanisms : Bias Dependence
• There is a growing reliability concern in advanced
nodes that designers need to ensure functionality
and performance until expected lifetime.
• 2 Ways to perform Reliability Simulation
• Relxpert Flow (prebert, posbert, prebert2)
• Spectre Native Mode
• Features supported in Foundry
• Hot carrier injection (HCI)
• Negative bias temperature instability (NBTI)
• Positive bias temperature instability (PBTI)
• Cadence ageMOS models
Cadence Flow Example for Aging Simulation
Electromagnetic tools are required

RLC Equivalent Circuit of Inductor Inductance vs Frequency is known

Typical Inductor in Foundry

Typical Cap Structure in Foundry Cap vs Frequency is changing orders or mag !!

EDA Vendors and Example Plot

Integrand EMX

Xpeedic IRIS (3D)

Emagnetic

Keysight Momentum
& EMPRO (3D)

Lorentz Solutions
Peakview

Helic RaptorRF

Sonnet SonnetSuites
PEX QA Example
Areas Covered Tests Examples Test Objectives Example Measurement
* SPEF produced
NDM-based StarRC ==> SPEF (nominal) Can extraction run through with SPEF produced?
* Warnings understood
* SPEF produced
NDM-based StarFS ==> SPEF (nominal) Obtaining field-solver result as golden
* Warnings understood
Synopsys Digital flow StarRC vs. StarFS total cap Comparison Verifying StarRC accuracy for total capacitance
* Result meeting Certification Criteria
StarRC vs. StarFS coupling cap Comparison Verifying StarRC accuracy for coupling capacitance
* Large outliers understood
StarRC vs. StarFS resistance Comparison Verifying StarRC accuracy for total capacitance
Verifying consistency of circuit topology between StarRC & StarFS in NDM * Matched net counts, number of opens and shorts.
StarRC vs. StarFS Comparison on net counts, number of opens/shorts
flow * Mismatch understood
* SPEF produced for one skew (nominal)
LEF/DEF-based StarRC ==> SPEF Can extraction run through with SPEF produced?
* Warnings understood
* SPEF produced for one skew (nominal)
LEF/DEF-based StarRC ==> SPEF Obtaining field-solver result as golden
* Warnings understood
Cadence Digital flow StarRC vs. StarFS total cap Comparison Verifying StarRC accuracy for total capacitance
* Result meeting Certification Criteria
StarRC vs. StarFS coupling cap Comparison Verifying StarRC accuracy for coupling capacitance
* Large outliers understood
StarRC vs. StarFS resistance Comparison Verifying StarRC accuracy for total capacitance
Verifying consistency of circuit topology between StarRC & StarFS in * Matched net counts, number of opens and shorts.
StarRC vs. StarFS Comparison on net counts, number of opens/shorts
LEF/DEF flow * Mismatch understood
NDM vs. LEF/DEF total cap Comparison Verifying StarRC accuracy for total capacitance
* Result meeting Certification Criteria (for lack of another criterion)
NDM vs. LEF/DEF coupling cap Comparison Verifying StarRC accuracy for coupling capacitance
* Large outliers understood
cross-flow comparison NDM vs. LEF/DEF resistnce Comparison Verifying StarRC accuracy for total capacitance
* Matched net counts, number of opens and shorts.
NDM vs. LEF/DEF comparison on net counts, number of opens/shorts Verifying consistency of circuit topology between NDM and LEF/DEF flows
* Mismatch understood
Functionality: with SMC turned on can StarRC run through with combined * Combined SPEF produced for all corners specified
NDM-based StarRC ==> SMC SPEF combined
SPEF produced? * Warnings understood
Funcationality: with SMC turned on can StarRC run through with separate * Separate SPEFs produced for all corners specified
SMC check (on one testcase) NDM-based StarRC ==> SMC SPEF separate
SPEFs produced? * Warnings understood
RC comparison between SMC "typ_nom" corner (nominal+25C) and non- RC result of SMC "typ-nom" and non-SMC SPF at nominal/25C agree
Are SMC & non-SMC result consistent?
SMC nominal skew at 25C within X % (Total cap, coupling cap and resistance)
* SPEF produced for all skews specified
NDM-based StarRC run for all skews
Skew trend check * Warnings understood
Does RC result match correct skew trend?
(on one testcase)
RC comparison for all skews * Result meeting the correct trend for skews:

Temperature variaction check 1. No difference seen in capacitance

NDM-based StarRC run at 25C and 125 (nominal) ==> 2 SPEFs Does RC result match correct temerature trend?
(on one testcase) 2. Resistance is higher at 125C
RF/mmWave Coverage
• RF and mmWave devices are available as additional library and cost
• 2x/3x CPP mmWave on selected
• Nf(number of fingers) -> nrep(no. of rows in the same p-cell)
• Improved gate resistance -> High Fmax
• Smaller foot frint
• Buck converters require few thousands devices to achieve power efficiency at 16nm and below
• Si Verified up to 30GHz ~ 100GHz
• Foundry offer digital/analog library in early stage
• RF/mmWave require additional thick BEOL and components
• Inductor Q can increase 20-30%
• Transformer, Balun, LDMOS, T-lines, Extremely Low Vt device
• Pcell is qualified up to top-level metals
Packaging and Thermal

FCBGA EMIB 2.5D Foveros 3D Foveros Direct

2D/2D+ 3D

Intel 2.5D EMIB (embedded multi-die interconnect bridge) Bump Pitch ≤100µm 45 ~ 36 µm 36 ~ 25 µm <10µm (Hybrid
Source semiwiki.com Bond)

Bump Density ≥100/mm2 495 ~772/mm2 772 ~ >12,000/mm2

1600/mm2

D2D spacing : 240µm-3mm 240µm-500µm 40µm-45µm 70µm-110µm

Power ~1.5pJ/bit 0.50 pJ/bit 0.15 pJ/bit < 0.05 pJ/bit

Intel 3D Foveros using TSV and microbump

Source semiwiki.com
Summary
• Foundries offers various technologies for different application
• Planner technology are ideal for low-cost applications while FinFet and GAA
technologies are great for higher GPU/CPU type application
• Process design kits are fundamental building blocks represent technology
and used for design, verification, signoff and fabrication.
• Process design kits contains techfiles, runset, utilities, end-to-end flow and
documentations.
• Feature rich PDK enables high quality and on-time product development