DSM250 Digital Sounder Module Service Manual

DSM250 Digital Sounder Module
DSM250

Digital Sounder Module
Service Manual
Document Number: 83166-1
Date: May 30, 2003

DRAFT
WARNING:
CE Marking of Equipment/Replacement Parts

If the Raymarine equipment under repair, test, calibration, installation or setting to work carries the European CE mark,
only parts and components supplied or approved for such use by Raymarine should be used in order to maintain
compliance with the relevant CE requirements.
Incorporation, use or attachment, by any means, of parts or components not supplied for or not approved for such use by
Raymarine or, if supplied or approved for use by Raymarine, not properly fitted in accordance with instructions
published, provided or recommended by Raymarine, may cause the equipment to malfunction and, in particular, to
become unsafe or to no longer meet the relevant CE requirements. In these circumstances, Raymarine excludes liability
to the fullest extent permissible in law for any loss or damage including any liability for its contribution to such loss or
damage by its negligent acts or omissions.
DSM250 Service Manual 83166-1 1

Intended Use
This Service Manual is intended to provide service instructions for the DSM250 Digital
Sounder Module.
Safety Notices
This equipment must be installed and operated in accordance with the instructions
contained in the Owner’s Handbook. Failure to do so can result in personal injury and/or
navigational inaccuracies.
High Voltage
This unit contains high voltages. The unit should always be turned off and power
disconnected before removing the covers. The unit’s high voltage can take up to 1 minute
DRAFT
to decay. Only qualified service technicians should perform the specialized service
procedures.
Warranty
When a repair is carried out by an authorized Raymarine service representative, some or all
of the cost may be covered by the Raymarine warranty. Refer to the Limited Warranty
Certificate in the handbook for your DSM250.
Service manual contents © Raymarine, 2003
2 DSM250 Service Manual 83166-1

Contents
Chapter 1: Introduction .................................................................................................... 5

Overview .............................................................................................................................5
Chapter 2: Technical Description .................................................................................... 7
2.1. Unit Configuration ..............................................................................................................7
2.2. Design Details .....................................................................................................................8
Power Supply ......................................................................................................................8
Boost Circuit........................................................................................................................9
CPU ...................................................................................................................................10
FPGA.................................................................................................................................11
ARCNET ...........................................................................................................................11
DRAFT
Chapter 3: Service Procedures ...................................................................................... 13

3.1. Master Reset ......................................................................................................................13
3.2. Status LED ........................................................................................................................15
3.3. Interface Connections........................................................................................................16
Power Cable End Connector .............................................................................................16
Communications Link – J1................................................................................................16
Transducer Link – J2 .........................................................................................................17
3.4. Spare Parts List..................................................................................................................17
3.5. Replacing Parts..................................................................................................................17
Access and Replacement ...................................................................................................17
Chapter 4: Drawings ....................................................................................................... 23
List of Drawings ................................................................................................................23
DSM250 Main Board – CPU Section ...............................................................................24
DSM250 Main Board – FPGA Section .............................................................................25
DSM250 Main Board – SDRAM/Flash/USB/Serial Debug .............................................26
DSM250 Main Board – ARCNET Controller...................................................................27
DSM250 Main Board – Sonar Transmitter and Receiver .................................................28
DSM250 Main Board – Power Supply/Boost ...................................................................29
DSM250 Main Board – Sonar Speed/Temperature...........................................................30
DSM250 Main Board – PCB Layout, Component Side....................................................31
DSM250 Main Board – PCB Layout, Solder Side............................................................32
DSM250 Connector I/O Board – Schematic .....................................................................33
DSM250 Connector I/O Board – PCB Layout..................................................................34

DRAFT

Chapter 1: Introduction
Chapter 1: Introduction
This Raymarine Service Manual contains information to assist with maintenance and

service of your DSM250. It is intended to be used by qualified Raymarine service
representatives.
Overview
Chapter 2 contains the technical description of the digital sounder module and theory of
operation.
Chapter 3 contains service information, the spare parts list, and instructions for
dismantling and reassembling the unit.
Chapter 4 contains the circuit diagrams and their associated layouts.

DRAFT

DRAFT

Chapter 2: Technical Description
2.1. Unit Configuration

J6
DRAFT
Main PC Board
J1 - Power/Signal connector
J2 - Transducer connector
J6 - Diagnostics connector
J1 J2
Connector I/O Board
D6349-1
Figure 2-1: DSM250 PC Boards and Interfaces
The DSM250 contains two PC boards, as shown in Figure 2-1.
The Connector I/O board provides connection to the outside world via bucket connec-
tors, which mate with the pins molded into the CPU board. The connections provided are:
Power, Transducer Sense, HSB, and Ground. The connector I/O board also contains the
three-color warning LED, which is controlled by the CPU.
The CPU/Sonar (Main) board contains the DSM250’s main circuitry. It is comprised of
the Sharp LH79520 processor, the Xilinx XC2S300E Field Programmable Gate Array
(FPGA), ARCNET controller for the hsb2 interface, and support circuitry such as
PROMS, SDRAM, Sonar/Transducer interfaces, non-volatile data storage in EEPROM,
RS485 and power control and supervisory circuits. The connections provided are Battery
In Positive & Negative, HSB data I/O, and data from the transducer: Transducer Sense,
Water Temperature, and Paddlewheel Speed. This board also contains connections to the
warning LED on the Connector I/O board and a thermistor that enables the CPU to
determine the temperature within the unit.

2.2. Design Details
Power Supply
The Power Supply circuitry provides power outputs of +5V, +3.3V, +1.8V, and +12V to
the DSM250. In addition, the +5V line is further divided into a filtered +5V for use by
the Sonar receiver circuitry, and an isolated +5V for use by the hsb2 circuitry.
The power supply circuitry begins on the Connector I/O PCB, where the incoming
Battery positive and negative pass through a differential “pi” LC-filter. The shield of the
power cable is connected to the ground stud, and through the stud, to the conductive
shielding coating the inside of the plastic case.
I/O BOARD MAIN BOARD
DRAFT
BOOST PWR
BATT + LOGIC PWR
BATT - RECEIVE GROUND

CMC FB RX
BOOST GROUND
FB
LOGIC GROUND
SHIELD FB
GROUND
STUD
5V
BUCK ISOLATED +5V
SMPS
LT1956 ISOLATED GROUND
T7 ISO
+5V
RECEIVE +5V
3.3 V
+3.3V
LINEAR
LT1086
1.8 V
+1.8V
LINEAR
LM317
12 V
STEP +12V
UP
LT1371
D6334-1
Figure 2-2: Power Supply Section

As the battery positive and negative pass onto the Main PCB, additional filtering and
transient protection is included. The battery positive is divided into two power signals,
one for Boost power and the other for Logic power. These are isolated from each other by
diodes. These diodes also provide battery voltage polarity reversal protection.

Logic Power is then utilized to provide the various output voltages. First a Buck Switch
Mode Power Supply (SMPS), using a LT1956 Pulse Width Modulation (PWM)
controller provides the +5V output. A secondary winding on the buck inductor, T7, is
used to provide the isolated +5V output used for the hsb2 circuitry. In addition, the +5V
is filtered with a “pi” LC filter to provide the filtered +5V used by the Sonar Receiver.
Linear voltage regulators are used, with the +5V as the input, to generate the +3.3V and
+1.8V outputs.
Since the input voltage can be any voltage in a wide range, +10V to +30V, it is not
practical to generate the +12V signal directly from the battery voltage. The +12V output
is generated using a Step-Up SMPS.
DRAFT
Boost Circuit
In order to provide the 120V required for a high power sonar transmission, a Boost
circuit is utilized. The input to this boost circuit is the Boost Power mentioned in the
Power Supply section, above. The Boost circuitry is completely controlled by the FPGA.
The Boost circuit is enabled or disabled using a MOSFET configured as a high side
switch, Q7. To charge the boost reservoir, the FPGA first selects the voltage level that it
wishes to impress on the voltage reservoir capacitors by outputting a pulse wave through
an RC filter to the positive input of the monitoring voltage comparator, U25. U25
compares this voltage to the voltage of the reservoir capacitors through the voltage
divider formed by R134 and R173. R134 and R173 also provide the slow bleed off path
for the reservoir in the event that the DSM250 is powered off before it has a chance to
discharge the reservoir capacitors.
After the boost level trip point has been set in this manner, The FPGA outputs a variable
frequency pulse wave through the FET driver U24A to the gate of the switching
MOSFET. The on time of this pulse wave is set by the FPGA depending upon the battery
voltage so that the peak current through the Boost Inductor T6 does not exceed its
maximum ratings. The off time of this pulse wave is determined by the boost current
sense circuit formed by the secondary winding of the boost inductor. When the boost
inductor has completely discharged the energy stored in it during the on time, the current
falls to zero, and the FPGA begins another cycle.
During the on time, the current through the inductor ramps up from zero to a maximum
current determined by the on time, the battery voltage, and the inductance. This results in
energy being stored in the boost inductor. During the off time, this energy is discharged
from the boost inductor in the form of current through the blocking diode, D20, causing
the voltage to rise in the reservoir capacitors. As soon as this current falls to zero another
cycle begins.

When the voltage reaches the trip point, the FPGA terminates the boost by ceasing to
output the pulse wave.
To discharge the boost reservoir, the FPGA turns on the discharge FET, Q10, allowing
the reservoir capacitors to discharge through R139 to ground.
CPU
The normal support circuits are required by the LH79520 including PROM, RAM, and
non-volatile EEPROM memory. There is also a reset / watchdog IC. The clock for the
LH79520 I/O is 38.0 MHz. The LH79520 core is clocked at 57 MHz. The CPU also
generates the reset for the ARCNET hsb2 controller. Refer to the schematic on page 27.
LH79520
DEBUG/TEST EXTERNAL 14.7456 MHz 32.768 kHz
DRAFT
INTERFACE RESET INTERRUPTS
OSCILLATOR,
PLL POWER REAL TIME
MANAGEMENT, and CLOCK
RESET CONTROL
GENERAL
32KB PURPOSE I/O
SRAM
TEST
LOGIC / PIN ARM 720T
MUXING CONDITIONED I/O
EXTERNAL CONFIGURATION
INTERRUPTS
VECTORED SYNCHRONOUS
INTERRUPT SERIAL PORT
CONTROLLER
STATIC
MEMORY
CONTROLLER TIMER (4)
EXTERNAL
BUS INTERNAL
INTERFACE INTERRUPTS
SDRAM WATCHDOG
CONTROLLER TIMER
DMA
CONTROLLER
DUAL
CHANNEL PWM
ADVANCED
PERIPHERAL
BUS BRIDGE UART (3)
IrDA
INTERFACE
COLOR
LCD
CONTROLLER
ADVANCED HIGH ADVANCED
PERFORMANCE PERIPHERAL
BUS (AHB) BUS (APB)
HR-TFT LCD
TIMING
CONTROLLER
Figure 2-3: CPU Block Diagram

The SHARP LH79520 Evaluation board combines a 32-bit ARM7TDMI RISC, 8KB
Cache, MMU, color LCD controller, and 32KB SRAM. Also included are a number of
essential peripherals such as a DMA Controller, Serial and Parallel Interfaces, Infrared
Support, Counter/Timers, Real Time Clock, Watchdog Timer, Pulse Width Modulators,

and an on-chip Phase Lock Loop. The applications that the platform may be used for
include development for GPS, PDA, Poin-of-Sale, Security Control Panels, etc.
Features:
• Sharp LH79520 ARM720T Processor
• ARM720T (ARM7TDMI + 8K Cache + MMU)
• Programmable clock divider enabling operating speeds of 10, 37.5, 50 and 75 MHZ
• 4 MB Flash ROM
• 2 MB SRAM
• 64 MB SDRAM
• 32 KB SRAM (on chip)
• Full JTAG scan support for debugging
• Two serial ports + IrDA
DRAFT
• Four user programmable buttons, separate interrupt and reset buttons

• DMA (4 Channels)
• LCD Controller (Color, to SVGA)
• Socket for compact flash card
• 16-bit IDE interface available via compact flash interface
• 10/100 Ethernet support
• Serial EEPROM for MAC configuration Data
• I2S Audio interface with CODEC and Mic-in, Line-in and Line-out connections
• Eight status LEDs
• Speaker
• Easy interface to Logic Analysers with six on-board Mictor connectors
FPGA
The FPGA contains the front end for all fishfinder operations (schematic on page 25),
including digital sonar transmitter pulse and receiver output signals (schematic on page
28). It is responsible for sonar filtering, automatic gain adjustments, and general I/O.
The FPGA also handles information from the transducer, reading the temperature sensor
resistance for temperature variation and monitoring paddlewheel speed. (schematic on
page 30). In addition, the FPGA generates the push-pull waveform for the power
amplifier.
ARCNET
A single chip ARCNET interface implements the low level protocol of the High Speed
Bus (hsb2) to carry fishfinder and control data among units on the hsb2 network. The
LH79520 processor transmits and receives data packets over the hsb2 via this chip. The
hardware interface onto the HSB cable is via a single RS485 transceiver chip carrying
data at a rate of 7.125 MHz. Refer to the schematic on page 27.

DRAFT

Chapter 3: Service Procedures

This chapter describes service issues for the DSM250. It details how to reset the unit and

then provides the connector pinouts and the Spare Parts List for the DSM250. This is
followed by procedures for opening the unit and removing the PC boards for repair or
replacement.
Other Raymarine Service Manuals only provide top level schematic drawings to help you
isolate faults to the PC board level. Because most of the circuitry for the DSM250 is
housed on one PC board, this Service Manual provides full schematics so you can
troubleshoot to the component level.
The DSM250 may be powered up with the case open after the rear case screws have been
removed. Refer to the Access and Replacement on page 17.
3.1. Master Reset

DRAFT
Before servicing the DSM250, you should reset the unit. There are two types of reset
available for the DSM250:
• Power-On Reset: When you turn the DSM250 off and on again, all previous settings
are retained except for those listed in the following table, which are reset to the factory
default:
Item Power-on Setting
Heading Mode North Up (chart)
Brightness*
Monochrome LCD ON at 40% if previously left ON, or else OFF if previously set to OFF.
Color LCD 40% if previously set to less than 40%, or else restores previous setting.
7" high brightness 54% if previously set to less than 54%, or else restores previous setting.
color LCD
Range Shift 0 feet
Manual Scroll Speed 100%
* of connected display unit
• Factory Reset: This resets all values back to their original factory settings.
WARNING: The factory reset clears the sonar depth offset and speed and
temperature calibrations.
To perform a factory reset:
1. Press MENU.
2. Press the SONAR SET UP soft key to display the Sonar Set Up page.
3. Press and hold MENU for 5 seconds.
The RESET TO DEFAULTS soft key appears.
4. Press RESET TO DEFAULTS.
New soft keys appear: ARE YOU SURE? YES. NO.

Pressing NO returns you to the Sonar Setup Menu.

Pressing YES results in the DSM250 resetting all settings to factory default:
i. The power on the DSM250 cycles OFF and ON.
ii. The message SONAR DATA UNAVAILABLE appears.

iii. An audible alarm is sounded.
iv. The normal sonar image resumes scrolling across the display.
The reset is complete.
To cancel the reset:
Before pressing YES as described in item 4 above, press any of the following keys:
DISPLAY, MULTI, VRM/EBL, MARKS, RANGE, GAIN, or ALARMS.
This action opens up a new menu according to the key pressed.
DRAFT
or
Press either the ENTER or CLEAR key. This action returns the unit to the Sonar Set
Up menu.

3.2. Status LED

The LED on the connector panel provides valuable information on the status of the

DSM250. The LED blinks green while the module is operating normally. If the unit detects
a problem, the LED blinks amber to indicate a warning or red for an error. The number of
times the LED blinks is a code representing the nature of the problem. For multiple
warnings/errors, the codes are given in sequence with a 1.5 second pause between strings.
The following table shows the various LED status codes and their meanings.
No. of Cleared every

Color blinks Meaning 10 minutes
Amber 1 Transducer Sense Failure
2 hsb2 not detected
3 High temperature Warning √
4 Reserved
DRAFT
5 Reserved
6 Reserved
7 Reserved
8 Watchdog Timeout Reboot √
Red 1 Unknown Error √
2 Battery Voltage Error √
3 High Temperature Error √
4 Flash Memory Error
5 Reserved
6 Reserved
7 Reserved
8 Hardware Monitor Failure
After 30 seconds of no hsb2 activity, the DSM250 enters Standby mode:

No sonar pings are emitted and no warnings are output on the LED. Instead, the LED
blinks green once every 10 seconds.
For example, if the Transducer Sense fails and hsb2 is not detected, the unit blinks amber
once, pauses 1.5 secs, blinks amber twice 0.5 secs apart, pause 1.5 secs, and then repeats
the sequence until the problems are resolved or (for some warnings/errors) up to 10
minutes elapse.
A solid red LED (not blinking) indicates a fatal error condition. If the event of a fatal error,
the system will power cycle to attempt to self-correct the condition.

3.3. Interface Connections
Power Cable End Connector

1 2
3
D6162-1
Figure 3-1: Power Cable End Connector
DRAFT
Pin No. Function Color
1 Battery positive (12/24/32 V Systems) Red
2 Battery negative Black
3 Screen (drain wire) No insulation
Communications Link – J1
Pin No. Signal Name Function
J1-1 BATT_IN_+ Battery positive to CPU
J1-4 CGND Chassis ground
J1-5 BATT_IN_- Battery negative
J1-8 SPEED Transducer paddlewheel
J1-9 TEMP Water temperature
J1-10 XDCR_SENSE Senses transducer
J1-11 DIG_LED_RED_IOPCB Red LED (error) on
J1-12 DIG_LED_GRN_IOPCB Green LED (normal) on
J1-13 GND Logic ground
J1-14 HSB_A HSB I/O – Differential side 1
J1-15 HSB_B HSB I/O – Differential side 2
J1-16 HSB_SHLD HSB I/O –Signal shield

Transducer Link – J2
Ref. Signal Name Function

J2-1 XDCR+ Transducer positive
J2-2 XDCR_SHLD Transducer shield
J2-3 XDCR- Transducer negative
3.4. Spare Parts List

When ordering spares, quote the Spare Description and the Part No.
Spare Description Part No.
CPU PCB R69054
Connector I/O PCB R69055
Perimeter seal (gasket) R69060
Power cable R69053
DRAFT
3.5. Replacing Parts

The following describes how to disassemble and reassemble the DSM250 for replacing
parts.
Access and Replacement

Refer to the unit Spare Parts List and the photographs as specified.
Opening the unit

1. Remove all cables from the connector I/O panel.
2. Place the unit upside-down (Raymarine logo down) and loosen the 8 securing screws.
3. Flip the unit over (right side up) so the screws fall out; then lift the housing and remove
it from the rear cover.
If the housing does not remove easily, it may be that the gasket is sealing the two
halves together. In this case, turn the unit upside-down again. Insert a screwdriver into
the center screw hole on one end and gently pry the rear cover away from the housing
assembly. Return the unit right side up. See Figure 4-1:

DRAFT
D6327-1
Figure 4-1: Removing the Rear Cover from the Main Housing
Removing the CPU board

1. Remove the 8 screws securing the CPU board.
2. Slide your thumbs under the two cutouts on each side of the CPU board and grab the
PCB. See Figure 4-2:
3. Gently and evenly pull the PCB away from the connector I/O board.
D6329-1
Figure 4-2: Removing the CPU Board from the Main Housing

Removing the Connector I/O board

1. Remove the nut retaining the Power connector by turning it counter-clockwise.
2. Remove the screw retaining the grounding wing nut. See Figure 4-3:

3. Remove the PC board.
DRAFT
remove
D6328-1
remove
Figure 4-3: Removing the Connector I/O Board from the Main Housing
Reassembly
1. Reattach and secure the Connector I/O board.
2. Slide the CPU board in at an angle as shown in Figure 4-4: and mate the connectors.
1 1
D6325-1
Figure 4-4: Mating the CPU Board with the Connector I/O Board

3. Sliding the CPU board along the PCB Guides, press the PCB down into the housing, as
shown in Figure 4-5:
PCB guides
DRAFT
D6326-1
Figure 4-5: Using the PCB Guides to Reinsert the CPU Board onto the Main Housing
4. Reattach the eight securing screws.

5. Fit a new case gasket to the groove in the rear cover and lower the housing assembly
onto the gasket.
Note: T o ensure a secure fit, you should always replace the gasket seal with a new
one. Do not reuse old gaskets.
6. Check that the housing and cover assemblies are properly located.
7. Refit the securing screws.


2
1 3
4
CPU/Sonar
board
5 8
DRAFT
6
Connector
I/O board
D6324-1
Housing Power Connector Transducer Connector
Figure 4-6: Rear Cover Removed Showing Location of 8 Retaining Screws

DRAFT

Chapter 5: Drawings
Chapter 4: Drawings
This chapter contains the schematic and layout drawings for the DSM250.
List of Drawings
DSM250 Main Board – CPU Section .................................................................................................................................................................................................. 24
DSM250 Main Board – FPGA Section ................................................................................................................................................................................................ 25
DSM250 Main Board – SDRAM/Flash/USB/Serial Debug ................................................................................................................................................................ 26
DSM250 Main Board – ARCNET Controller ...................................................................................................................................................................................... 27
DSM250 Main Board – Sonar Transmitter and Receiver .................................................................................................................................................................... 28
DSM250 Main Board – Power Supply/Boost ...................................................................................................................................................................................... 29
DSM250 Main Board – Sonar Speed/Temperature .............................................................................................................................................................................. 30
DSM250 Main Board – PCB Layout, Component Side........................................................................................................................................................................ 31
DSM250 Main Board – PCB Layout, Solder Side................................................................................................................................................................................ 32
DSM250 Connector I/O Board – Schematic ......................................................................................................................................................................................... 33
DSM250 Connector I/O Board – PCB Layout ..................................................................................................................................................................................... 34

DSM250 Main Board – CPU Section

5 4 3 2 1
TP281
TP282
TP283
TP284
TP285
TP286
TP287
TP288
TP289
TP290
TP291
TP292
TP293
TP294
TP295
TP296
TP297
TP298
TP299
CLKOUT EXINT0b
EXINT1b
EXINT2b
A[25:0] GPIO[27:0] EXINT3
EXINT4b
GPIO0
GPIO1
A25 TXD0 HSB DMA +3.3V
TP300
A24 RXD0
TP301
A23 XDEOT0
TP302
A22 FPGA_CCLK XDACK0b
TP303
XDREQ0 JTAG/E-ICE Connect
TP304 A21
A20 FPGA_DIN FPGA DMA
TP305 R1 R2 R3 R4
A19 FPGA_DOUT 10K 10K 10K 10K JTAG 20 PIN
TP306
D A18 XDEOT1 CONNECTOR D
TP307
A17 TO JTAG XDACK1b J4
TP308
A16 XDREQ1
TP309
A15 TMS 1 2
TP310
A14 TDO TRSTb 3 4
TP311
A13 TDI GPIO[27:0] TDI 5 6
TP312
A12 TCK GPIO0 TMS 7 8
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
TP313 TP314
A11 TRSTb GPIO1 TCK 9 10
TP315 TP316 TP317
TP318 A10 +3.3V GPIO2 TP319 11 12
TP320 A9 TP321 GPIO3 TP322 13 14
A8 +1.8V GPIO4 RESETb 15 16
TP323 TP324 TP325
TP326 A7 GPIO5 TP327 TP328 17 18
A6 TEST2 GPIO6 19 20
TP329 TP330
TP331 A5 GPIO7 TP332
TP340 A3 GPIO9 TP342 TP380 TP381
A2 GPIO10 TP336 TP337 TP338 TP339
TP343 TP344 TP345
TP335 TP341
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
GPIO13 TP350
ADDR[25:0] GPIO14 J3
TP351
TEST1
TEST2
FID3
FID2
FID1
TRST
TCLK
TDI
TDO
TMS
SSIEN
SSICLK
SSIFRM
U0TXD
SSIIN
VSSO
SSIOUT
U0RXD
VDDO
PA3
PA4
VSSC
DEOT1
CLKOUT
INT0
VDDC
INT1
INT2
INT3
INT4
VSS0
DEOT0
DACK0
DREQ0
DACK1
DREQ1
VDDO
PB4
PB5
PB6
PB7
VSSC
PC0
VDDC
PC1
PC2
PC3
GPIO15 TP352 1 2 +3.3V
GPIO16 TDI + +
R6 22R TP353 3 4
ADDR25 A25 GPIO17 TDO + +
TP354 5 6
1 GPIO10 GPIO18 TEST2 + +
R7 22R 132 TP355
ADDR24 A24 A25 2 TSTA PC4 GPIO11 GPIO19 TP356
131 (CON6AP)
RP1 A24 3 A25 PC5 GPIO12 GPIO20 TP357
A24 PC6 130 J3-5 to J3-6 in for
ADDR23 1 8 A23 A23 4 129 GPIO13 GPIO21 TP358
A23 PC7 JTAG
ADDR22 2 7 A22 A22 5 128 GPIO22 TP359
ADDR21 A21 A21 6 A22 VSSO GPIO14 GPIO23 TP360
3 6 A21 LCDVD0 127
ADDR20 4 5 A20 A20 7 126 GPIO15 GPIO24 TP361
RP2 8 A20 LCDVD1 GPIO25 TP362
VDDO VDDO 125
ADDR19 1 8 22R A19 A19 9 124 GPIO16 GPIO26 TP363 +3.3V
ADDR18 A18 A18 10 A19 PD0 GPIO17 GPIO27 GPIO[27:0]
2 7 123 TP364
ADDR17 A17 A17 11 A18 PD1 GPIO18
3 6 A17 PD2 122
ADDR16 4 5 A16 A16 12 121 GPIO19 J7
RP3 13 A16 PD3 TP126 TP366
VSSO VSSC 120 1
C ADDR15 22R 1 8 A15 A15 14 119 GPIO20 GPIO2 C
ADDR14 A14 A14 15 A15 PD4 GPIO21 GPIO3 2
2 7 A14 PD5 118 3
ADDR13 3 6 A13 A13 16 117 GPIO22 GPIO4
ADDR12 A12 A12 17 A13 PD6 GPIO23 GPIO5 4
4 5 A12 PD7 116 5
RP4 18 115 GPIO6
ADDR11 A11 A11 VDDO INT6 EXINT6 GPIO7 6
1 8 22R 19 114
ADDR10 A10 A10 20 A11 INT7 EXINT7 GPIO8 7
2 7 A10 VDDC 113 8
ADDR9 3 6 A9 A9 21 112 GPIO9
ADDR8 4 5 A8 A8 22 A9 U1 DQM0
111
DQM0
R5 R12 GPIO10 9
A8 DQM1 DQM1 GPIO24 10
RP5 23
VSSO
LH79520 PE2 110 10K 10K GPIO11
11
ADDR7 22R 1 8 A7 A7 24 109 GPIO25 GPIO12
ADDR6 A6 A6 25 A7 PE3 GPIO13 12
ADDR5
ADDR4
2
3
4
7
6
5
A5
A4
A5
A4
26
27
A6
A5
A4
L H 79520 CAS
RAS
SDWE
108
107
106
SCASb
SRASb
SDWEb
GPIO14
GPIO15
13
14
15
RP6 28 105 GPIO16
VDDO DCS0 SCS0b 16
ADDR3 1 8 22R A3 A3 29 104 GPIO26 Keep as close to U18 as possible. GPIO17
ADDR2 A2 A2 30 A3 PE6 100nF as close to VDDA and VSSA. GPIO18 17
2 7 A2 VSSO 103 18
ADDR1 3 6 A1 A1 31 102 GPIO19
A1 SDCKE SCKE 19
ADDR0 4 5 A0 A0 32 101 +1.8V GPIO20
A0 SDCLK SCLK 20
33 100 GPIO21
22R 34 VSSO VDDO GPIO27 GPIO22 21
USB_SLEEPb PH7 PF1 99 22
35 TP367 GPIO23
1
USB_RESETb PH6 CLKIN 98 23
36 97 TP368 D1
BE1 37 BE1 RESETO EXINT6 24
96 R17 BAT54
BE0 38 BE0 RESETI RESETb EXINT7 25
95 100R 2
OEb OE VDDC 26
39 94 TP370
W Eb 40 WE XTALOUT
93 TP371 (CON26)
41 VDDC XTALIN
CS6b CS6 VSSA 92
42 91 TP375
3
CS5b 43 CS5 VDDA
90 TP376
CS4b CS4 XTAL32OUT R19 10M
44 89 TP377
CS3b CS3 XTAL32IN C2 + C3
Y1 100nF
CLKSEL
VDDO
VDDO
VDDO
22uF
VDDC
VSSO
VSSO
VSSO
VSSC
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
CS2
CS1
CS0
PH1
PH0
PF7
PF6
PF5
PF4
PF3
PF2
D15
D14
D13
D12
D11
D10
R20 R21 TP378
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TP85 TP86 TP87 TP419
10K 10K 14.7456MHz RESET CONTROL
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
C4 C5
B POWER FAIL IS CONNECTED TO +5VDD TO PREDICT POWER FALLING. B
22pF 22pF
SET AT 8.06V ON INPUT LINE.
+3.3V
TP379 F_BATT+ +3.3V
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
3
+3.3V
CS2b
CS1b
2 R15
CS0b
D28 10K
FPGA_RESET DATA[15:0]
R24 R16 BAT54
HSB_RESETb
10K 180K U2
FPGA_PGMb
FPGA_DONE 1 VCC RESET 6 RESETb
2 5
1
FPGA_RESET_OUT GND MR
TP382 +3.3V TP369 3 4
PFI PFO EXINT0b
TP383
TP384 DIAG_ENb MAX6343
R25 180R TP385 R18
R26 R27 C1 TP372
DIG_LED_RED_IOPCB
(10K) (10K) 1nF 33K TP374
DIG_LED_GRN_IOPCB
R28 180R TP386 +3.3V SDRAM_SEL_0 TP387
R29 SDRAM_SEL_1 TP388
THIS TO GO TO IO BOARD FOR LED.
10K
TP90 TP89 TP88
R30 R31 R32 R33
(10K) (10K) (10K) (10K) R34 R35
10K 10K CHIP SELECTS EXTERNAL INTERRUPTS
TP389 SYSTEM_INFO_3
TP390 SYSTEM_INFO_2 MEMORY MAP EXTERNAL INTERRUPTS
TP391 SYSTEM_INFO_1 CS0b = PROGRAM FLASH EXINT0b = POWER FAIL
TP392 SYSTEM_INFO_0 CS1b = FPGA EXINT1b = ARCNET CONTROLLER
CS2b = COM20022 (ARCNET) EXINT2b = USB RECEIVER BYTE IN FIFO
A R36 R37 R38 R39 CS3b = USB EXINT3 = FPGA A
10K 10K 10K 10K CS4b = EXINT4b = USB TX EMPTY
CS5b = EXINT5 = NOT AVAILABLE
CS6b = EXINT6 = FLASH READY
PLACED AROUND U1
+3.3V DSC0 = SDRAM0 EXINT7 = NOT USED
+1.8V
TP173 TP175 DSC1 =
U1 BYPASS U1 BYPASS U1 BYPASS U1 BYPASS U1 BYPASS U1 BYPASS U1 BYPASS U1 BYPASS U2 BYPASS U1 BYPASS U1 BYPASS U1 BYPASS U1 BYPASS TP172 TP174
C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 + C20 + C21 + C22 C23 C24 C25 C26 C27 C28 C29 C30 + C31 + C32
1nF 1nF 1nF 1nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 22uF 22uF 22uF 1nF 1nF 1nF 47nF 47nF 47nF 47nF 47nF 22uF 22uF Title
CPU
Size Document Number Rev
C 4519-002 J
Date: Thursday, February 20, 2003 Sheet 1 of 7
5 4 3 2 1

Chapter 5: Drawings
DSM250 Main Board – FPGA Section

5 4 3 2 1
+3.3V TP394 TP395 TP396 TP397 TP398 TP399 TP400 TP393 TP401 TP402 TP403 TP404 TP405 TP84 TP81 TP82 PROGRAMMING MODE SELECT
TP59 TP60 TP61

R44
BE0
4K7 BE1 M0
DUMMY OEb
M1
FPGA_RESET_OUT
XDEOT1 M2
TEMP_SEL_4 XDREQ1
TEMP_SEL_3 XDACK1b
TEMP_SEL_2
R46 R47 R48
TEMP_SEL_1 ADDR[25:0]
(0R0) (0R0) (0R0)
BOOST_CURRENT_SENSE_B0 SONAR_IO_9 W Eb
SONAR_IO_8 TP83
SDRAM_DATA[15:0]
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
D D
FPGA_RESET
+1.8V
SDRAM_DATA0 CS3b CS1b
TP43
USB_RDb
4
3
2
1
4
3
2
1
4
3
2
1
SDRAM_DATA1 TP44 JTAG INTERFACE FOR XILINX
SDRAM_DATA2 USB_WR FPGA_TDI
TP45 RP9 RP10 RP11 +3.3V
SDRAM_DATA3 TP46 4K7 4K7 4K7 FPGA_TCK
SDRAM_DATA4 FPGA_TDO
TP47 +3.3V
SDRAM_DATA5 TP48
SDRAM_DATA6 TP49 TP62 TP63 TP64 TP65
5
6
7
8
5
6
7
8
5
6
7
8
SDRAM_DATA7 TP50
SDRAM_DATA8 TP51 J5
SDRAM_DATA9 TP52
SDRAM_DATA10 TP53 1
SDRAM_DATA11 TP54 2
SDRAM_DATA12 TP55 3
SDRAM_DATA13 FPGA_TCK 4
TP56
SDRAM_DATA14 TP57 5
FPGA_TDO 6
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
SDRAM_DATA15 TP58
DATA[15:0] FPGA_TDI 7
8
VCC
TCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VSS
VCC
VCCINT
I/O
I/O
I/O
I/O
VSS
I/O
I/O
I/O
VCCINT
GCK3
VCC
VSS
GCK2
I/O
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O
VCCINT
VCC
VSS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WEb
CSb
TDI
VSS
TDO
FPGA_TMS 9
SDRAM_ADDR[12:0] SDRAM_DATA[15:0] FPGA_TMS
1 156 (no fit)
U4 VSS VCC TP407
2 TMS CCLK 155 FPGA_CCLK
SDRAM_DATA0 3 154
SDRAM_ADDR0 SDRAM_DATA0 SDRAM_DATA1 I/O DOUT FPGA_DOUT J8
23 A0 DQ0 2 4 I/O DIN 153 FPGA_DIN DATA0
SDRAM_ADDR1 24 4 SDRAM_DATA1 SDRAM_DATA2 5 152 1 2
SDRAM_ADDR2 A1 DQ1 SDRAM_DATA2 SDRAM_DATA3 I/O I/O DATA1 +1 +2
25 A2 DQ2 5 6 I/O I/O 151 3 +3 +4 4
SDRAM_ADDR3 26 7 SDRAM_DATA3 SDRAM_DATA4 7 150 DATA2
SDRAM_ADDR4 A3 DQ3 SDRAM_DATA4 SDRAM_DATA5 I/O I/O DATA3 (CON4AP)
29 A4 DQ4 8 8 I/O I/O 149
SDRAM_ADDR6 A5 DQ5 SDRAM_DATA6 SDRAM_DATA7 I/O I/O DATA5
31 A6 DQ6 11 10 I/O I/O 147 TP409
SDRAM_ADDR8 A7 DQ7 SDRAM_DATA8 I/O I/O DATA7
33 A8 DQ8 42 12 VSS I/O 145
SDRAM_ADDR9 34 44 SDRAM_DATA9 13 144
SDRAM_ADDR10 A9 DQ9 SDRAM_DATA10 VCC VSS
22 A10 DQ10 45 14 VCCINT VCC 143
SDRAM_ADDR11 35 47 SDRAM_DATA11 SDRAM_DATA9 15 142
SDRAM_ADDR12 A11 DQ11 SDRAM_DATA12 SDRAM_DATA10 I/O VCCINT DATA8
36 A12 DQ12 48 16 I/O I/O 141
C 50 SDRAM_DATA13 SDRAM_DATA11 17 140 DATA9 C
DQ13 SDRAM_DATA14 SDRAM_DATA12 I/O I/O DATA10
DQ14 51 18 I/O I/O 139
53 SDRAM_DATA15 19 138 DATA11
DQ15 SDRAM_DATA13 VSS I/O PLACE ON EDGE OF BOARD FOR EASY ACCESS TO POD.
20 I/O VSS 137
TP373 40 38 SDRAM_DATA14 21 136 DATA12
N/C CLK SDRAM_DATA15 I/O I/O DATA13 TP73 TP74
22 I/O I/O 135
DQMH 39 SDRAM_CLK 23 I/O
U3 I/O 134 DATA14
15 SDRAM_DQMH 24 133 DATA15
+3.3V DQML I/O XC2S300E I/O
25 VSS I/O 132 SONAR_DRIVE_3
BA0 20 26 VCC VSS 131
SDRAM_DQML
BA1 21
SDRAM_BA0
27
28
I/O
VCCINT
XC2S300E VCC
I/O
130
129 SONAR_DRIVE_2
3 VDDQ CKE 37 29 I/O VCCINT 128
9 16 SDRAM_BA1 30 127
VDDQ WE SDRAM_CKE I/O I/O SONAR_DRIVE_1
43 19 31 126 TP77
VDDQ CS I/O I/O SONAR_DRIVE_0 SONAR_ACTIVE
49 32 125 TP78
VDDQ SDRAM_W E_b VSS I/O
33 I/O VSS 124
1 17 SDRAM_CS_b 34 123
VDD CAS SDRAM_CAS_b I/O I/O SONAR_SENSE_1
14 VDD RAS 18 35 I/O I/O 122 SONAR_SENSE_0
27 SDRAM_RAS_b 36 121
VDD I/O I/O BOOST_DISCHARGE_0
VSSQ 6 37 VCCINT I/O 120 BOOST_DRIVE_0
28 12 38 119 TP79 TP80
GND VSSQ VCC VCCINT
41 GND VSSQ 46 39 VSS VCC 118
54 52 SDRAM_ADDR0 40 117 R11
GND VSSQ TP152 TP153 TP154 TP155 TP156 SDRAM_ADDR1 I/O VSS
41 I/O I/O 116 BOOST_DISCHARGE_1 4K7
SDRAM_ADDR2 42 115
SDRAM_ADDR3 I/O I/O BOOST_DRIVE_1
MT48LC8M16A2 43 114
SDRAM_ADDR4 I/O I/O SONAR_IO_0
TP157 TP158 TP159 TP160 TP161 44 I/O I/O 113 SONAR_IO_1
SDRAM_ADDR5 45 112
46 I/O I/O 111 SONAR_IO_3
SDRAM_ADDR7 47 110
48 I/O I/O 109 SONAR_IO_5
SDRAM_ADDR9 49 108
I/O I/O SPEED_IN
M1 50 M1 INITb 107 EXINT3
51 VSS PROGRAMb 106 FPGA_PGMb
52 105
VCCINT
VCCINT
VCCINT
M0 M0 VCC
DONE
GCK1
GCK0
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
M2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B B
100
101
102
103
104
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
TP217 SDRAM_ADDR0
TP31 SDRAM_ADDR1
TP32 SDRAM_ADDR2
TP33 SDRAM_ADDR3
SDRAM_ADDR4 M2
TP34
TP35 SDRAM_ADDR5 SONAR I/O FUNCTIONS
TP36 SDRAM_ADDR6 SONAR_IO_0 = LM 1971 LOAD
TP37 SDRAM_ADDR7
SDRAM_ADDR8 SONAR_IO_1 = LM 1971 DATA
TP38
SDRAM_ADDR9 SONAR_IO_2 = LM 1971 CLK
TP39
TP40 SDRAM_ADDR10 SONAR_IO_3 = RECEIVER ENABLE
SDRAM_ADDR10
SDRAM_ADDR11
SDRAM_ADDR12
TP41 SDRAM_ADDR11 SONAR_IO_4 = PA FEEDBACK ENABLE

TP42 SDRAM_ADDR12 SONAR_IO_5 = WAVEGEN FEEDBACK ENABLE
FPGA_DONE SONAR_IO_6 = UNUSED
SONAR_IO_7 = 50/n200
TEMP_CHARGE
TEMP_REF_LOW
TEMP_REF_HIGH
TEMP_SEL_TEMP
+3.3V
TEMP_SEL_REF U3 Bypass
WAVEGEN_DTOA[7:0] WAVEGEN_DTOA7 TEMP_SEL_0
WAVEGEN_DTOA6 SONAR_ADC_CONV
U4 BYPASS for Control WAVEGEN_DTOA5 SONAR_ADC_DI
+3.3V U4 BYPASS for Output
(Pins 1, 14, 27) WAVEGEN_DTOA4 SONAR_ADC_DO
(Pins 3, 9, 43, 49) C63 C64 C65 C66 C67 C68 C69 C70
WAVEGEN_DTOA3 SONAR_ADC_CLK 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF
WAVEGEN_DTOA2 BOOST_CHARGED_1
WAVEGEN_DTOA1 BOOST_CHARGED_0
WAVEGEN_DTOA0 BOOST_POWER_PWM_1
C33 C34 C35 C36 + C37 C38 C39 C40
47nF 47nF 47nF 47nF 22uF 1nF 1nF 1nF BOOST_POWER_PWM_0
TP67 TP68 TP69 TP70 TP71 TP72
SONAR_IO_6
+3.3V
SONAR_IO_7 U3 Bypass
SONAR_PREAMP_CLK
XDCR_SENSE_PWM_0 SONAR_PREAMP_DATA
BOOST_ENABLE_1
A A
BOOST_ENABLE_0
+ C55 + C56 + C57 + C58 C59 C60 C61 C62
SONAR_PREAMP_CS_b 22uF 22uF 22uF 22uF 47nF 47nF 47nF 47nF
SDRAM_CLK
CLKOUT PLACED AROUND U3
TP177 TP179
TP176 TP178
4
3
2
1
+1.8V
U3 BYPASS TP147 TP148 TP149 TP150
RP12
4K7
C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 + C53 + C54 Title
5
6
7
8
47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 22uF 22uF FPGA
C 4519-002 J
5 4 3 2 1

DSM250 Main Board – SDRAM/Flash/USB/Serial Debug

5 4 3 2 1
DATA[15:0]
ROM footprint to take
2MB, 4MB, and 16MB. +5V
ADDR[25:0]
DATA0 TP224 +3.3V TP408
TP192 ADDR0 +3.3V DATA1 TP225 TP221
TP193 ADDR1 DATA2 TP226 U6
TP194 ADDR2 DATA3 TP227 TP406
37
VCC_IN 23
TP195 ADDR3 U5 DATA4 TP228 R165 R166 R49 TP410 20
THESE TP'S ARE NOT ADDR4 ADDR1 DATA0 DATA5 CS3b CS DATA0
TP196 25 29 TP229 10K 10K 10K 21 19
VCC
D ADDR5 ADDR2 A0 O0 DATA1 DATA6 WEb WE D0 DATA1 D
FOR USE. RESERVED TP197 24 31 TP230 22 18
ADDR6 ADDR3 A1 O1 DATA2 DATA7 OEb OE D1 DATA2
FOR ATE. TP198 23 33 TP231 17
TP199 ADDR7 ADDR4 A2 O2 DATA3 DATA8 TP232 D2 DATA3
22 A3 O3 35 USB_RESETb 1 EXTRSTb D3 16
TP200 ADDR8 ADDR5 21 38 DATA4 DATA9 TP233 2 15 DATA4
ADDR9 ADDR6 A4 O4 DATA5 DATA10 USB_SLEEPb SLEEPb D4 DATA5
TP216 TP248 TP280 TP201 20 40 TP234 +3.3V 3 14
ADDR10 ADDR7 A5 O5 DATA6 DATA11 EXINT4b TXEb D5 DATA6
TP202 19 42 TP235 4 13
ADDR11 ADDR8 A6 O6 DATA7 DATA12 EXINT2b RXFb D6 DATA7
TP203 18 44 TP236 5 12
ADDR12 ADDR9 A7 O7 DATA8 DATA13 USB_WR WR D7
TP244 TP245 TP246 TP204 8 30 TP237 6
ADDR13 ADDR10 A8 O8 DATA9 DATA14 USB_RDb RDb ADDR1
TP205 7 32 TP238 7
A9 O9 ADD1
3
TP206 ADDR14 ADDR11 6 34 DATA10 DATA15 TP239 TP183 TP412 10 8 ADDR2
TP247 TP207 ADDR15 ADDR12 A10 O10 DATA11 R62 R50 R51 R52 VCC_OUT ADD2 ADDR3
5 A11 O11 36 TP411 11 GND ADD3 9
TP208 ADDR16 ADDR13 4 39 DATA12 TP413 TP240 10K 10K 10K D4 10K
TP209 ADDR17 ADDR14 A12 O12 DATA13 TP415 TP416 BAV70
3 A13 O13 41
TP210 ADDR18 ADDR15 2 43 DATA14 L4
TP's for flash are set for TP211 ADDR19 ADDR16 A14 O14 DATA15 (DLP-USB1)
1 A15 O15/A-1 45
TP212 ADDR20 ADDR17 TDK MMZ2012S800A
2
ATE. Do not change 48 13
TP213 ADDR21 ADDR18 A16 N/C
numbers. 17 A17 WP# 14
TP214 ADDR22 ADDR19 16 R64 0R0
TP241 TP242 TP215 ADDR23 A18
9 A19 BYTEb 47 CS4b
TP417 ADDR24 ADDR21 10 15
TP418 ADDR25 A20 READY
RESETb 12 RESETb
CS0b 26 CEb WEb 11 WEb
28 R53 1K0
GND
GND
OEb OEb
C
R54 (10K) C
R120 (0R0) TP414 TP243
EXINT6
ADDR20
27
46
TP182 LH28F128 R119 0R0
R125 0R0
ADDR20
TP218
ADDR22
DEBUG ONLY. NOT FOR PRODUCTION.
ADDR[25:0]
U7
ADDR13 ADDR0 23 2 DATA0 +3.3V

ADDR1 A0 DQ0 DATA1
SDRAM SELECTION 24 A1 DQ1 4
ADDR14 ADDR2 25 5 DATA2
SIZE R57 R58 R59 ADDR3 A2 DQ2 DATA3
26 A3 DQ3 7
64/128Mb OUT IN OUT ADDR12 ADDR4 29 8 DATA4 R55
256Mb IN OUT IN ADDR5 A4 DQ4 DATA5 1K0
30 A5 DQ5 10
ADDR6 31 11 DATA6
R57 R58 R59 ADDR7 A6 DQ6 DATA7 TP420 TP421
32 A7 DQ7 13
(0R0) 0R0 (0R0) ADDR8 33 42 DATA8
A8 DQ8 RXD0
3
TP422 TP423 ADDR9 34 44 DATA9 R56
ADDR10 A9 DQ9 DATA10 DIAG_RXD Q1
22 A10 DQ10 45 1
ADDR11 35 47 DATA11 BC817 J6
A11 DQ11
3
36 48 DATA12 4K7 DIAG_TXD
A12 DQ12 DATA13 DIAG_RXD 1
2
B
DQ13 50 2 B
20 51 DATA14 D5
BA0 DQ14 DATA15 BAV70 TP181 3
21 BA1 DQ15 53 4
TP424 TP425 TP426 TP427 TP428 TP429 TP430 TP431
5
RP7 TP432
2
1 8 38 40 +3.3V 9600CONN3
SCLK CLK N/C
2 7 37 +5V
SCKE CKE
DQM1 3 6 39 DQMH VDD 1 TO BE PLACED ON THE EDGE OF
DQM0 4 5 15 DQML VDD 14 BOARD SERVICE CONNECTION.
TP436 TP437 TP438 TP439 TP440 TP441 TP442 TP443 27
22R VDD R60 R61 THIS IS THE SAME SMT
RP8 270R 270R CONNECTOR USED FOR CCFL.
VDDQ 3
1 8 19 9 IT IS CHEAP AND ALREADY ON
SCS0b CSb VDDQ TP433 HAND.
SDWEb 2 7 16 WEb VDDQ 43
SCASb 3 6 17 CASb VDDQ 49
TP435
SRASb 4 5 18 RASb DIAG_TXD
3
22R 6 TP180 R63
VSSQ 1 Q2
28 GND VSSQ 12 TXD0
41 46 BC817
GND VSSQ 4K7
54 GND VSSQ 52
2
U7 BYPASS for
A +3.3V U7 BYPASS for Output Control (Pins A
U5 Bypass (Pins 3, 9, 43, 49) MT48LC8M16A2
1, 14, 27)
+ C71 C72 C73 C74 C75 C76 C77 + C78 C79 C80 C81 Title
22uF 47nF 1nF 47nF 47nF 47nF 47nF 22uF 1nF 1nF 1nF SDRAM/FLASH/USB/SERIAL DEBUG

B 4519-002 J

5 4 3 2 1

Chapter 5: Drawings
DSM250 Main Board – ARCNET Controller

5 4 3 2 1
DATA[15:0] 5V_DATA[15:0]
+3.3V
+5V 5V_DATA0 TP444

5V_DATA1 TP445
5V_DATA2 TP446
5V_DATA3 TP447
U8 5V_DATA4 TP448
23
24
1
D 5V_DATA5 TP449 D
DATA0 21 3 5V_DATA0 5V_DATA6 TP450
VCCB
VCCB
VCCA
DATA1 B1 A1 5V_DATA1 5V_DATA7 TP451
20 B2 A2 4
DATA2 19 5 5V_DATA2
18 B4 A4 6
16 B6 A6 8
14 B8 A8 10
5V_DATA13 TP457 +5V +5V_ISO +5V_ISO PLACE T4, R175 AND R176 CLOSE
2 5V_DATA14 TP458 TO U10 WHILE PLACING T8, R177
WEb DIR 5V_DATA15 TP459 AND R178 CLOSE CONNECTOR.
CS2b 22 OE L3
GND
GND
GND
R65
+5V TDK MMZ2012S800A 1K0
L18
11
12
13
74LVC4245 R66 R67 R68 R175 BLM11B121SB
U9 TP461 TP462 TP463 TP543
COM20022 4K7 4K7 4K7 U10 TP219
20
32
43
8
1 16 TP66 (0R0)
VDD1 VDD2 HSB_A
+3.3V
VDD
VDD
VDD
VDD
+5V 5V_DATA0 1 24 6 12
AD0 PULSE1 D A
4
5V_DATA1 2 29 5 13
C AD1 nTXEN DE B C
5V_DATA2 4 28 3
5V_DATA3 AD2 RXIN R T4 TP220 T8
7 D3 PULSE2 25 4 RE N/C3 14
U11 5V_DATA4 9 11 TP91
23
24
D4 N/C2
1
5V_DATA5 10 27 TP464 C175 C174 C181 7 10
6
DATA8 5V_DATA8 5V_DATA6 D5 N/C1 TP465 TP467 N/C1 ISODE
21 3 12 19 2 15
VCCB
VCCB
VCCA
DATA9 B1 A1 5V_DATA9 5V_DATA7 D6 N/C2 GND1A GND2A HSB_B

20 4 13 40 TP466 C82 22pF 8 9 R176
DATA10 B2 A2 5V_DATA10 5V_DATA8 D7 nREFEX (22pF) (22pF) (22pF) GND1B GND2B L19
19 B3 A3 5 47 D8 XTAL2 22
DATA11 18 6 5V_DATA11 5V_DATA9 48 Y2 R70
B4 A4 D9 IL485
DATA12 17 7 5V_DATA12 5V_DATA10 3 R69 1K0 (0R0) BLM11B121SB
DATA13 B5 A5 5V_DATA13 5V_DATA11 D10
16 B6 A6 8 5 D11 4M3 C83
DATA14 15 9 5V_DATA14 5V_DATA12 14 19MHz 22pF
DATA15 B7 A7 5V_DATA15 5V_DATA13 D12 9600TOKOCM1 (9600TOKOCM1)
14 B8 A8 10 15 D13 XTAL1 21
5V_DATA14 16
5V_DATA15 D14 TP469
2 DIR 17 D15 nINTR 34
ISO
22 OE TC 38
ADDR1 44 26 TP471
GND
GND
GND
ADDR2 A0/nMUX BUSTMG

45 A1
ADDR3 46
TP472 A2/ALE
42 nIOCS16 DREQ 33
11
12
13
74LVC4245 39 35
nRD/nDS nDACK +3.3V +5V_ISO
37 nWR/DIR
36 31
GND
GND
GND
GND
GND
GND
nCS nRST U8 BYPASS U11 U10 ISOLATED SIDE BYPASS
B B
BYPASS
18
30
41
23
11
+ C182 C172 C173
6
C84 C85 C86 C87 22uF 1nF

1nF 47nF 47nF 1nF 100nF
ADDR[25:0]
OEb
ISO
WEb
TP473
CS2b
+5V
HSB_RESETb U9 BYPASS U8 BYPASS U11 BYPASS U10 BYPASS
XDACK0b
XDREQ0
+ C88 C89 C90 C91 C92 C93 C94 C95 C96
PLACED AROUND 22uF 47nF 47nF 47nF 47nF 47nF 47nF 100nF 1nF
XDEOT0
U8,9,10 & 11
EXINT1b
TP185 TP187
A TP184 TP186 A
Title
ARCNET CONTROLLER

B 4519-002 J

5 4 3 2 1

DSM250 Main Board – Sonar Transmitter and Receiver

5 4 3 2 1
+5V_RX
+5V_RX
R71
R72 22R
180R
TP474
TP475
R73 +2.5V C97 + C98

+ C99 C100 180R 1nF 22uF
22uF TP276
TP16 TP277 1nF R74
1K0
R76 1K1 RX RX
XDCR+ RX RX RX TP476
D TP477 D
T1 10mH
D6 4 3 C101 C102 +5V_RX
J2 TP479 SMBJ5.0CA
1 1nF 2.2nF
1 XDCR_SHLD
2 2 5 2
TP481 TP482
8
3 U12A C105 TP480
3 TP483 TP484 RX R77 T2 1.16mH + C106
3 +
MOLEX RX D7 R78 1 4 3 1nF C107 22uF
SMBJ5.0CA 6 1 2 R79 1nF
-
10K 1K5
R80 1K1 5K6 LM6152A C108 C109 5 2 RX
XDCR- RX RX TP487 TP488 TP489 TP490
4
8200pF 560pF TP485 TP486 U16A U14
TP493
8
TP274 R81 U12B TP491 TP492 4066
14
TP17 6 1 5 R82 8 1
RX + VCC CONV SONAR_ADC_CONV
TP494 7 1 2 2 5
9
TP15 CH0 DIN SONAR_ADC_DO
5K6 6 3 6
8 10
- CH1 DOUT SONAR_ADC_DI
TP496 270R TP275 4 7
GND CLK SONAR_ADC_CLK
LM6152A C110 C177
R83 1K0 U17A
13
RX MCP42050 TP278 1nF 100pF LTC1861
7
TP191
RX RX
C183 C111 10pF RX U17B TP93 TP249 TP500 TP501
7
+5V_RX MCP42050 RX RX R170 U18A
(100pF) U13 TP498 100R 74ACT125
7 5 SONAR_IO_3
2 VCC S1 6 3 2 SONAR_PREAMP_CLK
C112 3 5
RX 1nF GND S2 C178
S3 4
1 (10pF)
EN SONAR_IO_7
14
C113 10pF
1
DG9431_allegro
RX RX
+5V_RX
U17C TP502
C
TP250 TP503 C
7
14 R171 U18B
TP504 VDD 100R 74ACT125
12 SHDNb CLK 2
C114 11 3 6 5
RSb SDI SONAR_PREAMP_DATA
SDO 13
1nF 4 1
VSS CSb C179
14
T3 (10pF)
4
C115 30 x 19 DS CORE RX MCP42050
1 XDCR+ +5V_RX
+12V (1nF/1kv) TP505
TP507
7
C116 R172 U18C
D8 MBR0530T1 TP508 6 RX 100R 74ACT125
2
2.2nF/1KV R84 TP251 8 9
TP509 TP510 TP511 TP512 TP513 SONAR_PREAMP_CS_b
6
2
TP75 Q3 7 3 XDCR- 100R U16B
RESERVOIR
R85 U19A 8 4066
14
2 7 1 D10 C117 R91 D9 C180
SONAR_DRIVE_0
10
14
R22 9 5 3 BAV99 11 10 (10pF)
1K0 TC4427 R86 22R IRFIB7N50A 33R
R92 R93 10 3K0
3
10K (2K4) R42 TP514 47nF R94 TP94

8
3
33R 100R
MURS360T
12
TP470 TP515 +5V_RX
7
RX SONAR_IO_4
C118 TP279
(100nF)
+12V U16C R75
TP517 TP518
8
RX 4066 U15B 22R
14
+ 5
4 3 7
C119+ C120 6 TP478
-
10uF/25V 100nF C121
D11 MBR0530T1 TP519 TP95 LMC6032
2
2.2nF/1KV C103 + C104
4
TP521 TP522
6
TP76 TP520 Q4 1nF 22uF
5
R95 U19B
SONAR_IO_5
4 5 1 D12
SONAR_DRIVE_1
R23
B
1K0 TC4427 R96 22R IRFIB7N50A 33R TP96 RX RX B
8
R99 U15A TP495
3
R100 (2K4) 3
1
3
+
10K TP497 +5V 1
MURS360T
2 -
C122 LMC6032
(100nF) C123
4
R101 47nF
TP523 TP524 TP527 RX
WAVEGEN_DTOA[7:0] C124
R102 3K0 4K7
TP525 U20
7
WAVEGEN_DTOA7
VDD
R103 1
TP526 1K5 47nF VREF TP528 RX
R104 3K0
WAVEGEN_DTOA6 TP529 8 2
IN OUT
R105
TP530 1K5 R106 4
R107 3K0 LOAD
5 DATA
WAVEGEN_DTOA5 TP531 + C187 4K7 6 +5V_RX
GND
22uF CLK
R108
TP532 1K5 C125 +5V
R109 3K0 LM1971M
3
WAVEGEN_DTOA4 TP533 1nF
R110 U16D C126
13
14
TP534 1K5 TP535 TP536 TP537 RX 4066
14
R111 3K0 1nF
WAVEGEN_DTOA3 TP538 8 9 11 12
SONAR_IO_0
R112 74ACT125
TP539 SONAR_IO_1
1K5 U18D
SONAR_IO_2
R113 3K0
7
WAVEGEN_DTOA2 TP540
6
A A
R114
TP252 1K5
R115 3K0
WAVEGEN_DTOA1 TP253 For shield can around receiver.
R116 MP1 MP2 MP3 MP4 RX

TP254 1K5
R117 3K0
WAVEGEN_DTOA0 TP255
1
R118
1
Title
3K0
Sonar Transmitter and Receiver
RX RX RX RX Size Document Number Rev
C 4519-002 J
5 4 3 2 1

Chapter 5: Drawings
DSM250 Main Board – Power Supply/Boost

5 4 3 2 1
HS4 FOR D13
L5
TP101 TP22
D13 B_BATT+
BOOST POWER
MTG1
MUR1520 BEADA
TP1 TP2 TP4 TP5 TP7 TP8 SHORT, WIDE TRACES! SHORT, WIDE TRACES!
1
L6
TP97 TP99 TP102 TP23
J1 L7 D14 F_BATT+
BATT_IN_+ LOGIC POWER
1
D 2 15385 SMALL BEAD
D
3 10BQ060
4 C185 L8
5 TP24 TP163
2
(100nF)
6 D15 T5
7 C129
C128 10nF C130
8 SPEED 100nF 220uF/50V 3030-241 RECEIVE GROUND
V56ZA2 C127
9 TEMP 100nF BIPOLAR
C164 L15 MCB-1206
10 XDCR_SENSE
11 DIG_LED_RED_IOPCB RX
(1nF/1kv)
4
MOLEX 16-PIN
12 DIG_LED_GRN_IOPCB
(SMALL BEAD) C186 L9
13 (100nF) TP98 TP100 TP25 TP164
14 L10
15 BATT_IN_-
16 BOOST GROUND
SHORT, WIDE TRACES! 15385 TP103 TP105 SHORT, WIDE TRACES! BEADA
D3 +5V_ISO
+5V +5V_ISO TP13
TP9 TP11 TP14
L11
TP26 TP165
10BQ060 L17 + C170 C171
TP10 TP12 10uF/25V 100nF
TP19 D17 TP106
BAS16 LOGIC GROUND
C131 TP30 SMALL BEAD
HSB_A
4
R13 TP111 100nF
TP20 (357K) SMALL BEAD ISO
F_BATT+ TP104 L16
BUCK SMPS U22 T7 V=5.1V TP115 TP21 +5V +5V_RX TP162
HSB_B TP112 BOOST_CURRENT_SENSE_B0
4 6 CTX15-2A
VIN BST
3
13 2 R40
TP18 HSB_SHLD NC13 SW Q5
15 10 1
2
+ R121 ON BIA MCB-1206 TP542 BC817
14 SYN FB 12
C132 C133 (43K) 1 3 + C134 + C166 47K D16
C184 100uF/100V 100nF GD1 NC3 R122 330uF/16V 22uF BAS16 R41
8 5
2
C TP108 GD8 NC5 15K R174 (10K) C
9 GD9 NC7 7
L1 R179 16 11 TP166 TP167 47K
0R0 10nF/1kv C168 GD16 VC TP113 TP107 SONAR RESERVOIR CHARGING CIRCUITS
(BLM21P300) R14 LT1956 TP114
ISO (22K) (1nF) D19 RX
3
OPTION TO TP109 R123
ISO GND. 10BQ060 4K7
B_BATT+ T6
ISO R124 Q7 TP129 3030-486 TP27 BOOST RESERVOIR
2K2 IRFR5305 D20
3 4 RESERVOIR
TP110
2
R126 MUR1520
C135 10K + THIS TRACE MUST BE SHORT AND WIDE!
TP151 TP130 TP131
10nF C136 C137
1
1nF TP128 100uF/100V R163 C163
TP127
3
R127
1 Q8 47 2W 1nF/1KV
SEE LAYOUT CONSIDERATIONS IN DATA SHEETS BOOST_ENABLE_0 BC817
UNDERVOLTAGE LOCKOUT 1K0
2
R128 +12V
10K
12 V STEP UP + C165
LINEAR SUPPLIES 10uF/25V C140
TP117 TP120 TP121 +12V V=11.7V +5V 100nF C141 + C138 + C139
L14 D21 TP116 TP28 +3.3V TP136
U26
LT1086 2.2nF/1KV
3 2 D27 (MBR0530T1) 470uF/200V 470uF/200V
15uH VIN VOUT1
VOUT2 4
+5V 10BQ060 R129 + C142 D22
U23 TP132 TP133 TP134 Q9
2
ADJ
47K 470uF/25V C148 R141 C149 + C150 R161 R130 R134

B 7 5 100nF 909R 100nF 470uF/25V U24A R131 180K B
VIN SW TP122 TP171 (68R) 68R
6 SS FB 2 BOOST_DRIVE_0 2 7 1
4 3 TP123 TP169
1
C143 GD4 NFB R132 TC4427 22R IRFP250N TP541

8 1
MURS360T
100nF GD8 VC TP119 5K6 R133
10K R160 (2.2K)
8
3
LT1371
R144 TP135 R173
R135 1K5 +12V C162 180K
2K2 +3.3V (100nF)
TP118 C145
C144 TP434
4.7nF R136 100nF TP168
1K0 TP138
TP137
8
6
5
C146 R164 C147 1nF
47nF (180R) U25 2 TP139
+
BOOST_CHARGED_0 7
TP365 3 TP145
-
LM311
C167 TP125 TP29 +1.8V R137 R138 R139

U27
1
4
(330pF) LM317 1K0 10K 82 3W
3 VIN VOUT1 2
4 R162
VOUT2 TP146
TP140 TP141
ADJ
C152 R145 C153 + C154

100nF 909R 100nF 470uF/25V R140 100K +12V
BOOST_POWER_PWM_0
TP124 TP170
1
1K0 + C151
2
1uF
TP142 TP143 TP144
6
Q10
R146 U24B R142
390R 4 5 1
BOOST_DISCHARGE_0
A R143 TC4427 IRFIB7N50A A
10K 0R0
3
1
3
Title
Power Supply/Boost
C 4519-002 J
5 4 3 2 1

DSM250 Main Board – Sonar Speed/Temperature

5 4 3 2 1
+5V
+12V
R147 R148
22K
3
2K7
R150 47K
R149 D23
470R BAV70
U28A
TP257
3
TP256
2
TP258 D24 TP259 7 +
2
1 SPEED_IN
SPEED 3 1 6 - TP189
D D
LM339
12
5V6
R151 C155 D25 R152

10K 10nF BAV70 22K
+5V
2
R153
TP260
R154 4K7
R155
2
4K7
TP261 C156 2K7
D26 47nF U28B
3
3 BAV99 U29A
TEMP TP262
4066 5
14
+
TP263 2 TEMP_REF_HIGH
1 2 4 -
C157 LM339 TP264
1
TP265 TP266 TP267 TP268
12
220nF
13
R156
7
TEMP_CHARGE
4K7 R157
U29B
TEMP_SEL_REF
4066 2K7
14
TP269
TEMP_SEL_TEMP
3
11 10
TP270 9 U28C
TEMP_SEL_0 MUST BE 1%. +
14 TEMP_REF_LOW
C R158 8 C
TEMP_SEL_1 -
10K LM339
12
TP271
7
TEMP_SEL_2
12
R159
TEMP_SEL_3 TP190
4K7
U29C
4066
14
4 3
5
TP92
+5V R8
XDCR_SENSE_PWM_0
4K7 C160
C158 10nF
47nF
+5V +5V
U29D
TP272 4066 +3.3V
14
8 9 C159
47nF R9
1
R10 4K7
TP222 TP273
3
RT1 3K0 U28D
10K NTC 11
PLACED BY PA FETS +
R169 13
7
SONAR_SENSE_0
B
t XDCR_SENSE 10 - TP188 B
C161 1K0 C176 LM339

2
12
10nF 10nF
U30A
TP499 4066
14
1 2
1
RT2
10K NTC
PLACED BY D13 OR
t
13
D16 DIODE
7
2
U30B
TP506 4066
14
11 10
1
RT3
10K NTC
PLACED BY Q7 FET
t
12
+5V
7
2
+3.3V F_BATT+
C169
47nF
2
R168 U30D
10K TP223 4066
14
A U30C D2 A
TP516 4066 BAV99 3 8 9
14
4 3
1
RT4 R167
10K NTC (10K)
1
PLACED BY Q9 FET
t
7
5
2
Title
TEMP_SEL_4 SONAR SPEED/TEMP
C 4519-002 J
5 4 3 2 1

Chapter 5: Drawings
DSM250 Main Board – PCB Layout, Component Side

5 4 3 2 1
D D
C C
B B
A A
Title
Assembly Drawing, DSM250, Component Side
C 4519-002 J
5 4 3 2 1

DSM250 Main Board – PCB Layout, Solder Side

5 4 3 2 1
D D
C C
B B
A A
Title
Assembly Drawing, DSM250, Solder Side
C 4519-002 J
5 4 3 2 1

Chapter 5: Drawings
DSM250 Connector I/O Board – Schematic

5 4 3 2 1
REV DATE CHANGES

TP1 TP2 TP3
XDCR C JAN-14, 2003 RELEASE TO PRODUCTION
J2
SK4-7 XDCR +
XDCR SHIELD 1
SK4-3
XDCR- 2
SK4-6
3
D TP4 TP5 TP6 TP7 D
MOLEX
SK4-4
SK4-2
SK4-1
SK4-5
TP8 TP9 TP10

POWER TP16
L1
SK3-1 C_BATT+
C1
2773009112 C3 PLACE NEAR SK4-5 J3 4.5MM HOLE. POSITION TO
C SK3-3 47uF 100nF BE SPECIFIED BY MECH. C
C2 1
ENGINEER
L2 C4 C5 MOUNTING HOLE (102.500,25.500)
SK3-2 C_BATT- 47uF 100nF
10nF
2773009112
TP17 J1
TP11 BATT+ 1
2
CGND 3
AR
4
DIAG LED BATT- 5
TLT-30 6
D1 K SPEED 7
TEMP 8
TP12 XD_SENSE 9
RED_LED 10
B 11 B
GRN_LED
AG
12
HSB_A 13
TP13 TP14 TP15 HSB_B 14
HSB_S_C 15
HSB 16
SK1-3 MOLEX 16-PIN

TP18
SK1-2
SK1-1 HSB_SHLD
C6
1nF/1KV
A A
NOTES: Title
1) SK1 AND 4 ARE FOR HARWIN SOCKET 3165-01. USE DRILL DSM-250 CONNNECTOR I/O
1.90 +/- .05MM.
3) PCB IS 3015-273 Issue. Size Document Number Rev
4) J P ’ s A R E . 4 " S P A C I N G . A 4519-004 C
5) C6 TO BE AS CLOSE TO SK1-1 AS POSSIBLE. Date: Thursday, April 03, 2003 Sheet 1 of 1
5 4 3 2 1

DSM250 Connector I/O Board – PCB Layout

Service Manual

May 2003
Raymarine Ltd Raymarine Inc www.raymarine.com
Anchorage Park, Portsmouth, England, 22 Cotton Road, Unit D
PO3 5TD Nashua, NH 03063-4219, USA
Telephone: +44 (0)23 9269 3611 Telephone: 603 881 5200
Fax: +44 (0)23 9269 4642 Fax: 603 864 4756

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