APS11500

Two-Wire Hall-Effect Switch

FEATURES AND BENEFITS DESCRIPTION

• ASIL A functional safety
APS11500 devices are two-wire planar Hall-effect sensor
□□ Developed in accordance with ISO 26262:2011
integrated circuits (ICs) developed in accordance with
(pending assessment)
ISO 26262 :2011 (pending assessment). They include internal
□□ Internal diagnostics and a defined Safe State
diagnostics and support a functional safety level of ASIL A.
□□ A2-SIL™ documentation available
The enhanced two-wire current-mode interface provides
• Multiple product options
interconnect open/short diagnostics and adds a Safe State
□□ Magnetic polarity, switch points, and hysteresis
to communicate diagnostic information while maintaining
□□ Temperature coefficient (supports SmCo, NdFeB, and
compatibility with legacy two-wire systems. Two-wire sensors
ferrite magnets)
are well-suited to safety applications, especially those involving
□□ Output polarity and current levels
long wire harnesses.
• Reduces module bill of materials (BOM) and assembly cost
□□ Integrated overvoltage clamp (40 V load-dump) and The APS11500 product options include magnetic switch points,
reverse-battery diode temperature coefficient, hysteresis, and whether the device
□□ Integrated series resistor and bypass capacitor (UC package) responds to north or south magnetic fields (unipolar switch) or
□□ Enables PCB-less sensor modules both (bipolar latch or omnipolar switch). The response can be
• Automotive-grade ruggedness and fault tolerance matched to SmCo, NdFeB, or low-cost ferrite magnets. There is
□□ Extended AEC-Q100 Grade 0 qualification a choice of two output current levels and either output polarity.
□□ Operation at –40°C to 175°C junction temperature
Continued on the next page…
□□ 3 to 24 V operating voltage range
□□ High EMC/ESD immunity
□□ Overtemperature indication TYPICAL APPLICATIONS
• Automotive and industrial safety systems
PACKAGES • Seat position detection
3-pin SOT23-W (LH) 3-pin ultramini SIP (UA) 3-pin SIP (UC) • Seat belt buckles
• Hood/trunk/door latches
• Sun roof/convertible top/tailgate/liftgate actuation
• Brake/clutch pedals
• Electric power steering (EPS)
• Transmissions and shift selectors
• Wiper motors
Not to scale

VCC

68 Ω
VINT
Device
0.1 µF UVLO Regulator ICC Adjust
Configuration

0.01 µF

Clock Generator
UC Package Switch Point
Only Control
LH and UA
Packages
Dynamic Offset
Cancellation

Only
Output
Amp
Polarity

Low-Pass
Filter
Temp
Comp

GND
Functional Block Diagram
APS11500-DS, Rev. 4 June 11, 2019
MCO-0000400
APS11500 Two-Wire Hall-Effect Switch

DESCRIPTION (continued)
APS11500 sensors are engineered to operate in the harshest The available SIP package with integrated discrete components
environments with minimal external components. They are qualified (UC) enables PCB-less applications by incorporating all of the EMC
beyond the requirements of AEC-Q100 Grade 0 and will survive protection components into the IC package. Other package options
extended operation at 175°C junction temperature. These monolithic include industry-standard surface-mount SOT (LH) and through-hole
ICs include on-chip reverse-battery protection, overvoltage protection SIP (UA) packages. All three packages are RoHS-compliant and
(40 V load dump), ESD protection, overtemperature detection, and an lead (Pb) free with 100% matte-tin-plated leadframes.
internal voltage regulator for operation directly from an automotive For situations where a functionally equivalent but factory-programmed
battery bus. These integrated features reduce the end-product bill two-wire latch or end-of-line programmable device is preferred, refer
of materials (BOM) and assembly cost. to the APS12400 and APS11900 device families, respectively.

Complete Part Number Format

Allegro Iden�fier (Device Family)
APS – Digital Posi�on Sensor
Allegro Device Number
11500 – 2-wire Planar Hall-Effect Switch
Configura�on Op�ons

RoHS

APS11500 L L H A L X - 0 S L 1 A
COMPLIANT

Temperature Coefficient
A – Flat
B – -0.035%/°C
Ambient Opera�ng Temperature Range C – -0.12%/°C
L – -40°C to +150°C D – -0.2%/°C
ICCLOW Selec�on
Package Designa�on 1 – 5 to 6.9 mA
LHA – 3-pin SOT23W Surface Mount 2 – 2 to 5 mA
UAA – 3-pin SIP Through-Hole Output Polarity for B > BOP
UCA – 3-pin SIP Through-Hole w/ passives H – ICC(H)
Instruc�ons (Packing) L – ICC(L)
LT – 7-in. reel, 3,000 pieces/reel (LH Only) Opera�ng Mode
LX – 13-in. reel, 10,000 pieces/reel (LH Only) N – Unipolar North Sensing
TN – 7-in. reel, 4,000 pieces/reel (UA Only) S – Unipolar South Sensing
P – Omnipolar (North and South) Sensing
(no op�on code) – Bulk, 500 pieces/bag (UA Only)
Device Switch Threshold Magnitude
0 – BOP: 50 to 110 G, BRP: 45 to 105 G (TA = -40 to 150°C)
A – Flat 1 – BOP: 20 to 60 G, BRP: 10 to 55 G (TA = -40 to 150°C)
Temperature 2 – BOP: 20 to 80 G, BRP: 10 to 60 G (TA = -40 to 150°C)
Coefficient
C – NdFeB 1 – BOP: 30 to 50 G, BRP: 13 to 27 G (TA = 25°C)

2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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APS11500 Two-Wire Hall-Effect Switch

SELECTION GUIDE [1]

Magnetic Device Switch ICC(L)
Operating Output Polarity for Selection
Part Number Package Packing Temperature Threshold
Mode B > BOP
Coefficient Magnitude (G) (mA)
3-pin SOT23-W 7-inch reel,
APS11500LLHALT-0SH1A
surface mount 3000 pieces/reel Unipolar BOP: 50 to 110;
Flat ICC(H) 5 to 6.9
3-pin SOT23-W 13-inch reel, South BRP: 45 to 105
APS11500LLHALX-0SH1A
surface mount 10000 pieces/reel
3-pin SOT23-W 7-inch reel,
APS11500LLHALT-0SL1A
surface mount 3000 pieces/reel Unipolar BOP: 50 to 110;
Flat ICC(L) 5 to 6.9
3-pin SOT23-W 13-inch reel, South BRP: 45 to 105
APS11500LLHALX-0SL1A
surface mount 10000 pieces/reel
3-pin SOT23-W 7-inch reel,
APS11500LLHALT-0SH1D
surface mount 3000 pieces/reel Unipolar BOP: 50 to 110;
–0.2%/°C ICC(H) 5 to 6.9
3-pin SOT23-W 13-inch reel, South BRP: 45 to 105
APS11500LLHALX-0SH1D
surface mount 10000 pieces/reel
3-pin SOT23-W 7-inch reel,
APS11500LLHALT-0SL1D
surface mount 3000 pieces/reel Unipolar BOP: 50 to 110;
–0.2%/°C ICC(L) 5 to 6.9
3-pin SOT23-W 13-inch reel, South BRP: 45 to 105
APS11500LLHALX-0SL1D
surface mount 10000 pieces/reel
3-pin SIP Bulk, Unipolar BOP: 50 to 110;
APS11500LUAA-0SH1A Flat ICC(H) 5 to 6.9
through-hole 500 pieces/bag South BRP: 45 to 105
3-pin SIP Bulk, Unipolar BOP: 50 to 110;
APS11500LUAA-0SH1D –0.2%/°C ICC(H) 5 to 6.9
through-hole 500 pieces/bag South BRP: 45 to 105
3-pin SIP Bulk, Unipolar BOP: 50 to 110;
APS11500LUAA-0SL1A Flat ICC(L) 5 to 6.9
through-hole 500 pieces/bag South BRP: 45 to 105
3-pin SIP Bulk, Unipolar BOP: 50 to 110;
APS11500LUAA-0SL1D –0.2%/°C ICC(L) 5 to 6.9
through-hole 500 pieces/bag South BRP: 45 to 105
3-pin SIP Bulk, Unipolar BOP: 20 to 60;
APS11500LUAA-1SH1C –0.12%/°C ICC(H) 5 to 6.9
through-hole 500 pieces/bag South BRP: 13 to 52
3-pin SIP
Bulk, Unipolar BOP: 20 to 60;
APS11500LUCD-1SH1C through-hole with –0.12%/°C ICC(H) 5 to 6.9
500 pieces/bag South BRP: 13 to 52
passives

[1] Contact Allegro MicroSystems for options not listed in the selection guide.

3
Allegro MicroSystems
955 Perimeter Road
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APS11500 Two-Wire Hall-Effect Switch

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Notes Rating Unit
Supply Voltage [1] VCC 40 V
Reverse Supply Voltage VRCC –23 V
Magnetic Flux Density B Unlimited G
165 °C
Maximum Junction Temperature TJ(max)
For 500 hours 175 °C
Storage Temperature Tstg –65 to 170 °C

[1] This
rating does not apply to extremely short voltage transients such as load dump and/or ESD. Those events have individual ratings
specific to the respective transient voltage event. Contact your local field applications engineer for information on EMC test results.

INTERNAL DISCRETE COMPONENT RATINGS (UC Package Only)

Characteristics
Component Symbol Test Conditions Rated Nominal Rated Rated Rated Temp. Rated Power
Resistance/Capacitance Voltage Tolerance Range Handling
Resistor RSERIES In series with VCC 68 Ω 50 V ±15% – 1/8 W
Capacitor CSUPPLY Connected between VCC and GND 100 nF 50 V ±10% X7R –

4
Allegro MicroSystems
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APS11500 Two-Wire Hall-Effect Switch

PINOUT DIAGRAMS AND TERMINAL LIST TABLE

Terminal List Table (LH, UA Packages)

Package Name
Number Function
LH UA
1 VCC VCC Supply voltage

2 GND GND Ground terminal

3 GND GND Ground terminal

Note: For best performance, tie Pins 2 and 3 together

close to the IC. 1 2
1 2 3

LH Package, 3-Pin SOT23W Pinout UA Package, 3-Pin SIP Pinout

Terminal List Table (UC Package)

Package Name
Number Function
UC
1 VCC Supply voltage
This pin reflects the internal
voltage, VINT, after the
2 VINT 100 nF
internal series resistor. This 68 Ω
pin should be kept floating.
3 GND Ground terminal

1 2 3

UC Package, 3-Pin SIP Pinout

5
Allegro MicroSystems
955 Perimeter Road
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APS11500 Two-Wire Hall-Effect Switch

ELECTRICAL CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for TJ < TJ(max) and
CBYP = 0.01 µF, unless otherwise specified
Characteristics Symbol Test Conditions Min. Typ. [3] Max. Unit
SUPPLY AND STARTUP
LH and UA
Operating, TJ < 165°C 3.0 – 24 V
Supply Voltage VCC packages
Operating, TJ < 165°C UC package 4.33 – 24 V
After power-on, as VCC increases, output LH and UA
– 2.6 – V
VCC(UV)DIS is forced to POS until this voltage is packages
reached UC package – 3.5 – V
Undervoltage Lockout [4]
LH and UA
After POK, when VCC drops below this – 2.3 – V
VCC(UV)EN packages
voltage, output is forced to POS
UC package – 3.2 – V
ICC(L1) 5 – 6.9 mA
ICC(L2) 2 – 5 mA
Supply Current ICC(H) 12 – 17 mA
Safe current state. Indicates overtemperature or device
ISAFE – – 1.8 mA
configuration error.
No bypass capacitor; CL [5] = 20 pF LH and UA – 50 – mA/µs
Output Slew Rate dI/dt CBYP = 100 nF; CL [5] = 20 pF packages – 0.22 – mA/µs
Internal bypass capacitor; CL [5] = 20 pF UC package – 0.22 – mA/µs
Power-On Time [6] tPO VCC ≥ VCC(min), B > BOP(max), B < BRP(min) – – 70 µs
Power-On State [7] POS t < tPO, VCC ≥ VCC(UV)EN ICC(H) mA
Chopping Frequency fC – 800 – kHz
Output Jitter (p-p) 1 kHz square wave signal – 5 – µs
ON-BOARD PROTECTION
Supply Zener Clamp Voltage VZ ICC = ICC(H) + 1 mA, TA = 25°C 40 – – V
Reverse Supply Zener Clamp
VRZ ICC = –1 mA – – –23 V
Voltage
Overtemperature Shutdown TSD Temperature increasing – 205 – °C
Overtemperature Hysteresis TJHYS – 25 – °C

[3] Typical data is at TA = 25°C and VCC = 12 V unless otherwise noted; for design information only.
[4] UC minimum VCC is higher to accomodate voltage drop in the internal series resistor. UC package minimum VCC is higher to accommodate voltage
drop in the internal series resistor. This also affects the VCC(UV).
[5] C – scope capacitance.
L
[6] Measured from V
CC ≥ VCC(MIN) to valid output.
[7] Power-on state is defined only when V
CC slew rate 1 V/s or greater.

6
Allegro MicroSystems
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APS11500 Two-Wire Hall-Effect Switch

MAGNETIC CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for TJ < TJ(max) and
CBYP = 0.01 µF, unless otherwise specified
Magnetic
Temperature
Characteristics Symbol Switch Point Test Conditions Min. Typ. [8] Max. Unit [9]
Coefficient
Option
A – Flat TA = –40°C to 150°C 50 – 110 G
TA = –40°C 65 – 111 G
C – NdFeB TA = 25°C 58 – 100 G
-0 TA = 150°C 50 – 81 G
TA = –40°C 72 – 118 G
D – Ferrite TA = 25°C 58 – 100 G
Operate Point BOP
TA = 150°C 37 – 68 G
A – Flat TA = –40°C to 150°C 20 – 60 G
TA = –40°C 23 43 63 G
-1
C – NdFeB TA = 25°C 20 40 60 G
TA = 150°C 19 34 50 G
-2 A – Flat TA = –40°C to 150°C 20 – 80 G
A – Flat TA = –40°C to 150°C 45 – 105 G
TA = –40°C 49 – 96 G
C – NdFeB TA = 25°C 46 – 85 G
-0 TA = 150°C 35 – 71 G
TA = –40°C 56 – 103 G
D – Ferrite TA = 25°C 46 – 85 G
Release Point BRP
TA = 150°C 22 – 58 G
A – Flat TA = –40°C to 150°C 10 – 55 G
TA = –40°C 15 37 60 G
-1
C – NdFeB TA = 25°C 13 32 52 G
TA = 150°C 10 27 46 G
-2 A – Flat TA = –40°C to 150°C 10 – 60 G
Hysteresis BHYS All All TA = –40°C to 150°C 5 – 30 G
A – Flat TA = –40°C to 150°C – 0 – %/°C
Switch Point Temperature
All C – NdFeB TA = –40°C to 150°C – –0.12 – %/°C
Coefficient
D – Ferrite TA = –40°C to 150°C – –0.2 – %/°C

[8] Typical data is at TA = 25°C and VCC = 12 V, unless otherwise noted; for design information only.
[9] Magnetic flux density, B, is indicated as a negative value for north-polarity magnetic fields, and a positive value for south-polarity magnetic fields.

7
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APS11500 Two-Wire Hall-Effect Switch

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions* Value Unit
Package LH, on 1-layer PCB based on JEDEC standard 228 °C/W

Package LH, on 2-layer PCB with 0.463 in.2 of copper area each side 110 °C/W
Package Thermal Resistance RθJA
Package UA, on 1-layer PCB with copper limited to solder pads 165 °C/W

Package UC, on 1-layer PCB with copper limited to solder pads 270 °C/W

*Additional thermal information available on the Allegro website.

Power Derating Curve

28
27
26 VCC(max)
25
24
23
22
Maximum Allowable VCC (V)

21
20
19
18
17
16 2-layer PCB, LH package
15 (RθJA = 110 °C/W)
14
13 1-layer PCB, Package UC
12
11 (RθJA = 270°C/W)
10
9 1-layer PCB, UA package
8 (RθJA = 165 °C/W)
7
6
5 1-layer PCB, LH package
4 (RθJA = 228°C/W) VCC(min)
3
2
20 40 60 80 100 120 140 160 180
Ambient Temperature (°C)

Power Dissipation versus Ambient Temperature

1900
1800
1700
1600 Package LH, 2-layer PCB
Power Dissipation, PD (mW)

1500 (RθJA = 110°C/W)

1400
1300 Package UA, 1-layer PCB
1200 (RθJA = 165°C/W)
1100
1000 Package LH, 1-layer PCB
900 (RθJA = 228°C/W)
800
700
600
500
400
300
200 Package UC, 1-layer PCB
100 (RθJA = 270°C/W)
0
20 40 60 80 100 120 140 160 180

Temperature (°C)

8
Allegro MicroSystems
955 Perimeter Road
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APS11500 Two-Wire Hall-Effect Switch

CHARACTERISTIC PERFORMANCE DATA

ICC(H) vs. TA ICC(H) vs. VCC

17 17
Supply Current, ICC(H) (mA)

Supply Current, ICC(H) (mA)

16 16
VCC (V) TA (°C)
15 15
3
-40
12
14 14 25
15
150
13 24 13

12 12
-50 -20 10 40 70 100 130 160 0 5 10 15 20 25 30
Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

ICC(L1) vs. TA ICC(L1) vs. VCC

7 7
6.75 6.8
Supply Current, ICC(L1) (mA)

Supply Current, ICC(L1) (mA)

6.6
6.5
VCC (V) 6.4 TA (°C)
6.25
3 6.2
6 6 -40
12
5.75 5.8 25
15 5.6
5.5 150
24 5.4
5.25
5.2
5 5
-50 -20 10 40 70 100 130 160 0 5 10 15 20 25 30
Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

ICC(L2) vs. TA ICC(L2) vs. VCC

5 5
Supply Current, ICC(L2) (mA)

Supply Current, ICC(L2) (mA)

4.5 4.5

4 VCC (V) 4 TA (°C)

3
3.5 3.5 -40
12
25
3 15 3
150
2.5 24 2.5

2 2
-50 -20 10 40 70 100 130 160 0 5 10 15 20 25 30
Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

ISAFE vs. TA ISAFE vs. VCC

2 2
1.75 1.75
Supply Current, ISAFE (mA)

Supply Current, ISAFE (mA)

1.5 1.5
VCC (V) TA (°C)
1.25 1.25
1 1 -40
3
0.75 0.75 25
24
0.5 0.5 150
0.25 0.25
0 0
-50 -20 10 40 70 100 130 160 0 5 10 15 20 25 30
Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

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APS11500 Two-Wire Hall-Effect Switch

BOP(0) vs. TA BOP(0) vs. VCC

115 115
Magnetic Flux Density, BOP (G)

Magnetic Flux Density, BOP (G)

105 105

95 VCC (V) 95 TA (°C)

85 85
-40
75 3 75
25
65 24 65
150
55 55

45 45
-50 -20 10 40 70 100 130 160 0 5 10 15 20 25
Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

BRP(0) vs. TA BRP(0) vs. VCC

100 100
Magnetic Flux Density, BRP (G)

Magnetic Flux Density, BRP (G)

89 89

78 VCC (V) 78 TA (°C)

67 67 -40
3
25
56 24 56
150
45 45

34 34
-50 -20 10 40 70 100 130 160 0 5 10 15 20 25
Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

BHYS(0) vs. TA BHYS(0) vs. VCC

30 30
Magnetic Flux Density, BHYS (G)

Magnetic Flux Density, BHYS (G)

25 25
VCC (V) TA (°C)
20 20
-40
3
15 15 25
24
150
10 10

5 5
-50 -20 10 40 70 100 130 160 0 5 10 15 20 25
Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

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APS11500 Two-Wire Hall-Effect Switch

BOP(1) vs. TA BOP(1) vs. VCC

60 60
Magnetic Flux Density, BOP (G)

Magnetic Flux Density, BOP (G)

55 55
50 50
VCC (V) TA (°C)
45 45
40 40 -40
3
35 35 25
24
30 30 150
25 25
20 20
-50 -20 10 40 70 100 130 160 0 5 10 15 20 25
Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

BRP(1) vs. TA BRP(1) vs. VCC

55 55
Magnetic Flux Density, BRP (G)

Magnetic Flux Density, BRP (G)

50 50
45 45
40 VCC (V) 40 TA (°C)
35 35
-40
30 3 30
25
25 24 25
20 20 150

15 15
10 10
-50 -20 10 40 70 100 130 160 0 5 10 15 20 25
Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

BHYS(1) vs. TA BHYS(1) vs. VCC

30 30
Magnetic Flux Density, BHYS (G)

Magnetic Flux Density, BHYS (G)

25 25
VCC (V) TA (°C)
20 20
-40
3
15 15 25
24
150
10 10

5 5
-50 -20 10 40 70 100 130 160 0 5 10 15 20 25
Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

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APS11500 Two-Wire Hall-Effect Switch

BOP(2) vs. TA BOP(2) vs. VCC

80 80
Magnetic Flux Density, BOP (G)

Magnetic Flux Density, BOP (G)

70 70

60 VCC (V) 60 TA (°C)

50 50 -40
3
25
40 24 40
150
30 30

20 20
-50 -20 10 40 70 100 130 160 0 5 10 15 20 25
Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

BRP(2) vs. TA BRP(2) vs. VCC

80 80
Magnetic Flux Density, BRP (G)

Magnetic Flux Density, BRP (G)

70 70

60 VCC (V) 60 TA (°C)

50 50
-40
40 3 40
25
30 24 30
150
20 20

10 10
-50 -20 10 40 70 100 130 160 0 5 10 15 20 25
Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

BHYS(2) vs. TA BHYS(2) vs. VCC

30 30
Magnetic Flux Density, BHYS (G)

Magnetic Flux Density, BHYS (G)

25 25
VCC (V) TA (°C)
20 20
-40
3
15 15 25
24
150
10 10

5 5
-50 -20 10 40 70 100 130 160 0 5 10 15 20 25
Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

12
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APS11500 Two-Wire Hall-Effect Switch

FUNCTIONAL DESCRIPTION

Functional Safety Operation

The APS11500 was designed in accordance with the international The APS11500 devices are two-wire unipolar planar Hall-effect
standard for automotive functional safety, switches. The user can select a device that respond to a north
2
ISO 26262:2011 (pending assessment). This or south magnetic field. There is a choice of two output current
- product achieves an ASIL (Automotive Safety levels, ICC(L1) and ICC(L2), and the user can determine which
Integrity Level) rating of ASIL A according to current state is applied, ICC(L) or ICC(H), when the magnetic field
the standard. The APS11500 is classified as a is present.
SEooC (Safety Element out of Context) and
The difference between the magnetic operate and release points is
can be easily integrated into safety-critical systems requiring
called the hysteresis of the device, BHYS. Hysteresis allows clean
higher ASIL ratings that incorporate external diagnostics or use
switching of the output even in the presence of external mechani-
measures such as redundancy. Safety documentation will be
cal vibration and electrical noise.
provided to support and guide the integration process. Contact
your local FAE for A2-SIL™ documentation: www.allegromicro. Figure 1 shows the potential configuration options for the
com/ASIL. APS11500. The direction of the applied magnetic field is perpen-
dicular to the branded face for the APS11500. See Figure 2 for an
The APS11500 has internal diagnostics to check the voltage supply
illustration.
(an undervoltage lockout regulator) and to detect overtemperature
conditions. See the Diagnostics section for more information.

Unipolar North Unipolar South

I+ I+
ICC(H) ICC(H)
Standard
Switch to High

Output
Switch to Low
Switch to Low
Switch to High

Polarity
(POL = 0) A X Y
B X Y
C X Y
ICC(L) ICC(L)
0 0
B- 0 0 B+
BRPS

BOPS
BOPN

BRPN

Z Z Z
BHYS BHYS

Unipolar North Unipolar South

Figure 2: Magnetic Sensing Orientations
I+ I+
Reversed ICC(H) ICC(H) APS11500 LH (Panel A), APS11500 UA (Panel B), and UC (Panel C)
Output
Switch to High
Switch to Low

Switch to Low
Switch to High

Polarity
(POL = 1)
ICC(L) ICC(L)
0 0
B- 0 0 B+
BOPN

BRPN

BRPS

BOPS

BHYS BHYS

Figure 1: Unipolar Hall Switch Magnetic and

Output Current Polarity Options
B- indicates increasing north polarity magnetic field strength, and
B+ indicates increasing south polarity magnetic field strength.

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APS11500 Two-Wire Hall-Effect Switch

Power-On Behavior Any value of ICC between the allowed ranges for ICC(H) and ICC(L)
indicates a general fault condition.
The APS11500 has an internal voltage regulator with undervolt-
age lockout. As the device powers up, it stays in the power-on + mA
state (POS) of ICC(H) until the supply voltage exceeds VCC(UV)DIS.
After tPO, the current consumption is ICC(L) or ICC(H), according Fault
to the magnetic field and the device configuration, as shown in ICC(H) (max)
Figure 1. ICC(H) Range
ICC(H) (min)
Similarly, when the supply voltage decreases, the device returns Fault
to the power on state (POS) when the supply voltage drops below ICC(L) (max)
VCC(UV)EN, as shown in Figure 3. ICC(L) Range
ICC(L) (min)
When the device powers on in the hysteresis range (less than BOP Fault
and higher than BRP), the output corresponds to the power-on ISAFE Overtemp, Device Config Error ISAFE Range
state. In this case, the correct state is attained after the first excur- Fault
sion beyond BOP or BRP. 0
Figure 4: Interpreting ICC for System-Level Diagnostics
Key

V POS
Temperature Coefficient and Magnet Selection
VCC for LH, UA;

VCC(min) The APS11500 allows the user to select the magnetic tempera-
VINT for UC

VCC(UV)DIS
VCC(UV)EN ture coefficient to compensate for drifts of SmCo, NdFeB, and
0 ferrite magnets over temperature—as indicated in the specifica-
V t tions table on page 5. This compensation improves the magnetic
tPO
POS POS system performance over the entire temperature range. For
ICC(H)
Output according to
example, the magnetic field strength from ferrite decreases as the
Current temperature increases from 25°C to 150°C. This lower magnetic
ICC

Current Undefined device se�ngs, based

on B Undefined
ICC(Lx)
field strength means that a lower switching threshold is required
t
to maintain switching at the same distance from the magnet to the
sensor. Correspondingly, higher switching thresholds are required
Figure 3: Power-On/UVLO Behavior
at cold temperatures, as low as –40°C, due to the higher magnetic
field strength from the ferrite magnet. The APS11500 compen-
Diagnostic Features sates the switching thresholds over temperature as described
When properly supplied, APS11500 always has current flowing at above. It is recommended that system designers evaluate their
a specified level: either ICC(H), ICC(L), or ISAFE. Any current out- magnetic circuit over the expected operating temperature range to
side of these narrow ranges is a fault condition. If there is a short, ensure the magnetic switching requirements are met.
current increases so that ICC > ICC(H) (max), outside the valid ICC(H)
For example, the typical ferrite compensation is –0.2%/°C.
range. If there is an open, the current lowers below the ICC(L) (min),
With a 25°C temperature BOP switch point of 80 G, the switch
outside the valid output current range. In this way, connectivity
point changes nominally by –0.2%/°C × 80 × (150°C – 25°C) =
issues between the ECU and the sensor can easily be detected.
–20 G to 80 G – 20 G = 60 G at 150°C. And at –40°C, the switch
Additionally, the APS11500 has an overtemperature feature: if point changes by –0.2%/°C × 80 × (–40°C – 25°C) = 10 G to
the junction temperature increases beyond TSD, then the current 80 G + 10 G = 90 G.
is reduced to ISAFE. The device current also changes to ISAFE if
there is an error in the device configuration which is checked at
power-on and after an overtemperature event.

14
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APS11500 Two-Wire Hall-Effect Switch

Applications
For the LH and UA packages, an external bypass capacitor (from
0.01 µF to 0.1 µF) should be connected (in close proximity to
the Hall element) between the supply and ground of the device
to reduce both external noise and noise generated by the chop-
per stabilization. Some applications may require additional EMC
immunity which is achieved with an enhanced protection circuit.
For example, increasing the bypass capacitor from 0.01 µF to
0.1 µF improves immunity to Powered ESD (ISO 10605) and
Direct Capacitive Coupling.
A series resistor and a 0.1 µF bypass capacitor is integrated into
the UC package, making it easy to achieve an EMC-robust design
with no external components or PCB required.
Note that the bypass capacitor selection directly affects the slew
rate. See the Electrical Characteristics table for the typical slew
rate with 0.1 µF bypass capacitor. A 0.01 µF bypass capacitor
slew rate is ten times faster.
Typical application circuits are shown in “Figure 5: Typical
Application Circuits” on page 16.
Extensive applications information for Hall-effect devices is
available in:
• Hall-Effect IC Applications Guide, AN27701
• Hall-Effect Devices: Guidelines For Designing Subassemblies
Using Hall-Effect Devices, AN27703.1
• Soldering Methods for Allegro’s Products – SMT and Through-
Hole, AN26009
•  www.allegromicro.com/ASIL
All are provided on the Allegro Web site:
www.allegromicro.com

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APS11500 Two-Wire Hall-Effect Switch

V+ ECU
VCC
R SENSE
APS11500 V SENSE
V+
C BYP
VCC
0.1 µF C BYP
A119x
APS11500
0.1 µF

GND

V SENSE
ECU
R SENSE GND

(A) Low-Side Sensing (LH, UA package) (B) High-Side Sensing (LH, UA package)

ECU
VCC
R SENSE
V+ APS11500
V SENSE
68 Ω
V+ VCC
VINT
APS11500
68 Ω
0.1 µF
VINT

GND
0.1 µF
V SENSE
ECU
R SENSE
GND

(C) Low-Side Sensing (UC package) (D) High-Side Sensing (UC package)

Figure 5: Typical Application Circuits

16
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APS11500 Two-Wire Hall-Effect Switch

Chopper Stabilization Technique

A limiting factor for switch point accuracy when using Hall- subsequent demodulation acts as a modulation process for the
effect technology is the small-signal voltage developed across
offset causing the magnetically induced signal to recover its origi-
the Hall plate. This voltage is proportionally small relative to the
nal spectrum at baseband while the DC offset becomes a high-
offset that can be produced at the output of the Hall sensor. This
frequency signal. Then, using a low-pass filter, the signal passes
makes it difficult to process the signal and maintain an accurate,
while the modulated DC offset is suppressed. Allegro’s innovative
reliable output over the specified temperature and voltage range.
chopper-stabilization technique uses a high-frequency clock.
Chopper stabilization is a proven approach used to minimize
Hall offset. The high-frequency operation allows a greater sampling rate that
produces higher accuracy, reduced jitter, and faster signal pro-
The technique, dynamic quadrature offset cancellation, removes
cessing. Additionally, filtering is more effective and results in a
key sources of the output drift induced by temperature and pack-
lower noise analog signal at the sensor output. Devices such as the
age stress. This offset reduction technique is based on a signal
APS11500 that use this approach have an extremely stable quies-
modulation-demodulation process. “Figure 6: Model of Chopper
cent Hall output voltage, are immune to thermal stress, and have
Stabilization Circuit (Dynamic Offset Cancellation)” illustrates
precise recoverability after temperature cycling. This technique is
how it is implemented.
made possible through the use of a BiCMOS process which allows
The undesired offset signal is separated from the magnetically the use of low offset and low noise amplifiers in combination with
induced signal in the frequency domain through modulation. The high-density logic and sample-and-hold circuits.

Regulator

Clock/Logic
Low-Pass
Hall Element Filter
Sample and
Hold

Amp

Figure 6: Model of Chopper Stabilization Circuit

(Dynamic Offset Cancellation)

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APS11500 Two-Wire Hall-Effect Switch

POWER DERATING
The device must be operated below the maximum junction First, using equation 3:
temperature, TJ (max). Reliable operation may require derating
supplied power and/or improving the heat dissipation properties ∆T (max) = TJ (max) – TA = 175°C – 150°C = 25°C
of the application. This provides the allowable increase to TJ resulting from internal
Thermal Resistance (junction to ambient), RθJA, is a figure of power dissipation. Then, from equation 2:
merit summarizing the ability of the application and the device to PD (max) = ∆T (max) ÷ RθJA = 25°C ÷ 165°C/W = 152 mW
dissipate heat from the junction (die), through all paths to ambi-
ent air. RθJA is dominated by the Effective Thermal Conductivity, Finally, using equation 1, solve for maximum allowable VCC for
K, of the printed circuit board which includes adjacent devices the given conditions:
and board layout. Thermal resistance from the die junction to VCC (est) = PD (max) ÷ ICC (max) = 152 mW ÷ 17 mA = 8.9 V
case, RθJC, is a relatively small component of RθJA. Ambient air The result indicates that, at TA, the application and device can
temperature, TA, and air motion are significant external factors in dissipate adequate amounts of heat at voltages ≤ VCC (est).
determining a reliable thermal operating point.
If the application requires VCC > VCC(est) then RθJA must by
The following three equations can be used to determine operation improved. This can be accomplished by adjusting the layout,
points for given power and thermal conditions. PCB materials, or by controlling the ambient temperature.
PD = VIN × IIN (1)
Determining Maximum TA
∆T = PD × RθJA (2)
In cases where the VCC (max) level is known, and the system
TJ = TA + ∆T (3) designer would like to determine the maximum allowable ambi-
ent temperature TA (max), for example, in a worst-case scenario
For example, given common conditions: TA = 25°C, VCC = 12 V, with conditions VCC (max) = 24 V, ICC (max) = 17 mA, and RθJA
ICC = 6 mA, and RθJA = 110°C/W for the LH package, then: = 228°C/W for the LH package using equation 1, the largest pos-
PD = VCC × ICC = 12 V × 6 mA = 72 mW sible amount of dissipated power is:

∆T = PD × RθJA = 72 mW × 110°C/W = 7.92°C PD = VIN × IIN

TJ = TA + ∆T = 25°C + 7.92°C = 32.92°C PD = 24 V × 17 mA = 408 mW

Then, by rearranging equation 3 and substituting with equation 2:
Determining Maximum VCC
TA (max) = TJ (max) – ΔT
For a given ambient temperature, TA, the maximum allow-
able power dissipation as a function of VCC can be calculated. TA (max) = 175°C – (408 mW × 228°C/W)
PD (max) represents the maximum allowable power level without
exceeding TJ (max) at a selected RθJA and TA. TA (max) = 175°C – 93°C = 82°C

Example: VCC at TA = 150°C, package UA, using low-K PCB. Finally, note that the TA (max) rating of the device is 150°C and
Using the worst-case ratings for the device, specifically: RθJA = performance is not guaranteed above this temperature for any
165°C/W, TJ (max) = 175°C, VCC (max) = 24 V, and ICC (max) = power level.
17 mA, calculate the maximum allowable power level, PD (max).

18
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APS11500 Two-Wire Hall-Effect Switch

Package LH, 3-Pin SOT23W

+0.12
2.98 –0.08

1.49 D
4°±4°
3 A
+0.020
0.180–0.053

0.96 D

+0.10 +0.19 2.40

2.90 –0.20 1.91 –0.06
0.70
D
0.25 MIN

1.00

1 2

0.55 REF 0.25 BSC 0.95

Seating Plane
Gauge Plane B PCB Layout Reference View

8× 10° REF Branded Face

1.00 ±0.13
XXX

+0.10 1
0.05 –0.05
0.95 BSC C Standard Branding Reference View
0.40 ±0.10
Line 1 = Three digit assigned brand number
For reference only; not for tooling use (reference DWG-0000367, Rev. 2).
Dimensions in millimeters.
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions.
Exact case and lead configuration at supplier discretion within limits shown.
A Active Area Depth, 0.28 ±0.04 mm
B Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C Branding scale and appearance at supplier discretion

D Hall element, not to scale

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APS11500 Two-Wire Hall-Effect Switch

Package UA, 3-Pin SIP

+0.08
4.09 –0.05

45°
B

C
E 2.05 NOM
1.52 ±0.05

10°
1.44 NOM E Mold Ejector
+0.08 E Pin Indent
3.02 –0.05

Branded 45°
Face
0.79 REF XXX
A
1.02
MAX
1
D Standard Branding Reference View
1 2 3 Line 1: Logo A
Line 2: Three digit assigned brand number

14.99 ±0.25 +0.03

0.41 –0.06
For reference only; not for tooling use (reference DWG-0000404, Rev. 1).
Dimensions in millimeters.
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions.
Exact case and lead configuration at supplier discretion within limits shown.
+0.05
0.43 –0.07
A Dambar removal protrusion (6×)
B Gate and tie bar burr area
C Active Area Depth, 0.50 ±0.08 mm
D Branding scale and appearance at supplier discretion
E Hall element (not to scale)

1.27 NOM

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APS11500 Two-Wire Hall-Effect Switch

Package UC, 3-Pin SIP

For Reference Only – Not for Tooling Use

(Reference DWG-0000409, Rev. 2)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

B 0.545 REF× 2 1.36 REF

+0.05 0.15 REF

0.10
–0.10
4×10°
+0.06 1.50 ±0.05
4.00
–0.05
C
Detail A R 0.20 All Corners
0.25 REF × 4
1.5 Detail A
Mold Ejector
+0.06 Pin Indent
4.00
–0.07
E
Branded
Face 45°

A
XXXXX
0.25 REF 0.85 ±0.05
Date Code
0.30 REF 0.42 ±0.05 Lot Number

1.27 REF × 2

D Standard Branding Reference View

1 2 3 Lines 1, 2, 3: max. 5 characters per line

18.00 ±0.10

Line 1: 5-digit Part Number

12.20 ±0.10
Line 2: 4-digit Date Code
+0.07 Line 3: Characters 5, 6, 7, 8 of
0.25
–0.03 Assembly Lot Number
Plating Included

0.38 REF
A Dambar removal protrusion (12×)
0.25 REF
B Gate and tie burr area

0.85 ±0.05
C Active Area Depth, 0.38 ±0.05 mm

+0.06 D Branding scale and appearance at supplier discretion

1.80
–0.07
F
E Hall element (not to scale)
R 0.30 All Corners
4.00 +0.06 1.50 ±0.05 F Molded Lead Bar to prevent damage to leads during shipment
–0.05

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APS11500 Two-Wire Hall-Effect Switch

REVISION HISTORY
Number Date Description
– March 23, 2018 Initial release
1 April 18, 2018 Corrected supply current values and plots (pages 6 and 9)
2 August 20, 2018 Added UC package availability footnote to Complete Part Number Format diagram (page 2)
3 April 1, 2019 Updated ASIL status (page 1 and 13) and other minor editorial updates
Added APS11500LUAA-1SH1C and APS11500LUCD-1SH1C part variants (pages 2, 3, 7);
4 June 11, 2019
updated Power Derating section (page 18)

Copyright 2019, Allegro MicroSystems.

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.

For the latest version of this document, visit our website:

www.allegromicro.com

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