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    Micron Design Rules: Chapter 3 CMOS Processing Technology

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    Carlos Saavedra
    This document discusses CMOS processing technology and design rules for a 65nm process. It provides details on layout dimensions and spacing rules for different layers like polysilicon, metal, and diffusion. Key dimensions include a minimum width and spacing of 0.065um and 0.07um for polysilicon layers and 0.1um and 0.12um for diffusion/active layers. The document also includes Table 3.1 which lists specific design rules for layers like well, active, and poly in a 65nm process.

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    Micron Design Rules: Chapter 3 CMOS Processing Technology

    Uploaded by

    Carlos Saavedra
    80 views1 page
    This document discusses CMOS processing technology and design rules for a 65nm process. It provides details on layout dimensions and spacing rules for different layers like polysilicon, metal, and diffusion. Key dimensions include a minimum width and spacing of 0.065um and 0.07um for polysilicon layers and 0.1um and 0.12um for diffusion/active layers. The document also includes Table 3.1 which lists specific design rules for layers like well, active, and poly in a 65nm process.

    Original Title

    CMOS-VLSI-design-145

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    This document discusses CMOS processing technology and design rules for a 65nm process. It provides details on layout dimensions and spacing rules for different layers like polysilicon, metal, and diffusion. Key dimensions include a minimum width and spacing of 0.065um and 0.07um for polysilicon layers and 0.1um and 0.12um for diffusion/active layers. The document also includes Table 3.1 which lists specific design rules for layers like well, active, and poly in a 65nm process.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    80 views1 page

    Micron Design Rules: Chapter 3 CMOS Processing Technology

    Uploaded by

    Carlos Saavedra
    This document discusses CMOS processing technology and design rules for a 65nm process. It provides details on layout dimensions and spacing rules for different layers like polysilicon, metal, and diffusion. Key dimensions include a minimum width and spacing of 0.065um and 0.07um for polysilicon layers and 0.1um and 0.12um for diffusion/active layers. The document also includes Table 3.1 which lists specific design rules for layers like well, active, and poly in a 65nm process.

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    © All Rights Reserved
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    118 Chapter 3 CMOS Processing Technology

    Section 1.5.3 introduced the SCMOS design rules. More extensive rules are illus-
    trated and summarized on the inside back cover. Layouts consist of a set of rectangles on
    various layers such as polysilicon or metal. Width is the minimum width of a rectangle on a
    particular layer. Spacing is the minimum spacing between two rectangles on the same or
    different layers. Overlap specifies how much a rectangle must surround another on another
    layer. Dimensions are all specified in Q except for overglass cuts that do not scale well
    because they must contact large bond wires or probe tips. Select layers are often generated
    automatically and thus are not shown in the layout. If the active layer satisfies design rules,
    the select will too.
    Contacts and vias must be exactly 2 × 2 Q. Larger connections are made from arrays of
    small vias to prevent current crowding at the periphery. The spacing rules of polysilicon or
    diffusion to arrays of multiple contacts is slightly larger than that to a single contact.
    Section 1.5.5 estimated the pitch of lower-level metal to be 8 Q: 4 Q for the width and
    4 Q for spacing. Technically, the minimum width and spacing are 3 Q, but the minimum
    metal contact size is 2 × 2 Q plus 1 Q surround on each side, for a width of 4 Q. Thus, the
    pitch for contacted metal lines can be reduced to 7 Q. Moreover, if the lines are drawn at
    3 Q and the contacts are staggered so two adjacent lines never have adjacent contacts, the
    pitch reduces to 6.5 Q. Nevertheless, using a pitch of 8 Q for planning purposes is good
    practice and leaves a bit of “wiggle room” to solve difficult layout problems.

    3.3.4 Micron Design Rules


    Table 3.1 lists a set of micron design rules for a hypothetical 65 nm process representing
    an amalgamation of several real processes. Rule numbers reference the diagram on the
    inside back cover. Observe that the rules differ slightly but not immensely from lambda-
    based rules with Q = 0.035 Rm. A complete set of micron design rules in this generation
    fills hundreds of pages. Note that upper level metal rules are highly variable depending on
    the metal thickness; thicker wires require greater widths and spacings and bigger vias.

    TABLE 3.1 Micron design rules for 65 nm process


    Layer Rule Description 65 nm Rule
    (Rm)
    Well 1.1 Width 0.5
    1.2 Spacing to well at different potential 0.7
    1.3 Spacing to well at same potential 0.7
    Active 2.1 Width 0.10
    (diffusion) 2.2 Spacing to active 0.12
    2.3 Source/drain surround by well 0.15
    2.4 Substrate/well contact surround by well 0.15
    2.5 Spacing to active of opposite type 0.25
    Poly 3.1 Width 0.065
    3.2 Spacing to poly over field oxide 0.10
    3.2a Spacing to poly over active 0.10
    3.3 Gate extension beyond active 0.10
    3.4 Active extension beyond poly 0.10
    3.5 Spacing of poly to active 0.07

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