Lambda based design rules

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• The physical mask layout of any circuit to be manufactured using a particular
process must conform to a set of geometric constraints or rules, which are generally
called layout design rules.
• These rules usually specify the minimum allowable line widths for physical objects
on-chip such as metal and polysilicon interconnects or diffusion areas, minimum
feature dimensions, and minimum allowable separations between two such features.
• If a metal line width is made too small, for example, it is possible for the line to
break during the fabrication process or afterwards, resulting in an open circuit.
• If two lines are placed too close to each other in the layout, they may form an
unwanted short circuit by merging during or after the fabrication process.
• The main objective of design rules is to achieve, for any circuit to be manufactured
with a particular process, a high overall yield and reliability while using the smallest
possible silicon area.

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• Note that there is usually a trade-off between higher yield, which is obtained
through conservative geometries, and better area efficiency, which is obtained
through aggressive, high-density placement of various features on the chip.
• The layout design rules which are specified for a particular fabrication process
normally represent a reasonable optimum point in terms of yield and density.
• It must be emphasized, however, that the design rules do not represent strict
boundaries which separate "correct" designs from "incorrect" ones.
• A layout which violates some of the specified design rules may still result in an
operational circuit with reasonable yield, whereas another layout observing all
specified design rules may result in a circuit which is not functional and/or has very
low yield.
• To summarize, we can say, in general, that observing the layout design rules
significantly increases the probability of fabricating a successful product with high
yield.

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• The design rules are usually described in two ways:
1. Micron rules, in which the layout constraints such as minimum feature sizes
and minimum allowable feature separations are stated in terms of absolute
dimensions in micrometers, or,
2. Lambda rules, which specify the layout constraints in terms of a single
parameter (X) and thus allow linear, proportional scaling of all geometrical
constraints.

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• Lambda-based layout design rules were originally devised to simplify the
industry standard micron-based design rules and to allow scaling capability for
various processes.
• It must be emphasized, however, that most of the submicron CMOS process
design rules do not lend themselves to straightforward linear scaling. The use
of lambda-based design rules must therefore be handled with caution in
submicron geometries.

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Illustration of
some of the
typical lambda
rules for layout
design

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Rule number Description λ-Rule

Active area rules

R1 Minimum active area width 3λ
R2 Minimum active area spacing 3λ

Polysilicon rules
R3 Minimum poly width 2λ
R4 Minimum poly spacing 2λ
R5 Minimum gate extension of poly over active 2λ
R6 Minimum poly-active edge spacing (poly outside active area) 1λ
R7 Minimum poly-active edge spacing (poly inside active area) 3λ

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Rule number Description λ-Rule

Metal rules
R8 Minimum metal width 3λ
R9 Minimum metal spacing 3λ

Contact rules
R10 Poly contact size 2λ
R11 Minimum poly contact spacing 2λ
R12 Minimum poly contact to poly edge spacing 1λ
R13 Minimum poly contact to metal edge spacing 1λ
R14 Minimum poly contact to active edge spacing 3λ

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Rule number Description λ-Rule

Metal rules
R15 Active contact size 2λ
R16 Minimum active contact spacing (on the same active region) 2λ
R17 Minimum active contact to active edge spacing 1λ
R18 Minimum active contact to metal edge spacing 1λ
R19 Minimum active contact to poly edge spacing 3λ
R20 Minimum active contact spacing (on different active regions) 6λ

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CMOS Inverter Layout Design

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• The design of physical layout is very tightly linked to overall circuit
performance (area, speed, and power dissipation) since the physical structure
directly determines the transconductances of the transistors, the parasitic
capacitances and resistances, and obviously, the silicon area which is used for
a certain function.
• On the other hand, the detailed mask layout of logic gates requires a very
intensive and time-consuming design effort, which is justifiable only in special
circumstances where the area and/or the performance of the circuit must be
optimized under very tight constraints.
• Therefore, automated layout generation (e.g., using a standard cell library,
computer aided placement-and-routing) is typically preferred for the design of
most digital VLSI circuits.
• In order to judge the physical constraints and limitations, however, the VLSI
designer must also have a good understanding of the physical mask layout
process.
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• The physical (mask layout) design of CMOS logic gates is an iterative process
which starts with the circuit topology (to realize the desired logic function)
and the initial sizing of the transistors (to realize the desired performance
specifications).
• At this point, the designer can only estimate the total parasitic load at the
output node, based on the fanout, the number of devices, and the expected
length of the interconnection lines.
• If the logic gate contains more than 4 to 6 transistors, the topological graph
representation and the Euler-path method allow the designer to determine the
optimum ordering of the transistors. A simple stick diagram layout can now be
drawn, showing the locations of the transistors, the local interconnections
between the transistors, and the locations of the contacts.

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• After a topologically feasible layout is found, the mask layers are drawn (using a layout
editor tool) according to the layout design rules. This procedure may require several small
iterations in order to accommodate all the design rules, but the basic topology should not
change very significantly.
• Following the final DRC (Design Rule Check), a circuit extraction procedure is performed
on the-finished layout to determine the actual transistor sizes, and more importantly, the
parasitic capacitances at each node.
• The result of the extraction step is usually a detailed SPICE input file, which is
automatically generated by the extraction tool. Now, the actual performance of the circuit
can be determined by performing a SPICE simulation, using the extracted net-list.
• If the simulated circuit performance (e. g., transient response times or power dissipation) do
not match the desired specifications, the layout must be modified and the whole process
must be repeated.
• The layout modifications are usually concentrated on the (W/L) ratios of the transistors
(transistor resizing), since the width-to-length ratios of the transistors determine the device
transconductance and the parasitic source/drain capacitances.
• The designer may also decide to change parts or all of the circuit topology in order to
reduce the parasitics.

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Typical
design flow
for the
production of
a mask layout

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• In the following, the mask layout design of a CMOS inverter will be examined step-
bystep, as an example for the application of layout design rules.
• First, we need to create the individual transistors according to the design rules.
• Assume that we attempt to design the inverter with minimum-size transistors.
• The width of the active area is then determined by the minimum diffusion contact
size (which is necessary for source and drain connections) and the minimum
separation from diffusion contact to both active area edges.
• The width of the polysilicon line over the active area (which is the gate of the
transistor) is typically taken as the minimum poly width.
• Then, the minimum overall length of the active area is determined by the following
sum:
(minimum polysilicon width) +
2 x (minimum poly-to-contact spacing) +
2 x (minimum contact size) +
2 x (minimum spacing from contact to active area edge).
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Design rules which determine the dimensions of a minimum-size transistor.

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• The pMOS transistor must be placed in an n-well region, and the minimum
size of the n-well is dictated by the pMOS active area and the minimum n-well
overlap over n+.
• The distance between the nMOS and the pMOS transistor is determined by the
minimum separation between the n+ active area and the n-well.
• The polysilicon gates of the nMOS and the pMOS transistors are usually
aligned, so that the gate connections can be made with a single polysilicon line
of least possible length.
• The reason for avoiding long polysilicon connections (as a general layout
practice) is the fact that the large parasitic resistance and the parasitic
capacitance of polysilicon lines may result in significant RC delays; Thus,
even local signal connections are preferably made with metal lines as much as
possible, and metal-polysilicon contacts are used to provide the electrical
connection between the two layers, wherever necessary.

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Design rules
which
determine the
separation
between the
nMOS and the
pMOS
transistor of
the CMOS
inverter.

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• The final step in the mask layout is the local interconnections in metal for the
output node, VDD and GND contacts.
• The dimensions of metal lines in a mask layout are usually dictated by the
minimum metal width and the minimum metal separation (between two
neighboring lines, on the same level).
• Notice that in order to be biased properly, the n-well region must also have a
VDD contact.

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Complete
mask
layout of
the
CMOS
inverter

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NPTEL / Swayam Course:
1. https://nptel.ac.in/courses/117/101/117101058/
2. https://nptel.ac.in/courses/108/107/108107129/

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VLABs
1. https://vlsi-iitg.vlabs.ac.in/

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