1. Question 1. What Is Uvm? What Is The Advantage Of Uvm?

Answer :
UVM (Universal Verification Methodology) is a standardized methodology for verifying the both
complex & simple digital design in simple way.
UVM Features:
o First methodology & second collection of class libraries for Automation
o Reusability through test bench
o Plug & Play of verification IPs
o Generic Test bench Development
o Vendor & Simulator Independent
o Smart Test bench i.e. generate legal stimulus as from pre-planned coverage plan
o Support CDV –Coverage Driven Verification
o Support CRV –Constraint Random Verification
o UVM standardized under the Accelerate System Initiative
o Register modeling
2. Question 2. Uvm Derived From Which Language?
Answer :
Here is the detailed connection between SV, UVM, OVM and other methodologies.

Perl Scripting Interview Questions

3. Question 3. What Is The Difference Between Uvm_component And Uvm_object? Or We
Already Have Uvm_object, Why Do We Need Uvm_component Which Is Actually Derived Class Of
Uvm_object?
Answer :
uvm_component:
o Quasi Static Entity (after build phase it is available throughout the simulation).
o Always tied to a given hardware (DUT Interface) or a TLM port.
o Having phasing mechanism for control the behavior of simulation.
o Configuration Component Topology.
uvm_object:
o Dynamic Entity (creates when needed, transfer from one component to other & then
dereference).
o Not tied to a given hardware or any TLM port.
o Not phasing mechanism.
4. Question 4. Which Uvm Phase Is Top - Down, Bottom – Up & Parallel?
Answer :
Only build phase is a top-down & other phases are bottom-up except run phase which is parallel. The
build phase works top-down since the test bench hierarchy may be configure so we need to build the
branches before leafs.

Perl Scripting Tutorial

5. Question 5. Why Build Phase Is Top – Down & Connect Phase Is Bottom – Up?
Answer :
The connect phase is intended to be used for making TLM connections between components, which
is why it occur after build phase. It work bottom-up so that its got the correct implementation all the
way up the design hierarchy, if worked top-down this would be not possible.
 Adobe Indesign Interview Questions
6. Question 6. Which Phase Is Function & Which Phase Is Task?
Answer :
Only run phase is a task (time consuming phase) & other phases are functions (non-blocking).
7. Question 7. Which Phase Takes More Time And Why?
Answer :
As previously said the run phase is implemented as task and remaining all are function. run phase will
get executed from start of simulation to till the end of simulation. run phase is time consuming,
where the test case is running.

VLSI Design Tutorial   System Verilog Interview Questions

8. Question 8. How Uvm Phases Initiate?
Answer :
UVM phases initiate by calling run test (“test1”) in top module. When run test() method call, it first
create the object of test top & then call all phases.
9. Question 9. How Test Cases Run From Simulation Command Line?
Answer :
In top module write run test(); i.e. Don't give anything in argument.
Then in command line: +UVM_TESTNAME=test name.
IDMS (Integrated Database Management System) Interview Questions
10. Question 10. Difference Between Module & Class Based Tb?
Answer :
o A module is a static object present always during of the simulation.
o A Class is a dynamic object because they can come and go during the life time of
simulation.
11. Question 11. What Is Uvm_config_db? What Is Difference Between Uvm_config_db &
Uvm_resource_db?
Answer :
o Uvm_config_db is a parameterized class used for configuration of different type of
parameter into the uvm database, So that it can be used by any component in the lower
level of hierarchy.
o Uvm_config_db is a convenience layer built on top of uvm_resource_db, but that
convenience is very important. In particular, uvm_resource_db uses a "last write wins"
approach. The uvm_config_db, on the other hand, looks at where things are in the
hierarchy up through end_of_elaboration, so "parent wins." Once you start
start_of_simulation, the config_db becomes "last write wins."
o All of the functions in uvm_config_db#(T) are static, so they must be called using the ::
operator. It is extended from the uvm_resource_db#(T), so it is child class of
uvm_resource_db#(T).
VLSI Interview Questions
12. Question 12. What Is The Advantage And Difference Of `uvm_component_utils() And
`uvm_object_utils()?
Answer :
 o The utile macros define the infrastructure needed to enable the object/component for
correct factory operation. 
o The reason there are two macros is because the factory design pattern fixes the
number of arguments that a constructor can have. Classes derived from uvm_object have
constructors with one argument, a string name. Classes derived from uvm_component
have two arguments, a name and a uvm_component parent.  
o The two `uvm_*utile macros inserts code that gives you a factory create() method that
delegates calls to the constructors of uvm_object or uvm_component. You need to use
the respective macro so that the correct constructor arguments get passed through. This
means that you cannot add extra constructor arguments when you extend these classes
in order to be able to use the UVM factory.
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13. Question 13. Difference Between `uvm_do And `uvm_rand_send ?
Answer :
uvm_do perform the below steps:
o Create
o Start item
o Randomize
o Finish item
o get response (optional)
While `uvm_rand_send perform all the above steps except create. User needs to create sequence /
sequence item.
o Question 14. Difference Between Uvm_transaction And Uvm_seq_item?
Answer :
class uvm_sequence_item extends uvm_transaction
Uvm_sequence_item extended from uvm_transaction only, uvm_sequence_item class has more
functionality to support sequence & sequencer features. Uvm_sequence_item provides the hooks for
sequencer and sequence, So you can generate transaction by using sequence and sequencer , and
uvm_transaction provide only basic methods like do print and do record etc .
o Question 15. Is Uvm Is Independent Of Systemverilog?
Answer :
UVM is a methodology based on Systemverilog language and is not a language on its own.  It is a
standardized methodology that defines several best practices in verification to enable efficiency in
terms of reuse and is also currently part of IEEE 1800.2 working group.

Circuit design Interview Questions

o Question 16. What Are The Benefits Of Using Uvm?
Answer :
Some of the benefits of using UVM are:
o Modularity and Reusability – The methodology is designed as modular components
(Driver, Sequencer, Agents , env etc) which enables reusing components across unit level
to multi-unit or chip level verification as well as across projects.
o Separating Tests from Test benches – Tests in terms of stimulus/sequencers are kept
separate from the actual test bench hierarchy and hence there can be reuse of stimulus
across different units or across projects.
 o Simulator independent – The base class library and the methodology is supported by
all simulators and hence there is no dependence on any specific simulator.
o Better control on Stimulus generation – Sequence methodology gives good control on
stimulus generation. There are several ways in which sequences can be developed which
includes randomization, layered sequences, virtual sequences etc which provides a good
control and rich stimulus generation capability.
o Easy configuration – Config mechanisms simplify configuration of objects with deep
hierarchy. The configuration mechanism helps in easily configuring different test bench
components based on which verification environment uses it and without worrying about
how deep any component is in test bench hierarchy.
o Factory mechanism – Factory mechanisms simplifies modification of components
easily. Creating each components using factory enables them to be overridden in different
tests or environments without changing underlying code base.
o Question 17. Can We Have User Defined Phase In Uvm?
Answer :
In addition to the predefined phases available in uvm , the user has the option to add his own phase
to a component. This is typically done by extending the uvm_phase class the constructor needs to
call super. new which has three arguments.
o Name of the phase task or function
o Top down or bottom up phase
o Task or function
The call task or call_func and get_type_name need to be implemented to complete the addition of
new phase.
Below is a simple example 
Example:
Class custom phase extends uvm_phase;
   Function new ();
      Super. New (“custom”, 1, 1);
   End function
  Task call task (uvm_component parent);
     My_comp_type comp;
     If ( $cast(comp, parent) )
             comp.custom phase ();
   End task
   Virtual function string get_type_name ();
      Return “custom”;
   End function
End class

Ethernet Interview Questions

o Question 18. What Is Uvm Ral Model? Why It Is Required?
Answer :
 In a verification context, a register model (or register abstraction layer) is a set of classes that model
the memory mapped behavior of registers and memories in the DUST in order to facilitate stimulus
generation and functional checking (and optionally some aspects of functional coverage). The UVM
provides a set of base classes that can be extended to implement comprehensive register modeling
capabilities.

Adobe Indesign Interview Questions

o Question 19. What Is The Difference Between New() And Create?
Answer :
We all know about new () method that is use to allocate memory to an object instance. In UVM (and
OVM), the create () method causes an object instance to be created from the factory. This allows you
to use factory overrides to replace the desired object with an object of a different type without
having to recode.
o Question 20. What Is Analysis Port?
Answer :
Analysis port (class uvm_tlm_analysis_port) — a specific type of transaction-level port that can be
connected to zero, one, or many analysis exports and through which a component may call the
method write implemented in another component, specifically a subscriber.
port, export, and imp classes used for transaction analysis.
uvm_analysis_port
Broadcasts a value to all subscribers implementing a uvm_analysis_imp.
uvm_analysis_imp
Receives all transactions broadcasted by a uvm_analysis_port.
uvm_analysis_export
Exports a lower-level uvm_analysis_imp to its parent.

Advanced C++ Interview Questions

o Question 21. What Is Tlm Fifo?
Answer :
In simpler words TLM FIFO is a FIFO between two UVM components, preferably between Monitor
and Scoreboard. Monitor keep on sending the DATA, which will be stored in TLM FIFO, and
Scoreboard can get data from TLM FIFO whenever needed.
// create a FIFO with depth 4
   tlm_fifo = new ("uvm tlm_fifo", this, 4);
o Question 22. How Sequence Starts?
Answer :
Start item starts the sequence
Virtual task start item (uvm_sequence_item item,   
int set priority  =  -1,
Uvm_sequencer_base sequencer =  null )
Start item and finish item together will initiate operation of a sequence item.  If the item has not
already been initialized using create item, then it will be initialized here to use the default sequencer
specified by m_sequencer.
o Question 23. What Is The Difference Between Uvm Ral Model Backdoor Write/read
And Front Door Write/read?
Answer :
o Font door access means using the standard access mechanism external to the DUTY to
read or write to a register. This usually involves sequences of time-consuming
transactions on a bus interface. 
o Backdoor access means accessing a register directly via hierarchical reference or
outside the language via the PLI. A backdoor reference usually in 0 simulation time.
Physical Design Engineer Interview Questions
o Question 24. What Is Objection?
Answer :
o The objection mechanism in UVM is to allow hierarchical status communication among
components which is helpful in deciding the end of test.
o There is a built-in objection for each in-built phase, which provides a way for
components and objects to synchronize their testing activity and indicate when it is safe
to end the phase and, ultimately, the test end.
o The component or sequence will raise a phase objection at the beginning of an activity
that must be completed before the phase stops, so the objection will be dropped at the
end of that activity. Once all of the raised objections are dropped, the phase terminates.
Raising an objection: phase.raise_objection (this);
Dropping an objection: phase.drop_objection (this);
System Verilog Interview Questions
o Question 25. What Is M_sequencer? Or Difference Between M_sequencer And
M_sequencer?
Answer :
M_sequencer is the default handle for uvm_vitual_sequencer and m_sequencer is the hook up for
child sequencer.
M_sequencer is the generic uvm_sequencer pointer. It will always exist for the uvm_sequencer and
is initialized when the sequence is started.
P_sequencer is a typed-specific sequencer pointer, created by registering the sequence to the
sequencer using macros (`uvm_declare_p_sequencer) . Being type specific, you will be able to access
anything added to the sequencer (i.e. pointers to other sequencers, etc.). M_sequencer will not exist
if we have not registered the sequence with the `uvm_declare_p_sequencer macros.
The drawback of m_sequencer is that once the m_sequencer is defined, one cannot run the
sequence on any other sequencer type.
o Question 26. What Is The Difference Between Active Mode And Passive Mode With
Respect To Agent?
Answer :
An agent is a collection of a sequencer, a driver and a monitor.
In active mode, the sequencer and the driver are constructed and stimulus is generated by
sequences sending sequence items to the driver through the sequencer. At the same time the
monitor assembles pin level activity into analysis transactions.
 In passive mode, only the monitor is constructed and it performs the same function as in an active
agent. Therefore, your passive agent has no need for a sequencer. You can set up the monitor using
a configuration object.

FPGA Interview Questions

o Question 27. What Is The Difference Between Copy And Clone?
Answer :
The built-in copy () method executes the __m_uvm_field_automation() method with the required
copy code as defined by the field macros (if used) and then calls the built-in do copy() virtual
function. The built-in do copy () virtual function, as defined in the uvm_object base class, is also an
empty method, so if field macros are used to define the fields of the transaction, the built-in copy()
method will be populated with the proper code to copy the transaction fields from the field macro
definitions and then it will execute the empty do copy() method, which will perform no additional
activity.
The copy() method can be used as needed in the UVM test bench. One common place where the
copy() method is used is to copy the sampled transaction and pass it into a sb_calc_exp() (scoreboard
calculate expected) external function that is frequently used by the scoreboard predictor.
The clone () method calls the create () method (constructs an object of the same type) and then calls
the copy() method. It is a one-step command to create and copy an existing object to a new object
handle.

IDMS (Integrated Database Management System) Interview Questions

o Question 28. What Is Uvm Factory?
Answer :
UCM Factory is used to manufacture (create) UVM objects and components. Apart from creating the
UVM objects and components the factory concept essentially means that you can modify or
substitute the nature of the components created by the factory without making changes to the test
bench. 
For example, if you have written two driver classes, and the environment uses only one of them. By
registering both the drivers with the factory, you can ask the factory to substitute the existing driver
in environment with the other type. The code needed to achieve this is minimal, and can be written
in the test.
o Question 29. What Are The Types Of Sequencer? Explain Each?
Answer :
There are two types of sequencers:
uvm_sequencer #(REQ, RSP) :
When the driver initiates new requests for sequences, the sequencer selects a sequence from a list
of available sequences to produce and deliver the next item to execute. In order to do this, this type
of sequencer is usually connected to a driver uvm_driver #(REQ, RSP).
uvm_push_sequencer #(REQ, RSP) :
The sequencer pushes new sequence items to the driver, but the driver has the ability to block the
item flow when it’s not ready to accept any new transactions. This type of sequencer is connected to
a driver of type uvm_push_driver # (REQ, RSP).
 o Write pseudo code for implementing an AHB-Lite driver.

o What is Semaphore in System Verilog?

Conceptually, a semaphore is a bucket. When a semaphore is allocated, a bucket
that contains a fixed number of keys is created. Processes using semaphores must
first procure a key from the bucket before they can continue to execute. If a specific
process requires a key, only a fixed number of occurrences of that process can be in
progress simultaneously. All others must wait until a sufficient number of keys is
returned to the bucket. Semaphores are typically used for mutual exclusion, access
control to shared resources, and basic synchronization.

Semaphore is a built-in class that provides the following methods:

-- Create a semaphore with a specified number of keys: new()
-- Obtain one or more keys from the bucket: get()
-- Return one or more keys into the bucket: put()
-- Try to obtain one or more keys without blocking: try_get()

o Is there any relation between set_config* and uvm_config_db? If yes, what

is the relation?
Yes, set_Config always maps to the config_db database for all variables.

o Difference between m and p sequencer?

One of the most confusing UVM stuff is about m_sequencer and p_sequencer and the
difference between the two. In reality, its just a game of polymorphism.
 Referring to some forum answer, m_sequencer is a generic sequencer pointer of
type uvm_sequencer_base. It will always exist for a uvm_sequence and is initialized
when the sequence is started.
The p_sequencer is a type specific sequencer pointer, created by registering the
sequence to a sequencer using the `uvm_declare_p_sequencer macros. Being type
specific, you will be able to access anything added to the sequencer (i.e. pointers to
other sequencers, etc.). p_sequencer will not exist if
the `uvm_declare_p_sequencer macros isn’t used.

1. What are some of the benefits of UVM methodology?

2. What are some of the drawbacks of UVM methodology?
3. Explain the concept of Transaction Level Modelling?
4. What is the difference between an uvm_object and uvm_component class?
5. What are TLM ports and TLM Fifos?
6. What is an analysis port and analysis fifo and where are they used?
7. Explain the protocol handshake between a sequencer and driver ?
8. What is the difference between a sequence and sequence item?
9. Is it possible to collect responses from DUT back to a sequence and if so how?
10. What is the difference between SEQ_ARB_RANDOM and SEQ_ARB_STRICT_RANDOM
arbitration mechanism on sequencer?
11. What is the difference between grab() and lock() on sequencer?
12. What is the difference between a pipelined and non-pipelined driver?
13. What is the difference between early randomization and late randomization of
sequences?
14. Write a sample sequence code that generates a stream of ethernet packets?
15. How can you specify weightage for a sequence when started on a sequencer?
16. What is the difference between a monitor and a scoreboard in UVM methodology?
17. What is meant by factory and what is its importance?
18. What is the difference between creating an object using new() and create()?
19. What are the difference phases in UVM and what is the order of their execution?
20. What are objections and how are they useful?
21. How can you implement a simulation timeout mechanism using UVM methodology?
22. What is meant by factory override and what are different types of overriding possible
with UVM factory?
23. What is a virtual sequence and where do we use a virtual sequence? What are its
benefits?
24. What is uvm_config_db and what is it used for?
25. Why should any uvm component be registered with factory?
1. Question 1. What Is Callback ?
Answer :
In computer programming, a callback is executable code that is passed as an
argument to other code. It allows a lower-level software layer to call a subroutine (or
function) defined in a higher-level layer.
2. Question 2. What Is Factory Pattern ?
Answer :
Factory Pattern Concept : 
Methodologies like OVM and VMM make heavy use of the factory concept. The
factory method pattern is an object-oriented design pattern. Like other creational
patterns, it deals with the problem of creating objects (products) without specifying
the exact class of object that will be created. The factory method design pattern
handles this problem by defining a separate method for creating the objects, whose
subclasses can then override to specify the derived type of product that will be
created. More generally, the term factory method is often used to refer to any method
whose main purpose is creation of objects.
Or in simple terms factory pattern help in creation of the object when you dont know
the exact type of the object. the normal way of creating the object is :
01.// Normal Type based object creation
02. 
03.// Class object
04.class my_class;
05.int i;
06.endclass
07. 
08.program main;
09.// Create object type my_class
10.my_class obj1;
11.obj1 = new
12.endprogram
13. 
14.// Using Factory I should be able to do the following
15. 
16.program main;
17.base_class my_class_object;
 18. 
19.base_class = factory.create_object("my_class"); // See here the type of the object
to be created is passed as a string so we dont know the exact type of the object
20.endprogram
Perl Scripting Interview Questions
3. Question 3. Explain The Difference Between Data Types Logic And Reg And
Wire ?
Answer :
Wire are Reg are present in the verilog and system verilog adds one more data type
called logic. 
Wire : Wire data type is used in the continuous assignments or ports list. It is treated
as a wire So it can not hold a value. It can be driven and read. Wires are used for
connecting different modules. 
Reg : Reg is a date storage element in system verilog. Its not a actual hardware
register but it can store values. Register retain there value until next assignment
statement. 
Logic : System verilog added this additional datatype  extends the rand eg type so it
can be driven by a single driver such as gate or module. The main difference between
logic dataype and reg/wire is that a logic can be driven by both continuous
assignment or blocking/non blocking assignment.
4. Question 4. What Is The Need Of Clocking Blocks ?
Answer :
o It is used to specify synchronization characteristics of the design
o It Offers a clean way to drive and sample signals
o Provides race-free operation if input skew > 0
o Helps in testbench driving the signals at the right time
o  Features
                  - Clock specification
                  - Input skew,output skew
                  - Cycle delay (##)
o Can be declared inside interface,module or program
Example :
01.Module M1(ck, enin, din, enout, dout);
02.input         ck,enin;
03.input  [31:0] din    ;
04.output        enout  ;
05.output [31:0] dout   ;
06. 
07.clocking sd @(posedge ck);
 08.input  #2ns ein,din    ;
09.output #3ns enout, dout;
10.endclocking:sd
11. 
12.reg [7:0] sab ;
13.initial begin
14.sab = sd.din[7:0];
15.end
16.endmodule:M1
Perl Scripting Tutorial
5. Question 5. What Are The Ways To Avoid Race Condition Between Testbench
And Rtl Using Systemverilog?
Answer :
There are mainly following ways to avoid the race condition between testbench and
RTL using system verilog 
o Program Block
o Clocking Block
o Using non blocking assignments.

Shell Scripting Interview Questions

o Question 6. What Are The Types Of Coverages Available In Sv ?
Answer :
Using covergroup : variables, expression, and their cross
Using cover keyword : properties
o Question 7. What Is Oops?
Answer :
Here are some nice OOP links on SystemVerilog OOP which can be used as a good
starting point/reference.
o Object Oriented Programming for Hardware Verification
o Improve Your SystemVerilog OOP Skills by Learning Principles and
Patterns
o SystemVerilog OOP OVM Feature Summary
o Enhancing SystemVerilog with AOP Concepts (On how to mimic AOP
features in OOP, good for guyz coming from e background)
o Testbench.in OOP Tutorial

Shell Scripting Tutorial   C Interview Questions

o Question 8. What Is The Need Of Virtual Interfaces ?
Answer :
 An interface encapsulate a group of inter-related wires, along with their directions
(via modports) and synchronization details (via clocking block). The major usage of
interface is to simplify the connection between modules.
But Interface can't be instantiated inside program block, class (or similar non-module
entity in SystemVerilog). But they needed to be driven from verification environment
like class. To solve this issue virtual interface concept was introduced in SV.
Virtual interface is a data type (that implies it can be instantiated in a class) which
hold reference to an interface (that implies the class can drive the interface using the
virtual interface). It provides a mechanism for separating abstract models and test
programs from the actual signals that make up the design. Another big advantage of
virtual interface is that class can dynamically connect to different physical interfaces
in run time.
o Question 9. What Is The Difference Between Mailbox And Queue?
Answer :
A queue is a variable-size, ordered collection of homogeneous elements. A Queue is
analogous to one dimensional unpacked array that grows and shrinks automatically.
Queues can be used to model a last in, first out buffer or first in, first out buffer.
// Other data type as reference
// int q[]; dynamic array
// int q[5]; fixed array
// int q[string]; associate array 
// include <
// List#(integer) List1;    //
int q[$] = { 2, 4, 8 };
int p[$];
int e, pos;
e = q[0]; // read the first (leftmost) item
e = q[$]; // read the last (rightmost) item
q[0] = e; // write the first item
p = q; // read and write entire queue (copy)
A mailbox is a communication mechanism that allows messages to be exchanged
between processes. Data can be sent to a mailbox by one process and retrieved by
another.

VHDL Interview Questions

o Question 10. What Data Structure You Used To Build Scoreboard?
Answer :
In SV, we use mailbox to get data from different modules and compare the result.
class Scoreboard;
mailbox drvr2sb;
mailbox rcvr2sb;
function new(mailbox drvr2sb,mailbox rcvr2sb);
  this.drvr2sb = drvr2sb;
  this.rcvr2sb = rcvr2sb;
endfunction:new
task start();
  packet pkt_rcv,pkt_exp;
  forever
  begin
    rcvr2sb.get(pkt_rcv);
    $display(" %0d : Scorebooard : Scoreboard received a packet from receiver ",
$time);
    drvr2sb.get(pkt_exp);
    if(pkt_rcv.compare(pkt_exp)) 
    $display(" %0d : Scoreboardd :Packet Matched ",$time);
    else
      $root.error++;
  end
endtask : start
endclass
In VMM, we use channels to connect all the modules and compare the result.
class Scoreboard extends vmm_xactor;
   Packet_channel   drvr2sb_chan;
   Packet_channel   rcvr2sb_chan;
function new(string inst = "class",
             int unsigned stream_id = -1,
             Packet_channel   drvr2sb_chan = null,
             Packet_channel   rcvr2sb_chan = null);
      super.new("sb",inst,stream_id);
          if(drvr2sb_chan == null)
           `vmm_fatal(this.log,"drvr2sb_channel is not constructed");
      else
           this.drvr2sb_chan = drvr2sb_chan;
            if(rcvr2sb_chan == null)
           `vmm_fatal(this.log,"rcvr2sb_channel is not constructed");
      else
           this.rcvr2sb_chan = rcvr2sb_chan;
           `vmm_note(log,"Scoreboard created ");
endfunction:new
task main();
  Packet pkt_rcv,pkt_exp;
  string msg;
  super.main(); 
  forever
  begin
    rcvr2sb_chan.get(pkt_rcv);
    $display(" %0d : Scoreboard : Scoreboard received a packet from receiver ",$time);
    drvr2sb_chan.get(pkt_exp);
    if(pkt_rcv.compare(pkt_exp,msg)) 
    $display(" %0d : Scoreboard :Packet Matched ",$time);
    else
    `vmm_error(this.log,$psprintf(" Packet MissMatched n %s ",msg));
  end
endtask : main
endclass
C Tutorial
o Question 11. What Is The Difference Between $random() And
$urandom()?
Answer :
o $random system function returns a 32-bit signed random number each
time it is called
o $urandom system function returns a 32-bit unsigned random number
each time it is called. (newly added in SV, not present in verilog)
VLSI Interview Questions
o Question 12. What Is Scope Randomization?
Answer :
Scope randomization ins SystemVerilog allows assignment of unconstrained or
constrained random value to the variable within current scope
01.module MyModule;
02.integer var, MIN;     
03. 
04.initial begin
05.MIN = 50;         
06.for ( int i = 0;i begin             
07.if( randomize(var) with { var < 100 ; var > MIN ;})
  08.$display(" Randomization sucsessfull : var = %0d Min = %0d",var,MIN);
09.else            
10.$display("Randomization failed");
11.end
12. 
13.$finish;    
14.end
15.endmodule
Perl Scripting Interview Questions
o Question 13. List The Predefined Randomization Methods.
Answer :
o randomize
o pre_randomize
o post_randomize

VLSI Design Tutorial

o Question 14. What Is The Dfference Between Always_combo And
Always@(*)?
Answer :
From SystemVerilog LRM 3.1a:-
o always_comb get executed once at time 0, always @* waits till a change
occurs on a signal in the inferred sensitivity list
o Statement within always_comb can't have blocking timing, event control,
or fork-join statement. No such restriction of always @*
o Optionally EDA tool might perform additional checks to warn if the
behavior within always_comb procedure doesn't represent combinatorial
logic
o Variables on the left-hand side of assignments within an always_comb
procedure, including variables from the contents of a called function, shall
not be written to by any other processes, whereas always @* permits
multiple processes to write to the same variable.
o always_comb is sensitive to changes within content of a function,
whereas always @* is only sensitive to changes to the arguments to the
function.
A small SystemVerilog code snippet to illustrate #5
01.module dummy;
02.logic a, b, c, x, y;
03. 
04.// Example void function
 05.function void my_xor;
06.input a;         // b and c are hidden input here
07.x = a ^ b ^ c;
08.endfunction : my_xor
09. 
10.function void my_or;
11.input a;         // b and c are hidden input here
12.y = a | b | c;
13.endfunction : my_xor
14. 
15.always_comb          // equivalent to always(a,b,c)
16.my_xor(a);       // Hidden inputs are also added to sensitivity list
17. 
18.always @*          // equivalent to always(a)
19.my_or(a);     // b and c are not added to sensitivity list
20.endmodule
o Question 15. What Is The Use Of Packages?
Answer :
In Verilog declaration of data/task/function within modules are specific to the
module only. They can't be shared between two modules. Agreed, we can achieve the
same via cross module referencing or by including the files, both of which are known
to be not a great solution.
The package construct of SystemVerilog aims in solving the above issue. It allows
having global data/task/function declaration which can be used across modules. It
can contain module/class/function/task/constraints/covergroup and many more
declarations (for complete list please refer section 18.2 of SV LRM 3.1a)
The content inside the package can be accessed using either scope resolution
operator (::), or using import (with option of referencing particular or all content of the
package). 
01.package ABC;
02.// Some typedef
03.typedef enum {RED, GREEN, YELLOW} Color;
04. 
05.// Some function
06.void function do_nothing()
07....
08.endfunction : do_nothing
09. 
10.// You can have many different declarations here
11.endpackage : ABC
 12. 
13.// How to use them
14.import ABC::Color;   // Just import Color
15.import ABC::*;     // Import everything inside the package
Semiconductor Interview Questions
o Question 16. What Is The Use Of $cast?
Answer :
Type casting in SV can be done either via static casting (', ', ') or dynamic casting via
$cast task/function. $cast is very similar to dynamic_cast of C++. It checks whether
the casting is possible or not in run-time and errors-out if casting is not possible.
o Question 17. How To Call The Task Which Is Defined In Parent Object
Into Derived Class ?
Answer :
super.task_name();

Advanced Linux Interview Questions

o Question 18. What Is The Difference Between Rand And Randc?
Answer :
rand - Random Variable, same value might come before all the the possible value
have been returned. Analogous to throwing a dice.
randc - Random Cyclic Variable, same value doesn't get returned until all possible
value have been returned. Analogous to picking of card from a deck of card without
replacing. Resource intensive, use sparingly/judiciously

Shell Scripting Interview Questions

o Question 19. What Is $root?
Answer :
$root refers to the top level instance in SystemVerilog
1.package ABC;
2.$root.A;     // top level instance A
3.$root.A.B.C; // item C within instance B within top level instance A
o Question 20. What Are Bi-directional Constraints?
Answer :
Constraints by-default in SystemVerilog are bi-directional. That implies that the
constraint solver doesn't follow the sequence in which the constraints are specified.
All the variables are looked simultaneously. Even the procedural looking constrains
like if ... else ... and -> constrains, both if and else part are tried to solve concurrently.
 For example (a==0) -> (b==1) shall be solved as all the possible solution of (!(a==0) ||
(b==1)).

ASIC Interview Questions

o Question 21. What Is Solve And Before Constraint ?
Answer :
In the case where the user want to specify the order in which the constraints solver
shall solve the constraints, the user can specify the order via solve before construct.
i.e.
1....
2.constraint XYZ  {
3.a inside {[0:100]|;
4.b < 20;
5.a + b > 30;
6.solve a before b;
7.}
The solution of the constraint doesn't change with solve before construct. But the
probability of choosing a particular solution change by it.
o Question 22. Without Using Randomize Method Or Rand,generate An
Array Of Unique Values?
Answer :
1....
2.int UniqVal[10];
3.foreach(UniqVal[i]) UniqVal[i] = i;
4.UniqVal.shuffle();
5....
o Question 23. Explain About Pass By Ref And Pass By Value?
Answer :
Pass by value is the default method through which arguments are passed into
functions and tasks. Each subroutine retains a local copy of the argument. If the
arguments are changed within the subroutine declaration, the changes do not affect
the caller.
In pass by reference functions and tasks directly access the specified variables
passed as arguments.Its like passing pointer of the variable.
example:
task pass(int i)    //  task pass(var int i) pass by reference 
{
delay(10);
i = 1;
 printf(" i is changed to %d at %dn",i,get_time(LO) );
delay(10);
i = 2;
printf(" i is changed to %d at %dn",i,get_time(LO) );
}
Universal Verification Methodology (UVM) Interview Questions
o Question 24. What Is The Difference Between Byte And Bit [7:0]?
Answer :
byte is signed whereas bit [7:0] is unsigned. 

C Interview Questions
o Question 25. What Is The Difference Between Program Block And
Module ?
Answer :
Program block is newly added in SystemVerilog. It serves these purposes
o It separates testbench from DUT
o It helps in ensuring that testbench doesn't have any race condition with
DUT
o It provides an entry point for execution of testbench
o It provides syntactic context (via program ... endprogram) that specifies
scheduling in the Reactive Region.
Having said this the major difference between module and program blocks are
o Program blocks can't have always block inside them, modules can have.
o Program blocks can't contain UDP, modules, or other instance of
program block inside them. Modules don't have any such restrictions.
o Inside a program block, program variable can only be assigned using
blocking assignment and non-program variables can only be assigned using
non-blocking assignments. No such restrictions on module 
o Program blocks get executed in the re-active region of scheduling queue,
module blocks get executed in the active region
o A program can call a task or function in modules or other programs. But
a module can not call a task or function in a program.
o Question 26. What Is The Use Of Modports ?
Answer :
Modports are part of Interface. Modports are used for specifing the direction of the
signals with respect to various modules the interface connects to.
o ...
o interface my_intf;
 o wire x, y, z;
o modport master (input x, y, output z);
o modport slave  (output x, y, input z);

VLSI Design Interview Questions

o Question 27. Write A Clock Generator Without Using Always Block.
Answer :
Use of forever begin end. If it is a complex always block statement like always (@
posedge clk or negedge reset_)
always @(posedge clk or negedge reset_) begin
   if(!reset_) begin
       data <= '0;
   end else begin
       data <= data_next;
   end
end
// Using forever : slightly complex but doable
forever begin
   fork
   begin : reset_logic
       @ (negedge reset_);
       data <= '0;
   end : reset_logic
   begin : clk_logic
       @ (posedge clk);
       if(!reset_)    data <= '0;
       else           data <= data_next;
   end : clk_logic
   join_any
   disable fork
end
VHDL Interview Questions
o Question 28. What Is Circular Dependency And How To Avoid This
Problem ?
Answer :
Over specifying the solving order might result in circular dependency, for which there
is no solution, and the constraint solver might give error/warning or no constraining.
Example
 1....
2.int x, y, z;
3.constraint XYZ  {
4.solve x before y;
5.solve y before z;
6.solve z before x;
7.....
8.}
o Question 29. What Is Cross Coverage ?
Answer :
Queue has a certain order. It's hard to insert the data within the queue. But Linkedlist
can easily insert the data in any location.
o Question 30. How To Randomize Dynamic Arrays Of Objects?
Answer :
class ABC;
// Dynamic array
rand bit [7:0] data [];
// Constraints
constraint cc {
// Constraining size
data.size inside {[1:10]};
// Constraining individual entry
data[0] > 5;
// All elements
foreach(data[i])
if(i > 0)
data[i] > data[i-1];|
}
endclass : ABC
o Question 31. What Is The Need Of Alias In Sv?
Answer :
The Verilog has one-way assign statement is a unidirectional assignment and can
contain delay and strength change. To have bidirectional short-circuit connection
SystemVerilog has added alias statement.
o Question 32. What Is "this"?
Answer :
"this" pointer refers to current instance.
o Question 33. What Is Tagged Union ?
Answer :
 An union is used to stored multiple different kind/size of data in the same storage
location.
1.typedef union{
2.bit [31:0]  a;
3.int         b;
4.} data_u;
Now here XYZ union can contain either bit [31:0] data or an int data. It can be written
with a bit [31:0] data and read-back with a int data. There is no type-checking done.
In the case where we want to enforce that the read-back data-type is same as the
written data-type we can use tagged union which is declared using the qualifier
tagged. Whenever an union is defined as tagged, it stores the tag information along
with the value (in expense of few extra bits). The tag and values can only be updated
together using a statically type-checked tagged union expression. The data member
value can be read with a type that is consistent with current tag value, making it
impossible to write one type and read another type of value in tagged union. (the
details of which can be found in section 3.10 and 7.15 of SV LRM 3.1a).
01.typedef union tagged{
02.bit [31:0]  a;
03.int         b;
04.} data_tagged_u;
05. 
06.// Tagged union expression
07.data_tagged_u data1 = tagged a 32'h0;
08.data_tagged_u data2 = tagged b 5;
09. 
10.// Reading back the value
11.int xyz = data2.b;
VLSI Interview Questions
o Question 34. What Is "scope Resolution Operator"?
Answer :
extern keyword allows out-of-body method declaration in classes. Scope resolution
operator ( :: ) links method declaration to class declaration.
class XYZ;
// SayHello() will be declared outside the body 
// of the class
extern void task SayHello();
endclass : XYZ
void task XYZ :: SayHello();
 $Message("Hello !!!n");
endtask : SayHello
o Question 35. What Is The Difference Between Bits And Logic?
Answer :
bits is 2-valued (1/0) and logic is 4-valued (0/1/x/z)
o Question 36. What Is The Difference Between $rose And Posedge?
Answer :
posedge return an event, whereas $rose returns a Boolean value. Therefore they are
not interchangeable.

Semiconductor Interview Questions

o Question 37. What Is Layered Architecture ?
Answer :
In SystemVerilog based constrained random verification environment, the test
environment is divided into multiple layered as shown in the figure. It allows
verification component re-use across verification projects.
o Question 38. What Is The Difference Between Initial Block And Final
Block?
Answer :
There are many difference between initial and final block. I am listing the few
differences that is coming to mind now.
o The most obvious one : Initial blocks get executed at the beginning of the
simulation, final block at the end of simulation
o Final block has to be executed in zero time, which implies it can't have
any delay, wait, or non-blocking assignments. Initial block doesn't have any
such restrictions of execution in zero time (and can have delay, wait and
non-blocking statements)
Final block can be used to display statistical/genaral information regarding the
status of the execution like this:-
1.final begin
2.$display("Simulation Passed");
3.$display("Final value of xyz = %h",xyz);
4.$display("Bye :: So long, and Thanks for all the fishes");
5.end
o Question 39. How To Check Weather A Handles Is Holding Object Or
Not ?
Answer :
It is basically checking if the object is initialized or not. In SystemVerilog all
uninitialized object handles have a special value of null, and therefore whether it is
 holding an object or not can be found out by comparing the object handle to null. So
the code will look like:-
01.usb_packet My_usb_packet;
02....
03.if(My_usb_packet == null) begin
04.// This loop will get exited if the handle is not holding any object
05.....
06.end else begin
07.// Hurray ... the handle is holding an object
08....
09.end

o How many ways to connect assertion to RTL?

Answer: There are 3 ways to connect assertion to RTL: inline, Instantiation and
Virtual Instantiation (bind).

             Inline Assertion:  Assertion directly put into the RTL by designer. Use
compile option for synthesis.

o Assertion for synchronous D flip flop behavior:

// A synchronous D Flip-Flop
moduledff (input logic [7:0] D, input RST_, input CLK, output logic [7:0] Q);
always @(posedge CLK)
if (!RST_) Q<= 8'h0;
else Q <= D;

// assertions
1. propertyd_q_property_0 (clk, rst_, q);
@(posedge clk) !rst_ |->##1(q == 8'h0);
endproperty
assert_d_q_property_0 : assert property(d_q_property_0(CLK, RST_, Q));

o Usage of clocking block and modports

It is used to specify synchronization characteristics of the design
- It Offers a clean way to drive and sample signals
- Provides race-free operation if input skew > 0
- Helps in testbench driving the signals at the right time
-  Features
    - Clock specification
    - Input skew,output skew
    - Cycle delay (##)
- Can be declared inside interface,module or program
o What are the ways to avoid race condition between testbench and RTL using
SystemVerilog?

There are mainly following ways to avoid race condition between testbench
and RTL using system verilog
1. Program Block
2. Clocking Block
3. Using non blocking assignments.

According to the eRM and OVM monitors and drivers should always be
completely separate. This approach was adopted mainly in order to facilitate
reuse of block level agents in a top level testbench: at block level both driver
and monitor are used, while at top level only the monitor is used.