Implement Randc Function Using Rand In

System Verilog ?
Companies Related Questions, Functional Verification, System Verilog October
10, 2018DV admin 0 Comments
How do you implement randc function using rand in system verilog ?

Program :

Understand the difference between randc and rand function

rand : it is random number , it can be repeated.

randc : it is random number with no repetition for a cycle. it may repeat once it
complete one cycle.

Lets write System Verilog Program :

module randc_function;

class rand_clas;

rand bit [1:0] myvar;

bit [1:0] list[$];

constraint cycle { unique {myvar,list};}

function void pre_randomize;

if (list.size() == 4) list = {};

endfunction

function void post_randomize;

list.push_back(myvar);

endfunction

endclass:rand_clas

initial

begin
int x;

rand_clas rand_class = new();

for (int i=0;i<=20;i++) begin

if(rand_class.randomize());

$display(“sucsessfull : Var = %0d “,rand_class.myvar);

end

end

endmodule:randc_function

output

************************************

sucsessfull : Var = 0

sucsessfull : Var = 2

sucsessfull : Var = 3

sucsessfull : Var = 1

sucsessfull : Var = 3

sucsessfull : Var = 2

sucsessfull : Var = 0

sucsessfull : Var = 1

sucsessfull : Var = 2

sucsessfull : Var = 0

sucsessfull : Var = 1

sucsessfull : Var = 3

sucsessfull : Var = 2

sucsessfull : Var = 3

sucsessfull : Var = 0

sucsessfull : Var = 1

sucsessfull : Var = 0
sucsessfull : Var = 1

sucsessfull : Var = 3

sucsessfull : Var = 2

sucsessfull : Var = 1

Write A System Verilog Constraint To Generate

Unique Values In Array Without Unique
Keyword ?
Companies Related Questions, Programming Questions, System Verilog October
1, 2018DV admin 0 Comments

module unique_array;
class data;
rand bit [7:0] data[];
constraint data_values { foreach(data[i])
foreach(data[j])
if(i != j) data[i] != data [j] ;}
endclass

data cl_ob;

initial
begin
cl_ob = new();
cl_ob.data = new[5];
assert(cl_ob.randomize());
foreach(cl_ob.data[i])
$display(“%d”,cl_ob.data[i]);
end
endmodule

Fork Join Tricky Example

Companies Related Questions, System Verilog October 1, 2018DV admin 0
Comments

Lets write some code

module fork_test;
initial begin
for (int j=0; j<3; j++)
begin

fork

$display(j);

join_none

end
end
endmodule

Output

3
3
3
It outputs 3 because there is only one variable j shared by all the threads, and its
value is 3 before any of the threads start executing. None of the threads spawned
by the fork/join_none start executing until the thread spawned by the initial
block finishes.

module fork_test1;
initial begin
for (int j=0; j<3; j++)
begin
#1;
fork

$display(j);

join_none

end
end
endmodule:fork_test1

if you put delay , thread will see different values of j ..but will miss first value .. 0

Output

1
2
3

Using AutoMatic

module fork_test;
initial begin
for (int j=0; j<3; j++)
begin
fork
automatic int k=j;
$display(k);

join_none

end
end
endmodule:fork_test

Output

0
1
2

This works because k, as an automatic variable, is created for each iteration of

the fork block and initialized with the current value if j. Creation and
initialization of automatic variables occurs as each block is activated and does
not wait for execution of the block

Example Of Polymorphism In System Verilog

Companies Related Questions, System Verilog September 24, 2018DV admin 0
Comments

Example 1

// Code your testbench here

// or browse Examples
module poly_case1;
class BaseC;

virtual function void func1;

$display (“func1 in BaseC”);

endfunction

endclass: BaseC

class DerivedC extends BaseC;

function void func1;

$display (“func1 in DerivedC”);

endfunction

endclass : DerivedC

BaseC P1 ;
DerivedC P2 = new;

initial begin
P1 = P2;
P1.func1;
end

endmodule

Output

func1 in DerivedC

Example 2

module poly_case2;

class BaseC;
virtual function void func1;
$display (“func1 in BaseC”);
func2;
endfunction

function void func2;

$display (“func2 in BaseC”);
endfunction

endclass: BaseC

class DerivedC extends BaseC;

function void func1;

$display (“func1 in DerivedC”);
func2;
endfunction

function void func2;

$display (“func2 in DerivedC”);
endfunction

endclass : DerivedC

BaseC P1 ;
DerivedC P2 = new;

initial begin
P1 = P2;
P1.func1;
end

endmodule:poly_case2

output
func1 in DerivedC
func2 in DerivedC

What Is The Need Of Virtual Interfaces?

Companies Related Questions, System Verilog September 14, 2018DV admin 0
Comments

An interface encapsulate a group of inter-related wires, along with their

directions (via modports) and synchronization details (via clocking block). The
major usage of interface is to simplify the connection between modules.

But Interface can’t be instantiated inside program block, class (or similar non-
module entity in SystemVerilog). But they needed to be driven from verification
environment like class. To solve this issue virtual interface concept was
introduced in SV.

Virtual interface is a data type (that implies it can be instantiated in a class)

which hold reference to an interface (that implies the class can drive the
interface using the virtual interface). It provides a mechanism for separating
abstract models and test programs from the actual signals that make up the
design. Another big advantage of virtual interface is that class can dynamically
connect to different physical interfaces in run time.

What Is The Need Of Clocking Blocks ?

Companies Related Questions, System Verilog clocking, verilogSeptember 14,
2018DV admin 0 Comments
What is the need of clocking blocks ?
In Verilog, the communication between blocks is specified using module ports.
SystemVerilog adds the interface, a key construct that encapsulates the
communication between blocks, thereby enabling users to easily change the level
of abstraction at which the intermodule communication is to be modeled. An
interface can specify the signals or nets through which a testbench
communicates with a device under test (DUT). However, an interface does not
explicitly specify any timing disciplines, synchronization requirements, or
clocking paradigms.

SystemVerilog adds the clocking block that identifies clock signals and captures
the timing and synchronization requirements of the blocks being modeled. A
clocking block assembles signals that are synchronous to a particular clock and
makes their timing explicit. The clocking block is a key element in a cycle-based
methodology, which enables users to write testbenches at a higher level of
abstraction. Rather than focusing on signals and transitions in time, the test can
be defined in terms of cycles and transactions. Depending on the environment, a
testbench can contain one or more clocking blocks, each containing its own clock
plus an arbitrary number of signals. The clocking block separates the timing
and synchronization details from the structural, functional, and procedural
elements of a Testbench.

Thus, the timing for sampling and driving clocking block signals is implicit and
relative to the clocking block’s clock. This enables a set of key operations to be
written very succinctly, without explicitly using clocks or specifying timing.
These operations are as follows:
— Synchronous events
— Input sampling
— Synchronous drives
Clocking block in SystemVerilog are used for specifying the clock signal, timing,
and synchronization requirements of various blocks. It separates the timing
related information from structural, functional and procedural element of the TB.
There are quite a few links on clocking block in the internet.

These are links to learn about SV clocking blocks.

– Specify synchronization characteristics of the design
– Offer a clean way to drive and sample signals
– Provides race-free operation if input skew > 0
– Helps in testbench driving the signals at the right time
– Features
– Clock specification
– Input skew,output skew
– Cycle delay (##)
– Can be declared inside interface,module or program

Example :
01.Module Clocking (ck, enin, din, enout, dout);
02.input ck,enin;
03.input [31:0] din ;
04.output enout ;
05.output [31:0] dout ;
06.
07.clocking sd @(posedge ck);
08.input #2ns ein,din ;
09.output #3ns enout, dout;
10.endclocking:sd
11.
12.reg [7:0] sab ;
13.initial begin
 14.sab = sd.din[7:0];
15.end
16.endmodule:Clocking

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Home » Companies Related Questions » What is callback ?

What Is Callback ?
Companies Related Questions, System Verilog September 14, 2018DV admin 0
Comments
We can pass data member to any function. Now consider a case where you are
passing a function (say func1) as a data member to another function (say func2)
and you get what is called callback. The reason why it is called callback is that the
function func2 now can call anywhere in its code function func1.

From wikipedia
In computer programming, a callback is executable code that is passed as an
argument to other code. It allows a lower-level software layer to call a subroutine
(or function) defined in a higher-level layer.

Note that SV doesn’t give a straight-forward way of passing a function as

argument for another function. But we can get the same result (almost we can
say!) by using OOP. The idea is to describe all the functions (both func1 type and
func2 type) in a base class (don’t implement the funct2 kind of function and
make them virtual for polymorphism), and then extend the class to a derived
class where you implement the func2 type of function.

Example:-
class abc_transactor;
virtual task pre_send(); endtask
virtual task post_send(); endtask

task xyz();
// Some code here
this.pre_send();
// Some more code here
this.post_send();
// And some more code here
endtask : xyz
endclass : abc_transactor

class my_abc_transactor extend abc_transactor;

virtual task pre_send();
… // This function is implemented here
endtask

virtual task post_send();

… // This function is implemented here
endtask

endclass : my_abc_transactor

Now let me explain how it is going to work. The base class abc_transactor has 3
tasks, 2 of which are declared virtual and are not implemented. But they are
 being called from another task xyz() which is fully implemented. The
unimplemented virtual task are called callback class.

The child class, which extends from the base class, implements the previous
unimplemented tasks. It inherits the xyz() task from the base class and hence
doesn’t need to change it. By this we can inject executable code to a function
without modifying it.

Now the next question is why is done. There are many reasons for it.

1. The biggest advantage is that you can modify the behavior of task xyz()
without modifying it in the base or child class. It is a big advantage as no
one wants to fiddle with known good functioning code.
2. Consider a case where you are writing a base class which is going to be
used by multiple test environment, and for each test environment a known
part of the code, or a known function/task is going to change. The natural
choice is to implement those change-in-every-case functions/tasks as
callback method and let the user extend your base class with specifying
only that part of the code which need to be changed in his case.
Simple callback using the above approach does have some known
limitations, which can be solved using design patterns (from OOP land),
the details of which can be found at Janik’s article of vmm_callback.
Suppose if you are doing transmitting data using mailboxes, Once you are
send ing data to design from genetarator . The same data you need to put
back in score board for latter comparison. This is called callbacks

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Home » Companies Related Questions » During a project if we observe high code coverage and low functional
coverage what can be inferred and other way around ?

During A Project If We Observe High Code

Coverage And Low Functional Coverage What
Can Be Inferred And Other Way Around ?
Companies Related Questions, System Verilog code coverage, coverage, coverage
metric, functional coverageSeptember 8, 2018DV admin 0 Comments

If coverage metric shows high code coverage

and a low functional coverage then one or
more of following possibilities could be the
cause:
1) Not all functionality is implemented in the design as per the specification.
Hence the code for same is missing while functional coverage metrics exists with
no test

2) There could be potential bugs in the functional coverage monitor

implementation causing them to be not covered even though tests might be
simulated and exercising the design code.

3) There could be a possibility that tests and stimulus exists for covering all
features but those might be failing because of some bugs and hence being
excluded from the measurement for functional coverage.

If coverage metric shows high

functional coverage and a low code coverage
then one or more of following possibilities
could be the cause:
1) some redundant code is written in the design.

2) Extra code is written in the design coverage.

3) Re visit functional coverage see, if the functionality, is it captured correctly ?

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Home » Companies Related Questions » What is the practical application of associative arrays in SV? Can you
explain with a scenario?

What Is The Practical Application Of Associative

Arrays In SV? Can You Explain With A Scenario?
Companies Related Questions, Functional Verification, System
Verilog, UVM September 8, 2018DV admin 0 Comments

When the size of the collection is unknown or the data space is sparse, an
associative array is used, which does not have any storage allocated until it is
used. That means, it is dynamically allocated, but has non-contiguous elements.
Associative array’s index expression is not restricted to integral expressions, but
can be of any type.

Practical Example

RAM(RANDOM ACCESS MEMORY)

in RAM ,huge amount of data needs to be accessed , why do you want to declare the
size in compile time, so it is declared as associative array

Building uvm config using associative array

to build UVM config DB feature , you wanted something which can accessible
from any where with any type ..

See below code for implementation of UVM confib db

// This class is generated using static method and use of associative array !

uvm_config_db::set and uvm_config_db::get methods are used to store and retrive

the information from database respectively.

class uvm_type_of_config_db #( type T =int)

static T db[string]; // static associative array

static function void set(input string name, input T value)

db[name]= value;

endfunction
static function void get(input string name , ref T value);

value= db[name];

endfunction

static function void print();

$display(“Configuration databse %s”, $typename(T));

foreach(db[i])

$diaplay(“db[%s} =%p”,i,db[i]);

endfunction

endclass

We will see example here , how do we use above class

class Dv_testing;

int i,j;

endclass

int i=2;

int val;

real pi=3.14;

Dv_testing dv;

initial begin

//calling set method

uvm_type_of_config_db#(int)::set(“i”,i);

uvm_type_of_config_db#(real)::set(“pi,pi);
dv=new()

dv.i=8;

dv.j=6;

uvm_type_of_config_db#(Dv_testing)::set(“dv”,dv);

//calling get method

uvm_type_of_config_db#(int)::get(“i”,val);

$display(“Value get return of i is %0d”,k); // val value is 2

uvm_type_of_config_db#(int)::print();

uvm_type_of_config_db#(real)::print();

uvm_type_of_config_db#(Dv_testing)::print();

end

Home » Companies Related Questions » Is function overloading possible in SystemVerilog?

Is Function Overloading Possible In

SystemVerilog?
Companies Related Questions, System Verilog September 8, 2018DV admin 0
Comments
No it is possible , as it is not supported , you cannot have different input type of
same function type,

like

Class myClass

int Func(int x) { }
int Func(string s) { }

int Func(int x,string s) { }