Microwave Amplifier Design

1
 Microwave
c owave Amplifier
p e Design
es g

• Two-Port Power Gains

Figure 11-1 (p. 537) A two-port network with general source and load impedances.
Pavs  Pin
Power Gain  G  L S , L 
P in  S

Pin Pavn  PL  
L  out

Available Gain  G A 
Pavn
S , S  L 
Z L  Z0
Pavs
Z L  Z0
Transducer Power Gain  GT 
PL
S , S , L  S 
Z S  Z0
Pavs
Z S  Z0
2
 Two
wo Port
o t Power
owe Gains
Ga s

2
V1
1     8Z 1   
2 2
2 VS 1  S 2
Pin  in 2 in
2Z 0 0 1  S in
V2  S 21V1  S 22V2  S 21V1  S 22 LV2
VS S 21 1  S 

2 1  S 22 L 1  S in 
V1 S S  Z  Z0
in    S11  12 21 L  in
V1 1  S 22L Z in  Z 0
PL 
V
2
 2

1  
2 VS
2 2

S 21 1  L 1  S
2
 2

L 2 2
V 
S S  2Z 0 8Z 1  S 0 22 L 1  S in
out   S 22  12 21 S
S 1   
2

V2 1  S11S P
2 2

G  21
. L

1    1  S 
L

 V1  V1  V1 1  in 

Z in P 2 2
V1  VS in
in 22 L
Z S  Z in
VS 1  S
V1 
2 1  S in

3
 Two
wo Port
o t Power
owe Gains
Ga s

VS
2
1  S
2
Special case 1 : both input and
Pavs  Pin in  S

8Z 0 1  S  2
 output matched
 L  S  0
Pavn  PL   
VS
2 2

S 21 1  out 1  S
2
 2

GT  S 21
2

L  outt
8Z 0 1  S   2 1    2
22 out S in 
L  out Special case 2 : unilateral transducer
VS
2 2
S 21 1  S
2 power gain, S12  0

 
8Z 0 1  S11S 2 1  out 2  in  S11

P S 1   
2 2
GTU 
2
S 21 1  S  2
1   
L
2

1  S  1   
G A  avn  21
2
S
2
2
1  S11S 1  S 22 L
2
Pavs 11 S out

S 1   1   
2 2 2
PL
GT   21
2
S L
2
Pavs 1  S in 1  S 22 L

4
 Two
wo Port
o t Power
owe Gains
Ga s

• Example 11.1 Comparison of Power Gain Definitions

A microwave transistor has the following S parameters at 10 GHz, with a 50 
reference impedance :
S11  0.45150o , S12  0.01  10o , S 21  2.0510o , S 22  0.40  150o
Z S  20 , Z L  30 .
Solution
L 
Z L  Z0
 0.250 G
 2
S 21 1  L  5.94
2

Z L  Z0
Z  Z0
1    1  S 
in
2
22 L
2

S  S  0.429 S 1   
2 2
Z S  Z0 G  21
 5.85 S

1  S  1   
A
S S  2 2
in  S11  12 21 L  0.455150o 11 S out

S 1   1   
1  S 22 L 2 2 2

S S  G  21
 5.49S L

out  S 22  12 21 S  0.408  151o T

1  S in 1  S 22L
2 2

1  S11S
5
 Two
wo Port
o t Power
owe Gains
Ga s

Figure 11-2 (p. 540) The general transistor amplifier circuit.

Eff ti gain
Effective i for
f ththe input
i t (source)
( ) Effective
Eff ti gain
i for
f th the output
t t (load)
(l d)
matching network : matching network :
2 2
1  S 1  L
GS  2
GL  2
1  in S 1  22 L
Transducer power gain for transistor : The overall transducer gain :
G0  S 21
2
GT  GS G0GL

6
 Two
wo Port
o t Power
owe Gains
Ga s

• If the transistor is unilateral, Conjugate match GaAs FET equivalent CKT

so that S12 = 0
→ in = S11,
out = S22
2
1  S
GS  2
1  S11S
1
2 X  Z in  Z S
G0  S 21  C gs
2 B   Cds  Z out  Z L
1  L
GL  2 VS
1  S 22 L Vc 
2 j Ri C gs
The overall transducer gain : 2 2
GT  GS G0GL PL 1
g mVc Rds 2
g Rds Rds  fT 
GTU   8
 m
  
Pavs 1
8 VS
2
Ri 4 Ri C gs2 4 Ri
2
 f 
7
 Two
wo Port
o t Power
owe Gains
Ga s

Figure
g 11-4 (p.
p 542)
Photograph of a low noise MMIC amplifier using three HEMTs with coplanar waveguide circuitry. The
amplifier has a gain of 20 dB from 20 to 24 GHz. The contact pads on the left and right of the chip are for RF
input and output, with DC bias connections at the top. Chip dimensions are 1.1  2.0 mm.
Courtesy of R.
R W.
W Jackson and B
B. Hou of the University of Massachusetts and JJ. Wendler of M/A-COM.
M/A-COM

8
 Stab ty
Stability

• Unconditional stability:
in  1, out  1 for all p
passive source and load impedances
p
i.e., S  1, L  1
• Conditional stability:
in  1, out  1 only for a certain range of passive source and load
impedances, This case is also referred to as potentially unstable

• Frequency dependence

• Rigorous treatment of stability requires that the network S parameters have

no poles
l ini the
h right-half
i h h lf complex
l frequency
f plane,
l in
i addition
ddi i to |in| < 1
and |out| < 1.

9
 Stab ty
Stability

• Stability Circles
Conditions for unconditionally The equation for the output stability circle :
stable amplifier : S12 S 21L
in  S11  1
S12 S 21L 1  S 22 L
ini  S11  1
1  S 22 L or S11 1  S 22 L   S12 S 21L  1  S 22 L
S12 S 21S   S11S 22  S12 S 21
outt  S 22  1
1  S11S  S11  L  1  S 22L
If the device is unilateral ( S12  0)
L L 
S 
  
 
22  S11 L  S 22   S11 L  
2
S11  1
these
h conditions
di i d
reduce to : 2 2 2 2
S 22   S 22  
S11  1
S 22  1
Adding S 22  S  2
11 S 22
2
 
2 2
to both sides

 L 
S 
22  S11  


S12 S 21
2 2 2 2
S 22   S 22  
10
 Stab ty
Stability

• Stability Circles
Output stability circle : Input stability circle :
L  C L  RL S  CS  RS

CL 
S 
22  S11  

( t )
(center) CS 
S 
11  S 22 


( t )
(center)
2 2 2 2
S 22   S11  

S12 S 21 S12 S 21
RL  2 2
(radius) RS  2 2
(radius)
S 22   S11  

If we set Z L  Z 0 , then L  0 If the device is unconditional stable,

stable
 in  S11  stability circle is completely
 S11  1  Figure 11.5(a)
11 5(a) outside the Smith chart.

 S11  1  Figure 11.5(b) C L  RL  1, for S11  1

CS  RS  1, for S 22  1
11
 Stab ty
Stability

Figure 11-5 (p. 544)

p stabilityy circles for a conditionallyy stable device. ((a)) ||S11| < 1. ((b)) ||S11| > 1.
Output

12
 Stab ty
Stability

• Tests for Unconditional Stability

K   test :   test :
Rollet' s condition S12 S 21S S  S
out  S 22   22 1
2
1  S11  S 22  
2 2
1  S11S 1  S11S
K  1,
2 S12 S 21 S 22  out
S boundary  S  e j  1
Auxiliary condition   S11out
  S11S 22  S12 S 21  1, 
2 2
S  S 22 S12 S 21
 out  11

are simultaneously satisfied.
Also, we must have
1  S11
2
1  S 
11
2 2

 out  C  R
S11  1
2
S 22  1  C  R  1  S 22  S11  S12 S 21  1  S11 ,
2
1  S11
  
 1.
S 22  S  S12 S 21
11
13
 Stab ty
Stability

• Example 11.2 Transistor Stability

The S parameters for the HP HFET - 102 GaAs FET at 2 GHz with a bias voltage
Vgs  0 are given as follows ( Z 0  50 )
S11  0.894  60.6o , S12  0.0262.4o , S 21  3.122123.6o , S 22  0.781  27.6o
Solution
K   test :
Rollet' s condition CL 
S 22  S 
11 

 1.36147 o
2 2
2 2 2
S 22  
1  S11  S 22  
K  0.607 S12 S 21
2 S12 S 21 RL   0.50
2 2
Auxiliary condition S 22  

  S11S 22  S12 S 21  0.696

CS 
S 
11  S 22 

 1.13268o
2 2
  test : S11  
2
1  S11 S12 S 21
 
 0.86 RS  2 2
 0.199
S 22  S  S12 S 21
11 S11  
14
 Stab ty
Stability

Figure 11-6 (p. 549)

Stability circles for Example 11.2.

15
 Single-Stage
S g e Stage Transistor
a s sto Amplifier
p e Design
es g

• Design for Maximum Gain (Conjugate Matching)

Since G0 is fixed,, the overall g
gain Solvingg for S
will be controlled by GS and GL . S12 S 21

S  S  11
Maximum Gain if conjugate matching 1 L  S 22

in  S and out  L S 22  S

L 
1  L
2 1  S11S
1
 
2
 GTmax 
1  S
2
S 21
1  S 22 L
2  
 S11  S 22  2 2
S2    S11  S 22  1 S
2

In the general bilateral circuit :  

 S11   S 22  0
matching condition require B1  B12  4 C1
2

S12 S 21L S 

  S11  2C1
1  S 22 L
S
2
B2  B22  4 C2
S12 S 21S Similarly, L 
L  S 22  2C2
2C
1  S11S
16
 Single-Stage
S g e Stage Transistor
a s sto Amplifier
p e Design
es g

The variables B1 , C1 , B2 , C2 are The unilateral case :

defined as S12  0
2
B1  1  S11  S 22  
2 2
 S  S11 , L  S 22


2 2 2 1 2 1
B2  1  S 22  S11   GTU max  2
S 21 2

1  S11 1  S 22
C1  S11  S 22

If the transistor is unconditionally stable,
C2  S 22  S 11
so that K  1

1
2 2
 B  4 C1  0, GTmax 
S 21
S12
K  K 2 1 
2
B22  4 C2  0 If K  1, simultaneous conjugate matching
 K 1 possible  maximum stable gain :
is not possible,
S 21
Gmsg 
S12

17
 Single-Stage
S g e Stage Transistor
a s sto Amplifier
p e Design
es g

• Example 11.3 Conjugately Matched Amplifier Design

Design an amplifier for maximum gain at 4.0 GHz using single - stub matching
sections. Calculate and plot the input return loss and the gain from 3 to 5 GHz.
The GaAs FET has the following S parameters ( Z 0  50 )
f (GHz)
(GH ) S11 S 21 S12 S 22
3.0 0.80  89o 2.8699o 0.0356o 0.76  41o
40
4.0 0.72  116o 2.6076o 0.0357 o 0.73  54o
5.0 0.66  142o 2.3954o 0.0362o 0.72  68o
Solution
For maximum gain,
Check K   test at 4.0 GHz
2
2
1  S11  S 22  
2 2 B1  B12  4 C1
K  1.195 S   0.872123o
2 S12 S 21 2C1
2
  S11S 22  S12 S 21  0.488  162o B2  B22  4 C2
L   0.87661o
2C2
18
 Single-Stage
S g e Stage Transistor
a s sto Amplifier
p e Design
es g

Solution (continued)
1
GS  2
 4.17  6.20 dB
1  S
2
G0  S 21  6.76  8.30 dB
2
1  L
GL  2
 1.67  2.22 dB
1  S 22 L
The overall transducer gain,
GTmax  6.20  8.30  2.22  16.72 dB

Figure
g (p. 553)) ((b)) RF circuit.
11-7b (p Figure 11-7a (p. 552)
(a) Smith chart for the design of the input matching network.
19
Single-Stage
S g e Stage Transistor
a s sto Amplifier
p e Design
es g

Fi
Figure 11 7b ((p. 553) (c)
11-7b ( )FFrequency response.
20
 Single-Stage
S g e Stage Transistor
a s sto Amplifier
p e Design
es g

• Constant Gain Circles and Design for Specified Gain

S12 is small enough
g to ignored,
g 1
GS max 
 unilateral. 1  S11
2

1 GT 1 1
  GLmax 
1  U 2
GTU 1  U 2
1  S 22
2

U : unilateral figure of merit

Define normalized gain factors :
S12 S 21 S11 S 22
1  S ,
2
U 1  S
1  S  1  S 
G 2
2 2 gS  S  2 11
11 22 GS max 1  S11S
2
1  S
1  S .
2
GS  GL 1  L 2
2 gL  
1  S11S GLmax 1  S 22 L 2 22

2
1  L
GL  2
1  S 22L

21
 Single-Stage
S g e Stage Transistor
a s sto Amplifier
p e Design
es g

• Constant Gain Circles and Design for Specified Gain

For fixed value of g S : g S S11
CS 
 1  S ,
,
1  1  g S  S11
2 2 2 2
g S 1  S11S  1  S 11


S  

g S S11S  S 
11  2
1  S11  g S
RS 

1  g S 1  S11
2
.
1  1  g S  S11 1  1  g S  S11 1  1  g S  S11
S 2 2 2

S 
g S S11


1  g S 1  S11
2

Similarly, for fixed value of g L :
1  1  g S  S11 1  1  g S  S11
2 2

L  C L  RL


g L S 22
S  CS  RS CL  ,
1  1  g L  S 22
2

RL 

1  g L 1  S 22
2
.
1  1  g L  S 22
2

22
 Single-Stage
S g e Stage Transistor
a s sto Amplifier
p e Design
es g

• Example 11.4 Amplifier Design for Specified Gain

Design an amplifier to have a gain of 11 dB at 4.0 GHz. Plot constant gain
circles for GS  2 dB and 3 dB, and GL  0 dB and 1 dB. Calculate and plot the
input return loss and overall amplifier gain from 3 to 5 GHz. The FET has the
following S parameters ( Z 0  50 )
f (GHz) S11 S 21 S12 S 22
30
3.0 0.80  90o 2.8100o 0 0.66  50o
4.0 0.75  120o 2.586o 0 0.60  70o
50
5.0 0.71  140o 2.360o 0 0.58  85o
Solution
1
GS max  2
 2.29  3.6 dB 2
G0  S 21  6.25  8.0 dB
1  S11
GTU max  3.6  1.9  8.0  13.5 dB
1
GLmax  2
 1.56  1.9 dB
1  S 22
23
 Single-Stage
S g e Stage Transistor
a s sto Amplifier
p e Design
es g

Solution (continued)
GS  3 dB g S  0.875
CS  0.706120o RS  0.166
GS  2 dB g S  0.691
CS  0.627120o RS  0.294
GL  1 dB g L  0.806
C L  0.52070o RL  0.303
GL  0 dB g L  0.640
C L  0.44070o RL  0.440

Figure 11-8a/b (p. 556) (a) Constant gain circles. (b) RF circuit.
24
Single-Stage
S g e Stage Transistor
a s sto Amplifier
p e Design
es g

Figure
g (p. 557)) ((c)) Transducer ggain and return loss.
11-8b (p

25
 Single-Stage
S g e Stage Transistor
a s sto Amplifier
p e Design
es g

• Low-Noise Amplifier Design

Derivation of circles of constant noise figure  1 1  S
YS 
Noise figure for a two - port amplifier : Z 0 1  S
R 2
F  Fmin  N YS  Yopt , 1 1  opt
Yopt 
GS Z 0 1  opt
where
YS  GS  jBS  source admittance
Yopt  optimum source admittance Fmin  
Fmin  minimum noise figure 
 Noise parameters of the device
RN  equivalent noise resistance of transistor 
GS  reall partt off source admittance
d itt

26
 Single-Stage
S g e Stage Transistor
a s sto Amplifier
p e Design
es g

2 4 S  opt
2
S 
 opt  S  opt


 N 1  S  2

YS  Yopt  2
Z0 1   2 1  
S optt
2

S S  S opt

 Sopt  opt opt

 N  N S
2

GS  ReYS  
1  1  S 1  S 
   S S 
  S

opt

 
S opt  N   opt
2

 
2Z 0  1  S 1  S  N 1 N 1


1 1  S
2

2 S 
opt


N N  1  opt
2

Z 0 1  S N 1 N 1
S  opt
2

4 RN
F  Fmini  .
Z0 1 
S
2

1  opt
2
 S  C F  RF
opt
Define the noise figure parameter, N : CF 
N 1
 
2
S  opt F  Fmin 2 2
N  1  opt N N  1  opt
1  S
2
4 RN Z 0 RF 
N 1
27
 Single-Stage
S g e Stage Transistor
a s sto Amplifier
p e Design
es g

• Example 11.5 Low-Noise Amplifier Design

A GaAs FET is biased for minimum noise figure, and has the following S para -
meters and noise parameters at 4 GHz ( Z 0  50 ) : S11  0.6  60o , S12  0.0526o ,
S 21  1.981o , S 22  0.5  60o ; Fmin  1.6 dB, opt  0.62100o , RN  20 . Calculate
the maximum error in GT if device is assumed unilateral. Then design an amplifier
having a 2 dB noise figure with the maximum gain with this noise figure.
Solution
S12 S 21 S11 S 22 F  Fmin 2
U  0.059 N 1  optt  0.0986
1  S  1  S 
11
2
22
2
4 RN Z 0
1 GT 1 opt
  CF   0.56100o
1  U 2 GTU 1  U 2 N 1

or 0.891 0.5 dB 

GT
 1.1300.5 dB RF 

N N  1  opt
2
  0.24
GTU N 1
28
 Single-Stage
S g e Stage Transistor
a s sto Amplifier
p e Design
es g

Solution (continued)
constant g
gain circles
GS (dB) gS CS RS
1.0 0.805 0.5260o 0.300
1.5 0.904 0.5660o 0.205
1.7 0.946 0.5860o 0.150
 S  0.5375o

Choose L  S 22  0.5600 for
maximum GL :

GL  1 1  S 22
2
  1.33  1.25 dB
2
G0  S 21  3.61  5.58 dB
Figure 11-9a (p. 561)
GTU  GS  G0  GL  8.53 dB Circuit design for the transistor amplifier of Example 11.5.
11 5
(a) Constant gain and noise figure circles. (b) RF circuit.
29
 Broadband
oadba d Transistor
a s sto Amplifier
p e Design
es g

• Narrow bandwidth due to

– Matching requirement for maximum gain ↔ transistors are not 50
– |S21| decreases with frequency at the rate of 6 dB/octave

• Common approaches for broadband (cost: gain, complexity…)

– Compensated matching networks (|S21|,| cost: input/output matching)
– Resistive matching networks (matching, cost: gain loss and noise figure)
– Negative feedback (frequency response, matching, stability, cost: gain
and noise figure)
– Balanced amplifiers (broadband match, cost: twice transistor & power)
– Distributed amplifiers (broadband gain, matching, noise figure, cost:
circuit size, single stage gain)

30
 Broadband
oadba d Transistor
a s sto Amplifier
p e Design
es g

• Balanced Amplifiers

Figure 11-10 (p. 562) A balanced amplifier using 90° hybrid couplers.
 S11 S12  1  A  B  j S12 A  S12 B 
S    
 21 S 22  2  j G A  GB   S 22 A  S 22 B  
IF the amplifier are identical  S11  0, G  G A  GB
1
F  FA  FB 
2
31
 Broadband
oadba d Transistor
a s sto Amplifier
p e Design
es g

• Example 11.6 Performance and Optimization of a Balanced Amplifier

Matching Network Before After

Parameter Optimization Optimization
Input section stub length 0.100 0.109
Input section line length 0.179 0.113
Output section line length 0.045 0.134
Output section stub length 0.432 0.461

Figure 11-11 (p. 564) Gain and return loss, before and after
optimization,
ti i ti for
f the
th balanced
b l d amplifier
lifi off Example
E l 11.6.
11 6
32
 Broadband
oadba d Transistor
a s sto Amplifier
p e Design
es g

• Distributed Amplifiers

Figure 11-12 (p. 565) Configuration of an N-stage distributed amplifier.

Figure 11-13 (p. 566) (a) Transmission line circuit

for the gate line of the distributed amplifier;
33
 Broadband
oadba d Transistor
a s sto Amplifier
p e Design
es g

• Distributed Amplifiers

Figure 11-13 (p. 566) (b) equivalent circuit Figure 11-14 (p. 566) (b) equivalent circuit
of a single unit cell of the gate line. of a single unit cell of the drain line.

Figure 11-14 (p. 566) (a) Transmission line circuit

f the
for th drain
d i line
li off the
th distributed
di t ib t d amplifier;
lifi
34
 Broadband
oadba d Transistor
a s sto Amplifier
p e Design
es g

• Distributed Amplifiers Example 11.7

 2 Ri C gs2 Z g  C gs  Assume Z d  Z g  Z 0  50 ,
 g   g  j g  
 j Lg C g  
2 lg  l g  Ri  10 , Rds  300 ,

C gs  0.27 pF, g m  35 mS.
Zd  Cds 
 d   d  j d  
 j Ld  Cd  
 N  2, 4, 8, 16; f  1 ~ 18 GHz.
2 Rds ld  ld 
 N l
g mVi e g g  e  N d ld
Io  
2 e  g l g  e  d l d
2  N g l g 2
 N d ld
Pout g Z d Z g e e
G 
m
 l
Pin 4 e g g  e  d l d



g m2 Z d Z g e  N g l g  e  N d ld 
2

4 e 
 g l g
e  d ld 2

ln  g l g  d ld 
N optt 
 g l g   d ld
35
 Power
owe Amplifiers
p es

• Characteristics of Power Amplifiers and Amplifier Classes

– Important considerations for power amplifier: efficiency,
efficiency gain,
gain
intermodulation products, thermal effects.
– LNA, fixed gain Amp: small-signal amplifiers (transistor: linear device)
Amplifier efficiency : Compressed Gain :
Pout G1 dB  G0 dB  1

PDC  Linearity, intermodulation distortion
power added efficiency : Class A : linear, always conduct
Pout  Pin maximum efficiency 50%
 PAE  PAE 
PDC Class B : conduct only 1/2 cycle
 1P  1 pushh - pull
ll type, 78%
 1   out  1  
 G  PDC  G  Class C : near cutoff more than 1/2 cycle
efficiency near 100%,
100% resonant circuit
36
 Power
owe Amplifiers
p es

• Large-Signal Characterization of Transistors

– For power near or larger than P1, S parameters will depend on input
power level, output impedance, frequency, bias condition, temperature.

– Table 11.1 Small-Signal S Parameters and Large-Signal Reflection

Coefficients (Silicon Bipolar Power Transistor)
f MHz  S11 S12 S 21 S 22 SP LP GP dB
800 0.76176o 4.1076o 0.06549o 0.35  163o 0.856  167 o 0.455129o 13.5
900 0 76172o
0.76 3.4272o 0 07352o
0.073 0 35  167 o
0.35 0 747  177 o
0.747 0 478161o
0.478 12 0
12.0
1000 0.76169o 3.0869o 0.07953o 0.36  169o 0.797  187 o 0.491185o 10.0

37
 Power
owe Amplifiers
p es

• Load-pull contours
Automated measurement
with electromechanical
stub tuners

Nonlinar models :
C gs , g m , C gd , Rds

Temperature!!!

Figure 11-16 (p. 572)

Constant output power contours versus load impedance for a typical power FET.
38
 Power
owe Amplifiers
p es

• Example 11.8 Design of a Class A Power Amplifier

Design
g a ppower amplifier
p at 900 MHz usingg Motorola MRF858S NPN silicon BJT.

Solution

39
 Power
owe Amplifiers
p es

Figure 11-17 (p. 574) RF circuit for the amplifier of Example 11.8.

40