F_ID FEATURE DESCRIPTION

To configure the registers for write

1 All Registers
and read operation

To check the default value of registers

2 Default register values
after reset

To check reading data from the

3 Empty FIFO Read
empty receive FIFO

To check reading from Tx_data

register which is write only and also
4 Illegal Write & Read
writing into Rx_data register which is
read only

To check stop bit in received UART

5 Framing Error
frame is 0.

To check the behaviour when a new

6 Overrun Error character is received while receiver
FIFO is FULL.

To check both the data and the stop

7 Break Error
bit received are all zeros.
 To check if the number of elements
8 Tx Threshold present in the transmit FIFO is above
or below the set threshold

To check if the number of elements

9 Rx Threshold present in the receive FIFO is above
or below the set threshold

To check behaviour of invalid stop

10 Different stop bit
bits like 1.5(01) and 2(10)

To check behaviour of illegal stop bit

11 Illegal Stop bit value 3(11)

To check no parity, odd parity and

12 Parity condition
even parity condition

13 Illegal parity condition To check behaviour of illegal parity bit

value 3(11)

To check different data bit size in

14 Different data size
UART frame other than 8 like (5,6,7)

15 Interrupt To enable all the interrupts

 To enable frame_error interrupt in
16 Framing error interrupt interrupt_en register

To enable break_error interrupt in

17 Break error interrupt
interrupt_en register

To enable overrun_error interrupt in

18 Overrun error interrupt
interrupt_en register

Tx_threshold_hit To enable tx_thld_hit interrupt in

19
interrupt interrupt_en register

Rx_threshold_hit To enable rx_thld_hit interrupt in

20 interrupt interrupt_en register

Min & Max register To check the minimum and maximum

21
values values of all registers

22 Different baud values To check different baud divisor value

within and above given limit(16 bit)
 PROJECT TITLE : C3
Team member : Athira, Phebeyal
TESTCASE NAME TESTCASE FLOW

C testcase : Generate clock and after applying the reset, 1.

1. uart_write Writing values to tx_data register 2.
2. uart_write_reg Writing values to control register,baud register and
3. uart_read status_clear register
4. uart_read_reg 3. Read values from rx_data register
4. Read values from baud register, control register,
status register, interrupt_en register

Generate clock and after applying reset, read the default

C testcase : uart_reg_values_after_reset
value of all the registers

Generate clock and after applying reset, without

C testcase : uart_empty_fifo_read trasmitting any data from VIP , trying to read the value
from FIFO

C testcase : Generate clock and after applying reset,

1. uart_tx_reg_illegal_read 2. 1. read the value from tx_data register (write-only) 2.
uart_rx_reg_illegal_write write the value into rx_data register(read-only)

UVM testcase : Generate clock and after applying reset, driving the value
chromite_soc_uart_framing_error to tx_data register from VIP by configuring stop bit as 0

Generate clock and after applying reset, driving data

C testcase : uart_overrun_error
more than the receive FIFO depth from VIP

Generate clock and after applying reset, driving the value

UVM testcase :
to tx_data register from VIP by configuring both data and
chromite_soc_uart_break_error
stop bit as 0
 Generate clock and after applying reset, configure the
12th bit of control register, 1.
12th bit as 1 to indicate value in transmit FIFO is greater
C testcase :
than threshold value set at [19:16] bit of control register
1. uart_tx_thld_dir_1
2. 12th bit as 0 to
2. uart_tx_thld_dir_0
indicate value in transmit FIFO is less than or equal to
threshold value set at [19:16] bit of control register

Generate clock and after applying reset, configure the

13th bit of control register, 1.
C testcase : 13th bit as 1 to indicate value in receive FIFO is greater
1. uart_rx_thld_dir_1 than threshold value set at [23:20] bit of control register
2. uart_rx_thld_dir_0 2. 13th bit as 0 to
indicate value in receive FIFO is less than or equal to
threshold value set at [23:20] bit of control register

Generate clock and after applying reset, configure the

C testcase : control register [1:0] bit for different stop bit,
1. uart_invalid_stop_bit_1.5 2. 1. [1:0] bit as 01(1.5 stop bit)
uart_invalid_stop_bit_2 2. [1:0[ bit as 10(2 stop bit)

Generate clock and after applying reset, configure the

C testcase : uart_illegal_stop_bit control register [1:0] bit for stop bit as 11 which is illegal.

Generate clock and after applying reset, configure the

C testcase : control register [3:2] bit for different parity,
1. uart_parity_0 1. [3:2] bit as 00(no parity condition)
2. uart_parity_odd 2. [3:2] bit as 01(odd parity
3. uart_parity_even condition) 3. [3:2] bit as 10(even
parity condition)

Generate clock and after applying reset, configure the

C testcase :
control register [3:2] bit for parity bit as 11 which is
uart_parity_illegal
illegal.

Generate clock and after applying reset, configure the

C testcase : control register [7:4] bit for different data size,
1. uart_data_bit_5 1. [7:4] bit as 0101(data bit size as 5)
2. uart_data_bit_6 2. [7:4] bit as 0110(data bit size
3. uart_data_bit_7 as 6) 3. [7:4] bit as 0111(data bit size
as 7)

C testcase: Generate clock and after applying reset, configure the

uart_interrupt interrupt_en register and enable all the register
 Generate clock and after applying reset, configure the
C testcase: 10th bit of interrupt_en register to 1 in c testcase and
uart_frame_error_interrupt also include logic for framing error to occur in UVM
testcase

Generate clock and after applying reset, configure the

C testcase: 11th bit of interrupt_en register to 1 in c testcase and
uart_break_error_interrupt also include logic for break error to occur in UVM
testcase

Generate clock and after applying reset, configure the 9th

C testcase:
bit of interrupt_en register to 1 and also include logic for
uart_overrun_error_interrupt
overrun error to occur

Generate clock and after applying reset, configure the 4th

C testcase:
bit of interrupt_en register to 1 and also include logic for
uart_tx_thld_hit_interrupt
tx_thld_hit to occur

Generate clock and after applying reset, configure the 5th

C testcase:
uart_rx_thld_hit_interrupt bit of interrupt_en register to 1 and also include logic for
rx_thld_hit to occur

C testcase : Generate clock and after applying reset,write the

uart_min_max_reg_values minimum and maximum values to all the registers

C testcase :
Generate clock and after applying reset, configure the
1.uart_baud_1 baud register with different divisor value and data in
2. uart_baud_5
tx_data register
3. uart_baud_65535
PROJECT TITLE : C32 SoC (UART)

REGISTER VALUES CHECK BY

Written values :
tx_data reg = ef, 57, 64, 27 baud
reg = 5
control reg = FF0080
status_clear = 11111
interrupt_en = 111111111111 Read Scoreboard checker
values : rx_data reg
= ef, 48, ab, 32 baud reg = 5
control reg =
FF0080 interrupt_en =
111111111111 status = 17

Read values :
Baud = 5, tx_data = 0, rx_data = 0,
From C testacse
control = 2880, status = 17, interrupt_en
= 0, status_clear = 0

Read value : 0 From C testcase

- From C testcase

Written values :
tx_data reg = ef (In uart_config stop bit From C testcase
as 0)

Written values :
tx_data reg = ef, 48, ab, 32 (same value From C testcase
are reeated until FIFO becomes full )

Written values :
tx_data reg = 00 (In uart_config stop bit From C testcase
as 0)
 Written values :
1.tx_data reg = ef, 57, 64, 27
control reg =
F10480(tx_thld_dir = 1) From C testcase
2. tx_data reg = ef, 57, 64, 27
control reg =
F21480 (tx_thld_dir = 0)

Written values :
1.control reg = 2F3C80(rx_thld_dir = 1)
From C testcase
2. control reg =
2F1C80(rx_thld_dir =0)

Written values :
1.control reg = FF0081(stop_bits=01)
From C testcase
2. control reg =
FF0082(stop_bits=10)

Written values :
control reg = FF0083(stop_bits=11) From C testcase

Written values :
1.control reg = FF0080(parity=00)
2. control reg = From C testcase
FF0084(parity=01) 3. control reg =
FF0088(parity=10)

Written values :
From C testcase
control reg = FF008C(parity=11)

Written values :
1.control reg = FF0050(charsize=00)
2. control reg = From C testcase
FF0060(charsize=01) 3. control reg =
FF0070(charsize=10)

Written values :
From C testcase
interrupt_en = 111111111111
Written values :
interrupt_en = 010000000000 From C testcase

Written values :
From C testcase
interrupt_en = 100000000000

Written values :
From C testcase
interrupt_en = 001000000000

Written values :
From C testcase
interrupt_en = 000000010000

Written values :
interrupt_en = 000000100000 From C testcase

Written values :
tx_data reg = random values
baud reg = 0, 65534
From C testcase
control reg = 000000,
FFFFFF interrupt_en =
111111111111,0

Written values :
baud reg = 0, 5, 65535(above 16 bit) From C testcase
tx_data reg = ef
 PASSING CRITERIA COVER_POINT VERIFIED

Written values :
tx_data reg = ef, 57, 64, 27 baud
reg = 5 control
reg = FF0080 status_clear =
11111 interrupt_en =
111111111111 Read values :
rx_data reg = ef, 48, ab, 32
baud reg = 5
control reg = FF0080
interrupt_en = 111111111111
status = 17

Baud = 5, tx_data = 0, rx_data = 0, control

= 2880, status = 17, interrupt_en = 0,
status_clear = 0

Warning message from CPU

Trap will occur for writing in read only

register and reading from write only
register

In received frame, stop bit should be 0 for

1 clock cycle and 10th bit of status
register should be 1

FIFO over flow condition should occur in

receiver and 9th bit of status register
should be 1

Whole frame should be 0(data+stop) and

11th bit of status register should be 1
 1. 4th bit of status register will be set if
no.of.elements in TX FIFO are greater
than threshold
2. 4th bit of status register will be
set if no.of.elements in TX FIFO are less
than or equal to threshold

1. 5th bit of status register will be set if

no.of.elements in RX FIFO are greater
than threshold
2. 5th bit of status register will be
set if no.of.elements in RX FIFO are less
than or equal to threshold

1.Stop bit value will be 1 for one and half

clock cycle
2. Stop bit value will be 1 for
two clock cycle

Stop bit value of 1 will be generated

continuously for all clock cycle

1. In UART frame there will be no parity

bit for no parity condition(00)
2. Parity bit will be 1, if
no.of.ones in data is odd for odd parity
condition 3. Parity bit will be 1 if
no.of.ones in data is even for even parity
condition

Parity bit will be always 0 independent of

no.of.ones present in the data

1.For data size 5, the frame will not be

generated
2.For data size 6, the frame will
have 6 bit data
3. For data size 7, the frame will
have 7 bit data

Corresponding interrupt should be

generated based on the status register
 10th bit of status bit should become 1
and frame_error interrupt should be
generated

11th bit of status bit should become 1

and break_error interrupt should be
generated

9th bit of status bit should become 1 and

overrun_error interrupt should be
generated

4th bit of status bit should become 1 and

tx_thld_hit interrupt should be generated

5th bit of status bit should become 1 and

rx_thld_hit interrupt should be generated

Written values :
tx_data reg = random values
baud reg = 0, 65534
control reg = 000000,
FFFFFF interrupt_en =
111111111111,0

For baud 65535, the entire UART frame

will be 0. For other baud divisor values it
should have proper baud clock