M2 – Instruction Set Architecture

Module Outline
●
RISC-V ISA
●
Addressing modes, Instruction classes
●
High level languages, Assembly languages
and object code.
●
Translating and starting a program.
●
Subroutine and subroutine call. Use of stack
for handling subroutine call and return.
 Module Outline
●
RISC-V ISA
●
Addressing modes, Instruction classes
●
High level languages, Assembly languages
and object code.
●
Translating and starting a program.
●
Subroutine and subroutine call. Use of stack
for handling subroutine call and return.
 Instruction Set Architecture
●
Instruction Set: A vocabulary of commands
understood by an architecture
 Instruction Set Architecture
●
Instruction Set: A vocabulary of commands
understood by an architecture
●
ISA includes:
– All available instructions (Instruction Set)
– How are operands specified (Addressing modes)
– What does each instruction look like (Instruction
format)
 Instruction Set Architecture
●
Instruction Set: A vocabulary of commands
understood by an architecture
●
ISA includes:
– All available instructions (Instruction Set)
– How are operands specified (Addressing modes)
– What does each instruction look like (Instruction
format)
●
ISA design goal:
– Find a language that makes it easy to build the
hardware and compiler while maximizing
performance and minimizing cost.
 Types of Instructions
●
Arithmetic and Logic Instructions
–

●
Data Transfer Instructions
–

–
 Types of Instructions
●
Arithmetic and Logic Instructions
– add, subtract, multiply, divide, compare (int/fp)
– or, and, xor, not
– shift (left/right, arithmetic/logical), rotate
●
Data Transfer Instructions
–

–
 Types of Instructions
●
Arithmetic and Logic Instructions
– add, subtract, multiply, divide, compare (int/fp)
– or, and, xor, not
– shift (left/right, arithmetic/logical), rotate
●
Data Transfer Instructions
– load (copy data to a register from memory)
– store (copy data to a memory location from a
register)
 Types of Instructions
●
Control transfer instructions
–

●
System instructions
–
 Types of Instructions
●
Control transfer instructions
– jump, conditional branch, function call, return
●
System instructions
–
 Types of Instructions
●
Control transfer instructions
– jump, conditional branch, function call, return
●
System/Privileged instructions
– scall, eret, ...
 Types of Instructions
●
Control transfer instructions
– jump, conditional branch, function call, return
●
System/Privileged instructions
– scall, eret, ...
– to access system functionality, might require
privileged access
 Types of Instructions
●
Control transfer instructions
– jump, conditional branch, function call, return
●
System/Privileged instructions
– scall, eret, ...
●
Atomic, Counters, FP conversion, ...
 RISC-V Instruction Set
●
Pronounced “risk-five”
●
Created from 2010 in UC Berkely

The RISC-V Instruction Set Manual, Volume I: User-Level ISA, v2.2. https://riscv.org/
 RISC-V Instruction Set
●
Pronounced “risk-five”
●
Created from 2010 in UC Berkely
●
An open ISA
●
An ISA supporting extensive user-level ISA
extensions and specialized variants.

The RISC-V Instruction Set Manual, Volume I: User-Level ISA, v2.2. https://riscv.org/
 RISC-V Instruction Set
●
Pronounced “risk-five”
●
Created from 2010 in UC Berkely
●
An open ISA
●
An ISA supporting extensive user-level ISA
extensions and specialized variants.
●
An ISA with support for highly-parallel multicore
or manycore implementations, including
heterogeneous multiprocessors.

The RISC-V Instruction Set Manual, Volume I: User-Level ISA, v2.2. https://riscv.org/
 RISC-V Instruction Set
●
Base Int ISA: RV64I (64b registers)
– RV32I: Int ISA with 32b registers
 RISC-V Instruction Set
●
Base Int ISA: RV64I (64b registers)
– RV32I: Int ISA with 32b registers
●
M: Integer multiplication and division extension.
 RISC-V Instruction Set
●
Base Int ISA: RV64I (64b registers)
– RV32I: Int ISA with 32b registers
●
M: Integer multiplication and division extension
●
A: Atomic instruction extension.
– Atomically read, modify, and write memory for inter-
processor synchronization.
 RISC-V Instruction Set
●
F: Single-precision floating-point extension
– FP registers, SP computational instructions, and SP
loads and stores.
●
D: Double precision
 RISC-V Instruction Set
●
Base Int ISA: RV64I (64b registers)
– RV32I: Int ISA with 32b registers
●
G: IMAFD. General purpose Scalar Instruction
set.
– RV64G
 RV64I
●
Fixed-length 32 bit instructions
●
 RV64I
●
Fixed-length 32 bit instructions
●
31 general-purpose integer registers x1–x31
– Register x0 is hardwired to the constant 0
 RV64I
●
Fixed-length 32 bit instructions
●
31 general-purpose integer registers x1–x31
– Register x0 is hardwired to the constant 0
●
Registers are 64 bits wide
– 32 bits wide in RV32I
●
 RV64I
●
Fixed-length 32 bit instructions
●
31 general-purpose integer registers x1–x31
– Register x0 is hardwired to the constant 0
●
Registers are 64 bits wide
– 32 bits wide in RV32I
●
Program counter pc holds the address of the
current instruction.
 RV64I Logical Instructions
Mnemonics Example Meaning

AND

OR

XOR
 RV64I Logical Instructions
Mnemonics Example Meaning

AND AND, ANDI

OR OR, ORI

XOR XOR, XORI

 RV64I Logical Instructions
Mnemonics Example Meaning

AND, ANDI and x5, x6, x7 x5 ← x6 & x7

AND
andi x6, x7, 4 x6 ← x7 & SE(4)

OR OR, ORI

XOR XOR, XORI

 RV64I Logical Instructions
Mnemonics Example Meaning

AND, ANDI and x5, x6, x7 x5 ← x6 & x7

AND
andi x6, x7, 4 x6 ← x7 & SE(4)
OR, ORI or x5, x6, x7 x5 ← x6 | x7
OR
ori x6, x7, 4 x6 ← x7 | SE(4)
XOR XOR, XORI xor x5, x6, x7 x5 ← x6 ^ x7
xori x6, x7, 4 x6 ← x7 ^ SE(4)
 RV64I Logical Instructions
Mnemonics Example Meaning

AND, ANDI and x5, x6, x7 x5 ← x6 & x7

AND
andi x6, x7, 4 x6 ← x7 & SE(4)
OR, ORI or x5, x6, x7 x5 ← x6 | x7
OR
ori x6, x7, 4 x6 ← x7 | SE(4)
XOR XOR, XORI xor x5, x6, x7 x5 ← x6 ^ x7
xori x6, x7, 4 x6 ← x7 ^ SE(4)

●
NOT a =
 RV64I Logical Instructions
Mnemonics Example Meaning

AND, ANDI and x5, x6, x7 x5 ← x6 & x7

AND
andi x6, x7, 4 x6 ← x7 & SE(4)
OR, ORI or x5, x6, x7 x5 ← x6 | x7
OR
ori x6, x7, 4 x6 ← x7 | SE(4)
XOR XOR, XORI xor x5, x6, x7 x5 ← x6 ^ x7
xori x6, x7, 4 x6 ← x7 ^ SE(4)

●
NOT a = a XOR (-1)
 RV64I Arithmetic Instructions
Mnemonics Example Meaning

ADD add, addi, add x5, x6, x7 x5 ← x6 + x7

addw, addiw addi x5, x6, 5 x5 ← x6 + 5
 RV64I Arithmetic Instructions
Mnemonics Example Meaning

ADD add, addi, add x5, x6, x7 x5 ← x6 + x7

addw, addiw addi x5, x6, 5 x5 ← x6 + 5
addw x5, x6, x7 x531-0 ← x631-0 + x731-0
addiw x5, x6, 5 x531-0 ← x631-0 + 5
 RV64I Instruction Encoding
●
add x5, x6, x7
 RV64I Instruction Encoding
●
add x5, x6, x7
●
From the ISA Manual
 RV64I Instruction Encoding
●
add x5, x6, x7
●
From the ISA Manual
 RV64I Instruction Encoding
●
add x5, x6, x7
●
Instruction Fields
31 0
 RV64I Instruction Encoding
●
add x5, x6, x7
●
Instruction Fields
31 0

●
opcode: Basic operation of the instruction
●
rd: Register destination operand. Gets the result.
●
funcx8: An additional opcode field.
●
rs1: The first register source operand.
●
rs2: The second register source operand.
●
funct7: An additional opcode field.
 RV64I Instruction Encoding
●
add x5, x6, x7
●
Instruction Fields
31 0

●
rs1: 6, rs2: 7, rd: 5
 RV64I Instruction Encoding
●
add x5, x6, x7
●
Instruction Fields
31 0

Fig. 2.18. RISC-V instruction encoding. PH-COD-RISCVe.

 RV64I Instruction Encoding
●
add x5, x6, x7
●
Instruction Fields
31 0

0000000 00111 00110 000 00101 0110011

7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
 RV64I Instruction Encoding
●
add x5, x6, x7
●
Instruction Fields
31 0

0000000 00111 00110 000 00101 0110011 0x007302B3

0x007302B3
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
 RV64I Arithmetic Instructions
Mnemonics Example Meaning

ADD add, addi, add x5, x6, x7 x5 ← x6 + x7

addw, addiw addi x5, x6, 5 x5 ← x6 + 5

SUB sub, subw sub x5, x6, x7 x5 ← x6 - x7

 RV64I Shift Instructions
Mnemonics Example Meaning

Shift sll, slli,

left sllw, slliw

Shift srl, srli,

right srlw, srliw

SR Arith- sra, srai

metic

●
Word version operates on lower32 bits only
●
Arithmetic shift replicates sign bit
 RV64I Shift Instructions
Mnemonics Example Meaning

Shift sll, slli, sll x5, x6, x7 x5 ← x6 << x7

left sllw, slliw slli x5, x6, 5 x5 ← x6 << 5

Shift srl, srli,

right srlw, srliw

SR Arith- sra, srai

metic

●
Word version operates on lower32 bits only
●
Arithmetic shift replicates sign bit
 RV64I Shift Instructions
Mnemonics Example Meaning

Shift sll, slli, sll x5, x6, x7 x5 ← x6 << x7

left sllw, slliw slli x5, x6, 5 x5 ← x6 << 5

Shift srl, srli, srl x5, x6, x7 x5 ← x6 >> x7

right srlw, srliw srli x5, x6, 5 x5 ← x6 >> 5

SR Arith- sra, srai sra x5, x6, x7 x5 ← x6 >> x7

metic srai x5, x6, 5 x5 ← x6 >> 5

●
Word version operates on lower32 bits only
●
Arithmetic shift replicates sign bit
RV64I – Data Transfer Instructions
Mnemonics Example Meaning

Load LB, LBU, LH, LD x7, 4(x8) x7 ← Mem(x8 + 4)

LHU, LW,
LWU, LD

B: Byte (8b), H: Half Word (16b),

L: Load
●
●
W: Word (32b), D: Double Word
(64b)
●
U: Upper
●
I: Immediate
RV64I Data Transfer Instructions
Mnemonics Example Meaning

Load LB, LBU, LH, LB x7, 4(x8)

LHU, LW, LBU x7, 4(x8) x7 ← Mem(x8 + 4)
LWU, LD
LW x7, 4(x8)
LD x7, 4(x8)
RV64I Data Transfer Instructions
Mnemonics Example Meaning

Load LB, LBU, LH, LB x7, 4(x8) x77-0 ← Mem(x8+4)7-0

LHU, LW, LBU x7, 4(x8)
LWU, LD x763-8 ← x77
LW x7, 4(x8)
LD x7, 4(x8)
 RV64I Data Transfer Instructions
Mnemonics Example Meaning

Load LB, LBU, LH, LB x7, 4(x8) x77-0 ← Mem(x8+4)7-0

LHU, LW, LBU x7, 4(x8)
LWU, LD x763-8 ← x77
LW x7, 4(x8)
LD x7, 4(x8)

Memory x8
0x100

...
...
...
0x2D8A10EF 0x104
...
 RV64I Data Transfer Instructions
Mnemonics Example Meaning

Load LB, LBU, LH, LB x7, 4(x8) x77-0 ← Mem(x8+4)7-0

LHU, LW, LBU x7, 4(x8)
LWU, LD x763-8 ← x77
LW x7, 4(x8) Sign Extension
LD x7, 4(x8)

Memory x8
0x100

x7
...
... 0xFFFF FFFF FFFF FFEF
...
0x2D8A10EF 0x104
...
 RV64I Data Transfer Instructions
Mnemonics Example Meaning

Load LB, LBU, LH, LB x7, 4(x8) x77-0 ← Mem(x8+4)7-0

LHU, LW, LBU x7, 4(x8) x7 ← 0
LWU, LD 63-8
LW x7, 4(x8)
LD x7, 4(x8)

Memory x8
0x100

x7
...
... 0x0000 0000 0000 00EF
...
0x2D8A10EF 0x104
...
 RV64I Data Transfer Instructions
Mnemonics Example Meaning

Load LB, LBU, LH, LB x7, 4(x8) x77-0 ← Mem(x8+4)7-0

LHU, LW, LBU x7, 4(x8) x7 ← 0
LWU, LD 63-8
LW x7, 4(x8) Zero Extension
LD x7, 4(x8)

Memory x8
0x100

x7
...
... 0x0000 0000 0000 00EF
...
0x2D8A10EF 0x104
...
RV64I Data Transfer Instructions
Mnemonics Example Meaning

Load LB, LBU, LH, LB x7, 4(x8) x731-0 ← Mem(x8+4)31-0

LHU, LW, LBU x7, 4(x8) x7
LWU, LD 63-32
← x731
LW x7, 4(x8) Sign Extension
LD x7, 4(x8)
RV64I Data Transfer Instructions
Mnemonics Example Meaning

Load LB, LBU, LH, LB x7, 4(x8) x763-0 ← Mem(x8+4)

LHU, LW, LBU x7, 4(x8)
LWU, LD
LW x7, 4(x8)
LD x7, 4(x8)
RV64I Data Transfer Instructions
Mnemonics Example Meaning

Load LB, LBU, LH, LB x7, 4(x8)

LHU, LW, LBU x7, 4(x8)
LWU, LD
LW x7, 4(x8)
LD x7, 4(x8)

I Format
 Encoding Example
●
From the RV64 ISA Manual
 Encoding Example
●
From the RV64 ISA Manual

ld x2, 4(x28)
 Encoding Example
●
From the RV64 ISA Manual

ld x2, 4(x28)

immed rs1 funcx8 rd 000 0011

12 bits 5 bits 3 bits 5 bits 7 bits
 Encoding Example
●
From the RV64 ISA Manual

ld x2, 4(x28)
op rd, immed(rs1)

immed rs1 funct3 rd 000 0011

12 bits 5 bits 3 bits 5 bits 7 bits
 Encoding Example
●
From the RV64 ISA Manual

ld x2, 4(x28)
op rd, immed(rs1)

0...0100 11100 011 00010 000 0011

12 bits 5 bits 3 bits 5 bits 7 bits
 Encoding Example
●
From the RV64 ISA Manual

0...0100 11100 011 00010 000 0011

12 bits 5 bits 3 bits 5 bits 7 bits

ld x2, 4(x28) 0x004E3103

RV64I Data Transfer Instructions
Mnemonics Example Meaning

Load LB, LBU, LH, LB x7, 4(x8)

LHU, LW, LBU x7, 4(x8) x7 ← Mem(x8 + 4)
LWU, LD
LW x7, 4(x8)
LD x7, 4(x8)

Store SB, SH, SW, SD SB x7, -8(t4) Mem(t4 - 8) ← x7

 RV64I Branch Instructions
Mnemonics Example Meaning

Branch BEQ, BNE,

BLT, BGE,
BLTU, BGEU
 RV64I Branch Instructions
Mnemonics Example Meaning

Branch BEQ, BNE, beq rs1, rs2, imm if(R[rs1] == R[rs2])

BLT, BGE, PC = PC + {imm,1’b0}
BLTU, BGEU
 RV64I Branch Instructions
Mnemonics Example Meaning

Branch BEQ, BNE, beq rs1, rs2, imm if(R[rs1] == R[rs2])

BLT, BGE, PC = PC + {imm,1’b0}
BLTU, BGEU

●
imm: 12-bit, signed offset in multiples of 2
●
Target address = pc + imm
●
Branch range is ±4 KiB.
– imm range = 0x001 to 0xFFF
0000 0000 0000 1111 1111 1111
 RV64I Branch Instructions
Mnemonics Example Meaning

Branch BEQ, BNE, beq rs1, rs2, imm if(R[rs1] == R[rs2])

BLT, BGE, PC = PC + {imm,1’b0}
BLTU, BGEU

●
imm: 12-bit, signed offset in multiples of 2
●
Target address = pc + imm
●
Branch range is ±4 KiB.
– imm range = 0x001 to 0xFFF
– Branch range = 0x0 to 0x1FFF.
0 0000 0000 0000 1 1111 1111 1110
 RV64I Branch Instructions
Mnemonics Example Meaning

Branch BEQ, BNE, beq rs1, rs2, imm if(R[rs1] == R[rs2])

BLT, BGE, PC = PC + {imm,1’b0}
BLTU, BGEU

●
Eg. Branch forward to the 16th instruction.
What is the immediate value?
●
beq x4, x5, ___
– pc = 0x0100
 RV64I Branch Instructions
Mnemonics Example Meaning

Branch BEQ, BNE, beq rs1, rs2, imm if(R[rs1] == R[rs2])

BLT, BGE, PC = PC + {imm,1’b0}
BLTU, BGEU

●
Eg. Branch forward to the 16th instruction.
What is the immediate value?
●
beq x4, x5, ___ 0x0100 beq x4, x5, ___
add # 1st after beq
or
– pc = 0x0100 ...
...
...
...
xor ... # 16th. Branch here.
 RV64I Branch Instructions
Mnemonics Example Meaning

Branch BEQ, BNE, beq rs1, rs2, imm if(R[rs1] == R[rs2])

BLT, BGE, PC = PC + {imm,1’b0}
BLTU, BGEU

●
Eg. Branch forward to the 16th instruction.
What is the immediate value?
●
beq x4, x5, ___ 0x0100
0x0104
beq x4, x5, ___
add # 1st after beq
or
– pc = 0x0100 ...
...
...
...
0x0140 xor ... # 16th. Branch here.
 RV64I Branch Instructions
Mnemonics Example Meaning

Branch BEQ, BNE, beq rs1, rs2, imm if(R[rs1] == R[rs2])

BLT, BGE, PC = PC + {imm,1’b0}
BLTU, BGEU

●
Eg. Branch forward to the 16th instruction.
What is the immediate value?
●
beq x4, x5, ___ 0x0100
0x0104
beq x4, x5, ___
add # 1st after beq
or
– pc = 0x0100 ...
...
...
...
0x0140 xor ... # 16th. Branch here.
0001 0100 0000
 RV64I Branch Instructions
Mnemonics Example Meaning

Branch BEQ, BNE, beq rs1, rs2, imm if(R[rs1] == R[rs2])

BLT, BGE, PC = PC + {imm,1’b0}
BLTU, BGEU

●
Eg. Branch forward to the 16th instruction. What is the
immediate value?
●
beq x4, x5, ___ 0x0100 beq x4, x5, ___
– pc = 0x0100 0x0104 add # 1st after beq
or
●
(pc – target address) = 0x40 ...
...
...
...
0x0140 xor ... # 16th. Branch here.
0001 0100 0000
 RV64I Branch Instructions
Mnemonics Example Meaning

Branch BEQ, BNE, beq rs1, rs2, imm if(R[rs1] == R[rs2])

BLT, BGE, PC = PC + {imm,1’b0}
BLTU, BGEU

●
Eg. Branch forward to the 16th instruction. What is the
immediate value?
●
beq x4, x5, ___ 0x0100 beq x4, x5, ___
– pc = 0x0100 0x0104 add # 1st after beq
or
●
(pc – target address) = 0x40 ...
...
0100 0000 0010 0000 ...
>>2 ...
0x0140 xor ... # 16th. Branch here.
0001 0100 0000
 RV64I Branch Instructions
Mnemonics Example Meaning

Branch BEQ, BNE, beq rs1, rs2, imm if(R[rs1] == R[rs2])

BLT, BGE, PC = PC + {imm,1’b0}
BLTU, BGEU

●
Eg. Branch forward to the 16th instruction. What is the immediate
value?
●
beq x4, x5, ___
0x0100 beq x4, x5, ___
– pc = 0x0100 0x0104 add # 1st after beq
●
(pc – target address) = 0x40 or
...
●
imm = 0x20 ...
...
beq x4, x5, 32 ...
0x0140 xor ... # 16th. Branch here.
 RV64I Branch Instructions
Mnemonics Example Meaning

Branch BEQ, BNE, beq rs1, rs2, imm if(R[rs1] == R[rs2])

BLT, BGE, PC = PC + {imm,1’b0}
BLTU, BGEU

●
Eg. Branch forward to the 16th instruction.
What is the immediate value?
0x0100 beq x4, x5, loop
● beq x4, x5, 32
0x0104 add # 1st after beq
or
...
...
...
...
0x0140 loop: xor ... # 16th. Branch here.
 RV64I Branch Instructions
Mnemonics Example Meaning

Branch BEQ, BNE, beq rs1, rs2, imm if(R[rs1] == R[rs2])

BLT, BGE, PC = PC + {imm,1’b0}
BLTU, BGEU

●
B-type instruction format
 RV64I Jump Instructions
Mnemonics Example Meaning

Jump JAL, JALR

 RV64I Jump Instructions
Mnemonics Example Meaning

Jump JAL, JALR jal rd, imm R[rd]=PC+4

PC=PC+{imm,1’b0}
jalr rd, rs1, imm R[rd]=PC+4
PC=PC+R[rs1]+imm
 RV64I Jump Instructions
Mnemonics Example Meaning

Jump JAL, JALR jal rd, imm R[rd]=PC+4

PC=PC+{imm,1’b0}
jalr rd, rs1, imm R[rd]=PC+4
PC=PC+R[rs1]+imm

●
J-immediate encodes a signed offset in multiples of 2 bytes
●
Jumps target a ±1 MiB range
●
JAL stores (pc+4) into rd
●
Calling convention uses x1 as the return address register
 RV64I – Load Upper Immediate
Mnemonics Example Meaning
Load lui lui x5, 0xabcde
Upper
lui rd,imm
Immed
 RV64I – Load Upper Immediate
Mnemonics Example Meaning
Load lui lui x5, 0xabcde
Upper
lui rd,imm
Immed

20
20bit
bitimmediate
immediate
value
value
 RV64I – Load Upper Immediate
Mnemonics Example Meaning
Load lui lui x5, 0xabcde
Upper
lui rd,imm
Immed

●
Used to build 32-bit constants
●
Places the immediate value in the top 20 bits (bits 31–12) of
the destination register, filling in the lowest 12 bits with
zeros.
●
32-bit result is sign-extended to 64 bits
 RV64I – Load Upper Immediate
Mnemonics Example Meaning
Load lui lui x5, 0xabcde
Upper
lui rd,imm
Immed

63 31 0
x5 0x1234
0x1234ABCD
ABCD0000
0000789A
789A
 RV64I – Load Upper Immediate
Mnemonics Example Meaning
Load lui lui x5, 0xabcde
Upper
lui rd,imm
Immed

63 31 0
0x1234
0x1234ABCD
ABCD0000
0000789A
789A

0x1234
0x1234ABCD
ABCDABCD
ABCDE000
E000
 RV64I – Load Upper Immediate
Mnemonics Example Meaning
Load lui lui x5, 0xabcde
Upper
lui rd,imm
Immed

63 31 0
0x1234
0x1234ABCD
ABCD0000
0000789A
789A

0x1234
0x1234ABCD
ABCDABCD
ABCDE000
E000

0xFFFF
0xFFFFFFFF
FFFFABCD
ABCDE000
E000
 RV64I – Load Upper Immediate
Mnemonics Example Meaning
Load lui lui x5, 0xabcde
Upper
lui rd,imm
Immed

63 32 0
x5 0001001000110100
00010010001101001010101111001101
10101011110011010000000000000000
00000000000000000111
01111000
10001001
10011010
1010

0x1234
0x1234ABCD
ABCD0000
0000789A
789A
Bit 11

63 0
x5 1111111111111111
11111111111111111111111111111111
11111111111111111010101111001101
10101011110011011110
11100000
00000000
00000000
0000
0xFFFF
0xFFFFFFFF
FFFFABCD
ABCDE000
E000
 RV64I – System Instructions
●
SCALL
– Make a request to the operating system
environment.
 RV64I – System Instructions
●
SCALL
– Make a request to the operating system
environment.
●
SBREAK
– Used by debuggers to cause control to be
transferred back to the debugging environment.
 Arithmetic Overflow

111101
+
111110
 Arithmetic Overflow

111101 -3
+ +
111110 -2
 Arithmetic Overflow
C 1111
111101 -3
+ +
111110 -2

111011 -5
 Arithmetic Overflow
C 1111
111101 -3 000001 1
+ + + +
111110 -2 011111 31

111011 -5
 Arithmetic Overflow
C 1111 C 11111
111101 -3 000001 1
+ + + +
111110 -2 011111 31

111011 -5 100000 - 32
 Arithmetic Overflow
C 1111 C 11111
111101 -3 000001 1
+ + + +
111110 -2 011111 31

111011 -5 100000 - 32

100000 -32
+ +
111111 -1
 Arithmetic Overflow
C 1111 C 11111
111101 -3 000001 1
+ + + +
111110 -2 011111 31

111011 -5 100000 - 32

C 1
100000 -32
+ +
111111 -1
011111 31
 Arithmetic Overflow
C 1111 C 11111
111101 -3 000001 1
+ + + +
111110 -2 011111 31

111011 -5 100000 - 32

C 1 ●
MSB0 = 0 && MSB1 =
100000 -32 0 && MSBofResult = 1
+ +
111111 -1 ●
MSB0 = 1 && MSB1 =
011111 31 1 && MSBofResult = 0
 Module Outline
●
RISC-V ISA
●
Addressing modes, Instruction classes
●
High level languages, Assembly languages
and object code.
●
Translating and starting a program.
●
Subroutine and subroutine call. Use of stack
for handling subroutine call and return.
Extras
 RV64I Compare Instructions
Mnemonics Example Meaning

Set SLT, SLTI, slt rd, rs1, rs2

SLTU, SLTIU slti rd, rs1, immed
 RV64I - AUIPC
Mnemonics Example Meaning
Add auipc auipc x5,
upper 0xabcde
immed auipc
to pc rd,imm
 RV64I - AUIPC
Mnemonics Example Meaning
Add auipc auipc x5,
upper 0xabcde
immed auipc
to pc rd,imm

●
Build pc-relative addresses
●
Forms a 32-bit offset from the 20-bit U-
immediate, fills lowest 12 bits with zeros, adds
to the pc, places result in register rd.
RV64I – LUI and AUIPC Encoding
Mnemonics Example Meaning
Load lui lui x5, 0xabcde
Upper
Immed
Add auipc auipc x5,
upper 0xabcde
immed auipc
to pc rd,imm
 RV64I Branch Instructions
Mnemonics Example Meaning

Branch BEQ, BNE, beq rs1, rs2, imm if(R[rs1] == R[rs2])

BLT, BGE, PC = PC + {imm,1’b0}
BLTU, BGEU
 RV64I Jump Instructions
Mnemonics Example Meaning

Jump JAL, JALR jal rd, imm R[rd]=PC+4

PC=PC+{imm,1’b0}
jalr rd, rs1, imm R[rd]=PC+4
PC=PC+R[rs1]+imm
R-type Instructions
Logical Instructions – Encoding
Mnemonics Example Meaning

AND, ANDI and x5, x6, x7 x5 ← x6 & x7

AND
andi x6, x7, 4 x6 ← x7 & SE(4)
OR, ORI or x5, x6, x7 x5 ← x6 | x7
OR
ori x6, x7, 4 x6 ← x7 | SE(4)
XOR XOR, XORI xor x5, x6, x7 x5 ← x6 ^ x7
xori x6, x7, 4 x6 ← x7 ^ SE(4)
Logical Instructions – Encoding
Mnemonics Example Meaning

AND, ANDI and x5, x6, x7 x5 ← x6 & x7

AND
andi x6, x7, 4 x6 ← x7 & SE(4)
OR, ORI or x5, x6, x7 x5 ← x6 | x7
OR
ori x6, x7, 4 x6 ← x7 | SE(4)
XOR XOR, XORI xor x5, x6, x7 x5 ← x6 ^ x7
xori x6, x7, 4 x6 ← x7 ^ SE(4)