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    Digital Design Report Modified

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    Usama
    The document discusses 4 tasks related to digital design. Task 1 involves designing a full adder in VHDL and obtaining the expected simulation log and timing diagram. Task 2 extends this to a sequential adder using D flip-flops, MUXs, and decoders. Task 3 compares the implementations and notes the carry propagation delay in the sequential adder. Task 4 discusses the effect of adding gate delays to obtain stable outputs for both the full adder and sequential adder designs.

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    Digital Design Report Modified

    Uploaded by

    Usama
    40 views6 pages
    The document discusses 4 tasks related to digital design. Task 1 involves designing a full adder in VHDL and obtaining the expected simulation log and timing diagram. Task 2 extends this to a sequential adder using D flip-flops, MUXs, and decoders. Task 3 compares the implementations and notes the carry propagation delay in the sequential adder. Task 4 discusses the effect of adding gate delays to obtain stable outputs for both the full adder and sequential adder designs.

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    The document discusses 4 tasks related to digital design. Task 1 involves designing a full adder in VHDL and obtaining the expected simulation log and timing diagram. Task 2 extends this to a sequential adder using D flip-flops, MUXs, and decoders. Task 3 compares the implementations and notes the carry propagation delay in the sequential adder. Task 4 discusses the effect of adding gate delays to obtain stable outputs for both the full adder and sequential adder designs.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    40 views6 pages

    Digital Design Report Modified

    Uploaded by

    Usama
    The document discusses 4 tasks related to digital design. Task 1 involves designing a full adder in VHDL and obtaining the expected simulation log and timing diagram. Task 2 extends this to a sequential adder using D flip-flops, MUXs, and decoders. Task 3 compares the implementations and notes the carry propagation delay in the sequential adder. Task 4 discusses the effect of adding gate delays to obtain stable outputs for both the full adder and sequential adder designs.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 6

    Digital Design – UFMFE8-30-2

    Individual Lab Report - Component B

    Task # 1
    VHDL code for full adder:

    Simulation log:

    Comments: Simulation log is obtained as expected. In this simulation log, there are 2 XOR gates for the sum logic
    expression and the output expression the for sum obtained is: (x XOR y XOR z). Similarly, 2 AND gates and 1 OR
    gate are used to obtain expression: “(x XOR y)z + yz”.
    Timing Diagram:

    Comments: A Timing diagram is obtained according to the truth table for the full adder. An intentional delay of
    10 ns is added between each state to observe the output.

    Task # 2

    State table:

    State Diagram:
    VHDL code for sequential adder:

    Simulation log:

    Comments: The simulation log obtained also had a D-Flip Flop circuit in it. Full adders are cascaded using MUX
    and Decoders. Also, there is a carry and flag register shown in the simulation log.

    Timing Diagram:

    Comments: The output results obtained from the timing diagram are not the same as those obtained in the
    truth table. It is because there is a propagational delay due to the carry flag in sequential architecture. It is
    explained in task # 3.
    Task # 3

    Implementation Comparison:
    Similar to the half adder, a logical circuit for full adder can perform addition operation on three binary
    digits and it can also generate a carry to the next addition column. The ‘c’ in implementation indicates a
    carry to a more significant digit unlike ‘z’ which represents any possible carry taken from a less
    significant digit.

    The purpose of ‘sequential adder’ is to obtain a weighted column, that results from a long binary
    addition, by cascading n number of full adders that are cascaded together. Since it can produce a ‘ripple’
    effect through binary addition from least significant bit to most significant bit, it is often called a ‘Ripple
    Carry’.

    Now it can be observed from the implementations of task 1 and task 2 that there is a carry propagation
    delay in the Sequential adder and not in the full adder. The carry propagation delay appears because
    when the addition of two large number (say input A and input B) happens, the summation is not valid
    until any possible carry has taken out through every full adder in cascaded series and thus, we can
    expect a delay as the MSB has to wait to make sure that there are no changes from carrying input of
    LSB. This fact can be explained by looking at a diagram below, where to add A3 and B3, Adder needs C3.

    Moreover, one can expect a finite delay at the adder’s output which will result from the accumulated
    delay of all the cascaded adders whenever they are subjected to a change. To minimize the delay, 32-bit
    adders need to operate at a very high clock speed and it may take more than one clock cycle as the
    processes may not be processed completely during one single cycle.
    Task # 4

    Effect of gate delays:


    The purpose of gate delays is to clear the glitch in the output. Without the gate delays, out is not stable
    for a few nanoseconds, and after some glitches, it becomes stable. Thus when we use gate delays of 30,
    20, and 10 nanoseconds in AND, OR, and NOT gates, a stable and clean output will be obtained in task
    #1 i.e. full adder implementation. And similarly, if used 10 and 5 ns for hold time and D-Flip Flop, then a
    clean and stable expected output will also be obtained in task # 2 i.e. sequential adder.
    REFERENCES
    • https://www.ece.mcmaster.ca/~shirani/2di4/chapter8p2.pd f

    • https://www.electronics-tutorials.ws/combination/comb_7.html

    • http://web.engr.uky.edu/~elias/projects/12.pd f

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