UTC CD4541 CMOS IC

PROGRAMMABLE TIMER

DESCRIPTION
The UTC CD4541 programmable timer comprise a SOP-14
16-stage binary counter, an integrated oscillator for use with
an external capacitor and two resistors, output control logic,
and a special power-on reset circuit. The counter divides the
oscillator frequency by any of 4 digitally controlled division
ratios.

DIP-14
FEATURES
*Operates at 2n frequency divider or as single transition
timer
*Pb-free plating product number: CD4541L
*Increments on positive edge clock transitions
*Wide supply voltage range: 3.0V ~ 15V
*Built-in low power RC oscillator
*Oscillator frequency range ~ DC to 100 kHz
*External clock applied to Pin 3 can be used instead of
oscillator
8 10 13 16
*Available division ratios 2 , 2 , 2 , or 2
*High noise immunity: 0.45 VDD (typ.)
*Master reset totally independent of automatic reset
operation
*Automatic reset initializes all counters when power turns on
*Q/Q select provides output logic level flexibility
*High output drive min. one TTL load
*Maximum input leakage 1μA at 15V over full temperature
range

PIN CONFIGURATION

Rtc 1 14 VDD
Ctc 2 13 B
Rs 3 12 A
N.C. 4 11 N.C.
AR 5 10 MODE
MR 6 9 Q/Q SELECT
Vss 7 8 Q

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UTC CD4541 CMOS IC
TRUTH TABLE
STATE
PIN
0 1
5 Auto Reset Operating Auto Reset Disabled
6 Timer Operational Master Reset On
9 Output Initially Low after Reset Output Initially High after Reset
10 Single Cycle Mode Recycle Mode

DIVISION RATIO TABLE

Number of Counter Stages Count
A B
n 2n
0 0 13 8192
0 1 10 1024
1 0 8 256
1 1 16 65536

BLOCK DIAGRAM

A 12
B 13

1 OF 3
MUX
8Q
Rtc 1 210 213 216
8-STAGE 8 B-STAGE
Ctc 2 OSC C COUNTER 2 C
COUNTER
Rs 3 RESET RESET RESET

AUTO RESET 5 POWER-ON

RESET
6 9
MASTER 10 Q/Q
VDD=Pin 14 SELECT
RESET MODE
Vss=Pin 7

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UTC CD4541 CMOS IC
ABSOLUTE MAXIMUM RATINGS
(Note 1, 2)
PARAMETER SYMBOL RATINGS UNIT
Supply Voltage VDD -0.5 ~ +18 V
Input Voltage VIN -0.5 ~ VDD+0.5 V
DIP-14 700
Power Dissipation PD mW
SOP-14 500
Lead Temperature (soldering, 10 seconds) TL 260 ℃
Storage Temperature Range Tstg -65 ~ +150 ℃

RECOMMENDED OPERATING CONDITIONS

(Note 2)
PARAMETER SYMBOL RATINGS UNIT
Supply Voltage VDD 3 ~ 15 V
Input Voltage VIN 0 ~ VDD V
Operating Temperature Range Topr -40 ~ +85 ℃
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed.
Except for “Operating Temperature Range” they are not meant to imply that the devices should be
operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device
operation.
Note 2: VSS=0V unless otherwise specified.

DC ELECTRICAL CHARACTERISTICS
(Note 2, Ta=25℃, unless otherwise noted.)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
VDD=5V, VIN=VDD or Vss 0.005 20
Quiescent Device Current IDD VDD=10V, VIN=VDD or Vss 0.010 40 μA
VDD=15V, VIN=VDD or Vss 0.015 80
VDD=5V 0 0.05
LOW Level Output Voltage VOL VDD=10V, I IO I<1μA 0 0.05 V
VDD=15V 0 0.05
VDD=5V 4.95 5
HIGH Level Output Voltage VOH VDD=10V, I IO I<1μA 9.95 10 V
VDD=15V 14.95 15
VDD=5V, Vo=0.5V or 4.5V 2 1.5
LOW Level Input Voltage VIL VDD=10V, Vo=1.0V or 9.0V 4 3.0 V
VDD=15V, Vo=1.5V or 13.5V 6 4.0
VDD=5V, Vo=0.5V or 4.5V 3.5 3
HIGH Level Input Voltage VIH VDD=10V, Vo=1.0V or 9.0V 7.0 6 V
VDD=15V, Vo=1.5V or 13.5V 11.0 9
VDD=5V, Vo=0.4V 1.96 3.6
LOW Level Output Current (Note
IOL VDD=10V, Vo=0.5V 2.66 9.0 mA
3)
VDD=15V, Vo=1.5V 10.4 34.0
VDD=5V, Vo=2.5V 4.27 130
HIGH Level Output Current (Note
IOH VDD=10V, Vo=9.5V 2.25 8.0 mA
3)
VDD=15V, Vo=13.5V 8.8 30.0
-5
VDD=15V, VIN=0V -10 -0.3
Input Current IIN -5 μA
VDD=15V, VIN=15V 10 0.3
Note 3: IOH and IOL are tested one output at a time.

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UTC CD4541 CMOS IC
AC ELECTRICAL CHARACTERISTICS
(Note 4, Ta=25℃, CL=50pF (refer to test circuits))
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
VDD=5V 50 200
Output Rise Time tTLH VDD=10V 30 100 ns
VDD=15V 25 80
VDD=5V 50 200
Output Fall Time tTHL VDD=10V 30 100 ns
VDD=15V 25 80
Turn-Off, Turn-On Propagation VDD=5V 1.8 4.0
Delay, tPLH, tPHL VDD=10V 0.6 1.5 μs
Clock to Q (28 Output) VDD=15V 0.4 1.0
Turn-On, Turn-Off Propagation VDD=5V 3.2 8.0
Delay, tPHL, tPLH VDD=10V 1.5 3.0 μs
Clock to Q (216 Output) VDD=15V 1.0 2.0
VDD=5V 400 200
Clock Pulse Width tWH(CL) VDD=10V 200 100 ns
VDD=15V 150 70
VDD=5V 2.5 1.0
Clock Pulse Frequency fCL VDD=10V 6.0 3.0 MHz
VDD=15V 8.5 4.0
VDD=5V 400 170
MR Pulse Width tWH(R) VDD=10V 200 75 ns
VDD=15V 150 50
Average Input Capacitance CI Any Input 5.0 7.5 pF
Power Dissipation Capacitance
CPD 100 pF
(Note 5)
Note 4: AC Parameters are guaranteed by DC correlated testing.
Note 5: CPD determines the no load AC power consumption of any CMOS device.

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UTC CD4541 CMOS IC
OPERATING CHARACTERISTICS
With Auto Reset pin set to a “0” the counter circuit is initialized by turning on power. Or with power already on,
the counter circuit is reset when the Master Reset pin is set to a “1”. Both types of reset will result in synchronously
resetting all counter stages independent of counter state.
The RC oscillator frequency is determined by the external RC network, i.e.:
1
f= if (1 kHz ≦ f ≦ 100kHz)
2.3 RtcCtc
and RS ~ 2 Rtc where RS≧10 kΩ
8 10 13
The time select inputs (A and B) provide a two-bit address to output any one of four counter stages (2 , 2 , 2 ,
16 n
and 2 ). The 2 counts as shown in the Division Ratio Table represent the Q output of the Nth stage of the counter.
When A is “1”, 216 is selected for both states of B.
However, when B is “0”, normal counting is interrupted and the 9th counter stage receives its clock directly from
the oscillator (i.e., effectively outputting 28).
The Q/Q select output control pin provides for a choice of output level. When the counter is in a reset condition
and Q/Q select pin is set to a “0” the Q output is a “0”. Correspondingly, when Q/Q select pin is set to a “1” the Q
output is a “1”.
When the mode control pin is set to a “1”, the selected count is continually transmitted to the output. But, with
mode pin “0” and after a reset condition the RS flip-flop resets (see Logic Diagram), counting commences and after
2n-1 counts the RS flip-flop sets which causes the output to change state. Hence, after another 2n-1 counts the output
will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset
the single cycle operation.

RC Oscillator Frequency as a Function of RTC and C RC Oscillator Frequency as a Function of RTC and C

1.0M 70
VDD =10V VDD =10V
DSCILLATOR FREQUENCY,f (kHz)

DSCILLATOR FREQUENCY,f (kHz)

100k 7

10k 0.7

1.0k 0.07
0.0001 0.001 0.01 0.1 1.0k 10k 100k 1.0M

RESISTANCE , RTC ( KΩ ) CAPACITANCE, C(µF)

f as a function of C and (RTC =56 KΩ, Rs =120k ) f as a function of RTC and (C=100pF, Rs=2RTC)

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UTC CD4541 CMOS IC

Oscillator Circuit Using RC Configuration

3 TO CLOCK
CIRCUIT

INTERNAL
RESET

2 1
CTC
RS RTC

TEST CIRCUIT AND WAVEFORMS

P o w e r D is s ip a tio n T e s t C ir c u it a n d
W a v e fo r m s
V DD

PU LSE
Rs
GENERATOR
AR
Q /Q S E L E C T
MODE Q
A
B CL
MR

V SS

( R t c a n d C tc o u tp u ts a r e le ft o p e n )

tW H (C L )

20 ns 20 ns

90%
50%
Rs
10%

50% D U TY C YC LE

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UTC CD4541 CMOS IC
S w itc h in g T im e T e s t C irc u it a n d W a v e fo rm s
VDD

PU LS E
Rs
GENERATOR
AR
Q /Q S E L E C T
MODE Q
A
B CL
MR

V SS

tW H (C L )

20 ns 20 ns

90%
50% 50%
Rs
10%

tP L H
tP H L

90%
50% 50%
Q
10%

tT L H tT H L

UTC assum es no responsibility for equipm ent failures that result from using products at v alues that
exceed, ev en m om entarily, rated v alues (such as m axim um ratings, operating condition ranges, or
other param eters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, dev ices or system s where
m alfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The inform ation
presented in this docum ent does not form part of any quotation or contract, is believ ed to be accurate
and reliable and m ay be changed without notice.

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