真藍牙耳機晶片與系統

設計
Data Converters

Su-Hao Wu (吳書豪)
 Where are we in a TWS?

Receiver Data Converter SerDes

Bluetooth
Transceiver Sensors / Lights
CPU
Actuators
User interface
Rx Apps Button
ADC/
DSP
DAC Operation
Tx
System Mic
Speaker

Transmitter Power Supply and Power Management

2
 Outlines
 Introduction of ADC & DAC
 Application and industrial value
 Challenge and opportunity
specification

application

architecture
3
 Takeaway
 ADC  Resolution
 DAC  Aliasing
 Bit  Spectrum
 Fs  Flash
 FS  Pipeline
 LSB  SAR
 DR  Delta Sigma
 FoM  TI
 SNR  LNA
 Q-noise  Calibration

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 Interconnection
Academy Industry

Electronics I/II/III

Electromagnetism
DSP
Signal & System
VSLI

Communication Sys.

Analog circuit Design

5
 Analog & Digital

Analog Digital
accuracy processing

(3.14159253 × 2) − 1 (3 × 2) − 1

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Poor Analog/Digital Signal Quality

No Signal

Analog Digital
accuracy processing

(3.14 × 2) − 1 (Unknown × 2) − 1

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 Signal Processing (1/2)
x (t) x [n]
continuous continuous
value value

continuous time discrete time

limited x (t) limited

x [n]
value value

continuous time discrete time

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 Signal Processing (2/2)
Sig. & Sys. Analog circuit
Electronics design
continuous continuous
value value

continuous time discrete time

Analog circuit DSP

Design VLSI
limited limited
value value

continuous time discrete time

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 Analog-to-Digital & Digital-to-Analog

ADC DAC

Analog Digital Analog

 Analog: voltage, current, pressure, time, force, voice, light …

 Digital: 1 or 0
 Data Converting: bridge between physical and virtual world
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Analog-to-Digital & Digital-to-Analog

ADC DAC

x (t) x [n] x (t)

Mixed signal design/processing

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 Resolution

HD ~ 90dB ~ 16b
FM ~ 70dB ~ 12b
AM ~ 50dB ~ 8b

 Resolution  how accurate is it ?

 Signal to noise ratio (SNR) = 6.02*Bit + 1.76

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 Least Significant Bit (LSB)
x (t) x (t)
0,2,1,-3,…
ADC DAC

 How many analog signal is 1 bit?

 Ex: 5.12V →code=512, ADC LSB is 5.12V/512=0.01V
 Ex: code=64 →64mA, DAC LSB is 64mA/64=1mA
 Note: In computing, LSB is the bit position in a binary
integer giving the units value, 1011001
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 Full Scale (FS)
x (t) x (t)
0,2,1,-3,…
ADC DAC

 How large analog signal can be converted ?

 FS = 2 Bit × LSB
 Ex: 12bit ADC with LSB=1mV, then FS=4096mV
 Ex: 10bit DAC with LSB=1mA, then FS=1024mV
 Note: FS is present in analog domain
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 Dynamic Range (DR)
Original

ADC#1

ADC#2

DR1 HDR HDR

ADC
DR2

 Idea dynamic range  Ratio of FS/LSB in dB

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Wrap up Bit, LSB, FS and DR
FS 1024

ruler
DR Bit

LSB
0

Analog Digital
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 Quantization Noise
Analog Code Q-Noise
11mV 11 0
x (t) 10.9mv 11 -0.1mV

ADC 10.1mV 10 0.1mV

10mV 10 0
LSB=1mV 9.9mV 10 -0.1mV
9.1mV 9 0.1mV
9mV 9 0

 Q-noise = root(LSB2/12)
 LSB ↓ Q-noise ↓

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 Which one is better?

10b 2mV-LSB 9b 2mV-LSB 10b 1mV-LSB 11b 1mV-LSB

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 Sampling Rate

Bio Audio 4G LTE Satellite

(Hz) (kHz) (MHz) (GHz)
 Sampling rate = Fs  how fast is it ?
 Nyquist rate = 2 * signal bandwidth
 Fs ≥ 2 * signal bandwidth
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 Aliasing
1/Fs < 1/f Alias to
Low freq.

Period=1/f 1/Fs=1/f
Alias to
DC

ADC

1/Fs = 0.5/f OK

OK

1/Fs < 0.5/f 20

 Aliasing in Life
 Rotation rate < 30Hz

 Rotation rate >> 30Hz

 Aliasing in image

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 Which one is better?

10b 2mV-LSB 9b 2mV-LSB 10b 1mV-LSB 11b 1mV-LSB

100MSPS 1GSPS 10MSPS 1MSPS
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 Constellation of Data Converter
More accuracy
 Leading conferences: ISSCC, VLSI,
24bit
ASSCC, CICC, ESSCIRC
 Top journal: JSSC
Resolution (bit)

18bit

13bit

12bit

11bit

10bit

7bit Wider BW
1KS/s 24KS/s 20MS/s 40MS/s 100MS/s 800MS/s 112GS/s
Sample Rate (Sample/s)

Power
 Figure of Merit =
Sample Rate × Resolution
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 Frequency in Life

La Si Do Re Mi Fa So La
Hz 440 466 494 523 554 587 622 659 698 740 783 830 880
n 49 50 51 52 53 54 55 56 57 58 59 60 61

2 times of Frequency = +12 keyboard = 高八度

Reference
https://en.wikipedia.org/wiki/Piano_key_frequencies
https://en.wikipedia.org/wiki/A440_(pitch_standard)
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 Transfer into Frequency Domain

Wanted

 Fourier transform, FFT  SFDR and Noise Floor

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 Spectrum Comparison

(kHz)

 Blue vs Red: SFDR +50dB, Noise Floor -10dB

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 ADC Architecture
 Flash
 Pipeline
 SAR
 Delta-Sigma
 TI

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 Flash ADC

19mV 19

 One-time with multi-threshold

 High speed low resolution
 Real life example: ruler
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 Problems of Flash ADC

19mV 19 19mV 20

9mV 5

 Many threshold
 Threshold mismatch

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Successive Approximation (SAR) ADC

24mV
19mV 20mV
16mV 18mV

∆=8mV ∆=4mV ∆=2mV

1 0 0 1

 Multi-cycles approaching with signal stage

 Low-to-medium speed medium resolution
 Real life example: Guess
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 Problem of SAR ADC

23mV
20mV
19mV
16mV 18mV

∆=7mV ∆=5mV ∆=2mV

1 0 0 1

 Residue error
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 Pipeline ADC

24mV
19mV
16mV 16mV
12mV
6mV
2*(19-16) 2*(6-0) 2*(12-0) 2*(24-16)
1 0 0 1 0

 Multi-cycles approaching with multi-stages

 Medium-to-high speed medium resolution
 Real life example: google map
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 Problem of Pipeline ADC

22.5mV
19mV
16mV 15mV
6mV 13mV
2*(19-16) 2.5*(6-0) 1.5*(15-0) 2*(22.5-16)
1 0 0 1 0

 Multi-stages mismatch
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 Problem of Residue (1/2)
① ②

④ ③

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 Problem of Residue (2/2)
① ②

④ ③

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 Delta-Sigma ADC
① ② ③ ④
① Typical
ADC 4098 4095 4090 4096
② ④

③ -3 -5 +6
1. Delta
① ② ③ ④
2. Sigma
4098 4095 4090 4096

 Data-compression
 Low speed high resolution
 Real life example: stock price
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 Time Interleaving ADC

① ADC#1
②
②
③ ① ADC#2
④
ADC#3
time ADC#4

 Parallel
 Ultrahigh speed medium resolution
 Real life example: multi-core CPU
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 Problem of TI ADC

① ADC#1
②
②
③① ADC#2
④
ADC#3
time ADC#4

 Multi-channel mismatch
 Quantization error: offset , gain
 Sampling error: skew
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 Constellation of ADC
16bit
Delta-sigma
Resolution (bit)

14bit

12bit

10bit
SAR Pipeline TI
8bit

6bit Flash

10KS/s 100kS/s 1MS/s 10MS/s 100MS/s 1GS/s 10GS/s

Sample Rate (Sample/s)

 General purpose  SAR or Pipeline

 High resolution  Delta-sigma
 High speed  Flash, TI
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 DAC
Code=1 Code=2 Code=4

 Turn on or off to generate analog output

 How to switch fast ?

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 Biggest Problem of DAC: Mismatch
Intel

 How to linearize? i.e. 1x/2x/4x

Reference: https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/03/Kaizad-Mistry-2017-Manufacturing.pdf

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 Calibration

Cali. engine Cali. engine

Analog Analog
DAC ADC DAC ADC
(DUT) (DUT)

 Device under test (DUT)

 Foreground mode: ADC/DAC must be off-line
 Background mode: without interrupting normal mode
 Require: circuits, signal processing, probability, etc

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 Major Industrial Players
 Analog Devices (ADI)
 Texas Instruments (TI)
 NXP Semiconductors
 Maxim Integrated
 Asahi Kasei Microdevices (AKM)
 STMicroelectronics
 Cirrus Logic
 Microchip Technology
 On Semiconductor
 Intersil (Renesas)

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 ADC in a Receiver Chain (I)
LNA TIA Filter ADC

 LNA = pupil  amplify signal

 Filer = lens  focus signal
 ADC = retina  quantize signal

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 ADC in a Receiver (II)
3.5G LNA TIA Filter ADC DSP
30M

Delta-Sigma
3.5G LNA Filter DSP
ADC
900M

Direct Sampling Mixer

3.5G LNA DSP
ADC Filter
7G
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 Challenges and Opportunities
More accuracy
24bit  Power constrain
18bit  Process scaling
Resolution (bit)

13bit
 Material performance
12bit

11bit
Leading edge Wider BW
10bit

7bit

1KS/s 24KS/s 20MS/s 40MS/s 100MS/s 800MS/s 112GS/s

Sample Rate (Sample/s)

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 Conclusions
 Introduction of ADC & DAC
 Application and industrial value
 Challenge and opportunity
 Keywords: Bit, Fs, … , See page 5

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 Q&A
Academy Industry

Electronics I/II/III

Electromagnetism
DSP
Signal & System
VSLI

Communication Sys.

Analog circuit Design

48