16-Bit, 310 MSPS, 3.3 V/1.8 V Dual Analog-to-Digital Converter (ADC)

16-Bit, 310 MSPS, 3.3 V/1.
8 V Dual
Analog-to-Digital Converter (ADC)
Data Sheet AD9652
FEATURES FUNCTIONAL BLOCK DIAGRAM
AVDD3 AVDD SDIO SCLK CSB DRVDD
High dynamic range
SNR = 75.0 dBFS at 70 MHz (AIN = −1 dBFS)
SPI
SFDR = 87 dBc at 70 MHz (AIN = −1 dBFS)
AD9652
Noise spectral density (NSD) = −156.7 dBFS/Hz input noise
at −1 dBFS at 70 MHz PROGRAMMING DATA OR+, OR–
NSD = −157.6 dBFS/Hz for small signal at −7 dBFS at 70 MHz VIN+A DDR DATA D15± (MSB)
ADC INTERLEAVER 16
90 dB channel isolation/crosstalk VIN–A LVDS OUTPUT
TO
D0± (LSB)*
On-chip dithering (improves small signal linearity) DRIVER
Excellent IF sampling performance

VREF CLK+
SNR = 73.7 dBFS at 170 MHz (AIN = −1 dBFS) DIVIDE 1
TO 8
SENSE CLK–
SFDR = 85 dBc at 170 MHz (AIN = −1 dBFS)
Full power bandwidth of 465 MHz REF DUTY CYCLE DCO DCO+
VCM SELECT STABILIZER GENERATION
On-chip 3.3 V buffer DCO–
Programmable input span of 2 V p-p to 2.5 V p-p (default) RBIAS
Differential clock input receiver with 1, 2, 4, and 8 integer VIN–B
inputs (clock divider input accepts up to 1.24 GHz) ADC MULTICHIP
VIN+B SYNC
Internal ADC clock duty cycle stabilizer
SYNC input allows multichip synchronization
AGND SYNC PDWN
12169-001
Total power consumption: 2.16 W
*THESE PINS ARE FOR CHANNEL A AND CHANNEL B.
3.3 V and 1.8 V supply voltages
DDR LVDS (ANSI-644 levels) outputs Figure 1.
Serial port control
Energy saving power-down modes
APPLICATIONS
Military radar and communications
Multimode digital receivers (3G or 4G)
Test and instrumentation
Smart antenna systems
GENERAL DESCRIPTION The 16-bit output data (with an overrange bit) from each ADC
The AD9652 is a dual, 16-bit analog-to-digital converter (ADC) is interleaved onto a single LVDS output port along with a
with sampling speeds of up to 310 MSPS. It is designed to double data rate (DDR) clock. Programming for setup and control
support demanding, high speed signal processing applications are accomplished using a 3-wire SPI-compatible serial interface.
that require exceptional dynamic range over a wide input The AD9652 is available in a 144-ball CSP_BGA and is
frequency range (up to 465 MHz). Its exceptional low noise specified over the industrial temperature range of −40°C to
floor of −157.6 dBFS and large signal spurious-free dynamic +85°C. This product is protected by pending U.S. patents.
range (SFDR) performance (exceeding 85 dBFS, typical) allows PRODUCT HIGHLIGHTS
low level signals to be resolved in the presence of large signals.
1. Integrated dual, 16-bit, 310 MSPS ADCs.
The dual ADC cores feature a multistage, pipelined architecture 2. On-chip buffer simplifies ADC driver interface.
with integrated output error correction logic. A high performance 3. Operation from 3.3 V and 1.8 V supplies and a separate
on-chip buffer and internal voltage reference simplify the inter- digital output driver supply accommodating LVDS outputs.
face to external driving circuitry while preserving the exceptional 4. Proprietary differential input maintains excellent signal-to-
performance of the ADC. noise ratio (SNR) performance for input frequencies of up
The AD9652 can support input clock frequencies of up to to 485 MHz.
1.24 GHz with a 1, 2, 4, and 8 integer clock divider to generate 5. SYNC input allows synchronization of multiple devices.
the ADC sample clock. A duty cycle stabilizer is provided to 6. Three-wire, 3.3 V or 1.8 V SPI port for register programming
compensate for variations in the ADC clock duty cycle. and readback.
Rev. C Document Feedback
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AD9652 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Voltage Reference ....................................................................... 23
Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 23
Functional Block Diagram .............................................................. 1 Power Dissipation and Standby Mode .................................... 25
General Description ......................................................................... 1 Internal Background Calibration ............................................. 25
Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 26
Revision History ............................................................................... 2 ADC Overrange.......................................................................... 26
Specifications..................................................................................... 3 Fast Threshold Detection (FDA/FDB) ........................................ 28
ADC DC Specifications ............................................................... 3 Serial Port Interface ........................................................................ 29
ADC AC Specifications ............................................................... 4 Configuration Using the SPI ..................................................... 29
Digital Specifications ................................................................... 5 Hardware Interface..................................................................... 29
Switching Specifications .............................................................. 7 Configuration Without the SPI ................................................ 29
Timing Specifications .................................................................. 7 SPI Accessible Features .............................................................. 30
Absolute Maximum Ratings............................................................ 9 Memory Map .................................................................................. 31
Thermal Characteristics .............................................................. 9 Reading the Memory Map Register Table............................... 31
ESD Caution .................................................................................. 9 Memory Map Register Table ..................................................... 32
Pin Configuration and Function Descriptions ........................... 10 Applications Information .............................................................. 35
Typical Performance Characteristics ........................................... 13 Design Guidelines ...................................................................... 35
Equivalent Circuits ......................................................................... 19 Outline Dimensions ....................................................................... 36
Theory of Operation ...................................................................... 20 Ordering Guide .......................................................................... 36
ADC Architecture ...................................................................... 20
Analog Input Considerations.................................................... 20
REVISION HISTORY
1/2018—Rev. B to Rev. C 5/2014—Rev. 0 to Rev. A
Changes to Transfer Register Map Section ................................. 31 Changes to Supply Current, Clock Divider = 1 Parameter and
Changes to Table 17 ........................................................................ 34 Power Consumption, Clock Divider = 1 Parameter, Table 1 .......3
Changes to Ordering Guide .......................................................... 36
4/2014—Revision 0: Initial Version
1/2017—Rev. A to Rev. B
Changes to DCO± to Data Skew (tSKEW) Parameter, Table 4 ............. 7
Changes to Clock Input Options Section .................................... 24
Rev. C | Page 2 of 36
Data Sheet AD9652
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD3 = 3.3 V, AVDD = AVDD_CLK = 1.8 V, SPIVDD = DRVDD = 1.8 V, sample rate = 310 MSPS (clock input = 1240 MHz, AD9652
divided by 4), VIN = −1.0 dBFS differential input, 2.5 V p-p full-scale input range, duty cycle stabilizer (DCS) enabled, dither disabled,
unless otherwise noted.
Table 1.
Parameter Temperature Min Typ Max Unit
RESOLUTION Full 16 Bits
ACCURACY
No Missing Codes Full Guaranteed
Offset Error Full 1.5 mV
Gain Error Full −0.3 % FSR
Differential Nonlinearity (DNL) 1 Full −0.76/+1.1 LSB
Integral Nonlinearity (INL)1 Full −4.5/+4.5 LSB
MATCHING CHARACTERISTIC
Offset Error Full ±0.7 mV
Gain Error Full ±0.1 %FSR
TEMPERATURE DRIFT
Offset Error Full ±0.8 ppm/°C
Gain Error Full ±16 ppm/°C
INPUT REFERRED NOISE
VREF = 1.25 V 25°C 3.7 LSB rms
ANALOG INPUT
Input Span (for VREF = 1.25 V) Full 2.5 V p-p
Input Capacitance 2 Full 5.8 pF
Input Resistance 3 Full 27 kΩ
Input Common-Mode Voltage Full 2.0 2.4 V
POWER SUPPLIES
Supply Voltage
AVDD3 Full 3.15 3.3 3.45 V
AVDD Full 1.7 1.8 1.9 V
AVDD_CLK Full 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 V
SPIVDD Full 1.7 1.8 3.6 V
Supply Current, Clock Divider = 1
IAVDD3 Full 145 mA
IAVDD Full 701 mA
IAVDD_CLK Full 56 mA
IDRVDD Full 180 mA
ISPIVDD Full 0.005 mA
POWER CONSUMPTION
Clock Divider = 1
Normal Operation1 Full 2160 2236 mW
Standby Power 4 Full 80 mW
Power-Down Power Full 1 mW
1
Measured with a low input frequency, full-scale sine wave.
2
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3
Input resistance refers to the effective resistance between one differential input pin and AGND.
4
Standby power is measured with a dc input and the CLK± pins inactive (that is, set to AVDD or AGND).
AD9652 Data Sheet
ADC AC SPECIFICATIONS
divided by 4), VIN = −1.0 dBFS differential input, 2.5 V p-p full-scale input range, DCS enabled, dither disabled, unless otherwise noted.
Table 2.
VREF = 1 V VREF = 1.25 V, Default
Parameter1 Temperature Min Typ Max Min Typ Max Unit
DIFFERENTIAL INPUT VOLTAGE 25°C 2.0 2.5 V p-p
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 30 MHz (Use Nyquist 1 Settings) 25°C 74.0 75.4 dBFS
fIN = 70 MHz (Use Nyquist 1 Settings) 25°C 73.6 74.0 75.0 dBFS
Full 73.3 dBFS
fIN = 70 MHz (Use Nyquist 1 Settings, with Dither Enabled) 25°C 73.1 74.3 dBFS
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 70 MHz (Use Nyquist 1 Settings) 25°C 73.5 73.8 74.6 dBFS
Full 73.2 dBFS
fIN = 305 MHz (Use Nyquist 2 Settings) 25°C 68.5 dBFS
fIN = 400 MHz (Use Nyquist 3 Settings) 25°C 65.8 dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz (Use Nyquist 1 Settings) 25°C 11.8 12.0 Bits
fIN = 70 MHz (Use Nyquist 1 Settings) 25°C 12 12.0 12.1 Bits
Full 11.9 Bits
fIN = 70 MHz (Use Nyquist 1 Settings, with Dither Enabled) 25°C 11.8 12.0 Bits
fIN = 170 MHz (Use Nyquist 2 Settings) 25°C 11.7 11.8 Bits
fIN = 170 MHz (Use Nyquist 2 Settings, with Dither Enabled) 25°C 11.5 11.6 Bits
fIN = 305 MHz (Use Nyquist 2 Settings) 25°C 11.1 Bits
fIN = 400 MHz (Use Nyquist 3 Settings) 25°C 10.6 Bits
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz (Use Nyquist 1 Settings) 25°C −96 −94 dBc
fIN = 70 MHz (Use Nyquist 1 Settings) 25°C −90 −87 −83 dBc
Full −83 dBc
fIN = 70 MHz (Use Nyquist 1 Settings, with Dither Enabled) 25°C −92 −89 dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz (Use Nyquist 1 Settings) 25°C 96 94 dBc
fIN = 70 MHz (Use Nyquist 1 Settings) 25°C 90 83 87 dBc
Full 83 dBc
fIN = 70 MHz (Use Nyquist 1 Settings. with Dither Enabled) 25°C 92 89 dBc
fIN = 170 MHz (Use Nyquist 2 Settings, with Dither Enabled) 25°C 87 85 dBc
Data Sheet AD9652
VREF = 1 V VREF = 1.25 V, Default
Parameter1 Temperature Min Typ Max Min Typ Max Unit
WORST OTHER (NOT INCLUDING 2nd or 3rd HARMONIC)
fIN = 70 MHz (Use Nyquist 1 Settings) 25°C −99 −98 −90 dBc
Full −86 dBc
TWO-TONE SFDR
fIN = 70.1 MHz (−7 dBFS ), 72.1 MHz (−7 dBFS ) 25°C 93 dBc
fIN = 184.12 MHz (−7 dBFS ), 187.12 MHz (−7 dBFS ) 25°C 83 dBc
CROSSTALK2 Full 90 90 dB
FULL POWER BANDWIDTH3 25°C 485 485 MHz
NOISE BANDWIDTH4 25°C 650 650 MHz
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2
Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
3
Full power bandwidth is the bandwidth of operation in which proper ADC performance can be achieved.
4
Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise can enter the ADC and is not attenuated internally.
DIGITAL SPECIFICATIONS
divided by 4), VIN = −1.0 dBFS differential input, 2.5 V p-p full-scale input range, DCS enabled, dither disabled, unless otherwise noted.
Table 3.
Parameter Test Conditions/Comments Temperature Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+,
CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage Full 0.3 3.6 V p-p
Input Voltage Range Full AGND AVDD_CLK V
Internal Common-Mode Bias Full 0.9 V
Input Common-Mode Range Full 0.9 1.4 V
High Level Input Current Full +10 +145 μA
Low Level Input Current Full −155 −15 μA
Input Capacitance1 Full 5 pF
Input Resistance1 Full 10 kΩ
SYNC INPUT
Logic Compliance CMOS/LVDS
Internal Bias Full 0.9 V
Input Voltage Range Full AGND AVDD_CLK V
High Level Input Voltage Full 1.2 AVDD_CLK V
Low Level Input Voltage Full AGND 0.6 V
High Level Input Current Full −15 +110 μA
Low Level Input Current Full −105 +15 μA
Input Capacitance Full 1.5 pF
Input Resistance Full 16 kΩ
AD9652 Data Sheet
LOGIC INPUT (CSB)2
High Level Input Voltage Full 1.22 SPIVDD V
Low Level Input Voltage Full 0 0.6 V
Low Level Input Current Full −135 0 μA
Input Capacitance Full 2 pF
LOGIC INPUT (SCLK)3
High Level Input Current Full 0 110 μA
LOGIC INPUTS (SDIO)2
Low Level Input Current Full −135 0 μA
LOGIC INPUTS (PDWN)3
High Level Input Voltage Full 1.22 DRVDD V
DIGITAL OUTPUTS
LVDS Data and OR± Outputs Assumes nominal 100 Ω differential
termination
ANSI Mode
Differential Output Voltage Maximum setting, default Full 310 350 450 mV
(VOD)
Output Offset Voltage (VOS) Full 1.15 1.22 1.35 V
Reduced Swing Mode
Differential Output Voltage Minimum setting Full 150 200 280 mV
(VOD)
Output Offset Voltage (VOS) Full 1.15 1.22 1.35 V
1
Input capacitance/resistance refers to the effective capacitance/resistance between one differential input pin and AGND.
2
Internal weak pull-up.
3
Internal weak pull-down.
Data Sheet AD9652
SWITCHING SPECIFICATIONS
Table 4.
CLOCK INPUT PARAMETERS (CLK±)
Input Clock Rate Full 80 1240 MHz
Conversion Rate 1 Full 80 310 MSPS
Period—Divide by 1 Mode (tCLK) Full 3.2 ns
Pulse Width High (tCH), Minimum
Divide by 1 Mode DCS enabled Full 0.8 ns
DCS disabled Full 1.3 ns
Divide by 2 Mode Through Divide by 8 Mode Full 0.8 ns
Aperture Delay (tA) Full 1.0 ns
Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms
DATA OUTPUT PARAMETERS
LVDS Mode
Data Propagation Delay (tPD) Full 290 ps
DCO± Propagation Delay (tDCO) Full 290 ps
DCO± to Data Skew (tSKEW) Full −80 −280 −480 ps 2
Pipeline Delay (Latency) Full 26 Cycles
Wake-Up Time From standby Full 100 µs
From power-down Full 1 sec
Out of Range Recovery Time Full 3 Cycles
1
Conversion rate is the clock rate after the divider.
2
Data transitions prior to DCO± edge transition.
TIMING SPECIFICATIONS
Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
SYNC TIMING REQUIREMENTS
tSSYNC SYNC to the rising edge of CLK+ setup time 0.1 ns
tHSYNC SYNC to the rising edge of CLK+ hold time 0.1 ns
SPI TIMING REQUIREMENTS
tDS Setup time between the data and the rising edge of SCLK 2 ns
tDH Hold time between the data and the rising edge of SCLK 2 ns
tCLK Period of the SCLK 40 ns
tS Setup time between CSB and SCLK 2 ns
tH Hold time between CSB and SCLK 2 ns
tHIGH Minimum period that SCLK is in a logic high state 10 ns
tLOW Minimum period that SCLK is in a logic low state 10 ns
tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative 10 ns
to the SCLK falling edge (not shown in Timing Diagrams)
tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative 10 ns
to the SCLK rising edge (not shown in Timing Diagrams)
tSPI_RST Time required after power-up, hard or soft reset until SPI access is available 500 µs
(not shown in Timing Diagrams)
AD9652 Data Sheet
Timing Diagrams
tA
N–1 N+4
N+5
N
N+3
VIN±x
N+1 N+2
tCH
tCLK
CLK+
CLK–
tDCO
DCO–
DCO+
tSKEW
tPD
PARALLEL
INTERLEAVED D0± (LSB) CH A CH B CH A CH B CH A CH B CH A CH B CH A
N – 26 N – 26 N – 25 N – 25 N – 24 N – 24 N – 23 N – 23 N – 22
CHANNEL A
AND
CHANNEL B
12169-002
D15± (MSB) CH A CH B CH A CH B CH A CH B CH A CH B CH A
N – 26 N – 26 N – 25 N – 25 N – 24 N – 24 N – 23 N – 23 N – 22
Figure 2. LVDS Data Output Timing
CLK±
tSSYNC tHSYNC
12169-003
SYNC
Figure 3. SYNC Timing Inputs
tHIGH
tDS tCLK tH
tS tDH tLOW
CSB
SCLK DON’T CARE DON’T CARE
12169-049
SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE
Figure 4. Serial Port Interface Timing Diagram
Data Sheet AD9652
ABSOLUTE MAXIMUM RATINGS

Table 6. THERMAL CHARACTERISTICS
Parameter Rating Typical θJA is specified for both a 4-layer printed circuit board
Electrical (PCB) with a solid ground plane from the JEDEC 51-2 and an
AVDD3 to AGND −0.3 V to +3.6 V 8-layer PCB. The 8-layer PCB has 2 oz copper layers (M1 and
AVDD_CLK to AGND −0.3 V to +2.0 V M8), 1 oz copper inner layers, and vias connecting to layers M2,
AVDD to AGND −0.3 V to +2.0 V M5, and M7.
DRVDD to AGND −0.3 V to +2.0 V As shown in Table 7, airflow increases heat dissipation, which
SPIVDD to AGND −0.3 V to +3.6 V reduces θJA. In addition, metal in direct contact with the
VIN+A/VIN+B, VIN−A/VIN−B to AGND 1.2 V to 3.0 V package leads from metal traces, through holes, ground, and
CLK+, CLK− to AGND −0.3 V to AVDD_CLK + power planes, reduces the θJA.
0.2 V
SYNC to AGND −0.3 V to AVDD_CLK + Table 7. Thermal Resistance
0.2 V Airflow
VCM to AGND −0.3 V to AVDD + 0.2 V Velocity
CSB to AGND −0.3 V to SPIVDD + 0.3 V Package Type (m/sec) Board Type θJA 2 Unit
SCLK to AGND −0.3 V to SPIVDD + 0.3 V 144-Ball CSP_BGA 0 8-layer PCB 15.8 °C/W
SDIO to AGND −0.3 V to SPIVDD + 0.3 V 10 mm × 10 mm 1.0 8-layer PCB 13.9 °C/W
PDWN to AGND −0.3 V to DRVDD + 0.3 V (BC-144-6)
0 JEDEC1 21.7 °C/W
OR+/OR− to AGND −0.3 V to DRVDD + 0.3 V 1.0 JEDEC1 19.2 °C/W
D0± Through D15± to AGND −0.3 V to DRVDD + 0.3 V 1
Per JEDEC JESD51-7, plus JEDEC 25-5 2S2P test board.
DCO± to AGND −0.3 V to DRVDD + 0.3 V 2
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Environmental
Operating Temperature Range −40°C to +85°C
(Ambient) ESD CAUTION
Maximum Junction Temperature 125°C
Under Bias
Storage Temperature Range −65°C to +150°C
(Ambient)
Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
AD9652 Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD9652
TOP VIEW
(Not to Scale)
1 2 3 4 5 6 7 8 9 10 11 12
A RBIAS VCM AVDD3 VIN+B VIN–B AVDD3 AVDD3 VIN–A VIN+A AVDD3 SENSE VREF
B AGND AVDD3 AVDD3 AGND AGND AVDD3 AVDD3 AGND AGND AVDD3 AVDD3 AGND
C AVDD_ AVDD_
AGND AGND AVDD AGND AGND CLK CLK AGND AGND AVDD AGND AGND
D AVDD_ AVDD_
CLK– AGND AVDD AGND AGND CLK CLK AGND AGND AVDD AGND CSB
AVDD_ AVDD_
E CLK+ AGND AVDD AGND AGND CLK CLK AGND AGND AVDD AGND SDIO
AVDD_ AVDD_
F TEST AGND AVDD AGND AGND CLK CLK AGND AGND AVDD AGND SCLK
G SYNC AGND AVDD AGND AGND AVDD AVDD AGND AGND AVDD AGND OR+
H PDWN AGND AVDD AGND AGND AVDD AVDD AGND AGND AVDD AGND OR–
J D0– D0+ DRGND DRGND DRGND DRGND DRGND DC0+ DRGND DRGND D15+ D15–
K D1– D1+ DRVDD DRVDD SPIVDD DRVDD DRVDD DC0– DRVDD DRVDD D14+ D14–
L D2+ D3+ D4+ D5+ D6+ D7+ D8+ D9+ D10+ D11+ D12+ D13+
M D2– D3– D4– D5– D6– D7– D8– D9– D10– D11– D12– D13–
12169-004
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions

Pin No. Mnemonic Type Description
ADC Power Supplies
K5 SPIVDD Supply Serial Interface Logic Voltage Supply (1.8 V Typical, 3.3 V Optional)
K3, K4, K6, K7, K9, K10 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal).
A3, A6, A7, A10, B2, B3, B6, B7, AVDD3 Supply 3.3 V Analog Power Supply (3.3 V Nominal).
B10, B11
C6, C7, D6, D7, E6, E7, F6, F7 AVDD_CLK Supply 1.8 V Analog Power Supply for Clock Circuitry (1.8 V Nominal).
C3, C10, D3, D10, E3, E10, F3, AVDD Supply 1.8 V Analog Power Supply (1.8 V Nominal).
F10, G3, G6, G7, G10, H3, H6,
H7, H10
B1, B4, B5, B8, B9, B12, C1, C2, AGND Analog Analog Ground Reference for AVDD3, AVDD_CLK, and AVDD.
C4, C5, C8, C9, C11, C12, D2, Ground
D4, D5, D8, D9, D11, E2, E4,
E5, E8, E9, E11, F2, F4, F5, F8,
F9, F11, G2, G4, G5, G8, G9,
G11, H2, H4, H5, H8, H9, H11
J3 DRGND Digital Ground Digital and Output Driver Ground Reference.
Data Sheet AD9652
ADC Analog
A9 VIN+A Input Differential Analog Input Pin (+) for Channel A.
A8 VIN−A Input Differential Analog Input Pin (−) for Channel A.
A4 VIN+B Input Differential Analog Input Pin (+) for Channel B.
A5 VIN−B Input Differential Analog Input Pin (−) for Channel B.
A2 VCM Output Common-Mode Level Bias Output for Analog Inputs. Decouple
this pin to ground using a 0.1 μF capacitor.
A1 RBIAS Output External Bias Resister Connection. A 10 kΩ resister must be
connected between this pin and analog ground (AGND).
A12 VREF Input/Output Voltage Reference Input/Output.
A11 SENSE Input Reference Mode Selection (See Table 12).
E1 CLK+ Input ADC Clock Input (True).
D1 CLK− Input ADC Clock Input (Complement).
Digital Inputs
F1 TEST Input Pull-Down. Unused digital input, pull to ground through a 50 Ω
resistor.
G1 SYNC Input Digital Input Clock Synchronization Pin. Tie low if unused.
H1 PDWN Input Power-Down Input (Active High). The operation of this pin
depends on the SPI mode and can be configured as power-down
or standby (see Register 0x08 in Table 17).
Digital Outputs
J2 D0+ Output Channel A/Channel B LVDS Output Data 0 (True, LSB).
J1 D0− Output Channel A/Channel B LVDS Output Data 0 (Complement, LSB).
K2 D1+ Output Channel A/Channel B LVDS Output Data 1 (True).
K1 D1− Output Channel A/Channel B LVDS Output Data 1 (Complement).
L1 D2+ Output Channel A/Channel B LVDS Output Data 2 (True).
M1 D2− Output Channel A/Channel B LVDS Output Data 2 (Complement).
K11 D14+ Output Channel A/Channel B LVDS Output Data 14 (True).
AD9652 Data Sheet
K12 D14− Output Channel A/Channel B LVDS Output Data 14 (Complement).
J11 D15+ Output Channel A/Channel B LVDS Output Data 15 (True, MSB).
J12 D15− Output Channel A/Channel B LVDS Output Data 15 (Complement, MSB).
G12 OR+ Output Channel A/Channel B LVDS Overrange (True).
H12 OR− Output Channel A/Channel B LVDS Overrange (Complement).
J8 DCO+ Output Channel A/Channel B LVDS Data Clock Output (True).
K8 DCO− Output Channel A/Channel B LVDS Data Clock Output (Complement).
SPI Control
F12 SCLK Input SPI Serial Clock.
E12 SDIO Input/Output SPI Serial Data Input/Output.
D12 CSB Input SPI Chip Select (Active Low). This pin must be pulled high at
power-up.
Data Sheet AD9652
TYPICAL PERFORMANCE CHARACTERISTICS

divide by 4), VIN = −1.0 dBFS differential, VREF = 1.25 V, DCS enabled, dither disabled, unless otherwise noted.
0 0
AIN = –1dBFS AIN = –1dBFS
SNRFS = 75.0dB SNRFS = 74.4dB
–20 SFDR = 89dBc –20 SFDR = 90dBc
–40 –40
AMPLITUDE (dB)
AMPLITUDE (dB)
–60 –60
–80 –80
–100 –100
–120 –120
–140 12169-005 –140
12169-006
0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140
fIN (MHz) fIN (MHz)
Figure 6. Single Tone Fast Fourier Transform (FFT) with fIN = 70.1 MHz Figure 9. Single Tone FFT with fIN = 70.1 MHz with Dither
(NSD = −156.7 dBFS/Hz) (NSD = −156.3 dBFS/Hz)
0 0
–20 SFDR = 91.9dBc –20 SFDR = 94.4dBc
–40 –40
AMPLITUDE (dB)
AMPLITUDE (dB)
–60 –60
–80 –80
–100 –100
–120 –120
–140 –140
12169-007
12169-008
0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140
fIN (MHz) fIN (MHz)
Figure 7. Single Tone FFT with fIN = 70.1 MHz at −7 dBFS Figure 10. Single Tone FFT with fIN = 70.1 MHz at −7 dBFS with Dither
(NSD = −157.6 dBFS/Hz) (NSD = −157.1 dBFS/Hz)
0 0
SFDR = 88dBc –20 SFDR = 88dBc
–20
–40 –40
AMPLITUDE (dB)
AMPLITUDE (dB)
–60 –60
–80 –80
–100 –100
–120 –120
–140 –140
12169-010
0 20 40 60 80 100 120 140

12169-009
0 20 40 60 80 100 120 140

fIN (MHz) fIN (MHz)
Figure 8. Single Tone FFT with fIN = 185 MHz. at −1 dBFS Figure 11. Single Tone FFT with fIN = 185 MHz at −1 dBFS with Dither
(NSD = −155.2 dBFS/Hz), Register 0x22A = 0x01 (NSD = −154.9 dBFS/Hz), Register 0x22A = 0x01
AD9652 Data Sheet
0 0
SNRFS = 75dB SNRFS = 74.5dB
–20 SFDR = 92dBc –20 SFDR = 93dBc
–40 –40
AMPLITUDE (dB)
AMPLITUDE (dB)
–60 –60
–80 –80
–100 –100
–120 –120
–140 –140
12169-012
12169-011
0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140
fIN (MHz) fIN (MHz)
Figure 12. Single Tone FFT with fIN = 185 MHz at −7 dBFS Figure 15. Single Tone FFT with fIN = 185 MHz at −7 dBFS with Dither
(NSD = −156.9 dBFS/Hz), Register 0x22A = 0x01 (NSD = −156.4 dBFS/Hz), Register 0x22A = 0x01
0 0
–20 SFDR = 86.9dBc –20 SFDR = 91.6dBc
–40 –40
MAGNITUDE (dB)
MAGNITUDE (dB)
–60 –60
–80 –80
–100 –100
–120 –120
–140 –140
12169-200
12169-201
0 50 100 150 0 50 100 150
fIN (MHz) fIN (MHz)
Figure 13. FFT fIN = 305 MHz, AIN = −1 dBFS, Dither Off, Figure 16. FFT fIN = 305 MHz, AIN = −1 dBFS, Dither On,
Register 0x22A = 0x01 Register 0x22A = 0x01
0 0
–20 SFDR = 90.7dBc –20 SFDR = 90.7dBc
–40 –40
MAGNITUDE (dB)
MAGNITUDE (dB)
–60 –60
–80 –80
–100 –100
–120 –120
–140 –140
12169-204
12169-205
0 50 100 150 0 50 100 150

fIN (MHz) fIN (MHz)
Data Sheet AD9652
0 0
–20 SFDR = 75.7dBc –20 SFDR = 75.0dBc
–40 –40
MAGNITUDE (dB)
MAGNITUDE (dB)
–60 –60
–80 –80
–100 –100
–120 –120
–140 –140
12169-202
12169-203
0 50 100 150 0 50 100 150
fIN (MHz) fIN (MHz)
0 0
–20 SFDR = 81.3dBc –20 SFDR = 80.2dBc
–40 –40
MAGNITUDE (dB)
–60 MAGNITUDE (dB) –60
–80 –80
–100 –100
–120 –120
–140 –140
12169-206
12169-207
0 50 100 150 0 50 100 150
fIN (MHz) fIN (MHz)
78 140 78 140
76 76
120 120
74 74
72 SNRFS (dB), –40°C 100 72 SNRFS (dB), –40°C 100

SNRFS (dB), +25°C SNRFS (dB), +25°C
SFDR (dB)
SFDR (dB)
SNR (dB)
SNR (dB)
70 SFDR (dBFS), –40°C 70 SFDR (dBFS), –40°C

SFDR (dBFS), +25°C 80 SFDR (dBFS), +25°C 80
SFDR (dBFS), +85°C SFDR (dBFS), +85°C
68 SFDR (dBc), –40°C 68 SFDR (dBc), –40°C
SFDR (dBc), +25°C SFDR (dBc), +25°C
66 60 66 60
64 64
40 40
62 62
60 20 60 20
12169-014
12169-114
–80 –60 –40 –20 0 –80 –60 –40 –20 0

AIN (–dBFS) AIN (–dBFS)
Figure 20. Single Tone SNR/SFDR vs. Input Amplitude (AIN) with Figure 23. Single Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 90.1 MHz, VREF = 1.25 V, Over Temperature, Dither Off fIN = 90.1 MHz, VREF = 1.25 V, Over Temperature, Dither On
AD9652 Data Sheet
78 140 78 140
76 76
120 120
74 74
72 SNRFS (dB), –40°C 100 72 SNRFS (dB), –40°C 100

SFDR (dB)
SFDR (dB)
SNR (dB)
SNR (dB)
70 SFDR (dBFS), –40°C 70 SFDR (dBFS), –40°C
SFDR (dBFS), +25°C 80 SFDR (dBFS), +25°C 80
SFDR (dBFS), +85°C SFDR (dBFS), +85°C
68 SFDR (dBc), –40°C 68 SFDR (dBc), –40°C
66 60 66 60
64 64
40 40
62 62
60 20 60 20
12169-015
12169-115
–80 –60 –40 –20 0 –80 –60 –40 –20 0
AIN (–dBFS) AIN (–dBFS)
Figure 24. Single Tone SNR/SFDR vs. Input Amplitude (AIN) with Figure 27. Single Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN =
fIN = 90.1 MHz, VREF = 1.0 V, Over Temperature, Dither Off 90.1 MHz, VREF = 1.0 V, Over Temperature, Dither On
76 110 76 110
SNRFS SNRFS
(NYQUIST SETTING 1) (NYQUIST SETTING 1)
74 SNRFS 106 74 SNRFS 106
72 SNRFS 102 72 SNRFS 102
70 98 70 98
68 94 68 94
SFDR (dBc)
SFDR (dB)
SNR (dB)
SNR (dB)
66 90 66 90
64 86 64 86
62 82 62 82
SFDR SFDR
60 (NYQUIST SETTING 1) 78 60 (NYQUIST SETTING 1) 78
SFDR SFDR
SFDR SFDR
56 70 56 70
12169-116
12169-016
0 50 100 150 200 250 300 350 400 450 500 550 0 50 100 150 200 250 300 350 400 450 500 550
fIN (MHz) fIN (MHz)
Figure 25. Single Tone SNR/SFDR vs. Input Frequency (fIN), Figure 28. Single Tone SNR/SFDR vs. Input Frequency (fIN),
Amplitude = −1 dBFS, VREF = 1.25 V Amplitude =−1 dBFS, VREF = 1.0 V
76 110 76 110
74 SNRFS 106 74 106

(NYQUIST SETTING 1) SNRFS
(NYQUIST SETTING 1)
72 SNRFS 102 72 102
(NYQUIST SETTING 2) SNRFS
(NYQUIST SETTING 2)
SNRFS
70 (NYQUIST SETTING 3) 98 70 SNRFS 98
(NYQUIST SETTING 3)
68 94 68 94
SFDR (dBc)
SFDR (dBc)
SNR (dB)
SNR (dB)
66 90 66 90
64 86 64 86
62 82 62 82
SFDR SFDR
SFDR SFDR
SFDR SFDR
56 70 56 70
12169-017
12169-117
0 50 100 150 200 250 300 350 400 450 500 550 0 50 100 150 200 250 300 350 400 450 500 550
fIN (MHz) fIN (MHz)
Figure 26. Single Tone SNR/SFDR vs. Input Frequency (fIN), Figure 29. Single Tone SNR/SFDR vs. Input Frequency (fIN),
Amplitude = −7 dBFS, VREF = 1.25 V Amplitude = −7 dBFS, VREF = 1.0 V
Data Sheet AD9652
0 105 0 105
–20 100 –20 100
–40 95 –40 95
SFDR (dBFS)
SFDR (dBFS)
IMD (dB)
IMD (dB)
–60 90 –60 90
SFDR (dBFS) SFDR (dBFS)
IMD2 (dBc) IMD2 (dBc)
–80 IMD3 (dBc) 85 –80 IMD3 (dBc) 85
IMD2 (dBFS) IMD2 (dBFS)
–100 80 –100 80
–120 75 –120 75
12169-329
12169-332
–80 –60 –40 –20 0 –80 –60 –40 –20 0
INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS)
Figure 30. Two Tone SFDR/Intermodulation Distortion (IMD) vs. Input Figure 33. Two Tone SFDR/IMD vs. Input Amplitude, for fIN = 70.1 MHz and
Amplitude, for fIN = 70.1 MHz and 72.1 MHz, Dither Disabled 72.1 MHz, Dither Enabled
0 105 0 105
–20 100 –20 100
–40 95 –40 95
SFDR (dBFS)
SFDR (dBFS)
IMD (dB)
IMD (dB)
–60 90 –60 90
SFDR (dBFS) SFDR (dBFS)
IMD2 (dBc) IMD2 (dBc)
–80 IMD3 (dBc) 85 –80 IMD3 (dBc) 85
–100 80 –100 80
–120 75 –120 75
12169-330
12169-333
–80 –60 –40 –20 0 –80 –60 –40 –20 0
INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS)
Figure 31. Two Tone SFDR/IMD vs. Input Amplitude, for fIN = 184 MHz and Figure 34. Two Tone SFDR/IMD vs. Input Amplitude, for fIN = 184 MHz and
187 MHz, Dither Disabled, Register 0x22A = 0x01 187 MHz, Dither Enabled, Register 0x22A = 0x01
0 70000
AIN1 = AIN2 = –7dBFS
SFDR = 87dBc (94dBFS)
–20 IMD2 = –92dBc (–99dBFS) 60000
IMD3 = –87dBc (–94dBFS)
–40 50000
NUMBER OF HITS
AMPLITUDE (dB)
–60 40000
–80 30000
–100 20000
–120 10000
–140 0
12169-331
N+4
N+6
N+8
N + 10
N + 12
N + 14
N + 16
N + 18
N + 20
0 25 50 75 100 125 150

N–8
N–6
N–4
N–2
N +2
N – 20
N – 18
N – 16
N – 14
N – 12
N – 10
12169-026
fIN (MHz)
CODES
Figure 32. Two Tone FFT with fIN = 89.1 MHz and 92.1 MHz, VREF = 1.25 V Figure 35. Grounded Input Histogram
AD9652 Data Sheet
100 100
95 95
SFDR (VREF = 1V)

SNRFS/SFDR (dB/dBc)
SNRFS/SFDR (dB/dBc)
SFDR (VREF = 1V)
90 90
85 85
SFDR (VREF = 1.25V)
SFDR (VREF = 1.25V)
80 80
SNRFS (VREF = 1.25V)

75 75 SNRFS (VREF = 1.25V)
SNRFS (VREF = 1V) SNRFS (VREF = 1V)

70 70
12169-335
12169-338
80 120 160 200 240 280 320 80 120 160 200 240 280 320
ENCODE RATE (MHz) ENCODE RATE (MHz)
Figure 36. Encode Rate Sweep, fIN = 90.1 MHz at −7 dBFS, Figure 39. Encode Rate Sweep, fIN = 90.1 MHz at −1 dBFS,
VREF = 1.25 V and 1.0 V VREF = 1.25 V and 1.0 V
1.0 6
0.8
0.6
3
0.4
0.2
DNL (LSB)
INL (LSB)
0 0
–0.2
–0.4
–3
–0.6
–0.8
–1.0 –6
12169-024
12169-124
0 10000 20000 30000 40000 50000 60000 0 10000 20000 30000 40000 50000 60000
CODES CODES
Figure 37. DNL with Dither Off, fIN = 30 MHz Figure 40. INL with Dither Off, fIN = 30 MHz
1.0 6
0.8
0.6
3
0.4
0.2
DNL (LSB)
INL (LSB)
0 0
–0.2
–0.4
–3
–0.6
–0.8
–1.0 –6
12169-025
12169-125
0 10000 20000 30000 40000 50000 60000 0 10000 20000 30000 40000 50000 60000
CODES CODES
Figure 38. DNL with Dither On, fIN = 30 MHz Figure 41. INL with Dither On, fIN = 30 MHz
Data Sheet AD9652
EQUIVALENT CIRCUITS
SPIVDD
AVDD3
350Ω
SCLK
VIN±x 26kΩ
12169-339
27kΩ
12169-027
Figure 42. Equivalent Analog Input Circuit Figure 47. Equivalent SCLK Input Circuit
AVDD_CLK
SPIVDD
AVDD AVDD
26kΩ
0.9V
350Ω
10kΩ 10kΩ CSB
CLK+ CLK–
12169-032
12169-028
Figure 43. Equivalent Clock Circuit Figure 48. Equivalent CSB Input Circuit
DRVDD
AVDD_CLK AVDD_CLK
V+ V–
DATAOUT– DATAOUT+ SYNC 0.9V

V– V+
16kΩ
12169-033
0.9V
12169-029
Figure 44. Equivalent LVDS Output Circuit (DCO±, OR±, and D0± to D15±) Figure 49. Equivalent SYNC Input Circuit
AVDD
SPIVDD
26kΩ
350Ω
350Ω SENSE
SDIO 12168-208
12169-030
Figure 45. Equivalent SDIO Circuit Figure 50. Equivalent SENSE Circuit
AVDD
350Ω
PDWN VREF
6kΩ
26kΩ
12169-209
12169-300
Figure 46. Equivalent PDWN Input Circuit Figure 51. Equivalent VREF Circuit
AD9652 Data Sheet
THEORY OF OPERATION
The AD9652 is a dual, 16-bit ADC with sampling speeds of up ANALOG INPUT CONSIDERATIONS
to 310 MSPS. The AD9652 is designed to support communications The analog inputs to the AD9652 are high performance
and instrumentation applications where high performance and differential buffers that are designed for optimum performance
wide bandwidth are desired. while processing a differential input signal. The input buffer
The dual ADC design can be used for diversity receivers, where provides a consistent input impedance to ease interface of the
the ADCs operate identically on the same carrier but from two analog input.
separate antennae. The ADCs can also be operated with inde- The differential analog input impedance is approximately 54 kΩ
pendent analog inputs. The user can sample frequencies from dc in parallel with a 5.8 pF capacitor. A passive network of discrete
to 310 MHz using appropriate low-pass or band-pass filtering at components can create a low-pass filter at the ADC input; the
the ADC inputs with little loss in ADC performance. A typical precise values are dependent on the application.
operation of 485 MHz at the analog input is permitted but occurs
at the expense of increased ADC noise and distortion. In intermediate frequency (IF) undersampling applications, reduce
the shunt capacitors. In combination with the driving source
Synchronization capability is provided to allow synchronized impedance, the shunt capacitors limit the input bandwidth. Refer
timing between multiple devices. to the Analog Dialogue article, “Transformer-Coupled Front-End
Programming and control of the AD9652 are accomplished for Wideband A/D Converters,” for more information on this
using a 3-wire, SPI-compatible serial interface. subject.
ADC ARCHITECTURE The AD9652 uses internal optimized settings for the various
The AD9652 consists of a dual, buffered front-end sample-and- input signal frequencies. Register 0x22A configures the ADC
hold circuit, followed by a pipelined switched-capacitor ADC. for the desired frequency band.
The AD9652 uses a unique architecture that utilizes the benefits Table 9. Register 0x22A Settings
of pipelined converters, as well as a novel input circuit to
Register 0x22A Setting Input Frequency Range
maximize performance of the first stage.
0 (Default) 0 to 155 MHz (1st Nyquist)
The quantized outputs from each stage are combined to produce 1 155 to 310 MHz (2nd Nyquist)
a 16-bit result in the digital correction logic. The pipelined archi- 2 310 MHz and above (3rd Nyquist)
tecture permits the first stage to operate on a new input sample,
For best dynamic performance, the source impedances driving
and the remaining stages to operate on the preceding samples.
each of the differential inputs, match VIN±x, and differentially
Sampling occurs on the rising edge of the clock.
balance the inputs.
Each stage of the pipeline, excluding the last, consists of a low
Input Common Mode
resolution flash ADC connected to a switched-capacitor digital-
to-analog converter (DAC) and an interstage residual multiplying The analog inputs of the AD9652 are not internally dc biased. In
DAC (MDAC). The MDAC magnifies the difference between ac-coupled applications, the user must provide this bias externally.
the reconstructed DAC output and the flash input for the next Setting the device so that the common-mode voltage equals
stage in the pipeline. One bit of redundancy is used in each stage 2.0 V is recommended for optimum performance. An on-board
to facilitate digital correction of flash errors. The last stage common-mode voltage reference is included in the design and
consists of a flash ADC. is available from the VCM pin. Using the VCM output to set the
input common mode is recommended. The VCM pin must be
The AD9652 uses internal digital processing to continually track
decoupled to ground with a 0.1 µF capacitor, as described in the
internal errors that occur at each of the pipeline stages and corrects
Applications Information section. Place this decoupling capacitor
for them to ensure continuous performance over various operating
close to the pin to minimize the series resistance and inductance
conditions. This requires additional start-up time due to the
between the device and this capacitor.
resetting and collection of correction data.
Common-Mode Voltage Servo
The input stage of each channel contains a differential sampling
circuit that can be ac-coupled or dc-coupled in differential or In applications where there may be a voltage loss between the VCM
single-ended modes. The output staging block aligns the data, output of the AD9652 and the analog inputs, the common-mode
corrects errors, and passes the data to the output buffers. The voltage servo can be enabled. When the inputs are ac-coupled and a
output buffers are powered from a separate supply, allowing resistance of >100 Ω is placed between the VCM output and the
digital output noise to be separated from the analog core. During analog inputs, a significant voltage drop can occur; enable the
power-down, the output buffers enter a high impedance state. common-mode voltage servo. Setting Bit 0 in Register 0x0F to a
logic high enables the VCM servo mode.
Data Sheet AD9652
In this mode, the AD9652 monitors the common-mode input Large Signal Fast Fourier Transform
level at the analog inputs and adjusts the VCM output level to In most cases, dithering does not improve SFDR for large signal
keep the common-mode input voltage at an optimal level. If both inputs close to full scale, for example, with a −1 dBFS input. For
channels are operational, Channel A is monitored. However, if large signal inputs, the SFDR is typically limited by front-end
Channel A is in power-down or standby mode, then Channel B sampling distortion, which dithering cannot improve. However,
input is monitored. even for such large signal inputs, dithering can be useful for
Dither certain applications because it makes the noise floor whiter. As
The AD9652 has an optional internal dither circuitry that can is common in pipeline ADCs, the AD9652 contains small DNL
improve SFDR, particularly for small signals. Dithering is the act errors caused by random component mismatches that produce
of injecting a known but random amount of white noise into the spurs or tones that make the noise floor somewhat randomly
input of the AD9652. Dithering has the effect of improving the colored device-to-device. Although these tones are typically at
local linearity within the ADC transfer function. The AD9652 very low levels and do not limit SFDR when the ADC is quantizing
allows dither to be added to either ADC input independently. large signal inputs, dithering converts these tones to noise and
The full scale of the dither DAC is small enough that enabling produces a whiter noise floor.
dither does not limit the external input signal amplitude. Small Signal FFT
As shown in Figure 52, the dither that is added to the input of For small signal inputs, the front-end sampling circuit typically
the ADC through the dither DAC is precisely subtracted out contributes very little distortion, and the SFDR is likely to be
digitally to minimize SNR degradation. When dithering is enabled, limited by tones caused by DNL errors due to random component
the dither DAC is driven by a pseudorandom number generator mismatches. Therefore, for small signal inputs (typically, those
(PN gen). In the AD9652, the dither DAC is precisely calibrated below −6 dBFS), dithering can significantly improve SFDR by
to result in only a very small degradation in SNR and SINAD converting these DNL tones to white noise.
when dither is enabled.
Static Linearity
AD9652 Dithering also removes sharp local discontinuities in the INL
VIN±x ADC CORE DOUT transfer function of the ADC and reduces the overall peak-to-
peak INL.
DITHER
Utilizing dither randomizes local small signal DNL errors that
DAC produce the discontinuities in the INL transfer function and
therefore improve the peak-to-peak INL performance.
12169-034
PN GEN DITHER ENABLE Differential Input Configurations

Figure 52. Dither Block Diagram Optimum performance is achieved by driving the AD9652 in a
differential input configuration. For baseband applications, the
The SFDR improvement comes at the expense of SNR degradation, ADL5566, AD8138, ADA4937-2, ADA4938-2, and ADA4930-2
but because the dither is internal and can be correlated, the impact differential drivers provide excellent performance and a flexible
on SNR is typically limited to less than 0.5 dB in the first Nyquist interface to the ADC.
zone. Enabling internal dither does not impact full-scale dynamic
range. The magnitude of dither is controllable, which allows the The output common-mode voltage of the ADA4930-2 is easily
user to select the desired trade-off between SFDR improvement set with the VCM pin of the AD9652 (see Figure 53), and the
vs. SNR degradation. driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
To enable dither, set Bit 4 of Register 0x30. To modify the dither 15pF
gain, use Register 0x212[7:4].
200Ω
33Ω 15Ω
Table 10. Dither Gain VIN±x 76.8Ω
90Ω VIN–x
Register 0x212[7:4] Setting Gain Ratio Gain (%) 5pF

ADA4930-2 ADC
0b0000 (default) Maximum dither 100 0.1µF
33Ω 15Ω
0b0001 255/256 × max 99.6 120Ω VIN+x VCM
0b0010 254/256 × max 99.2 15pF

200Ω
0b0011 252/256 × max 98.4
12169-035
33Ω 0.1µF
0b0100 248/256 × max 96.8
0b0101 240/256 × max 93.75
Figure 53. Differential Input Configuration Using the ADA4930-2
0b0110 224/256 × max 87.5
0b0111 192/256 × max 75
0b1000 Minimum dither 50
AD9652 Data Sheet
For baseband applications where SNR is a key parameter, input frequency ranges. However, these values are dependent on
differential transformer coupling is the recommended input the input signal; use the bandwidth only as a starting guide.
configuration. An example is shown in Figure 54. To bias the Note that the values given in Table 11 are for each R1, R2, C1,
analog input, the VCM voltage can be connected to the center C2, and R3 component shown in Figure 54 and Figure 56.
tap of the secondary winding of the transformer.
Table 11. Example RC Network
C2 Frequency R1 C1 R2 C2 R3
R3
R2
Range Series Differential Series Shunt Shunt
VIN+x (MHz) (Ω) (pF) (Ω) (pF) (Ω)
R1
2V p-p
0 to 100 33 Open 0 15 49.9
49.9Ω C1 ADC
100 to 300 15 Open 15 2.7 0
R1 R2
VIN–x VCM
An alternative to using a transformer-coupled input at frequencies

0.1µF R3 33Ω 0.1µF in the second Nyquist zone is to use an amplifier with variable
12169-036
C2 gain. The AD8375 or AD8376 digital variable gain amplifier
(DVGA) provides good performance for driving the AD9652.
Figure 54. Differential Transformer-Coupled Configuration
Figure 55 shows an example of the AD8376 driving the AD9652
The signal characteristics must be considered when selecting a through a band-pass antialiasing filter.
transformer. Most RF transformers saturate at frequencies below a 1000pF 180nH 220nH
few megahertz. Excessive signal power can also cause core
saturation, which leads to distortion. 1µH 165Ω 15pF
VPOS AD9652
At input frequencies in the second Nyquist zone and above, the AD8376
5.1pF 3.9pF VCM
noise performance of most amplifiers is not adequate to achieve 1µH 1nF 301Ω 165Ω
54kΩ║2.9pF
1nF
the true SNR performance of the AD9652. For applications 68nH
where SNR is a key parameter, differential double balun coupling is 180nH 220nH
1000pF
NOTES
the recommended input configuration (see Figure 56). In this 1. ALL INDUCTORS ARE COILCRAFT® 0603CS COMPONENTS WITH THE
configuration, the input is ac-coupled and the VCM voltage is EXCEPTION OF THE 1µH CHOKE INDUCTORS (COIL CRAFT 0603LS).
12169-037
2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER
provided to each input through a 33 Ω resistor. These resistors CENTERED AT 140MHz.
compensate for losses in the input baluns to provide a 50 Ω Figure 55. Differential Input Configuration Using the AD8376
impedance to the driver.
In the double balun and transformer configurations, the value
of the input capacitors and resistors is dependent on the input
frequency and source impedance. Based on these parameters,
the value of the input resistors and capacitors may need to be
adjusted, or some components may need to be removed. Table 11
displays recommended values to set the RC network for different
C2
R3
0.1µF 0.1µF R1 R2
2V p-p VIN+x
33Ω
PA S S P C1 ADC
33Ω 0.1µF
0.1µF R1 R2
VIN–x VCM
R3 33Ω 0.1µF
12169-038
C2
Figure 56. Differential Double Balun Input Configuration
Table 12. VREF Configuration Options

Selected Mode SENSE Voltage Resulting ADC Reference Voltage (V) Resulting Input Span (Differential V p-p)
External Reference AVDD N/A1 2 × external reference
Internal Fixed Reference GND VREF2 2 × VREF2
1
N/A means not applicable.
2
VREF is set via Register 0x18. The default VREF is 1.25 V.
Data Sheet AD9652
0
VOLTAGE REFERENCE VREF = 1.25V
A stable and accurate voltage reference is built into the AD9652.

The full-scale input range can be adjusted by varying the reference –1
voltage via the SPI. The input span of the ADC linearly tracks
VREF ERROR (%)

reference voltage changes.
Internal Reference Connection –2
A stable and accurate programmable reference is built into the

AD9652, allowing a voltage reference from 1.0 V to 1.25 V to
–3
provide up to a 2.5 V p-p differential full-scale input. By default
the VREF voltage is set 1.25 V, but can be modified using
Register 0x18[2:0], VREF select.
–4
12169-056
To configure the AD9652 for an internal reference, the SENSE 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (mA)
pin must be tied low. When SENSE is tied low, the ADC uses
Figure 58. Reference Voltage Error vs. Load Current
VREF directly and provides a differential input voltage of two
times the VREF value. External Reference Operation
To achieve optimal noise performance when using the internal The use of an external reference can be necessary to enhance
reference, it is recommended that the VREF pin be decoupled the gain accuracy of the ADC or improve thermal drift charac-
by 1.0 µF and 0.1 µF capacitors close to the pin. Figure 57 shows teristics.
the configuration for the internal reference connection resulting When the SENSE pin is tied to AVDD, the internal reference is
in a input voltage set by VREF, that is, a 2.5 V p-p differential disabled, allowing the use of an external reference that is applied to
full-scale input. the VREF pin. An internal reference buffer loads the external
VIN+A/VIN+B reference with an equivalent 6 kΩ load. The internal buffer
VIN–A/VIN–B generates the positive and negative full-scale references for the
ADC core. Therefore, the external reference must be limited to
ADC
a maximum of 1.25 V to maintain an input voltage of 2.5 V p-p
CORE differential full-scale input or less.
VREF
CLOCK INPUT CONSIDERATIONS
1.0µF 0.1µF For optimum performance, clock the AD9652 sample clock
SELECT
LOGIC
inputs, CLK+ and CLK−, with a differential signal with a high
SENSE slew rate. The signal is typically ac-coupled into the CLK+ and
CLK− pins via a transformer or via capacitors. These pins are
VSELECT
biased internally (see Figure 59) and require no external bias. If
the inputs are floated, the CLK− pin is intentionally biased
12169-039
AD9652 slightly lower than CLK+ to prevent spurious clocking (this is

not shown in Figure 59).
Figure 57. Internal Reference Configuration
AVDD_CLK
If the internal reference of the AD9652 drives multiple converters
to improve gain matching, the loading of the reference by the 0.9V
other converters must be considered. Figure 58 shows how the
CLK+ CLK–
internal reference voltage is affected by loading.
5pF 5pF
12169-041
Figure 59. Simplified Equivalent Clock Input Circuit
AD9652 Data Sheet
Clock Input Options A third option is to ac couple a differential LVDS signal to the
The AD9652 has a very flexible clock input structure. The clock sample clock input pins, as shown in Figure 63. The AD9510,
input can be a CMOS, LVDS, LVPECL, or sine wave signal. AD9511, AD9512, AD9513, AD9514, AD9515, AD9516-5,
Regardless of the type of signal being used, clock source jitter is AD9517-1, AD9518-1, AD9520-5, AD9522-1, AD9523, and
of the most concern, as described in the Jitter Considerations AD9524 clock drivers offer excellent jitter performance.
section.
Figure 60 and Figure 61 show two preferable methods for 0.1µF 0.1µF ADC
CLOCK CLK+
clocking the AD9652 (at clock rates of up to 1240 MHz). A low INPUT
jitter clock source is converted from a single-ended signal to a AD95xx 100Ω
0.1µF LVDS DRIVER
0.1µF
differential signal using an RF balun or RF transformer. CLOCK CLK–
INPUT
12169-045
The RF balun configuration is recommended for clock frequencies 50kΩ 50kΩ
between 125 MHz and 1240 MHz, and the RF transformer is

recommended for clock frequencies from 80 MHz to 200 MHz. Figure 63. Differential LVDS Sample Clock (Up to 625 MHz)
The back-to-back Schottky diodes are used across the transformer Input Clock Divider
secondary or the balun balanced side to limit clock amplitude
The AD9652 contains an input clock divider with the ability to
excursions into the AD9652 to approximately 0.8 V p-p differential.
divide the input clock by integer values of 1, 2, 4 or 8. In these
This limit helps prevent large voltage swings of the clock from
cases, the DCS is enabled by default on power-up. The clock
feeding through to other portions of the AD9652, while preserving
divide ratio is set in Register 0x0B.
fast rise and fall times of the clock, which are critical to low
jitter performance. The AD9652 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock
Mini-Circuits® divider to be resynchronized on every SYNC signal or only on
ADT1-1WT, 1:1Z
ADC the first SYNC signal after the register is written. A valid SYNC
390pF 390pF
CLOCK XFMR causes the clock divider to reset to its initial state. This synchron-
INPUT CLK+
50Ω 100Ω ization feature allows multiple devices to have their clock dividers
390pF
CLK– aligned to guarantee simultaneous input sampling. With the
SCHOTTKY divider enabled and the SYNC option used, the ADC clock divider
12169-042
DIODES:
HSMS2822 output phase can be adjusted after synchronization in increments
Figure 60. Transformer-Coupled Differential Clock (Up to 200 MHz) of input clock cycles using Register 0x16.
Drive the SYNC input using a single-ended CMOS type signal.
If not used, connect the SYNC pin to ground.
25Ω ADC
390pF 390pF
CLOCK
CLK+
Clock Duty Cycle
INPUT
390pF
Typical high speed ADCs use both clock edges to generate a
1nF CLK– variety of internal timing signals and, as a result, may be sensitive
SCHOTTKY to clock duty cycle. Commonly, a ±5% tolerance is required on the
12169-043
25Ω
DIODES:
HSMS2822 clock duty cycle to maintain dynamic performance characteristics.
Figure 61. Balun-Coupled Differential Clock (Up to 1240 MHz)
The AD9652 contains a clock DCS that retimes the nonsampling
If a low jitter clock source is not available, another option is to (falling) edge, providing an internal clock signal with a nominal
ac couple a differential PECL signal to the sample clock input 50% duty cycle. This allows the user to provide a wide range of
pins as shown in Figure 62. The AD9510, AD9511, AD9512, clock input duty cycles without affecting the performance of the
AD9513, AD9514, AD9515, AD9516-5, AD9517-1, AD9518-1, AD9652.
AD9520-5, AD9522-1, AD9523, AD9524, and ADCLK905/ Jitter on the rising edge of the input clock is still of paramount
ADCLK907/ADCLK925 clock drivers offer excellent jitter concern and is not reduced by the duty cycle stabilizer. The
performance. DCS control loop does not function for clock rates less than
80 MHz nominally. The loop has a time constant associated
0.1µF 0.1µF ADC
with it that must be considered when the clock rate changes
CLOCK CLK+ dynamically. A wait time of 1.5 µs to 5 µs is required after a
INPUT
AD95xx 100Ω
dynamic clock frequency increase or decrease before the DCS
PECL DRIVER
0.1µF 0.1µF loop is relocked to the input clock. During that time period, the
CLOCK CLK–
INPUT loop is not locked, the DCS loop is bypassed, and internal
12169-044
50kΩ 50kΩ 240Ω 240Ω

device timing is dependent on the duty cycle of the input clock
signal. In some cases, it may be appropriate to disable the duty
Figure 62. Differential PECL Sample Clock (Up to 1240 MHz)
Data Sheet AD9652
cycle stabilizer, for example, if a high quality RF clock is 1.0 2.5
AVDD3
AVDD_CLK
available to drive the AD9652 clock input and does not need 0.9
DRVDD/SPIVDD
adjustment in duty cycle correction. In most other applications, 0.8 AVDD 2.0
POWER
enabling the DCS circuit is recommended to maximize ac 0.7
performance.
CURRENT (A)
0.6 1.5
POWER (W)
Jitter Considerations 0.5
High speed, high resolution ADCs are sensitive to the quality 0.4 1.0
of the clock input. The degradation in SNR at a given input
0.3
frequency (fIN) due to jitter (tJ) can be calculated by
0.2 0.5
SNRHF = −10 log[(2π × fIN × tJRMS)2 + 10 ( − SNRLF /10) ] 0.1
In the equation, the rms aperture jitter represents the root- 0 0
12169-047
80 130 180 230 280
mean-square of all jitter sources, which includes the clock
SAMPLE RATE (MSPS)
input, the analog input signal, and the ADC aperture jitter
Figure 65. Power and Current vs. Sample Rate
specification. IF undersampling applications are particularly
sensitive to jitter, as shown in Figure 64. By asserting power-down (either through setting Register 0x08
80 or by asserting the PDWN pin high), the AD9652 is placed in
78 power-down mode. In this state, the ADC typically dissipates
less than 1 mW. During power-down, the output drivers are
76
placed in a high impedance state. Deasserting the PDWN pin
74
(forcing it low) returns the AD9652 to its normal operating
72 mode. Note that the level on PDWN is referenced to the digital
SNRFS (dB)
70 output driver supply (DRVDD) and cannot exceed that supply

68 voltage.
66 MEASURED Low power dissipation in power-down mode is achieved by
64
0.8ps shutting down the reference, reference buffer, biasing networks,
0.2ps
62
0.1ps and clock. Internal capacitors are discharged when entering
0.05ps
0.05ps power-down mode and then must be recharged when returning
60
to normal operation. As a result, wake-up time is related to the
12169-046
5 50 500
fIN (MHz) time spent in power-down mode, and shorter power-down
Figure 64. SNRFS vs. Input Frequency and Jitter cycles result in proportionally shorter wake-up times.
Treat the clock input as an analog signal in cases where aperture When using the SPI port interface, the user can place the ADC
jitter may affect the dynamic range of the AD9652. in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
Drive external clock sources and buffers from a clean ADC
faster wake-up times are required. See the AN-877 Application
output driver supply to avoid modulating the ADC clock with
Note, Interfacing to High Speed ADCs via SPI, for additional
noise. Low jitter, crystal controlled oscillators make the best
details.
clock sources. If the clock is generated from another type of
source (by gating, dividing, or another method), retime it by the INTERNAL BACKGROUND CALIBRATION
original clock at the last step. The AD9652 uses a background calibration to continually correct
Refer to the AN-501 Application Note, Aperture Uncertainty errors between internal analog circuits to maintain the high
and ADC System Performance, and the AN-756 Application level of noise performance over varying conditions. The calibration
Note, Sampled Systems and the Effects of Clock Phase Noise and correction digitally monitors the errors in the various analog
Jitter, for more information about jitter performance as it relates blocks, calculates the error, and applies corrections. The back-
to ADCs. ground correction is calculated every 3 × 233 samples; therefore,
when running at 310 MSPS, the update rate is about 83 seconds.
POWER DISSIPATION AND STANDBY MODE
Each calibration cycle is independent from previous calibrations to
As shown in Figure 65, the power dissipated by the AD9652 is improve tracking. There are no requirements on the input signal
proportional to its sample rate. The data in Figure 65 was taken for the background calibration.
using the same operating conditions as those used for the
The calibration occurs independently for each ADC path. The
Typical Performance Characteristics section.
background calibration continually operates but does not
update if the input signal is significantly out of range (beyond
the OTR) because this can cause errors in the calibration
calculation.
AD9652 Data Sheet
The calibration engine monitors any errors and resets the Although this is not recommended, in some instances such as
calibration cycle if the input signal exceeds the input range for when all the environmental, clocking, and input signals are very
1000 samples within a single calibration cycle. stable, the calibration can be paused. Pausing the background
At startup, when the AD9652 is first powered and a valid clock calibration causes a slight degradation in performance, but can
is applied, a fast start-up background calibration is performed be accomplished by writing 0x1 to Register 0x4FB, Bit 0. To re-
and converges 64 times faster than the normal calibration cycle. enable the background calibration, write 0x0 to Register 0x4FB,
At 310 MSPS, the fast start-up calibration updates after 1.3 seconds. Bit 0. Note: Register 0x4FB has reserved bits that must be
The fast start-up calibration allows the AD9652 to be used preserved when accessing that and similar registers.
sooner than waiting for a full calibration cycle and typically DIGITAL OUTPUTS
degrades SNR performance by less than 0.5 dB. This degradation The AD9652 output drivers are for standard ANSI LVDS, but
lasts until a full calibration cycle completes. optionally the drive current can be reduced using Register 0x15.
In cases where configuration of the AD9652 changes and a The reduced drive current for the LVDS outputs potentially
recalibration is needed, a fast start-up calibration can be reduce the digitally induced noise.
initiated by an SPI register write or by asserting and As detailed in the AN-877 Application Note, Interfacing to High
deasserting the PDWN pin. Speed ADCs via SPI, the data format can be selected for offset
To initiate using the SPI register, use Register 0x08[1:0]. To start binary, twos complement, or gray code when using the SPI
a new fast calibration, put either or both ADC channels in control.
standby and then return them to normal operation mode by The AD9652 has a flexible three-state ability for the digital
writing 0x2 and then 0x0 to Register 0x08[1:0]. After returning output pins. The three-state mode is enabled when the device is
to normal operation mode, the fast calibration is initiated one set for power-down mode.
time followed by the normal, full calibration cycle. In addition
to standby, this is also the case for power-down. Writing a 0x1 Timing
followed by a 0x0 initiates a fast calibration. Alternatively, a fast The AD9652 provides latched data with a pipeline delay of
start-up calibration can be initiated by writing 0x0C and then 26 input sample clock cycles. Data outputs are available one
0x08 to Register 0x4FB. propagation delay (tPD) after the rising edge of the clock signal.
The PDWN pin can be configured to put the device in power- Minimize the length of the output data lines and the corresponding
down or standby mode based on the setting in Register 0x08[1:0]. loads to reduce transients within the AD9652. These transients
Transitioning from either power-down or standby into normal can degrade converter dynamic performance.
mode causes a fast calibration to be initiated. Configuration The lowest typical conversion rate of the AD9652 is 80 MSPS.
changes that require a new calibration include, but are not At clock rates below 80 MSPS, dynamic performance may
limited to, changes of setting for VREF, dither enable/disable, degrade.
clock input changes, and DCS state changes.
Data Clock Output
There are various advanced configuration options associated
The AD9652 also provides a data clock output (DCO) intended
with the background calibration for applications that require
for capturing the data in an external register. Figure 2 shows a
special treatment. The options include an optional recovery
timing diagram of the AD9652 output modes. The DCO relative to
mode for standby and a pausing background calibration.
the data output can be adjusted using Register 0x17. There are 32
If standby is used in an application, by default, the AD9652 delay settings with approximately 81 ps per step. Data is output
keeps the current corrections, but initiates a new fast calibration in a DDR format and is aligned to the rising and falling edges of
when returning to normal operation mode. For standby, if the clock derived from DCO±.
conditions have not significantly changed, the AD9652 can be
configured to retain the last correction coefficients by writing ADC OVERRANGE
0x00 to Register 0x4FA before entering the standby mode. This The ADC overrange (OR) indicator is asserted when an
returns the device to the same operation as when it entered overrange is detected on the input of the ADC. The overrange
standby, retaining previous calibration values in standby mode condition is determined at the output of the ADC pipeline and,
and continuing the normal calibration cycle when returned to therefore, is subject to a latency of 26 ADC clocks. An
normal operation mode. overrange at the input is indicated by this bit, 26 clock cycles
after it occurs.
Data Sheet AD9652
Table 13. Output Data Format
Differential Input Voltage (V):
(VIN+x) – (VIN–x)
Input Span = 2.5 V p-p (V) Offset Binary Output Mode Twos Complement Mode (Default) OR± Pin Logic Level
<–1.25 00 0000 0000 0000 10 0000 0000 0000 1
–1.25 00 0000 0000 0000 10 0000 0000 0000 0
0 10 0000 0000 0000 00 0000 0000 0000 0
+1.25 11 1111 1111 1111 01 1111 1111 1111 0
>+1.25 11 1111 1111 1111 01 1111 1111 1111 1
AD9652 Data Sheet
FAST THRESHOLD DETECTION (FDA/FDB)

In receiver applications, it is desirable to have a mechanism to The selected threshold register is compared with the signal
reliably determine when the converter is about to be clipped. The magnitude at the output of the ADC. The fast upper threshold
standard overflow indicator on the OR± pins provide delayed detection has a latency of seven clock cycles. The approximate
information, which is synchronized with the output data. The upper threshold is a 4-bit value defined by
delayed indicator is of limited value in preventing clipping in this Upper Threshold (% Full Scale) =
case. Therefore, it is helpful to have a programmable threshold ((Register 0x47 value)/8) × 100%
below full scale that allows time to reduce external gain before the
clip occurs. In addition, because input signals can have significant The FD indicators are not cleared until the signal drops below
slew rates, latency of this function is of concern. the lower threshold for the programmed dwell time. The lower
threshold is programmed in the fast detect lower threshold
Using the SPI port, the user can provide a threshold above registers, Register 0x49 and Register 0x4A. The fast detect lower
which the fast detect (FD) output is active. Bit 0 of Register 0x45 threshold register is a 15-bit register that is compared with the
enables the FD feature. Register 0x47 to Register 0x4C allow the signal magnitude at the output of the ADC. This comparison is
user to set the threshold levels and timing. As long as the signal subject to the ADC pipeline latency but is accurate in terms of
is below the selected threshold, the FD output remains low. In converter resolution. The lower threshold is defined by
this mode, the magnitude of the data is considered in the calcu-
lation of the condition, but the sign of the data (either positive Lower Threshold (% Full Scale) =
or negative) is not considered. The threshold detection responds ((Register 0x49/Register 0x4A value)/32767) × 100%
identically to positive and negative signals outside the desired For example, to set an upper threshold of 50% full scale, write
range (magnitude). 0x04 to Register 0x47, and to set a lower threshold of 40% full
The fast detect indicators, FDA for Channel A and FDB for scale, write 0x3333 to Register 0x49 and Register 0x4A.
Channel B, are asserted when the input magnitude exceeds the The dwell time can be programmed from 1 sample clock cycle
value programmed in the fast detect upper threshold register, to 65,535 sample clock cycles by placing the desired value in the
Register 0x47. fast detect dwell time registers, Register 0x4B and Register 0x4C
(see Figure 66).
UPPER THRESHOLD
DWELL TIME
TIMER RESET BY
RISE ABOVE
LOWER LOWER THRESHOLD
THRESHOLD
MIDSCALE
DWELL TIME TIMER COMPLETES BEFORE

12169-048
SIGNAL RISES ABOVE

FDA OR FDB LOWER THRESHOLD
Figure 66. Threshold Settings for FDA and FDB Signals
Data Sheet AD9652
SERIAL PORT INTERFACE

The AD9652 serial port interface (SPI) allows the user to In addition to word length, the instruction phase determines
configure the converter for specific functions or operations whether the serial frame is a read or write operation, allowing
through a structured register space provided inside the ADC. the serial port to be used both to program the chip and to read
The SPI gives the user added flexibility and customization, the contents of the on-chip memory. If the instruction is a readback
depending on the application. Addresses are accessed via the operation, performing a readback causes the serial data input/
serial port and can be written to or read from via the port. output (SDIO/DCS) pin to change direction from an input to an
Memory is organized into bytes that can be further divided into output at the appropriate point in the serial frame.
fields. These fields are documented in the Memory Map Data can be sent in MSB first mode or in LSB first mode. MSB
section. For detailed operational information, see the AN-877 first is the default on power-up and can be changed via the SPI
Application Note, Interfacing to High Speed ADCs via SPI. port configuration register. For more information about this
CONFIGURATION USING THE SPI and other features, see the AN-877 Application Note.
Three pins define the SPI of this ADC: the SCLK pin, the SDIO HARDWARE INTERFACE
pin, and the CSB pin (see Table 14). The SCLK (serial clock) pin The pins described in Table 14 comprise the physical interface
synchronizes the read and write data presented from/to the ADC. between the user programming device and the serial port of the
The SDIO (serial data input/output) pin is a dual-purpose pin AD9652. The SCLK pin and the CSB pin function as inputs
that allows data to be sent and read from the internal ADC when using the SPI interface. The SDIO pin is bidirectional,
memory map registers. The CSB (chip select bar) pin is an functioning as an input during write phases and as an output
active low control that enables or disables the read and write cycles. during readback.
Table 14. Serial Port Interface Pins The SPI interface is flexible enough to be controlled by either
Pin Function field-programmable grid arrays (FPGAs) or microcontrollers.
SCLK Serial clock. The serial shift clock input, which synchronizes One method for SPI configuration is described in detail in the
serial interface reads and writes. AN-812 Application Note, Microcontroller-Based Serial Port
SDIO Serial data input/output. A dual-purpose pin that Interface (SPI) Boot Circuit.
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the The SPI port must not be active during periods when the full
timing frame. dynamic performance of the converter is required. Because the
CSB Chip select bar. An active low control that gates the read SCLK signal, the CSB signal, and the SDIO signal are typically
and write cycles. Must be pulled to logic high during asynchronous to the ADC clock, noise from these signals can
power up.
degrade converter performance. If the on-board SPI bus is used
for other devices, it may be necessary to provide buffers between
The falling edge of CSB, in conjunction with the rising edge of this bus and the AD9652 to prevent these signals from transi-
SCLK, determines the start of the framing. An example of the tioning at the converter inputs during critical sampling periods.
serial timing and its definitions can be found in Table 5 and
Figure 4. CONFIGURATION WITHOUT THE SPI
Other modes involving the CSB pin are available. The CSB pin In applications that do not interface to the SPI control registers,
can be held low indefinitely, which permanently enables the the SDIO pin and the SCLK pin serve as standalone CMOS-
device; this is called streaming. The CSB pin can stall high compatible control pins. When the device is powered up, it is
between bytes to allow for additional external timing. When assumed that the user intends to use the pins as static control
CSB is tied high, SPI functions are placed in a high impedance lines for the DCS and output data format feature control. In this
mode. mode, connect CSB to AVDD, which disables the serial port
interface.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined Table 15. Mode Selection
by the W0 and the W1 bits. Pin External Voltage Configuration
All data is composed of 8-bit words. The first bit of each SDIO AVDD (default) DCS enabled
individual byte of serial data indicates whether a read or write AGND DCS disabled
command is issued. This allows the serial data input/output SCLK AVDD Twos complement enabled
(SDIO) pin to change direction from an input to an output. AGND (default) Offset binary enabled
AD9652 Data Sheet
SPI ACCESSIBLE FEATURES
Table 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note.
Table 16. Features Accessible Using the SPI

Feature Name Description
Power Modes Allows the user to set either power-down mode or standby mode
Clock Allows the user to access the DCS via the SPI
Offset Allows the user to digitally adjust the converter offset
Test I/O Allows the user to set test modes to have known data on output bits
Output Mode Allows the user to set up outputs
Output Phase Allows the user to set the output clock polarity
Output Delay Allows the user to vary the delay of the clock derived from DCO±
VREF Allows the user to set the reference voltage
Data Sheet AD9652
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE Logic Levels
Each row in the memory map register table has eight bit An explanation of logic level terminology follows:
locations. The memory map is roughly divided into three • “Bit is set” is synonymous with “bit is set to Logic 1” or
sections: the chip configuration registers (Address 0x00 to “writing Logic 1 for the bit.”
Address 0x02); the channel index and transfer registers • “Clear a bit” is synonymous with “bit is set to Logic 0” or
(Address 0x05 and Address 0xFF); and the ADC functions “writing Logic 0 for the bit.”
registers, including setup, control, and test (Address 0x08 to
Address 0x4FB). Transfer Register Map
The memory map register table (see Table 17) documents the The 0x08, 0x0D, 0x10, 0x14, 0x30, and 0x45 to 0x4C registers
default hexadecimal value for each hexadecimal address shown. are shadowed. Writes to these addresses do not affect device
The column with the heading Bit 7 (MSB) is the start of the operation until a transfer command is issued by writing 0x01 to
default hexadecimal value given. For example, Address 0x09, Address 0xFF, which sets the transfer bit. This allows these registers
the global clock register, has a hexadecimal default value of to be updated internally and simultaneously when the transfer bit
0x01. This means that the LSB or Bit 0 = 1, and the remaining is set. The internal update occurs when the transfer bit is set,
bits are 0s. This setting is the default output format value, which and then the bit autoclears.
is twos complement. For more information on the functions Channel Specific Registers
controlled by Register 0x00 to Register 0x17, see the AN-877
Some channel setup functions, such as the signal monitor
Application Note. This application note also details the
thresholds, can be programmed to a different value for each
functions controlled by all remaining registers.
channel. In these cases, channel address locations are internally
Open and Reserved Locations duplicated for each channel. These registers and bits are designated
All address and bit locations that are not included in Table 17 in Table 17 as local. These local registers and bits can be accessed
are not currently supported for this device. Unused bits of a by setting the appropriate Channel A or Channel B bits in
valid address location must be written with 0s, unless otherwise Register 0x05. If both bits are set, the subsequent write affects
noted. Writing to these locations is required only when part of the registers of both channels. In a read cycle, only Channel A
an address location is open (for example, Address 0x18). If the or Channel B are set to read one of the two registers. If both bits
entire address location is open/unused/undocumented (for are set during an SPI read cycle, the device returns the value for
example, Address 0x13), this address location must not be written. Channel A. Registers and bits designated as global in Table 17
affect the entire device and the channel features for which
Default Values
independent settings are not allowed. The settings in Register 0x05
After the AD9652 is reset, critical registers are loaded with do not affect the global registers and bits.
default values. The default values for the registers are given in
the memory map register table, Table 17.
AD9652 Data Sheet
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17. Memory Map Registers

Default Default
Addr Register Bit 7 Bit 0 Value Notes/
(Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments
Chip Configuration Registers
0x00 SPI port 0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles
config- are mirrored
uration so that LSB
(global) 1 first mode
or MSB first
mode
registers
correctly,
regardless
of shift
mode
0x01 Chip ID 8-Bit Chip ID[7:0], (AD9652 = 0xC1) (default) 0xC1 Read only
(global)
0x02 Chip grade Speed grade ID, 0x00 Speed
(global) 0x00: default grade ID
differ-
entiates
devices;
read only
Channel Index and Transfer Registers
0x05 Channel Channel B Channel A 0x03 Bits are
index (default) (default) set to
(global) determine
which
device on
the chip
receives
the next
write
command;
applies to
local
registers
only
0xFF Transfer Transfer 0x00 Synchro-
(global) nously
transfers
data from
the master
shift register
to the slave
ADC Functions
0x08 Power Reserved, External Internal power-down 0x80 Controls
modes set to 1 power- mode (local) power-
(local) down pin 00 = normal operation down
function 01 = full power-down options
(local) 10 = standby
0= 11 = reserved
power-
down
1=
standby
0x09 Global clock Enable 0x01
(global) DCS
(default)
Data Sheet AD9652
Default Default
0x0B Clock divide Clock divide ratio 0x00
(global) 000 = divide by 1
001 = divide by 2
010 = reserved, do not use
011 = divide by 4
100 = divide by 8
0x0D Test mode Reset PN23 Reset Output test mode 0x00 When this
(local) long gen PN9 0000 = off (default) register is
PN23: short gen 0001 = midscale short set, the test
1 + x17 + PN9: 0010 = positive FS data is
x22 1 + x3 + x8 0011 = negative FS placed on
0100 = alternating checkerboard the output
0101 = PN23 long sequence pins (D0±
0110 = PN9 short sequence to D15±) in
0111 = one/zero word toggle place of
normal data
0x0F Common- Enable 0x00
mode servo common-
(global) mode
servo
0x10 Offset adjust Offset adjust in LSBs from +127 (0111 1111) to −128 (1000 0000) 0x00
(local) (twos complement format)
0x14 Output Output format 0x00 Configures
mode (local) 00 = offset binary the outputs
(default) and the
01 = twos complement format of
10 = gray code the data
11 = reserved
0x15 Output LVDS output drive current adjust 0x00
LVDS 000 = 3.72 mA (ANSI-LVDS,
control default)
(global) 001 = 3.50 mA
010 = 3.30 mA
011 = 2.96 mA
100 = 2.82 mA
101 = 2.57 mA
110 = 2.27 mA
111 = 2.00 mA (reduced swing
LVDS)
0x16 Clock phase Input clock divider phase adjust 0x00
adjust 000 = no delay
(global) 001 = 1 input clock cycle
010 = 2 input clock cycle
0x17 DCO± DCO± clock delay 0x00
output delay (Delay = (2500 ps × register value/31))
(global) 00000 = 0 ps
00001 = 81 ps
00010 = 161 ps
…
11110 = 2419 ps
11111 = 2500 ps
0x18 Input span Reserved, Reserved, VREF select 0xC0
select set to 1 set to 1 000 = 1.25 V (2.5 V p-p input), default
(global) 001 = 1.125 V (2.25 V p-p input)
010 = 1.20 V (2.4 V p-p input)
011 = 1.25 V (2.5 V p-p input)
100 = do not use
101 = 1.0 V (2.0 V p-p input)
0x30 Dither (local) Dither 0x00
enable
AD9652 Data Sheet
Default Default
0x45 Fast detect Enable 0x00
(FD) control fast
(local) detect
output
0x47 FD upper Fast Detect Upper Threshold[3:0] 0x08
threshold Valid programming range = 0x1 to 0x8
(local) Threshold = midscale ± (register value) × (1/8) ×
(full scale)
0x49 FD lower Fast Detect Lower Threshold[7:0] 0x00
threshold
(local)
0x4A FD lower Fast Detect Lower Threshold[14:8] 0x02
threshold
(local)
0x4B FD dwell Fast Detect Dwell Time[7:0] 0x00
time (local)
0x4C FD dwell Fast Detect Dwell Time[15:8] 0x08
time (local)
0x100 SYNC Clock Clock Master 0x00
control divider divider SYNC
(global) next SYNC SYNC buffer
only enable enable
0x212 Dither gain 0b0000: 100% dither applied Reserved, Reserved, Reserved, Reserved, 0x08
(global) 0b0001: 99.6% dither applied set to 0 set to 0 set to 0 set to 0
0b0010: 99.2% dither applied
0b0111: 75% dither applied
0b1000: 50% dither applied
0x22A Input 0: fIN in 1st Nyquist 0x00
frequency 1: fIN in 2nd Nyquist
settings 2: fIN in 3rd Nyquist or
(global) higher
0x4FA Calibration Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Power down/standby 0x03
power- set to 0 set to 0 set to 0 set to 0 set to 0 set to 0 initial calibration
down action:
config- 0b00: use previous
uration calibration correction
(global) 0b11: initiate a fast
calibration
0x4FB Calibration Reserved, Reserved, Reserved, Reserved, Reserved, Reset Reserved, Pause 0x08
power-down set to 0 set to 0 set to 0 set to 0 set to 1 back- set to 0 back-
configura- ground ground
tion (global) calibration, calibration
set high
then low
1
Set the channel index register at Address 0x05 to 0x03 (default) when writing to Address 0x00.
Data Sheet AD9652
APPLICATIONS INFORMATION
DESIGN GUIDELINES VCM
Before starting system level design and layout of the AD9652, it The VCM pin must be decoupled to ground with a 0.1 μF
is recommended that the designer become familiar with these capacitor, as shown in Figure 54. For optimal channel-to-channel
guidelines, which describes the special circuit connections and isolation, a 33 Ω resistor must be included between the AD9652
layout requirements needed for certain pins. VCM pin and the Channel A analog input network connection,
as well as between the AD9652 VCM pin and the Channel B
Power and Ground Recommendations
analog input network connection.
When connecting power to the AD9652, it is recommended that
three separate power supplies be used. AVDD3 requires a 3.3 V RBIAS
supply, AVDD_CLK and AVDD require a 1.8 V supply, and The AD9652 requires that a 10 kΩ resistor be placed between
DRVDD requires a 1.8 V supply. SPIVDD is typically connected the RBIAS pin and ground. This resistor sets the master current
to the same supply as DRVDD, but can be connected to a separate reference of the ADC core and must have at least a 1% tolerance.
supply between 1.8 V and 3.3 V to ease the interface to the logic Reference Decoupling
device that connects to the SPI pins (CLK, SDIO, and CSB).
Decouple the VREF pin externally to ground with a low ESR,
The AVDD3 supply must be supplied from a clean 3.3 V power 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic
source. Decoupling must be a combination of PCB plane capacitor.
capacitance and decoupling capacitors to cover both high and low
SPI Port
frequency noise sources. Typical capacitors of 0.1 μF and 1 μF
near the AD9652 AVDD3 pins are advised. The SPI port must not be active during periods when the full
dynamic performance of the converter is required. Because the
The AVDD and AVDD_CLK supply connection must be
SCLK, CSB, and SDIO signals are typically asynchronous to the
powered up simultaneously to achieve proper on-chip biasing;
ADC clock, noise from these signals can degrade converter
therefore, it is recommended to connect the two supply voltages
performance. If the on-board SPI bus is used for other devices,
to a single source. Similar to the AVDD3 supply, decoupling must
it may be necessary to provide buffers between this bus and the
be a combination of PCB plane capacitance and decoupling
AD9652 to keep these signals from transitioning at the converter
capacitors to cover both high and low frequency noise sources.
input pins during critical sampling periods.
Typical capacitors of 0.1 μF and 1 μF near the AD9652 AVDD
and AVDD_CLK pins is advised.
The DRVDD and SPIVDD supply connection must also have
decoupling but these can be placed slightly further away from
the AD9652. DRVDD and SPIVDD can be tied together for
applications that can use a 1.8 V SPI interface logic. Optionally,
SPIVDD can be driven with a supply of up to 3.3 V to support
higher voltage logic interfaces.
Multiple large area PCB ground planes are recommended and
provide many benefits. Low impedance power and ground
planes are needed to maintain performance. Stacking power and
ground planes in the PCB provides high frequency decoupling.
Ground planes and thermal vias help dissipate heat generated
by the device. With proper decoupling and smart partitioning
of the PCB analog, digital, and clock sections, optimum
performance is easily achieved.
AD9652 Data Sheet
OUTLINE DIMENSIONS
10.10
10.00 SQ A1 BALL
A1 BALL 9.90 CORNER
CORNER 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
8.80 D
BSC SQ E
F
G
0.80 H
BSC J
K
L
M
TOP VIEW 0.60 REF BOTTOM VIEW
1.11
DETAIL A DETAIL A 1.01
1.40
0.33 NOM 0.91
1.34
0.28 MIN
1.19
*0.50 COPLANARITY
SEATING 0.45 0.12
PLANE 0.40
BALL DIAMETER
11-18-2011-A
*COMPLIANT WITH JEDEC STANDARDS MO-275-EEAA-1
WITH THE EXCEPTION TO BALL DIAMETER.
Figure 67. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-144-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
AD9652BBCZ-310 −40°C to +85°C 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-144-6
AD9652BBCZRL7-310 −40°C to +85°C 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-144-6
1
Z = RoHS Compliant Part.
©2014–2018 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
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Excellent IF sampling performance

Figure 2. LVDS Data Output Timing

Figure 3. SYNC Timing Inputs

SCLK DON’T CARE DON’T CARE

Figure 4. Serial Port Interface Timing Diagram

ABSOLUTE MAXIMUM RATINGS

Stresses at or above those listed under Absolute Maximum

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 5. Pin Configuration

Table 8. Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS

–140 12169-005 –140

0 20 40 60 80 100 120 140

0 20 40 60 80 100 120 140

0 50 100 150 0 50 100 150

–60 MAGNITUDE (dB) –60

72 SNRFS (dB), –40°C 100 72 SNRFS (dB), –40°C 100

70 SFDR (dBFS), –40°C 70 SFDR (dBFS), –40°C

–80 –60 –40 –20 0 –80 –60 –40 –20 0

72 SNRFS (dB), –40°C 100 72 SNRFS (dB), –40°C 100

74 SNRFS 106 74 106

–20 100 –20 100

–20 100 –20 100

0 25 50 75 100 125 150

SFDR (VREF = 1V)

SNRFS (VREF = 1.25V)

SNRFS (VREF = 1V) SNRFS (VREF = 1V)

DATAOUT– DATAOUT+ SYNC 0.9V

PN GEN DITHER ENABLE Differential Input Configurations

Register 0x212[7:4] Setting Gain Ratio Gain (%) 5pF

0b0010 254/256 × max 99.2 15pF

An alternative to using a transformer-coupled input at frequencies

Figure 56. Differential Double Balun Input Configuration

Table 12. VREF Configuration Options

A stable and accurate voltage reference is built into the AD9652.

VREF ERROR (%)

A stable and accurate programmable reference is built into the

AD9652 slightly lower than CLK+ to prevent spurious clocking (this is

Figure 59. Simplified Equivalent Clock Input Circuit

between 125 MHz and 1240 MHz, and the RF transformer is

50kΩ 50kΩ 240Ω 240Ω

70 output driver supply (DRVDD) and cannot exceed that supply

FAST THRESHOLD DETECTION (FDA/FDB)

DWELL TIME TIMER COMPLETES BEFORE

SIGNAL RISES ABOVE

Figure 66. Threshold Settings for FDA and FDB Signals

SERIAL PORT INTERFACE

Table 16. Features Accessible Using the SPI

Table 17. Memory Map Registers

TOP VIEW 0.60 REF BOTTOM VIEW

©2014–2018 Analog Devices, Inc. All rights reserved. Trademarks and

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