Microprocessor Systems

Gökhan İnce
Berk Üstündağ
 Topics
 Computer Structure
 Memory Systems
 Computer Structure
 A computer is a programmable machine
designed to automatically carry out a sequence
of arithmetic or logical operations.

 Fundamental features of a computer

 Memory capability
 Computation capability
 Decision capability
 Input/Output capability
 What is a computer ?
 It is programmable – where does the code reside ?
 Memory

 Executes or processes the instructions of the program or code

 Arithmetic and logic processor

 How does the code or data get in to the computer?

 How does it output the result?

 Input/Output device(s)
Computer Organization

System bus: Address Bus, Data Bus, Control/Status

Bus
Control
unit System bus

Arithmetic
logic Disk
unit
memory
Registers Input/output
program data
unit Monitor
storage storage

Microprocessor
Keyboard
What is a computer ?

System Bus
(Common or Separate):
Address bus,
Data bus,
Control bus 6
 Memory
 Memory stores information such as instructions and data in
binary format (0’s and 1’s). It provides this information to the
microprocessor whenever it is needed.

 Usually, there is a memory “sub-system” in a microprocessor-

based system. This sub-system includes:
 The registers inside the microprocessor

 Read Only Memory (ROM)

 used to store information that does not change.
 Random Access Memory (RAM) (also known as Read/Write
Memory)
 used to store information supplied by the user such as programs
and data.
 Registers
 A flip flop is a 1-bit memory device. D Q(t+1)
 A register is a collection of flip flops 0 0
that are clocked as a unit.
1 1
 Combinational vs. sequential circuitry
Input Input Input Input
Bit “3” Bit “2” Bit “1” Bit “0”

D Q D Q D Q D Q

> CK > CK > CK > CK

Clock

Output Output Output Output

Bit “3” Bit “2” Bit “1” Bit “0”
 Registers
 Register is a group of n-flip-flops capable of
storing n-bits of information
 Registers are accessed very fast within the CPU
 Different CPUs have different set and size of
registers
 General-purpose registers are used to store
data during the CPU execution process
 Special-purpose registers control or monitor
various aspects of the microprocessor's function
(MAR, IR...).
 CPU Structure
 Memory Address Register (MAR) either stores
the memory address from which data will be
fetched to the CPU or the address to which data
will be sent and stored.

 The Memory Data Register (MDR) contains the

data to be stored in the computer storage (e.g.
RAM), or the data after a fetch from the computer
storage.

 Accumulator (ACC) stores intermediate arithmetic

and logic results.
 Arithmetic and Logic Unit (ALU)
 Arithmetic and Logic Unit (ALU) performs
arithmetic and logical operations
 The ALU receives data from main memory
and/or the register file, performs a
computation, and, if necessary, writes the
result back to main memory or registers.
 Control Unit
 Control Unit (CU) manages the computer operation
within and outside the CPU

 Sequencing and execution cycles of commands

 Register operations
 Bus regulation
 Interrupt handling
 System status
 Memory management
 Basic Computer Connections

Control Bus

Data Bus
Data
Register
Control
Address Bus I/O
Address
Register
CPU

Memory

13
 Basic Computer Architecture
Instruction

Memory Control

Data

Data Data
Control
Input/output Processing
Unit
Unit
Control/Status

Microprocessor
Clock
 Stored Program Procedure
 The Clock: The stored program processor is a large
synchronous sequential network (logic circuit) that requires a
clock signal to synchronize all its elements.
 The signal from the clock is a periodic pulse waveform.

 The Data Processing Unit: The principal part of the data

processing unit is a combinational logic circuit, called the ALU,
that manipulates binary numbers.
 Practical ALUs can perform dozens of different operations,
but only one at time. Usually ALUs can add, subtract,
complement bits, shift binary values and so on.
 Registers hold the data numbers operated or produced.

Arithmetic Logic
Registers
Unit ALU
 Stored Program Procedure
 The control unit is a synchronous sequential logic
circuit that sends control signals to the data
processing unit, memory and other parts of the system.
 The signals from the control unit tells the data processing
unit to manipulate data according to the algorithm built
into the sequential logic circuit.
 The control unit is instruction controlled; therefore it
can do more than one algorithm based on its design.
Typical control units recognize several hundred different
instruction codes.
 The Memory: The memory holds instruction code
numbers and data numbers
 The I/O Unit: The input/output unit includes any
hardware that allows data transfer between the CPU
and the real world.
 Von Neumann Architecture
Instruction and data are in the same memory
Memory

Control&Address
Address Instruction
Data
CPU
Input
Data
Control
I/O Processing
Unit
Unit
Output

Control/status
Clock
 Harvard Architecture
There are two memories: Instruction and data
Data Instruction
Memory Memory

Control&Address
Address Instruction
Data
CPU
Input
Data
Control
I/O Processing
Unit
Unit
Output

Control/status
Clock
 Operation of Computer
 Example: The X and Y numbers will be written on
memory addresses $3000 and $3001. The sum of
X and Y will be stored on address $3002
Memory Address Instruction
$1001 Load X to ACC (accumulator)
$1002 Store contents of ACC to address $3000
$1003 Load Y to ACC
$1004 Store contents of ACC to address $3001
$1005 Add contents of $3000 to ACC
$1006 Store contents of ACC to address $3002

$3000 X
$3001 Y Results after execution
$3002 X+Y
 Instruction Cycle
Fetch
Instruction

Decode

Fetch Cycle
Fetch-Decode-Execute Instruction

Read
Operand

Execute

Execution Cycle
Store
Results

Next
Instruction

 Two-cycle process because both instructions and data are in memory

 Fetch
 Decode or find instruction, load from memory into register and signal ALU
 Execute
 Performs operation that instruction requires
 Move/transform data
20
 Instruction Formats
Memory

 Instructions are stored in the 0 1 0 1 1 1 0 0

memory 1 1 1 0 0 0 0 1
 They are executed in a
sequence 1 0 1 0 1 0 1 0

 They instruct the computer

what to do
 The computer fetches the next
instruction and decodes it (See 0 1 0 1 1 0 0 1
Instruction Cycle). 1 1 1 0 0 1 0 0
 Each CPU has different set of
instructions 1 0 0 0 1 1 0 1

 Each CPU has different

template of instructions 1 0 1 0 1 0 1 0

8 bit
word
 Instruction Templates
 3+1 Address instruction template (Example: ADD X,Y,Z,N)

Opcode 1.Operand 2.Operand Result Address of next

address address address instruction
 3 Address instruction template (Example: ADD X,Y,Z)
Long instructions can take up
Opcode 1.Operand 2.Operand Result multiple words in memory
address address address
Example: 8-bit words in
memory, instruction template
 2 Address instruction template (Example: ADD X,Y)
can be 40bits, takes up 5
words in memory
Opcode 1.Operand 2.Operand
address address

 1 Address instruction template (Example: ADD A,X)

Opcode Register Operand 0, 1, and 2 address

address instructions are commonly
used in modern computers
 0 Address instruction template (Example: PSH A, PUL A)

Opcode Register
 Topics
 Computer Structure
 Memory Systems
 Memory
 The memory holds instruction code numbers
and data numbers
 Non-volatile memory
 Read only memory (ROM)
 Programmable read-only memory (PROM)
 Erasable programmable ROM (EPROM)
 Volatile memory
 Static random-access memory (SRAM)
 Dynamic random-access memory (DRAM)
Memory Types
 Non-volatile Memory
 Read-only memory (ROM) can only be read
but not written by the processor

 Mask-programmed read-only memory (MROM):

programmed when being manufactured

 Programmable read-only memory (PROM): the

memory chip can be programmed by the end
user
 Non-volatile Memory
 Erasable programmable ROM (EPROM)
 electrically programmable many times
 erased by ultraviolet light (through a window)
 erasable in bulk (whole chip in one erasure operation)
 Electrically erasable programmable ROM
(EEPROM)
 electrically programmable many times
 electrically erasable many times
 can be erased one location, one row, or whole chip in
one operation
 Flash memory
 electrically programmable many times
 electrically erasable many times
 can only be erased in bulk
 Volatile Memory
 DRAM: Dynamic Random Access Memory
Fast, dense (only 1 transistor/bit), works like charge storage, refreshed
periodically, read/write, cheap
row/column
store refresh refresh refresh
Vc

Vcc
HIGH

bit LOW 0
time

 SRAM: Static Random Access Memory

More power consumption than DRAM, each bit is stored in a flip-flop,
more expensive, read/write, faster Write Read

Small amounts are often used in cache

D Q
In Out
memory for high-speed memory access
EN EN
 Memory Units
 Each entry in a memory unit is called a word
 Each word is composed of M bits (width)
 Size of a RAM is the number of words N=2k
 A matrix of size N xM M

 N: number of rows (number of words) bit

 M: number of columns (number of bits)
N
word

 Common widths: Byte (8 bits), Short (16 bits), Int (32 bits)
CPU-Memory Connection
Data Bus (M)

0 0000111
Address Bus (k) 1 0001000
0 0010001
1 0010011
Decoder 2kxM 1 1110000
CPU 0 0001111
1 1000011
Adr.Dec.
CE
1 0011001
RD OE :
WR WE
Control Bus
:
Memory
 CPU-Memory Connection
Data Bus
1
1
0
0
1
0
0
1

0 0000111
Address Bus 1 0001000
0 0010001
1 0010011
Decoder 1 1110000
CPU 0 0001111
1 1000011
Adr.Dec.
CE
1 0011001
RD OE
WR WE :
Control Bus
Read instruction Memory :
 62C256 SRAM: Pin layout

62C256
1- 62C→CMOS SRAM: 𝑊𝐸 , 𝑂𝐸 , 𝐶𝐸

2- 62C→I/O0…I/O7

3- x256→ M=256kbit=256x1024 bit

Since 62C refers 8 bits I/O,

Address bus size= log2 (256x1024/8)=8+10-3=15

Address lines→ A0..A14

62C256 SRAM: Read Cycle
62C256 SRAM: Internal Block Diagram
62C256 SRAM: Write Cycle
 62C128 SRAM: Pin layout

1- 62C→CMOS SRAM: 𝑊𝐸 , 𝑂𝐸 , 𝐶𝐸

2- 62C→I/O0…I/O7

3- x128→ M=128kbit=128x1024=217bits

Since 62C refers 8 bits I/O,

Address bus size= log2 (217/23)=17-3=14

Address lines→ A0..A13

 55ns

AS6C4008-55PCN SRAM: Pin layout

AS5C4008
1- AS6C→CMOS SRAM: 𝑊𝐸 , 𝑂𝐸 , 𝐶𝐸 SRAM

2- Cxx8→I/O0…I/O7

3- C4008→ Memory=Mbit=4x1024x1024=222bits

Since 6Cxxx8 refers to 8 bits I/O,

Address bus size= log2 (222/23)=22-3=19

Address lines→ A0..A18

EPROM

ROM Device:
 120ns

27C64-12 IP EPROM: Pin layout

1- 27C→CMOS EPROM: 𝑃𝐺𝑀 , 𝑂𝐸 , 𝐶𝐸

2- 27C→O0…O7

3- C54→ Memory=64kbit=64x1024=216bits

Since 27C refers to 8 bits Output,

Address bus size= log2 (216/23)=16-3=13

Address lines→ A0..A12

27C64-12 IP EPROM: READ CYCLE
EPROM Memory components
 28C64 EEPROM: Pin layout

1- 28C→CMOS EEPROM: 𝑊𝐸 , 𝑂𝐸 , 𝐶𝐸

2- 28C→I/O0…I/O7

3- x64→ M=64kbit=64x1024 bit

Since 28C refers 8 bits I/O,

Address bus size= log2 (64x1024/8)=6+10-3=13

Address lines→ A0..A12

28C64 EEPROM: READ Waveform
28C64 EEPROM: Write Waveforms
28C64 EEPROM: Page write
 24C256 EEPROM: Pin layout

1- 24C→CMOS Serial EEPROM x8bit

2- 24C→SCL, SDA, A0, A1, A2, WP

3- x256→ M=256kbit=256x1024 bit

Since 24C refers SCL: Serial Clock and SDA: Serial Data with respect I2C standard,

Internal address size= log2 (256x1024/8)=8+10-3=15

Address bits→ A0..A14

24C256 EEPROM Block Diagram
I2C Serial communication
I2C Byte Write & Read
 4164 DRAM: Pin layout

1- 41xx→ DRAM: 𝑊 , 𝑅𝐴𝑆 , 𝐶𝐴𝑆

2- 41xx→D, Q

3- x64→ M=64kbit=64x1024 bit

Since 41 refers 1 bit I/O,

Address bus size= (log2 (64x1024))2=(6+10)/2=8

Address lines→ A0..A7

 Example
Memory Address Memory

Each word is 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0
identified with 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1
the address
2 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0
210=1024 (1K) :
words
:
Each word is 1021 1 1 1 1 1 1 1 1 0 1 0 1 0 1 1 0 0 1
8-bit wide
1022 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 1 0 0
1KByte 1023 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 1
memory

MAR 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 MDR

10 bit 8 bit
Example
Memory Address Memory
0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0

1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1

2 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0

1021 1 1 1 1 1 1 1 1 0 1 0 1 0 1 1 0 0 1

1022 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 1 0 0

1023 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 1

MAR 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 MDR

10 bit 8 bit
Relationship between MAR, MDR and Memory
Data
Address
MAR-MDR Example
 Memory Access
 Each memory location has a unique address
 Address from an instruction is copied to the MAR which
finds the location in memory
 CPU determines if it is a store or retrieval
 Transfer takes place between the MDR and memory
 MDR is a two way register

Data Bus

CPU Memory

Address Bus
 Memory Access
 For the microprocessor to access Data Bus
(Read or Write) information in
memory (RAM or ROM), it needs
to do the following:

Address Bus
 Select the right memory chip
Memory
(using part of the address bus).
 Identify the memory location
(using the rest of the address
bus).
 Access the data (using the data SELECT READ/WRITE

bus).
Memory Access
NxM

Control Bus 3NxM

Memory 1

NxM

Address Bus
CPU Memory 2

Data Bus NxM

Memory 3
Memory Access
NxM

Control Bus 3NxM

Memory 1

NxM
01 0001100011
Address Bus
CPU Memory 2

Data Bus NxM

Memory 3
Memory Access
NxM

Control Bus 3NxM

Memory 1

NxM
01 0001100011
Address Bus
CPU Memory 2

Data Bus NxM

Memory 3
 The Tri-State Buffer
 An important circuit element that is used
extensively in memory.
 This buffer is a logic circuit that has three states:
 Logic 0, Logic 1, and high impedance.
 When this circuit is in high impedance mode, it looks
as if it is disconnected from the output completely.

The Output is Low The Output is High High Impedance

 The Tri-State Buffer
 This circuit has two inputs and one output.
 The first input behaves like the normal input for the
circuit.
 The second input is an “enable”.
 If it is set high, the output follows the proper circuit
behavior.
 If it is set low, the output looks like a wire connected to
nothing.

Input Output OR Input Output

Enable Enable
 The Basic Memory Element
 The basic memory element is similar to a D
latch.
D Q(t+1)
 Input 0 0

 Output 1 1

 Enable
Data Input Data Output
D Q

Enable
EN
 The Basic Memory Element
 Data is always present on the input and the output is
always set to the content of the latch.
 Tri-state buffers are added at the input and output of
the latch.

WR RD

D Q
Data Input Data Output

Enable
EN
 The Basic Memory Element
 Data is always present on the input and the output is
always set to the content of the latch.
 Tri-state buffers are added at the input and output of
the latch.

Data Bus

WR Control Bus RD

D Q
Data Input Data Output

Enable
EN
 The Basic Memory Element
 The WR signal controls the input buffer.
 The bar over WR means that this is an active
low signal.
 If WR is 0 the input data reaches the latch
input.
 If WR is 1 the input of the latch looks like a
wire connected to nothing.
 The RD signal controls the output in a similar
manner.
 A Memory "Register"
 If four latches are connected together, a 4-bit
memory register is obtained

I0 I1 I2 I3
WR

D D D D
Q Q Q Q

EN EN EN EN
Enable
RD

O0 O1 O2 O3
 Memory Addressing
 Using the RD and WR controls we
can determine the direction of I0 I1 I2 I3
flow either into or out of memory.
WR Input Buffers
 Using the appropriate Enable input
we enable an individual memory EN0 Memory Register 0

register. EN1 Memory Register 1

 Since we can never have more EN2 Memory Register 2

than one of these enables active at EN3 Memory Register 3

the same time, we can have them Output Buffers

RD
encoded to reduce the number of
lines coming into the chip. O0 O1 O2 O3
 These encoded lines are the
address lines for memory.
 Memory Organization
Data Bus D1 D0
D3 D2

R/W

I O I O I O I O
EN EN
EN0 EN EN

I O I O I O I O
EN EN EN EN
EN1

I O I O I O I O
EN EN EN EN

EN2
 The Design of a Memory Chip
Data Bus Control Bus
 Since we have tri-state
buffers on both the inputs WR RD
and outputs of the flip D Q
flops, we can actually use Data Input
Data Output
one set of pins only.
Enable
EN

WR Input Buffers
D0 D0
A D D0
Memory Reg. 0
d e A1 D1 A1 D1
A1 d c D1
Memory Reg. 1
r o
D2 D2
e d A0 A0
Memory Reg. 2 D2
A0 s e
s r D3 D3
Memory Reg. 3 D3

RD Output Buffers Enable RD/WR CE OE WR

4x4 Memory
 Memory Components
 Decoder is a combinational circuit that converts
binary information from n-coded inputs to
maximum of 2n outputs

 n coded inputs to 2n outputs

One Dimensional Addressing

Data Bus

A2
Address Bus

A1
3 to 8
Decoder
A0

8x8 Memory
74HC138 2x8 Decoder Example
Two Dimensional Addressing

M
A0
3 to 8 decoder
A1 32X8 memory
A2
N arranged in 2D
configuration

A3
A4 2 to 4 decoder

Why?
 Two Dimensional Addressing II
 This arrangement is more economical than 5-
to-32 Decoder
 Check the cost of 2-4 decoder and 3-8 decoder

D0

A0 D1

D2

A1 D3
E
 Memory Read
Motorola 6802 example:

 CPU applies the address on the

address bus at the falling edge of
the clock ①

 Proper select input for the

memory is selected ②

 VMA signal indicates valid

memory address ②

 MPU applies R/W signal HIGH to

designate read cycle ②

 Memory places the data on the

data bus ③
Memory access time (Read Latency)
 CPU latches Data on the falling
edge of the clock ④
* Microprocessing Unit (MPU)
* Valid Memory Address (VMA)
 Memory Write
Motorola 6802 example:

 CPU applies the address on the

address bus at the falling edge
of the clock ①

 Proper select input for the

memory is selected ②

 VMA signal indicates valid

memory address ②

 CPU applies R/W signal LOW to

designate write cycle ②

 MPU places the data on the data

bus ③
Memory access time (Write Latency)
 Memory latches Data on the
falling edge of the clock ④
 References
 Lecture Slides: Dr. Şule Gündüz Öğüdücü
 Lecture Slides: Dr. Erdem Matoğlu
 Lecture Slides: Dr. Feza Buzluca
 Lecture Slides: Dr. Bassel Soudan
 Lecture Slides: Dr. Gökhan İnce
 Lecture Slides: Dr. B.Berk Üstündağ

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