FUNCTIONAL BUILDING BLOCKS OF A

PROCESSOR
Processor
A processor is the logic circuitry that responds to and processes the basic instructions that drives a
computer. The term processor has generally replaced the term central processing unit (CPU). The
processor in a personal computer or embedded in small devices is often called a microprocessor.

A central processing unit (CPU) is the electronic circuitry within a computer that carries out
the instructions of a computer program by performing the basic arithmetic, logical, control
and input/output (I/O) operations specified by the instructions. The term has been used in the
computer industry at least since the early 1960s. Traditionally, the term CPU refers to a processor,
more specifically to its processing unit and control unit (CU), distinguishing these core elements of a
computer from external components such as main memoryand I/O circuitry. The block diagram of
basic processor is as shown in the figure1.

basic processor
Figure 1 Basic processor

Basic blocks of processor :

ALU
An arithmetic logic unit (ALU) is a digital electronic circuit that performs arithmetic and bitwise
logical operations on integer binary numbers. This is in contrast to a floating-point unit(FPU), which
operates on floating point numbers. An ALU is a fundamental building block of many types of
computing circuits, including the central processing unit (CPU) of computers, FPUs, and graphics
processing units (GPUs). A single CPU, FPU or GPU may contain multiple ALUs.

The inputs to an ALU are the data to be operated on, called operands, and a code indicating
the operation to be performed; the ALU's output is the result of the performed operation. In many
designs, the ALU also exchanges additional information with a status register, which relates to the
result of the current or previous operations. The diagram of ALU is as shown in the figure2.

alu
Figure2 Arithmetic Logic Unit

Control Unit
The control unit (CU) is a component of a computer's central processing unit (CPU) that directs
operation of the processor. It tells the computer's memory, arithmetic/logic unit and input and output
devices how to respond to a program's instructions.

The Control Unit (CU) is digital circuitry contained within the processor that coordinates the
sequence of data movements into, out of, and between a processor's many sub-units. The result of
these routed data movements through various digital circuits (sub-units) within the processor produces
the manipulated data expected by a software instruction (loaded earlier, likely from memory). The
diagram of control unit is as show in the figure3.

control unit
figure3 : control unit
Registers
A register is a quickly accessible location available to a digital processor's central processing
unit (CPU). Registers usually consist of a small amount of fast storage, although some registers have
specific hardware functions, and may be read-only or write-only. Registers are typically addressed by
mechanisms other than main memory, but may in some cases be memory mapped.

Almost all computers, whether load-store architecture or not, load data from a larger memory
into registers where it is used for arithmetic operations and is manipulated or tested by machine
instructions. Manipulated data is then often stored back to main memory, either by the same
instruction or a subsequent one. Modern processors use either static or dynamic RAM as main
memory, with the latter usually accessed via one or more cache levels. Processor registers are
normally at the top of the memory hierarchy, and provide the fastest way to access data. The term
normally refers only to the group of registers that are directly encoded as part of an instruction, as
defined by the instruction set. The diagram of register unit is as shown in the figure4.

register unit

Figure4. Register Unit

Program Counter
The Program Counter is a register which is also known as PC. PC contains the memory address of the
next instruction to be executed. In the beginning PC contains the address of the memory location
where the program begins. Here, the program counter is a 32 bit register which needs a 32 bit input
and a clock. The output obtained is a 32 bit register. Instructions are usually fetched sequentially from
memory, but control transfer instructions change the sequence by placing a new value in the PC.
These include branches (sometimes called jumps), subroutine calls, and returns. A transfer that is
conditional on the truth of some assertion lets the computer follow a different sequence under
different conditions. The diagram of program counter is as shown in the figure5.

pc
Figure5 Program Counter

Data Memory
The Data Memory Register is also known as Memory Data Register. The Memory Data Register is
the register of a computer's control unit that contains the data to be stored in the computer
storage (e.g. RAM), or the data after a fetch from the computer storage. It acts like a buffer and holds
anything that is copied from the memory ready for the processor to use it.

The MDR is a two-way register. When data is fetched from memory and placed into the
MDR, it is written to go in one direction. When there is a write instruction, the data to be written is
placed into the MDR from another CPU register, which then puts the data into memory.

The Data Memory Register is half of a minimal interface between a

microprogram and computer storage, the other half is a memory address register .
The Memory Data Register (MDR) contains the data value being fetched or stored. It is a
common mistake to say that the MDR should be W bits wide, where W is the cell size. However, on
most computers the cell size is only 8-bits, and most data values occupy multiple cells. Thus, the size
of the MDR is usually a multiple of 8 bits. Typical values of MDR width are 32 and 64 bits, which
would allow us to fetch, in a single step, either an integer or a float value.
 Microprocessor - 8085 Architecture

8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor

designed by Intel in 1977 using NMOS technology.

It has the following configuration −

8-bit data bus

16-bit address bus, which can address upto 64KB
A 16-bit program counter
A 16-bit stack pointer
Six 8-bit registers arranged in pairs: BC, DE, HL
Requires +5V supply to operate at 3.2 MHZ single phase clock

It is used in washing machines, microwave ovens, mobile phones, etc.

8085 Microprocessor – Functional Units

8085 consists of the following functional units −

Accumulator
It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It
is connected to internal data bus & ALU.

Arithmetic and logic unit

As the name suggests, it performs arithmetic and logical operations like Addition,
Subtraction, AND, OR, etc. on 8-bit data.

General purpose register

There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register
can hold 8-bit data.

These registers can work in pair to hold 16-bit data and their pairing combination is like B-C,
D-E & H-L.

Program counter
It is a 16-bit register used to store the memory address location of the next instruction to
be executed. Microprocessor increments the program whenever an instruction is being
executed, so that the program counter points to the memory address of the next
instruction that is going to be executed.
Stack pointer
It is also a 16-bit register works like stack, which is always incremented/decremented by 2
during push & pop operations.

Temporary register
It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.

Flag register
It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon
the result stored in the accumulator.

These are the set of 5 flip-flops −

Sign (S)
Zero (Z)
Auxiliary Carry (AC)
Parity (P)
Carry (C)

Its bit position is shown in the following table −

D7 D6 D5 D4 D3 D2 D1 D0

S Z AC P CY

Instruction register and decoder

It is an 8-bit register. When an instruction is fetched from memory then it is stored in the
Instruction register. Instruction decoder decodes the information present in the Instruction
register.

Timing and control unit

It provides timing and control signal to the microprocessor to perform operations. Following
are the timing and control signals, which control external and internal circuits −

Control Signals: READY, RD’, WR’, ALE

Status Signals: S0, S1, IO/M’
DMA Signals: HOLD, HLDA
RESET Signals: RESET IN, RESET OUT

Interrupt control
As the name suggests it controls the interrupts during a process. When a microprocessor is
executing a main program and whenever an interrupt occurs, the microprocessor shifts the
control from the main program to process the incoming request. After the request is
completed, the control goes back to the main program.

There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5,
TRAP.

Serial Input/output control

It controls the serial data communication by using these two instructions: SID (Serial input
data) and SOD (Serial output data).

Address buffer and address-data buffer

The content stored in the stack pointer and program counter is loaded into the address
buffer and address-data buffer to communicate with the CPU. The memory and I/O chips
are connected to these buses; the CPU can exchange the desired data with the memory
and I/O chips.

Address bus and data bus

Data bus carries the data to be stored. It is bidirectional, whereas address bus carries the
location to where it should be stored and it is unidirectional. It is used to transfer the data
& Address I/O devices.

8085 Architecture
We have tried to depict the architecture of 8085 with this following image −
 Microprocessor - 8085 Pin Configuration

The following image depicts the pin diagram of 8085 Microprocessor −

The pins of a 8085 microprocessor can be classified into seven groups −

Address bus
A15-A8, it carries the most significant 8-bits of memory/IO address.

Data bus
AD7-AD0, it carries the least significant 8-bit address and data bus.

Control and status signals

These signals are used to identify the nature of operation. There are 3 control signal and 3
status signals.

Three control signals are RD, WR & ALE.

RD − This signal indicates that the selected IO or memory device is to be read and is
ready for accepting data available on the data bus.
 WR − This signal indicates that the data on the data bus is to be written into a selected
memory or IO location.
ALE − It is a positive going pulse generated when a new operation is started by the
microprocessor. When the pulse goes high, it indicates address. When the pulse goes
down it indicates data.

Three status signals are IO/M, S0 & S1.

IO/M
This signal is used to differentiate between IO and Memory operations, i.e. when it is high
indicates IO operation and when it is low then it indicates memory operation.

S1 & S0
These signals are used to identify the type of current operation.

Power supply
There are 2 power supply signals − VCC & VSS. VCC indicates +5v power supply and VSS
indicates ground signal.

Clock signals
There are 3 clock signals, i.e. X1, X2, CLK OUT.

X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to set
frequency of the internal clock generator. This frequency is internally divided by 2.
CLK OUT − This signal is used as the system clock for devices connected with the
microprocessor.

Interrupts & externally initiated signals

Interrupts are the signals generated by external devices to request the microprocessor to
perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and
INTR. We will discuss interrupts in detail in interrupts section.

INTA − It is an interrupt acknowledgment signal.

RESET IN − This signal is used to reset the microprocessor by setting the program
counter to zero.

RESET OUT − This signal is used to reset all the connected devices when the
microprocessor is reset.

READY − This signal indicates that the device is ready to send or receive data. If READY
is low, then the CPU has to wait for READY to go high.
 HOLD − This signal indicates that another master is requesting the use of the address
and data buses.
HLDA (HOLD Acknowledge) − It indicates that the CPU has received the HOLD request
and it will relinquish the bus in the next clock cycle. HLDA is set to low after the HOLD
signal is removed.

Serial I/O signals

There are 2 serial signals, i.e. SID and SOD and these signals are used for serial
communication.

SOD (Serial output data line) − The output SOD is set/reset as specified by the SIM
instruction.
SID (Serial input data line) − The data on this line is loaded into accumulator whenever a
RIM instruction is executed.
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1.4 MEMORY STRUCTURE IN 8085 PROCESSOR

Memory Structure and Its Requirements:
 Read/Write memory is a group of registers to store binary information. Fig 1.4.1
shows a typical R/W memory chip; it has “2n = M” registers (where n= no. of
address lines) and each can store N no. of bits.
 It has N no. of bidirectional (or separate input-output) data lines.
 It also has one Chip select (CS), and two control lines Read (RD) to enable the
output buffer and Write (WR) to enable the input buffer.
 Figure. 1.4.1 shows the logic diagram of typical EPROM (Erasable Programmable
Read Only memory) Memory with “2n = M” registers (where n= no. of address
lines).
 It has “n” no. of address lines, one Chip select (CS) and one Read (RD).
 This memory chip must be programmed before it can be used as Read-Only
memory.

Figure 1.4.1 logic diagram of typical EPROM

[Source: “Microprocessor Architecture Programming and Application” by R.S. Gaonkar, page-91]

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The 8085 microprocessor uses a16-bit wide address bus for addressing memories
and I/O devices. Using 16-bit wide address bus it can access 216 = 64K bytes of memory
and I/O devices. The 64K addresses are to be assigned to memories and I/O devices for
their addressing. There are two schemes for the allocation of addresses to memories and
input / output devices:
1. Memory mapped I/O scheme.
2. I/O mapped I/O scheme.
Memory mapped I/O scheme:
 In memory mapped I/O scheme there is only one address space.
 Address space is defined as the set of all possible addresses that microprocessor
can generate.
 Some addresses are assigned to memories and some addresses to I/O devices.
 An I/O device is also treated as memory location and one address is assign to it.
 Suppose that memory locations are assigned the addresses 2000 H to 24FF H then
each one address is assign to each memory location. The addresses for I/O devices
are different from the addresses which have been assigned to memories.
 The addresses which have not been assigned to memories can be assigned to each
I/O device.
 In this scheme all the data transfer instructions of the microprocessor can be valid
for data transfer from the memory location or I/O device whose address is in H-L
pair.
I/O mapped I/O scheme:
 In this scheme the addresses assigned to memory location can also be assigned to
I/O devices.
 Since the same address may be assigned to memory location or an I/O device, the
microprocessor must issue a signal to distinguish whether the address on the
address bus is for a memory location or an I/O device.
 The 8085 issues an IO/M signal for this purpose.
 Two extra instructions IN and OUT are used to address I/O devices.

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T1 T2 T3 T4
CLK

AD0

ALE

Figure 1.4.2 Timing Diagram: Transfer of Byte from Memory to Microprocessor

[Source: “Microprocessor Architecture Programming and Application” by R.S. Gaonkar, page-66]

 Figure 1.4.2 shows the timing diagram of how a data byte is transferred from
memory to the microprocessor from which the need for demultiplexing the bus
AD0-AD7 becomes easier to understand.
 This figure shows that the address on the high order bus (20H) remains on the bus
for three clock periods.
 However, the low order address (05H) is lost after the first clock period.
 This address needs to be latched and used for identifying the memory address.
 If the bus AD7-AD0 is used to identify the memory location (2005H), the address
will change to 204FH after the first clock period.
 Figure. 1.4.2 shows a schematic that uses a latch and the ALE signal to demultiplex
the bus. The bus AD7-AD0 is connected as input to latch 74LS373.
 The ALE signal is connected to Enable (G) pin of the Latch, and the Output control
(OC) signal of the latch is grounded.
 Figure 1.4.2 shows that the ALE goes high during T1. When the ALE is high, the
latch is transparent; that means output changes according to the input data.
 During T1 output of the latch is 05H.
 When ALE goes low, the data byte 05H is latched until the next ALE, and the
output of the latch represents the low-order address bus A7-A0 after the latching
operation.

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Figure 1.4.3 Schematic of Latching Low-Order Address Bus

[Source: “Microprocessor Architecture Programming and Application” by R.S. Gaonkar, page-82]

Generating Control Signals:

 Figure 1.4.3 shows the RD (Read) as a control signal. Because this signal is used
both for reading memory and for reading an input device, it is necessary to generate
two different Read signals: one for memory and another for input. Similarly, two
separate Write signals must be generated.
 This signal is Indeed with RD and WR signals by using the 74LS32 quadruple two-
input OR gates, as shown in Figure 1.4.3.
 When both the input goes low , the outputs of the gates go low and generate MEMR
(memory Read) and MEMW (memory Write) control Signals.

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 When IO/M goes high, it indicates the peripheral I/O operation. The table shows
that this signal is complemented and ANDed with RD and WR signals to generate
IOR (I/O Read) and IOW (I/O Write) control Signals.
  
  

IO/M RD WR Control Signal

0 0 1 Memory read

0 1 0 Memory write

1 0 1 I/O read

1 1 0 I/O write

Address Decoding:

 The address of a memory location is sent out by the microprocessor. The

corresponding memory chip or I/O device is selected by a decoding circuit.
 The decoding task can be performed by a decoder, a comparator, a bipolar PROM
or PLA (Programmed logic array).
 For memory interfacing we can use Decoder IC 74LS138 which has G1, G2A and
G2B enable signals.
 To enable 74LS138, G1 should be high, and G2A and G2B should be low. Also,
74LS138 has three select lines A, B & C. By applying proper logic to select ines
any one of the output cab be selected.
 Where, 74LS138 has Y0, Y1, …. Y7 output lines. An output lines goes low when
it is selected. Other output lines remain high. Thus as shown in Table1.1 (Truth
table for 74LS138), when G1 is low or G2A is high or G2B is high, all output lines
become high.
 Thus 74LS138 acts as decoder only when G1 is high, and G2A and G2B are low.

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INPUTS
OUTPUTS
ENABLE SELECT
G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H H X X X H H H H H H H H
L X X X X X H H H H H H H H
H L L L L L L H H H H H H H
H L L L L H H L H H H H H H
H L L L H L H H L H H H H H
H L L L H H H H H L H H H H
H L L H L L H H H H L H H H
H L L H L H H H H H H L H H
H L L H H L H H H H H H L H
H L L H H H H H H H H H H L

Following fig shows the simple interfacing of 8K memory with 8085

Figure 1.4.4 simple interfacing of 8K memory with 8085

[Source: “Microprocessor Architecture Programming and Application” by R.S. Gaonkar, page-82]

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 Interrupts in 8085
Interrupts are the signals generated by the external devices to request the microprocessor to perform a
task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
Interrupt are classified into following groups based on their parameter −
 Vector interrupt − In this type of interrupt, the interrupt address is known to the
processor. For example: RST7.5, RST6.5, RST5.5, TRAP.
 Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to the
processor so, the interrupt address needs to be sent externally by the device to perform
interrupts. For example: INTR.
 Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing some
instructions into the program. For example: RST7.5, RST6.5, RST5.5.
 Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt by writing
some instructions into the program. For example: TRAP.
 Software interrupt − In this type of interrupt, the programmer has to add the instructions into
the program to execute the interrupt. There are 8 software interrupts in 8085, i.e. RST0, RST1,
RST2, RST3, RST4, RST5, RST6, and RST7.
 Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts, i.e.
TRAP, RST7.5, RST6.5, RST5.5, INTA.
Note − NTA is not an interrupt, it is used by the microprocessor for sending acknowledgement. TRAP
has the highest priority, then RST7.5 and so on.

Interrupt Service Routine (ISR)

A small program or a routine that when executed, services the corresponding interrupting source is
called an ISR.
TRAP
It is a non-maskable interrupt, having the highest priority among all interrupts. Bydefault, it is enabled
until it gets acknowledged. In case of failure, it executes as ISR and sends the data to backup memory.
This interrupt transfers the control to the location 0024H.

RST7.5
It is a maskable interrupt, having the second highest priority among all interrupts. When this interrupt
is executed, the processor saves the content of the PC register into the stack and branches to 003CH
address.
RST 6.5
It is a maskable interrupt, having the third highest priority among all interrupts. When this interrupt is
executed, the processor saves the content of the PC register into the stack and branches to 0034H
address.
RST 5.5
It is a maskable interrupt. When this interrupt is executed, the processor saves the content of the PC
register into the stack and branches to 002CH address.
INTR
It is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled by
resetting the microprocessor.
When INTR signal goes high, the following events can occur −
 The microprocessor checks the status of INTR signal during the execution of each instruction.
 When the INTR signal is high, then the microprocessor completes its current instruction and
sends active low interrupt acknowledge signal.
 When instructions are received, then the microprocessor saves the address of the next
instruction on stack and executes the received instruction.
 UNIT-I
8086 Architecture
Introduction to Microprocessors
A microprocessor is a computer processor which incorporates the
functions of a computer's central processing unit (CPU) on a
single integrated circuit (IC), or at most a few integrated circuits
The microprocessor is a multipurpose, clock driven, register based,
digital-integrated circuit which accepts binary data as input, processes it
according to instructions stored in its memory, and provides results as
output. Microprocessors contain both combinational logic and sequential
digital logic. Microprocessors operate on numbers and symbols represented
in the binary numeral system.
Generation of Microprocessors:
 INTEL 4004 ( 1971)
 4-bit microprocessor
 4 KB main memory
 45 instructions
 PMOS technology
 was first programmable device which was used in calculators
 INTEL 8008 (1972)
 8-bit version of 4004
 16 KB main memory
 48 instructions
 PMOS technology
 Slow
 Intel 8080 (1973)
 8-bit microprocessor
 64 KB main memory
 2 microseconds clock cycle time
 500,000 instructions/sec
 10X faster than 8008
 NMOS technology
 Drawback was that it needed three power supplies.
  Small computers (Microcomputers) were designed in mid
1970’s
Using 8080 as CPU.

 INTEL 8086/8088

Year of introduction 1978 for 8086 and 1979 for 8088

 16-bit microprocessors
 Data bus width of 8086 is 16 bit and 8 bit for 8088
 1 MB main memory
 400 nanoseconds clock cycle time
 6 byte instruction cache for 8086 and 4 byte for 8088
 Other improvements included more registers and additional
instructions
 In 1981 IBM decided to use 8088 in its personal computer

 INTEL 80186 (1982)

 16-bit microprocessor-upgraded version of 8086

 1 MB main memory
 Contained special hardware like programmable counters,
interrupt controller etc.
 Never used in the PC
 But was ideal for systems that required a minimum of
hardware .
 INTEL 80286 (1983)
 16-bit high performance microprocessor with memory
management & protection
 16 MB main memory
 Few additional instructions to handle extra 15 MB
 Instruction execution time is as little as 250 ns
 Concentrates on the features needed to implement
MULTITASKING

 Intel 80386 (1986)

 Intel 80486 (1989)
 Pentium (1993)
 Pentium pro(1995)
 Pentium ii (1997)
 Pentium iii (1999)
 Pentium iv (2002)
 Latest is Intel i9 processor
General Architecture of Microprocessors

Buses
Register Organization of 8086
8086 has a powerful set of registers containing general purpose and
special purpose registers. All the registers of 8086 are 16-bit registers. The
general purpose registers, can be used either 8-bit registers or 16-bit
registers. The general purpose registers are either used for holding the data,
variables and intermediate results temporarily or for other purpose like
counter or for storing offset address for some particular addressing modes
etc. The special purpose registers are used as segment registers, pointers,
index registers or as offset storage registers for particular addressing
modes. Fig 1.4 shows register organization of 8086. We will categorize the
register set into four groups as follows:

General data Registers:

The registers AX, BX, CX, and DX are the general 16-bit registers.

AX Register: Accumulator register consists of two 8-bit registers AL and AH,

which can be combined together and used as a 16- bit register AX. AL in this
case contains the low-order byte of the word, and AH contains the high-
order byte. Accumulator can be used for I/O operations, rotate and string
manipulation.

BX Register: This register is mainly used as a base register. It holds the

starting base location of a memory region within a data segment. It is used
as offset storage for forming physical address in case of certain addressing
mode.

CX Register: It is used as default counter or count register in case of string

and loop instructions.
DX Register: Data register can be used as a port number in I/O operations
and implicit operand or destination in case of few instructions. In integer
32-bit multiply and divide instruction the DX register contains high-order
word of the initial or resulting number.

Segment registers:
To complete 1Mbyte memory is divided into 16 logical segments. The
complete 1Mbyte memory segmentation is as shown in fig 1.5. Each
segment contains 64Kbyte of memory. There are four segment registers.

Code segment (CS) is a 16-bit register containing address of 64 KB segment

with processor instructions. The processor uses CS segment for all accesses
to instructions referenced by instruction pointer (IP) register. CS register
cannot be changed directly. The CS register is automatically updated during
far jump, far call and far return instructions. It is used for addressing a
memory location in the code segment of the memory, where the
executable program is stored.

Stack segment (SS) is a 16-bit register containing address of 64KB segment

with program stack. By default, the processor assumes that all data
referenced by the stack pointer (SP) and base pointer (BP) registers is
located in the stack segment. SS register can be changed directly using POP
instruction. It is used for addressing stack segment of memory. The stack
segment is that segment of memory, which is used to store stack data.

Data segment (DS) is a 16-bit register containing address of 64KB segment

with program data. By default, the processor assumes that all data
referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is
located in the data segment. DS register can be changed directly using POP
and LDS instructions. It points to the data segment memory where the data
is resided.

Extra segment (ES) is a 16-bit register containing address of 64KB segment,

usually with program data. By default, the processor assumes that the DI
register references the ES segment in string manipulation instructions. ES
register can be changed directly using POP and LES instructions. It also
refers to segment which essentially is another data segment of the memory.
It also contains data.
Pointers and index registers.
The pointers contain within the particular segments. The pointers IP, BP, SP
usually contain offsets within the code, data and stack segments
respectively

Stack Pointer (SP) is a 16-bit register pointing to program stack in stack

segment.

Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP

register is usually used for based, based indexed or register indirect
addressing.

Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed
and register indirect addressing, as well as a source data addresses in string
manipulation instructions.

Destination Index (DI) is a 16-bit register. DI is used for indexed, based

indexed and register indirect addressing, as well as a destination data
address in string manipulation instructions.
Flag Register:

Flags Register determines the current state of the processor. They are
modified automatically by CPU after mathematical operations, this allows to
determine the type of the result, and to determine conditions to transfer
control to other parts of the program. The 8086 flag register as shown in
the fig 1.6. 8086 has 9 active flags and they are divided into two categories:

1. Conditional Flags
2. Control Flags

Conditional flags are as follows:

Carry Flag (CY): This flag indicates an overflow condition for unsigned
integer arithmetic. It is also used in multiple-precision arithmetic.

Auxiliary Flag (AC): If an operation performed in ALU generates a

carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7),
the AC flag is set i.e. carry given by D3 bit to D4 is AC flag. This is not a
general-purpose flag, it is used internally by the Processor to perform Binary
to BCD conversion.

Parity Flag (PF):This flag is used to indicate the parity of result. If lower
order 8-bits of the result contains even number of 1’s, the Parity Flag is set
and for odd number of 1’s, the Parity flag is reset.

Zero Flag (ZF):It is set; if the result of arithmetic or logical operation is zero
else it is reset.
Sign Flag (SF):In sign magnitude format the sign of number is indicated by
MSB bit. If the result of operation is negative, sign flag is set.

Control Flags

Control flags are set or reset deliberately to control the operations of the
execution unit. Control flags are as follows:

Trap Flag (TF): It is used for single step control. It allows user to execute one
instruction of a program at a time for debugging. When trap flag is set,
program can be run in single step mode.

Interrupt Flag (IF):It is an interrupt enable/disable flag. If it is set, the

maskable interrupt of 8086 is enabled and if it is reset, the interrupt is
disabled. It can be set by executing instruction sit and can be cleared by
executing CLI instruction.

Direction Flag (DF):It is used in string operation. If it is set, string bytes are
accessed from higher memory address to lower memory address. When it is
reset, the string bytes are accessed from lower memory address to higher
memory address.
 8086 Architecture

The 8086 is mainly divided into mainly two blocks

1. Execution Unit (EU)
2.Bus interface Unit (BIU)
Dividing the work between these two will speedup the processing
1) EXECUTION UNIT( EU)

The Execution unit tells the BIU where to fetch instructions or data
from
 decodes instructions and

 Executes instructions

The Execution unit contains:

1) Control circuitry
2) ALU
3) FLAGS
4) General purpose Registers
5) Pointer and Index Registers

Control Circuitry:
 It directs internal operations.
  A decoder in the EU translates instructions fetched from memory
Into series of actions which the EU carries out

Arithmetic Logic Unit:

16 bit ALU
Used to carry the operations
 ADD

 SUBTRACT

 XOR

 INCREMENT

 DECREMENT

 COMPLEMENT

 SHIFT BINARY NUMBERS

FLAG REGISTERS:
 A flag is a flip flop that indicates some condition produced by
execution of an instruction or controls certain operation of the EU.

 It is 16 bit

 It has nine active flags

Divided into two types

1. Conditional flags

2. Control flags

Conditional Flags

Carry Flag (CY): This flag indicates an overflow condition for unsigned
integer arithmetic. It is also used in multiple-precision arithmetic.

Auxiliary Flag (AC): If an operation performed in ALU generates a

carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7),
the AC flag is set i.e. carry given by D3 bit to D4 is AC flag. This is not a
general-purpose flag, it is used internally by the Processor to perform Binary
to BCD conversion.

Parity Flag (PF):This flag is used to indicate the parity of result. If lower
order 8-bits of the result contains even number of 1’s, the Parity Flag is set
and for odd number of 1’s, the Parity flag is reset.
Zero Flag (ZF):It is set; if the result of arithmetic or logical operation is zero
else it is reset.

Sign Flag (SF):In sign magnitude format the sign of number is indicated by
MSB bit. If the result of operation is negative, sign flag is set.

Control Flags

Control flags are set or reset deliberately to control the operations of the
execution unit. Control flags are as follows:

Trap Flag (TF): It is used for single step control. It allows user to execute one
instruction of a program at a time for debugging. When trap flag is set,
program can be run in single step mode.

Interrupt Flag (IF):It is an interrupt enable/disable flag. If it is set, the

maskable interrupt of 8086 is enabled and if it is reset, the interrupt is
disabled. It can be set by executing instruction sit and can be cleared by
executing CLI instruction.

Direction Flag (DF):It is used in string operation. If it is set, string bytes are
accessed from higher memory address to lower memory address. When it is
reset, the string bytes are accessed from lower memory address to higher
memory address.

General Purpose Registers:

The 8086 general purpose registers are similar to those of earlier
generations 8080 and 8085 .It was designed in such a way that many
programs written for 8080 and 8085 could easily be translated to run on
8086.The advantage of using internal registers for the temporary storage of
data is that since data already in the EU ., it can be accessed much more
quickly than it could be accessed from external memory.
General Purpose Registers
The registers AX, BX, CX, and DX are the general 16-bit registers.
AX Register: Accumulator register consists of two 8-bit registers AL and AH,
which can be combined together and used as a 16- bit register AX. AL in this
case contains the low-order byte of the word, and AH contains the high-
order byte. Accumulator can be used for I/O operations, rotate and string
manipulation.
BX Register: This register is mainly used as a base register. It holds the
starting base location of a memory region within a data segment. It is used
as offset storage for forming physical address in case of certain addressing
mode.
CX Register: It is used as default counter or count register in case of string
and loop instructions.
DX Register: Data register can be used as a port number in I/O operations
and implicit operand or destination in case of few instructions. In integer
32-bit multiply and divide instruction the DX register contains high-order
word of the initial or resulting number.
2) BUS INTERFACE UNIT (BIU)

The BIU sends out

 Addresses
 Fetches instructions from memory
 Read data from ports and memory
Or
The BIU handles all transfer of data and addresses on the buses for
the Execution Unit
The Bus interface unit contains
1) Instruction Queue
2) Instruction pointer
3) Segment registers
4) Address Generator

Instruction Queue:
BIU gets upto 6 bytes of next instructions and stores them in the
instruction queue. When EU executes instructions and is ready for its next
instruction, then it simply reads the instruction from this instruction queue
resulting in increased execution speed. Fetching the next instruction while
the current instruction executes is called pipelining.( based on FIFO) .This is
much faster than sending out an addresses to the system memory and
waiting for memory to send back the next instruction byte or bytes .Here
the Queue will be dumped and then reloaded from the new Address.
Segment Register:
The 8086 20 bit addresses So it can address upto 220 in memory ( 1 Mbyte)
but at any instant it can address upto 4 64 KB segments. This four segments
holds the upper 16 bits of the starting address of four memory segments
that the 8086 is working with it at particular time .The BIU always inserts
zeros for the lowest 4 bits of the 20 bit starting address
Example : If the code segment register contains 348AH then the code
segment starts at 348A0H .In other words a 64Kbyte segment can be
located anywhere within 1MByte address Space but the segment will
always starts at an address with zeros in the lowest 4 bits
Stack: is a section of memory set aside to store addresses and data while
subprogram executes is often called segment base . The stack segment
register always holds the upper 16 bit starting address of program stack.
The extra segment register and data segment register is used to hold the
upper 16 bit starting addresses of two memory segments that are used for
data .
Instruction Pointer holds the 16 bit address or offset of the next code byte
within the code segment. The value contained in the Instruction Pointer
called as Offset because the value must be added to the segment base
address in CS to produce the required 20 bit address.

CS register contains the Upper 16 bit of the starting address of the

code segment in the 1 Mbyte address range the instruction pointer contains
a 16 bit offset which tells wherein that 64 Kbyte code segment the next
instruction byte has to be fetched from.
Stack Register and Stack Pointer:
Stack: is a section of memory set aside to store addresses and data
while subprogram executes is often called segment base . The stack
segment register always holds the upper 16 bit starting address of program
stack. The Stack pointer (SP) holds the 16 bit offset from the starting of the
segment to the memory location where a word was most recently stored
.The memory location where the word is stored is called as top of the stack
Pointer and Index registers:
In addition to stack pointer register EU has
Base pointer Register (BP)
Source Pointer Register(SP)
Destination Pointer Register(DP)

These three registers are used to store temporary storage of data like
general purpose registers .They hold the 16 bit offset data of the data word
in one of the segment

Programming model

How can a 20-bit address be obtained, if there are only 16-bit

registers?
However, the largest register is only 16 bits (64k); so physical addresses
have to be calculated. These calculations are done in hardware within the
microprocessor.
The 16-bit contents of segment register gives the starting/ base address of
particular segment. To address a specific memory location within a segment
we need an offset address. The offset address is also 16-bit wide and it is
provided by one of the associated pointer or index register.

To be able to program a microprocessor, one does not need to know

all of its hardware architectural features. What is important to the
programmer is being aware of the various registers within the device and to
understand their purpose, functions, operating capabilities, and limitations.

The above figure illustrates the software architecture of the 8086

microprocessor. From this diagram, we see that it includes fourteenl6-bit
internal registers: the instruction pointer (IP), four data registers (AX, BX,
CX, and DX), two pointer registers (BP and SP), two index registers (SI and
DI), four segment registers (CS, DS, SS, and ES) and status register (SR), with
nine of its bits implemented as status and control flags.
 The point to note is that the beginning segment address must begin
at an address divisible by 16.Also note that the four segments need not be
defined separately. It is allowable for all four segments to completely
overlap (CS = DS = ES = SS).

Logical and Physical Address

Addresses within a segment can range from address 00000h to

address 0FFFFh. This corresponds to the 64K-bytelength of the segment. An
address within a segment is
called an offset or logical address.

A logical address gives the displacement from the base address of the
segment to the desired location within it, as opposed to its "real" address,
which maps directly anywhere into the 1 MByte memory space. This "real"
address is called the physical address.

What is the difference between the physical and the logical address?
The physical address is 20 bits long and corresponds to the actual binary
code output by the BIU on the address bus lines. The logical address is an
offset from location 0 of a given segment.
 You should also be careful when writing addresses on paper to do so
clearly. To specify the logical address XXXX in the stack segment, use the
convention SS:XXXX, which is equal to [SS] * 16 + XXXX.

Logical address is in the form of: Base Address: Offset Offset is the
displacement of the memory location from the starting location of the
segment. To calculate the physical address of the memory, BIU uses the
following formula:

Physical Address = Base Address of Segment * 16 + Offset

Example:

The value of Data Segment Register (DS) is 2222H.

To convert this 16-bit address into 20-bit, the BIU appends 0H to the LSB (by
multiplying with 16) of the address. After appending, the starting address of
the Data Segment becomes 22220H.

Data at any location has a logical address specified as:2222H: 0016H

Where 0016H is the offset, 2222 H is the value of DS Therefore the physical
address:22220H + 0016H
: 22236 H

The following table describes the default offset values to the corresponding
memory segments.

Some of the advantages of memory segmentation in the 8086 are as

follows:
 With the help of memory segmentation a user is able to work with
registers having only 16-bits.
 The data and the user’s code can be stored separately allowing for more
flexibility.
 Also due to segmentation the logical address range is from 0000H to
FFFFH the code can be loaded at any location in the memory.

Physical memory organization:

The 8086’s 1Mbyte memory address space is divided in to two

independent 512Kbyte banks: the low (even) bank and the high (odd) bank.
Data bytes associated with an even address (0000016, 0000216, etc.) reside
in the low bank, and those with odd addresses (0000116, 0000316, etc.)
reside in the high bank.

Address bits A1 through A19 select the storage location that is to be

accessed. They are applied to both banks in parallel. A0and bank high
enable (BHE) are used as bank-select signals.

The four different cases that happen during accessing data:

Case 1: When a byte of data at an even address (such as X) is to be

accessed:

 A0 is set to logic 0 to enable the low bank of memory.

 BHE is set to logic 1 to disable the high bank.

Case 2: When a byte of data at an odd addresses (such as X+1) is to be

accessed:
 A0is set to logic 1 to disable the low bank of memory.
 BHE is set to logic 0 to enable the high bank.

Case 3: When a word of data at an even address (aligned word) is to be

accessed:

 A0 is set to logic 0 to enable the low bank of memory.

 BHE is set to logic 0 to enable the high bank.
Case 4: When a word of data at an odd address (misaligned word) is to be
accessed, then the 8086 need two bus cycles to access it:
a) During the first bus cycle, the odd byte of the word (in the high bank) is
addressed
 A0 is set to logic 1 to disable the low bank of memory
 BHE is set to logic 0 to enable the high bank.
b) During the second bus cycle, the odd byte of the word (in the low bank) is
addressed

 A0is set to logic 0 to enable the low bank of memory.

 BHE is set to logic 1 to disable the high bank.
Signal Description of 8086 Microprocessor

The 8086 Microprocessor is a 16-bit CPU available in 3 clock rates, i.e.

5, 8 and 10MHz, packaged in a 40 pin CERDIP or plastic package. The 8086
Microprocessor operates in single processor or multiprocessor
configurations to achieve high performance. The pin configuration is as
shown in fig1. Some of the pins serve a particular function in minimum
mode (single processor mode) and others function in maximum mode
(multiprocessor mode) configuration.
 The 8086 signals can be categorized in three groups. The first are the
signals having common functions in minimum as well as maximum mode,
the second are the signals which have special functions in minimum mode
and third are the signals having special functions for maximum mode.

The following signal description is common for both the minimum

and maximum modes.

AD15-AD0:
These are the time multiplexed memory I/O address and data lines.
Address remains on the lines during T1 state, while the data is available on
the data bus during T2, T3, TW and T4. Here T1, T2, T3, T4 and TW are the
clock states of a machine cycle. TW is await state. These lines are active
high and float to a tristate during interrupt acknowledge and local bus hold
acknowledge cycles.
A19/S6, A18/S5, A17/S4, A16/S3:
These are the time multiplexed address and status lines. During T1,
these are the most significant address lines or memory operations. During
I/O operations, these lines are low. During memory or I/O operations, status
information is available on those lines for T2, T3, TW and T4 .The status of
the interrupt enable flag bit(displayed on S5) is updated at the beginning of
each clock cycle. The S4 and S3 combinedly indicate which segment register
is presently being used for memory accesses as shown in Table 1.1.
These lines float to tri-state off (tristated) during the local bus hold
acknowledge. The status line S6 is always low(logical). The address bits are
separated from the status bits using latches controlled by the ALE signal.

BHE/S7 (Active Low):

The bus high enable signal is used to indicate the transfer of data over the
higher order (D15-D8) data bus as shown in Table 1.2. It goes low for the
data transfers over D15-D8 and is used to derive chip selects of odd address
memory bank or peripherals. is low during T1 for read, write and
interrupt acknowledge cycles, when- ever a byte is to be transferred on the
higher byte of the data bus. The status information is available during T2,
T3 and T4. The signal is active low and is tristated during 'hold'. It is low
during T1 for the first pulse of the interrupt acknowledge cycle.

Read signal, when low, indicates the peripherals that the processor is
performing a memory or I/O read operation. is active low and shows
the state for T2, T3, TW of any read cycle. The signal remains tristated
during the 'hold acknowledge'.

READY:

This is the acknowledgement from the slow devices or memory that

they have completed the data transfer. The signal made available by the
devices is synchronized by the 8284A clock generator to provide ready input
to the 8086. The signal is active high.
INTR-Interrupt Request:

This is a level triggered input. This is sampled during the last clock
cycle of each instruction to determine the availability of the request. If any
interrupt request is pending, the processor enters the interrupt
acknowledge cycle. This can be internally masked by resetting the interrupt
enable flag. This signal is active high and internally synchronized.

TEST:

This input is examined by a 'WAIT' instruction. If the TEST input goes

low, execution will continue, else, the processor remains in an idle state.
The input is synchronized internally during each clock cycle on leading edge
of clock.

NMI-Non-maskable Interrupt:

This is an edge-triggered input which causes a Type2 interrrupt. The

NMI is not maskable internally by software. A transition from low to high
initiates the interrupt response at the end of the current instruction. This
input is internally synchronized.

RESET:

This input causes the processor to terminate the current activity and
start execution from FFFF0H. The signal is active high and must be active for
at least four clock cycles. It restarts execution when the RESET returns low.
RESET is also internally synchronized.

CLK-Clock Input:

The clock input provides the basic timing for processor operation and
bus control activity. Its an asymmetric square wave with 33% duty cycle.
The range of frequency for different 8086 versions is from 5MHz to 10MHz.

VCC :

+5V power supply for the operation of the internal circuit. GND
ground for the internal circuit.

MN/MX :

The logic level at this pin decides whether the processor is to operate
in either minimum (single processor) or maximum (multiprocessor) mode.
The following pin functions are for the minimum mode operation of 8086.
M/IO -Memory/IO:

This is a status line logically equivalent to S2 in maximum mode.

When it is low, it indicates the CPU is having an I/O operation, and when it
is high, it indicates that the CPU is having a memory operation. This line
becomes active in the previous T4 and remains active till final T4 of the
current cycle. It is tristated during local bus "hold acknowledge".

-Interrupt Acknowledge:

This signal is used as a read strobe for interrupt acknowledge cycles.

In other words, when it goes low, it means that the processor has accepted
the interrupt. It is active low during T2, T3 and TW of each interrupt
acknowledge cycle.

ALE-Address latch Enable:

This output signal indicates the availability of the valid address on the
address/data lines, and is connected to latch enable input of latches. This
signal is active high and is never tristated.

-Data Transmit/Receive:
This output is used to decide the direction of data flow through the
transreceivers (bidirectional buffers). When the processor sends out data,
this signal is high and when the processor is receiving data, this signal is low.
Logically, this is equivalent to S1 in maximum mode. Its timing is the same
as M/I/O. This is tristated during 'hold acknowledge'.

This signal indicates the availability of valid data over the

address/data lines. It is used to enable the transreceivers (bidirectional
buffers) to separate the data from the multiplexed address/data signal. It is
active from the middle ofT2 until the middle of T4 DEN is tristated during
'hold acknowledge' cycle.

HOLD, HLDA-Hold/Hold Acknowledge:

When the HOLD line goes high, it indicates to the processor that
another master is requesting the bus access. The processor, after receiving
the HOLD request, issues the hold acknowledge signal on HLDA pin, in the
middle of the next clock cycle after completing the current bus (instruction)
cycle. At the same time, the processor floats the local bus and control lines.
When the processor detects the HOLD line low, it lowers the HLDA signal.
HOLD is an asynchronous input, and it should be externally synchronized.

S2, S1, S0 -Status Lines:

These are the status lines which reflect the type of operation, being
carried out by the processor. These become active during T4 of the previous
cycle and remain active during T1 and T2 of the current bus cycle. The
status lines return to passive state during T3 of the current bus cycle so that
they may again become active for the next bus cycle during T4. Any change
in these lines during T3 indicates the starting of a new cycle, and return to
passive state indicates end of the bus cycle. These status lines are encoded
in table 1.3

This output pin indicates that other system bus masters will be
prevented from gaining the system bus, while the signal is low.
The signal is activated by the 'LOCK' prefix instruction and remains
active until the completion of the next instruction. This floats to tri-state
off during "hold acknowledge". When the CPU is executing a critical
instruction which requires the system bus, the LOCK prefix instruction
ensures that other processors connected in the system will not gain the
control of the bus. The 8086, while executing the prefixed instruction,
asserts the bus lock signal output, which may be connected to an
external bus controller.

QS1, QS0-Queue Status:

These lines give information about the status of the codeprefetch

queue. These are active during the CLK cycle after which the queue
operation is performed. These are encoded as shown in Table 1.4.
 ReQuest/Grant:

These pins are used by other local bus masters, in maximum mode, to
force the processor to release the local bus at the end of the processor's
current bus cycle. Each of the pins is bidirectional with having
higher priority than pins have internal pull-up resistors and
may be left unconnected. The request! Grant sequence is as follows:

1. A pulse one clock wide from another bus master requests the bus access
to 8086.

2. During T4 (current) or T1 (next) clock cycle, a pulse one clock wide from
8086 to the requesting master, indicates that the 8086 has allowed the local
bus to float and that it will enter the "hold acknowledge" state at next clock
cycle. The CPU's bus interface unit is likely to be disconnected from the local
bus of the system.

3. A one clock wide pulse from the another master indicates to 8086 that
the 'hold' request is about to end and the 8086 may regain control of the
local bus at the next clock cycle.

Minimum Mode 8086 System and Timings

In a minimum mode 8086 system, the microprocessor 8086 is
operated in minimum mode by strapping its MN/MX* pin to logic1. In this
mode, all the control signals are given out by the microprocessor chip itself.
There is a single microprocessor in the minimum mode system. The
remaining components in the system are latches, transreceivers, clock
generator, memory and I/O devices. Some type of chip selection logic may
be required for selecting memory or I/O devices, depending upon the
address map of the system.
Latches:

The latches are generally buffered output D-type flip-flops, like,

74LS373 or 8282. They are used for separating the valid address from the
multiplexed address/data signals and are controlled by the ALE signal
generated by 8086.

Transreceivers

Transreceivers are the bidirectional buffers and some times they are
called as data amplifiers. They are required to separate the valid data from
the time multiplexed address/data signal. They are controlled by two
signals, namely, DEN* and DT/R*. The DEN* signal indicates that the valid
data is available on the data bus, while DT/R indicates the direction of data,
i.e. from or to the processor.

Memory:

The system contains memory for the monitor and users program
storage. Usually, EPROMS are used for monitor storage, while RAMs for
users program storage.

IO Devices:

A system may contain I/O devices for communication with the processor as
well as some special purpose I/O devices.

Clock Generator:

The clock generator generates the clock from the crystal oscillator
and then shapes it and divides to make it more precise so that it can be
used as an accurate timing reference for the system. The clock generator
also synchronizes some external signals with the system clock.
 The general system organization is shown in above fig .Since it has 20
address lines and 16 data lines, the 8086 CPU requires three octal address
latches and two octal data buffers for the complete address and data
separation.

The working of the minimum mode configuration system can be

better described in terms of the timing diagrams rather than qualitatively
describing the operations. The opcode fetch and read cycles are similar.
Hence the timing diagram can be categorized in two parts.

1) Timing diagram for read cycle

2) Timing diagram for write cycle.

Timing diagram for Read cycle :

The read cycle begins in T1 with the assertion of the address latch
enable (ALE) signal and also M/IO* signal. During the negative going edge of
this signal, the valid address is latched on the local bus. The BHE* and
A0 signals address low, high or both bytes. From Tl to T4, the M/IO* signal
indicates a memory or I/O operation. At T2 the address is removed from the
local bus and is sent to the output. The bus is then tristated. The read (RD*)
control signal is also activated in T2 .
 The read (RD) signal causes the addressed device to enable its data
bus drivers. After RD* goes low, the valid data is available on the data bus.

The addressed device will drive the READY line high, when the
processor returns the read signal to high level, the addressed device will
again tristate its bus drivers.

Timing diagram for write cycle:

A write cycle also begins with the assertion of ALE and the emission
of the address. The M/IO* signal is again asserted to indicate a memory or
I/O operation. In T2 after sending the address in Tl the processor sends the
data to be written to the addressed location. The data remains on the bus
until middle of T4 state. The WR* becomes active at the beginning of T2.
 The BHE* and A0 signals are used to select the proper byte or bytes
of memory or I/O word to be read or written. The M/IO*, RD* and WR*
signals indicate the types of data transfer as specified in Table

HOLD Response Sequence

The HOLD pin is checked at the end of the each bus cycle. If it is
received active by the processor before T4 of the previous cycle or during
T1 state of the current cycle, the CPU activities HLDA in the next clock cycle
and for the succeeding bus cycles, the bus will be given to another
requesting master The control control of the bus is not regained by the
processor until the requesting master does not drop the HOLD pin low.
When the request is dropped by the requesting master, the HLDA is
dropped by the processor at the trailing edge of the next clock as shown in
fig
 Maximum Mode 8086 System and Timings
In the maximum mode, the 8086 is operated by strapping the
MN/MX* pin to ground. In this mode, the processor derives the status
signals S2*, S1* and S0*. Another chip called bus controller derives the
control signals using this status information. In the maximum mode, there
may be more than one microprocessor in the system configuration. The
other components in the system are the same as in the minimum mode
system. The general system organization is as shown in the fig1.1

The basic functions of the bus controller chip IC8288, is to derive

control signals like RD* and WR* (for memory and I/O devices), DEN*,
DT/R*, ALE, etc. using the information made available by the processor on
the status lines. The bus controller chip has input lines S2*, S1* and S0* and
CLK. These inputs to 8288 are driven by the CPU. It derives the outputs ALE,
DEN*, DT/R*, MWTC*, AMWC*, IORC*, IOWC* and AIOWC*. The AEN*, IOB
and CEN pins are specially useful for multiprocessor systems. AEN* and IOB
are generally grounded. CEN pin is usually tied to +5V.
 INTA* pin is used to issue two interrupt acknowledge pulses to the
interrupt controller or to an interrupting device.IORC*, IOWC* are I/O read
command and I/O write command signals respectively. These signals enable
an IO interface to read or write the data from or to the addressed port. The
MRDC*, MWTC* are memory read command and memory write command
signals respectively and may be used as memory read and write signals. All
these command signals instruct the memory to accept or send data from or
to the bus. For both of these write command signals, the advanced signals
namely AIOWC* and AMWTC* are available. They also serve the same
purpose, but are activated one clock cycle earlier than the IOWC* and
MWTC* signals, respectively. The maximum mode system is shown in fig.
1.1.

The maximum mode system timing diagrams are also divided in two
portions as read (input) and write (output) timing diagrams. The
address/data and address/status timings are similar to the minimum mode.
ALE is asserted in T1, just like minimum mode. The only difference lies in
the status signals used and the available control and advanced command
signals. The fig. 1.2 shows the maximum mode timings for the read
operation while the fig. 1.3 shows the same for the write operation.

Fig. 1.2 Memory Read Timing in Maximum Mode

Fig. 1.3 Memory Write Timing in Maximum Mode
 Microprocessor - 8086 Interrupts

Interrupt is the method of creating a temporary halt during program execution and allows
peripheral devices to access the microprocessor. The microprocessor responds to that
interrupt with an ISR (Interrupt Service Routine), which is a short program to instruct the
microprocessor on how to handle the interrupt.

The following image shows the types of interrupts we have in a 8086 microprocessor −

Hardware Interrupts
Hardware interrupt is caused by any peripheral device by sending a signal through a
specified pin to the microprocessor.

The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable
interrupt and INTR is a maskable interrupt having lower priority. One more interrupt pin
associated is INTA called interrupt acknowledge.

NMI
It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable
interrupt request pin (INTR)and it is of type 2 interrupt.

When this interrupt is activated, these actions take place −

Completes the current instruction that is in progress.

Pushes the Flag register values on to the stack.

Pushes the CS (code segment) value and IP (instruction pointer) value of the return
address on to the stack.
 IP is loaded from the contents of the word location 00008H.

CS is loaded from the contents of the next word location 0000AH.

Interrupt flag and trap flag are reset to 0.

INTR
The INTR is a maskable interrupt because the microprocessor will be interrupted only if
interrupts are enabled using set interrupt flag instruction. It should not be enabled using
clear interrupt Flag instruction.

The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is
disabled, then the microprocessor first completes the current execution and sends ‘0’ on
INTA pin twice. The first ‘0’ means INTA informs the external device to get ready and during
the second ‘0’ the microprocessor receives the 8 bit, say X, from the programmable
interrupt controller.

These actions are taken by the microprocessor −

First completes the current instruction.

Activates INTA output and receives the interrupt type, say X.

Flag register value, CS value of the return address and IP value of the return address
are pushed on to the stack.

IP value is loaded from the contents of word location X × 4

CS is loaded from the contents of the next word location.

Interrupt flag and trap flag is reset to 0

Software Interrupts
Some instructions are inserted at the desired position into the program to create interrupts.
These interrupt instructions can be used to test the working of various interrupt handlers. It
includes −

INT- Interrupt instruction with type number

It is 2-byte instruction. First byte provides the op-code and the second byte provides the
interrupt type number. There are 256 interrupt types under this group.

Its execution includes the following steps −

Flag register value is pushed on to the stack.

CS value of the return address and IP value of the return address are pushed on to the
stack.

IP is loaded from the contents of the word location ‘type number’ × 4

 CS is loaded from the contents of the next word location.

Interrupt Flag and Trap Flag are reset to 0

The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly
for type2 is 00008H and ……so on. The first five pointers are dedicated interrupt pointers.
i.e. −

TYPE 0 interrupt represents division by zero situation.

TYPE 1 interrupt represents single-step execution during the debugging of a program.

TYPE 2 interrupt represents non-maskable NMI interrupt.

TYPE 3 interrupt represents break-point interrupt.

TYPE 4 interrupt represents overflow interrupt.

The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and
interrupts from 32 to Type 255 are available for hardware and software interrupts.

INT 3-Break Point Interrupt Instruction

It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the
program so that when the processor reaches there, then it stops the normal execution of
program and follows the break-point procedure.

Its execution includes the following steps −

Flag register value is pushed on to the stack.

CS value of the return address and IP value of the return address are pushed on to the
stack.

IP is loaded from the contents of the word location 3×4 = 0000CH

CS is loaded from the contents of the next word location.

Interrupt Flag and Trap Flag are reset to 0

INTO - Interrupt on overflow instruction

It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH.
As the name suggests it is a conditional interrupt instruction, i.e. it is active only when the
overflow flag is set to 1 and branches to the interrupt handler whose interrupt type number
is 4. If the overflow flag is reset then, the execution continues to the next instruction.

Its execution includes the following steps −

Flag register values are pushed on to the stack.

CS value of the return address and IP value of the return address are pushed on to the
stack.
IP is loaded from the contents of word location 4×4 = 00010H

CS is loaded from the contents of the next word location.

Interrupt flag and Trap flag are reset to 0
 System timing in 8086
The bus cycle is also named as machine cycle. Bus cycle of 8086 is used to access memory,
peripheral devices (Input/output devices), and Interrupt controller. Bus cycle corresponds to a
sequence of events that starts with an address being output on system address bus followed
by a write or read data transfer. During these operations, a series of control signals are also
produced by microprocessor to control direction and timing of bus.
There are at least four clock periods in a bus cycle of 8086 microprocessor. These four clock
periods are called T1, T2, T3 and T4 states.
These four clock states gives bus cycle duration T of 200 ns *4 = 800 ns in 5-MHz 8086
system.
1. Read Cycle :
When a read cycle is to be performed, during T 1 microprocessor puts an address on
address bus, and then bus is put in high impedance state during T 2 state. Data to be read
must be out on bus during T3 and T4. During T3 bus is made “reserved for data in” and
finally data is read during T 4.

Write Cycle :
In case of write memory cycle, during T 1 state microprocessor puts an address on address
bus. Data is put on data bus by CPU during T 2 state and maintained during T3 and T4 states,
that is written out to memory or I/O devices.