PD - 96975A

IRF7832Z
HEXFET® Power MOSFET
Applications
VDSS RDS(on) max Qg
l Synchronous MOSFET for Notebook
Processor Power 30V 3.8m:@VGS = 10V 30nC
l Synchronous Rectifier MOSFET for
Isolated DC-DC Converters
A
A
1 8
S D
Benefits 2 7
S D
l Very Low RDS(on) at 4.5V VGS
3 6
S D
l Ultra-Low Gate Impedance
4 5
l Fully Characterized Avalanche Voltage G D

and Current SO-8

Top View
l 20V VGS Max. Gate Rating
l 100% tested for Rg

Absolute Maximum Ratings

Parameter Max. Units
VDS Drain-to-Source Voltage 30 V
VGS Gate-to-Source Voltage ± 20
ID @ TA = 25°C Continuous Drain Current, VGS @ 10V 21
ID @ TA = 70°C Continuous Drain Current, VGS @ 10V 17 A
IDM Pulsed Drain Currentc 160
PD @TA = 25°C Power Dissipation 2.5 W
PD @TA = 70°C Power Dissipation 1.6
Linear Derating Factor 0.02 W/°C
TJ Operating Junction and -55 to + 150 °C
TSTG Storage Temperature Range

Thermal Resistance
Parameter Typ. Max. Units
RθJL g
Junction-to-Drain Lead ––– 20 °C/W
RθJA Junction-to-Ambient fg ––– 50

Notes  through … are on page 10

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IRF7832Z
Static @ T J = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
BV DSS Drain-to-Source Breakdown Voltage 30 ––– ––– V V GS = 0V, I D = 250µA
∆ΒV DSS /∆T J Breakdown Voltage Temp. Coefficient ––– 0.023 ––– V/°C Reference to 25°C, I D = 1mA
R DS(on) Static Drain-to-Source On-Resistance ––– 3.1 3.8 mΩ V GS = 10V, ID = 20A e
––– 3.7 4.5 V GS = 4.5V, I D = 16A e
V GS(th) Gate Threshold Voltage 1.35 ––– 2.35 V V DS = V GS , ID = 250µA
∆V GS(th) Gate Threshold Voltage Coefficient ––– -5.5 ––– mV/°C
I DSS Drain-to-Source Leakage Current ––– ––– 1.0 µA V DS = 24V, V GS = 0V
––– ––– 150 V DS = 24V, V GS = 0V, TJ = 125°C
I GSS Gate-to-Source Forward Leakage ––– ––– 100 nA V GS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 V GS = -20V
gfs Forward Transconductance 80 ––– ––– S V DS = 15V, I D = 16A
Qg Total Gate Charge ––– 30 45
Q gs1 Pre-Vth Gate-to-Source Charge ––– 7.9 ––– V DS = 15V
Q gs2 Post-Vth Gate-to-Source Charge ––– 2.6 ––– nC V GS = 4.5V
Q gd Gate-to-Drain Charge ––– 11 ––– ID = 16A
Q godr Gate Charge Overdrive ––– 8.5 ––– See Fig. 16
Q sw Switch Charge (Q gs2 + Q gd) ––– 13.6 –––
Q oss Output Charge ––– 19 ––– nC V DS = 16V, V GS = 0V
Rg Gate Resistance ––– 1.2 1.9 Ω
t d(on) Turn-On Delay Time ––– 14 ––– V DD = 15V, V GS = 4.5V
tr Rise Time ––– 15 ––– ID = 16A
t d(off) Turn-Off Delay Time ––– 18 ––– ns Clamped Inductive Load
tf Fall Time ––– 5.6 –––
C iss Input Capacitance ––– 3860 ––– V GS = 0V
C oss Output Capacitance ––– 840 ––– pF V DS = 15V
C rss Reverse Transfer Capacitance ––– 370 ––– ƒ = 1.0MHz

Avalanche Characteristics
Parameter Typ. Max. Units
E AS Single Pulse Avalanche Energy d ––– 350 mJ
I AR Avalanche Current c ––– 16 A

Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 3.1 MOSFET symbol D

(Body Diode) A showing the

I SM Pulsed Source Current ––– ––– 160 integral reverse G

(Body Diode) c p-n junction diode. S

V SD Diode Forward Voltage ––– ––– 1.0 V TJ = 25°C, IS = 16A, V GS = 0V e

t rr Reverse Recovery Time ––– 16 24 ns TJ = 25°C, IF = 16A, V DD = 15V
Q rr Reverse Recovery Charge ––– 29 44 nC di/dt = 500A/µs e
t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

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 IRF7832Z
1000 1000
VGS VGS
TOP 10V TOP 10V
5.0V 5.0V
4.5V 4.5V
100
ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

3.5V 3.5V
3.0V 3.0V
2.7V 2.7V
2.5V 100 2.5V
BOTTOM 2.3V BOTTOM 2.3V
10

1
10

0.1
2.3V 2.3V
≤60µs PULSE WIDTH ≤60µs PULSE WIDTH
Tj = 25°C Tj = 150°C
0.01 1
0.1 1 10 100 1000 0.1 1 10 100 1000
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 2.0
ID = 21A
RDS(on) , Drain-to-Source On Resistance

VGS = 10V
ID, Drain-to-Source Current (Α)

100
1.5
(Normalized)

10 TJ = 150°C T J = 25°C

1.0
1

VDS = 15V
≤60µs PULSE WIDTH
0.1 0.5
1 2 3 4 -60 -40 -20 0 20 40 60 80 100 120 140 160
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

vs. Temperature
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 IRF7832Z
100000 6.0
VGS = 0V, f = 1 MHZ
ID= 16A
C iss = C gs + C gd, C ds SHORTED
C rss = C gd 5.0

VGS, Gate-to-Source Voltage (V)

C oss = C ds + C gd VDS= 24V
VDS= 15V
C, Capacitance(pF)

10000 4.0

Ciss
3.0

1000 Coss 2.0

Crss
1.0

100 0.0
1 10 100 0 10 20 30 40
VDS, Drain-to-Source Voltage (V) QG Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Fig 6. Typical Gate Charge Vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000 1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)

100 100 100µsec

T J = 150°C

T J = 25°C 10msec 1msec

10 10

1 1
T A = 25°C
VGS = 0V Tj = 150°C
Single Pulse
0.1 0.1
0.2 0.4 0.6 0.8 1.0 1.2 0 1 10 100
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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25 2.5

VGS(th) Gate threshold Voltage (V)

20
2.0
ID, Drain Current (A)

15 ID = 250µA
1.5

10

1.0
5

0 0.5
25 50 75 100 125 150 -75 -50 -25 0 25 50 75 100 125 150

T A , Ambient Temperature (°C) T J , Temperature ( °C )

Fig 9. Maximum Drain Current vs. Fig 10. Threshold Voltage vs. Temperature
Case Temperature

100

D = 0.50
10 0.20
0.10
Thermal Response ( Z thJA )

0.05
1 0.02 R1 R2 R3
R1 R2 R3 Ri (°C/W) τi (sec)
0.01 τJ
τJ
τC
τ
5.6971 0.015296
τ1 τ2 τ3
0.1 τ1 τ2 τ3 28.314 1.214900
Ci= τi/Ri 16 40.40000
Ci i/Ri
0.01 PDM

t1
SINGLE PULSE
( THERMAL RESPONSE ) t2
0.001
Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x Z thJA + TA
0.0001
1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10 100

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient

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IRF7832Z
10 1600
RDS(on), Drain-to -Source On Resistance (m Ω)

ID = 21A

EAS , Single Pulse Avalanche Energy (mJ)

ID
1400 TOP 1.0A
1.4A
8 1200 BOTTOM 16A

1000

6 800
T J = 125°C
600

4 T J = 25°C 400

200

2 0
2 4 6 8 10 25 50 75 100 125 150

VGS, Gate -to -Source Voltage (V) Starting T J , Junction Temperature (°C)

Fig 12. On-Resistance vs. Gate Voltage Fig 13. Maximum Avalanche Energy
vs. Drain Current
Current Regulator
Same Type as D.U.T.
V(BR)DSS
15V tp 50KΩ

12V .2µF
.3µF
L DRIVER
VDS
+
V
D.U.T. - DS
RG D.U.T +
- VDD
IAS A
VGS
20V
VGS
tp 0.01Ω
I AS 3mA

IG ID
Fig 14. Unclamped Inductive Test Circuit Current Sampling Resistors
and Waveform
LD Fig 15. Gate Charge Test Circuit
VDS
VDS
+ 90%
VDD -

D.U.T
10%
VGS
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
td(on) tr td(off) tf

Fig 16. Switching Time Test Circuit Fig 17. Switching Time Waveforms
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 IRF7832Z
Driver Gate Drive
P.W.
D.U.T P.W.
Period D=
Period
+

VGS=10V *
ƒ Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance
D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG V DD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 18. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

Id
Vds

Vgs

Vgs(th)

Qgs1 Qgs2 Qgd Qgodr

Fig 19. Gate Charge Waveform

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IRF7832Z
Power MOSFET Selection for Non-Isolated DC/DC Converters

Control FET Synchronous FET

Special attention has been given to the power losses The power loss equation for Q2 is approximated
in the switching elements of the circuit - Q1 and Q2. by;
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the Ploss = Pconduction + Pdrive + Poutput
*
MOSFET, but these conduction losses are only about
one half of the total losses.

Power losses in the control switch Q1 are given

( 2
Ploss = Irms × Rds(on) )
by; + (Qg × Vg × f )
⎛Q ⎞
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput + ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2 ⎠
This can be expanded and approximated by;
*dissipated primarily in Q1.
Ploss = (Irms 2 × Rds(on ) )
For the synchronous MOSFET Q2, Rds(on) is an im-
⎛ Qgd ⎞ ⎛ Qgs 2 ⎞ portant characteristic; however, once again the im-
+⎜I × × Vin × f ⎟ + ⎜ I × × Vin × f ⎟ portance of gate charge must not be overlooked since
⎝ ig ⎠ ⎝ ig ⎠ it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
+ (Qg × Vg × f ) trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
⎛ Qoss
+ × Vin × f ⎞ verse recovery charge Qrr both generate losses that
⎝ 2 ⎠ are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
This simplified loss equation includes the terms Qgs2 MOSFETs’ susceptibility to Cdv/dt turn on.
and Qoss which are new to Power MOSFET data sheets. The drain of Q2 is connected to the switching node
Qgs2 is a sub element of traditional gate-source of the converter and therefore sees transitions be-
charge that is included in all MOSFET data sheets. tween ground and Vin. As Q1 turns on and off there is
The importance of splitting this gate-source charge a rate of change of drain voltage dV/dt which is ca-
into two sub elements, Qgs1 and Qgs2, can be seen from pacitively coupled to the gate of Q2 and can induce
Fig 16. a voltage spike on the gate that is sufficient to turn
Qgs2 indicates the charge that must be supplied by the MOSFET on, resulting in shoot-through current .
the gate driver between the time that the threshold The ratio of Qgd/Qgs1 must be minimized to reduce the
voltage has been reached and the time the drain cur- potential for Cdv/dt turn on.
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
Figure A: Qoss Characteristic
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 IRF7832Z
SO-8 Package Outline (Dimensions are shown in millimeters (inches)

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SO-8 Part Marking

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IRF7832Z
SO-8 Tape and Reel
Dimensions are shown in millimeters (inches)

TERMINAL NUMBER 1

12.3 ( .484 )
11.7 ( .461 )

8.1 ( .318 )
7.9 ( .312 ) FEED DIRECTION

NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

330.00
(12.992)
MAX.

14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.

Notes:
 Repetitive rating; pulse width limited by max. junction temperature.
‚ Starting TJ = 25°C, L = 2.7mH, RG = 25Ω, IAS = 16A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ When mounted on 1 inch square copper board.
… Rθ is measured at T J of approximately 90°C.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.06/05
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