CO Unit 2

Unit 2
The Processor
§4.1 Introduction
Introduction
 CPU performance factors
 Instruction count
 Determined by ISA and compiler
 CPI(clock cycles per Instn) and Cycle time
 Determined by CPU hardware
 We will examine two MIPS implementations
 A simplified version
 A more realistic pipelined version
 Simple subset, shows most aspects
 Memory reference: LW, SW
 Arithmetic/logical: add, sub, and, or, slt
 Control transfer: beq, j
Chapter 4 — The Processor — 2

Instruction Execution
 PC  instruction memory, fetch instruction
 Read registers
 Depending on instruction class
 Use ALU to calculate (except jump)
 Arithmetic result
 Memory address for load/store
 Branch target address
 Access data memory for load/store
 PC  target address or PC + 4

CPU Overview

Multiplexers(data selectors)
 Can’t just join
wires together
 Use multiplexers

Control
Control unit has

1.Instn as I/p
2.Determine how to set ctrl
lines for funtional units &
Mux
Ex: PC+4 determined by 0
from ALU & Used to perform
the comparison of Beq Chapter 4 — The Processor — 6
§4.2 Logic Design Conventions
Logic Design Basics
 Information encoded in binary
 Low voltage = 0, High voltage = 1
 One wire per bit
 Multi-bit data encoded on multi-wire buses
 MIPS Data Path has two Logic elements
 1. Combinational element
 Operate on data
 Output is a function of input
 No storage so for a given set of I/ps it always produces same o/p
 2. State (sequential) elements (Memory/Register)
 Store information (atleast 2 I/ps & one o/p)
Combinational Elements
 AND-gate  Adder A
Y
+
 Y=A&B  Y=A+B B
 Arithmetic/Logic Unit
 Multiplexer  Y = F(A, B)
 Y = S ? I1 : I0
A
I0 M
u Y ALU Y
I1 x
B
S F

Sequential Elements
 Register: stores data in a circuit – D flip flop
 Uses a clock signal to determine when to write the
stored value, state elmt can read at any time
 Edge-triggered: update when Clk changes from 0
to 1
 Asserted – logically high , deassert - low
Clk
D Q
D
Clk
Q

Sequential Elements
 Register with write control
 Only updates on clock edge when write control
input is 1(asserted)
 Used when stored value is required later
Clk
D Q Write
Write D
Clk
Q

Clocking Methodology
 Combinational logic transforms data during clock cycles ( read & write )
 Ensures predictablity
specify timings for read & write
– If both R/W at same time – value of read may correspond to a old value
– prevents
– Hence follows Edge triggering
 Between clock edges
 Input from state elements, output to state element (Length of Clock
cycle)
 Longest delay determines clock period
No feedback with in the same

←------------------------------------> clock cycle hence can be
Clock cycle (length) represented
32 bits wide (thicker lines)
Color – Ctrl lines Chapter 4 — The Processor — 11
§4.3 Building a Datapath
Building a Datapath
 Datapath
 Elements that process data and addresses
in the CPU
 Registers, ALUs, mux’s, memories, …
 We will build a MIPS datapath
incrementally
 Refining the overview design

Instruction Fetch
Require
Two state elements
Instruction Memory (Read access)
PC (32 bit)
Adder (Adds 32 bit and o/p sum)
Instruction Fetch
Increment by
4 for next
32-bit instruction
register

R-Format Instructions
 Read two register operands
 Perform arithmetic/logical operation
 Write register result
 Also called as arithmetic logic instn(add,sub,add,or,slt)
 CPU's 32 General purpose R are stored in a structure called
Register File

Load/Store Instructions
 LDR R2,R1,#Offset | STR R2,R1,#offset
 Read register operands
 Calculate address using 16-bit offset
 Use ALU, but sign-extend offset
 Load: Read memory and update register
 Store: Write register value to memory
To increase the
size by
replicating higher
order signbit

Branch Instructions
 Read register operands
 Compare operands
 Use ALU, subtract and check Zero output
 Calculate target address
 Sign-extend displacement
 Shift left 2 places (word displacement)
 Add to PC + 4
 Already calculated by instruction fetch

Delayed Branching
Instructions immediately following the
Branch Instructions branch is always executed independent of
whether the branch condition is true / false
Just
re-routes
wires
16 32 Replacing lower 28 bits of PC

with lower 26 bits of Instruction
ShIft lefted by 2 bits.

Composing the Elements
 First-cut data path does an instruction in
one clock cycle
 Each datapath element can only do one
function at a time
 Hence, we need separate instruction and data
memories
 Use multiplexers where alternate data
sources are used for different instructions

R-Type/Load/Store Datapath
Single Data path construction
Does dataprocessing
That uses single Register file & Single ALU Along with functional units

Full Datapath
COMBINES
Instruction fetch, Rtype, Memory operations, branches

§4.4 A Simple Implementation Scheme
ALU Control
 ALU used for
 Load/Store: F = add
 Branch: F = subtract
 R-type: F depends on opcode (And,or,sub,add,slt)
ALU control Function
0000 AND
0001 OR

6 4
ALU Control
2-bit ALUOp derived from opcode & 6 BIT Function field to derive 4 bit alu ctrl
 Combinational logic derives ALU control
opcode ALUOp Operation Funct field ALU function ALU control
LW 00 load register XXXXXX add 0010
SW 00 store register XXXXXX add 0010
Branch equal 01 Branch equal XXXXXX subtract 0110

Truth table for 4 bit ALU
I/P ALU op & Funct Fields – to get the
desired O/P
X- Dont care
Then turned into gates – Completely

Mechanical
The Main Control Unit
 Control signals derived from instruction
Observations on the Instruction format (MIPS)

1. Op field (Opcode) in 31:26
2.Registers to be read rs,rt are in 25:21 & 20:16
3.Base register for load & store is in 25:21
4.16 bit offset is in bit position 15:0
5.Destination in two places . For load in rt 20:16 & for R type it is in 15:11
Datapath With Control

R-Type Instruction
Four Steps to
Exec (In one
clock cycle)
1. Instruction
fetched , PC
incremented
2.Reg t2,t3
read
3.Alu Operates
4.Results of
ALU written to
T1.
Load Instruction

BEQ Instruction

Implementing Uncnd’l Branch
Jump 2 address
31:26 25:0
 Jump uses word address

 Update PC with concatenation of
 Top 4 bits of old PC (31:28 bits seq following
instr address)
 26-bit jump address
 00 (Lower order always )
 Need an extra control signal decoded from
opcode( opcode 2 -000010)
Datapath With jump Added
Instruction [25– 0] Shift Jump address [31– 0]
left 2
26 28 0 1
PC+4 [31– 28] M M

u u
x x
ALU
Add result 1 0
Add Shift
RegDst
Jump left 2
4 Branch
MemRead
Instruction [31– 26]
Control MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Instruction [25– 21] Read

Read register 1
PC address Read
Instruction [20– 16] data 1
Read
register 2 Zero
Instruction 0 Registers Read ALU ALU
[31– 0] 0 Read
M Write data 2 result Address 1
Instruction u register M data
u M
memory Instruction [15– 11] x u
1 Write x Data
data x
1 memory 0
Write
data
16 32
Instruction [15– 0] Sign
extend ALU
Additional Mux to choose either control
Instruction [5– 0]
branch /jump target

Performance Issues
 Longest delay determines clock period
 Critical path: load instruction
 Instruction memory  register file  ALU 
data memory  register file
 Not feasible to vary period for different
instructions
 Violates design principle
 Making the common case fast
 We will improve performance by pipelining

§4.5 An Overview of Pipelining
Pipelining Analogy
 Pipelined laundry: overlapping execution
 Parallelism improves performance
 Four loads:
 Speedup = non piplined/pipelined
 n*k*tp / (n+k-1)*tp
 4*4*0.5/(4+4-1)0.5
= 8/3.5 = 2.3 faster
 Start up & wind down
problem affects (pipeline
not full)
•Non-stop: Speeds up
 If loads are more, then equal to
stages
= n*k/n (if n is more) so equal to
K stage
= number of stages

Pipeline
 Five stages, one step per stage
1. IF: Instruction fetch from memory
2. ID: Instruction decode & register read
3. EX: Execute operation or calculate address
4. MEM: Access memory operand
5. WB: Write result back to register

Pipeline

Performance
Assume time for stages is
 100ps for register read or write
 200ps for other stages
 Compare pipelined datapath with single-cycle datapath
Instr Instr fetch Register

read ALU op Memory
access Register
write Total time
LW 200ps 100 ps 200ps 200ps 100 ps 800ps
SW 200ps 100 ps 200ps 200ps 700ps

Pipeline Performance Single-cycle (Tc= 800ps)
Pipelined (Tc= 200ps)

Pipeline Speedup
 If all stages are balanced
 i.e., all take the same time
 Time between instructionspipelined
= Time between instructionsnonpipelined
Number of stages
 If not balanced, speedup is less
 Speedup due to increased throughput
 Latency (time for each instruction) does not
decrease

Pipelining and ISA Design
 ARM designed for pipelining
 All instructions are 32-bits
 Easier to fetch and decode in one cycle
 Few and regular instruction formats

 Can decode and read registers in one step
 Load/store addressing
 Can calculate address in 3rd stage, access memory
in 4th stage
 Alignment of memory operands
 Memory access takes only one cycle

Hazards
 Situations that prevent starting the next
instruction in the next cycle
 Structure hazards
 A required resource is busy
 Data hazard
 Need to wait for previous instruction to
complete its data read/write
 Control hazard
 Deciding on control action depends on
previous instruction

Structure Hazards
 Conflict for use of a resource
 In pipeline with a single memory
 Load/store requires data access
 Instruction fetch would have to stall for that
cycle
 Would cause a pipeline “bubble”
 Hence, pipelined datapaths require
separate instruction/data memories
 Or separate instruction/data caches

Data Hazards
 An instruction depends on completion of
data access by a previous instruction
 ADD X19, X0, X1
SUB X2, X19, X3

Forwarding ( Bypassing)
 Use result when it is computed
 Don’t wait for it to be stored in a register
 Requires extra connections in the datapath

Load-Use Data Hazard
 Can’t always avoid stalls by forwarding
 If value not computed when needed
 Can’t forward backward in time!

Code Scheduling to Avoid Stalls
 Reorder code to avoid use of load result in
the next instruction
 C code for A = B + E; C = B + F;
LDUR X1, [X0,#0] LDUR X1, [X0,#0]

LDUR X2, [X0,#8] LDUR X2, [X0,#8]
stall ADD X3, X1, X2 LDUR X4, [X0,#16]
STUR X3, [X0,#24] ADD X3, X1, X2
LDUR X4, [X0,#16] STUR X3, [X0,#24]
stall ADD X5, X1, X4 ADD X5, X1, X4
STUR X5, [X0,#32] STUR X5, [X0,#32]
Lesser by 2 cycles

Control Hazards
 Branch determines flow of control
 Fetching next instruction depends on branch
outcome
 Pipeline can’t always fetch correct instruction
 Still working on ID stage of branch(Predict)
 In pipeline
 Need to compare registers and compute target
early in the pipeline
 Add hardware to do it in ID stage

Stall on Branch
Predict not
taken as
solution

Branch Prediction
 Longer pipelines can’t readily determine
branch outcome early
 Stall penalty becomes unacceptable
 Predict outcome of branch
 Only stall if prediction is wrong
 In pipeline
 Can predict branches not taken
 Fetch instruction after branch, with no delay

More-Realistic Branch Prediction
 Static branch prediction
 Based on typical branch behavior
 Example: loop and if-statement branches
 Predict backward branches taken
 Predict forward branches not taken
 Dynamic branch prediction
 Hardware measures actual branch behavior
 e.g., record recent history of each branch
 Assume future behavior will continue the trend
 When wrong, stall while re-fetching, and update history

Pipeline Summary
The BIG Picture
 Pipelining improves performance by
increasing instruction throughput
 Executes multiple instructions in parallel
 Each instruction has the same latency
 Subject to hazards
 Structure, data, control
 Instruction set design affects complexity of
pipeline implementation
§4.6 Pipelined Datapath and Control
single Pipelined Datapath
MEM
Right-to-left
flow leads to WB
hazards
2 stages: PC
inc &
Register
Write Chapter 4 — The Processor — 51
Pipeline registers
 Need registers between stages(64,128,97,64 bits)
 To hold information produced in previous cycle

Pipeline Operation
 Cycle-by-cycle flow of instructions through
the pipelined datapath
 “Single-clock-cycle” pipeline diagram
 Shows pipeline usage in a single cycle
 Highlight resources used
 Compare “multi-clock-cycle” diagram
 Graph of operation over time
 We’ll look at “single-clock-cycle” diagrams
for load & store

IF for Load, Store, …
Left half to indicate write

Right half for read
ID for Load, Store, …

EX for Load

MEM for Load

WB for Load
Wrong
register
number

Corrected Datapath for Load

EX for Store

MEM for Store

WB for Store

Multi-Cycle Pipeline Diagram
 Form showing resource usage

Multi-Cycle Pipeline Diagram
 Traditional form

Single-Cycle Pipeline Diagram
 State of pipeline in a given cycle

Pipelined Control
 Control signals derived from instruction
 As in single-cycle implementation

Pipelined Control (Simplified)

§4.7 Data Hazards: Forwarding vs. Stalling
Data Hazards in ALU Instructions
 Consider this sequence:
SUB X2, X1,X3
AND X12,X2,X5
OR X13,X6,X2
ADD X14,X2,X2
STUR X15,[X2,#100]
 We can resolve hazards with forwarding

 How do we detect when to forward?

Detecting the Need to Forward
 Pass register numbers along pipeline
 e.g., ID/EX.RegisterRs = register number for Rs sitting in
ID/EX pipeline register

 ALU operand register numbers in EX stage are given by
 ID/EX.RegisterRs, ID/EX.RegisterRt
 Data hazards when Fwd from

1a. EX/MEM.RegisterRd = ID/EX.RegisterRs EX/MEM
pipeline reg
1b. EX/MEM.RegisterRd = ID/EX.RegisterRt
Fwd from
2a. MEM/WB.RegisterRd = ID/EX.RegisterRs MEM/WB
2b. MEM/WB.RegisterRd = ID/EX.RegisterRt pipeline reg
Above example
Sub & and hazard 1a.
EX/MEM.RegisterRd= ID/EX.RegisterRs = X2
Similary
Sub – or hazard 2b.
MEM/WB.RegisterRd = ID/EX.RegisterRt= X2 Chapter 4 — The Processor — 69
Dependencies & Forwarding

Detecting the Need to Forward
 But only if forwarding instruction will write
to a register!
 EX/MEM.RegWrite, MEM/WB.RegWrite
 And only if Rd for that instruction is not

(ex:sll $0,$1,1$2) every use of $0 must
yield value 0 – so avoid forwarding a
non zero value)
 EX/MEM.RegisterRd ≠ 0,
MEM/WB.RegisterRd ≠ 0
Forwarding Paths

Forwarding Conditions
Mux control Source Explanation
ForwardA = 00 ID/EX The first ALU operand comes from the register file.
ForwardA = 10 EX/MEM The

ALU first ALU operand is forwarded from the prior
result.
ForwardA = 01 MEM/WB The first ALU

memory or anoperand
earlier is Chapter
forwarded from
4 — The data — 73
Processor
ALU result.
Control signal
Double Data Hazard
 Consider the sequence:
add $1,$1,$2
add $1,$1,$3
add $1,$1,$4
 Both hazards occur
 Want to use the most recent
 Revise MEM hazard condition
 Only fwd if EX hazard condition isn’t true

Revised Forwarding Condition
 MEM hazard Check if not Ex/Mem
 if (MEM/WB.RegWrite
and (MEM/WB.RegisterRd ≠ 0)
and not(EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)
and (EX/MEM.RegisterRd ≠ ID/EX.RegisterRs))
and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01
 if (MEM/WB.RegWrite
and (MEM/WB.RegisterRd ≠ 0)
and not(EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)
and (EX/MEM.RegisterRd ≠ ID/EX.RegisterRt))
and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01

Datapath with Forwarding

Load-Use Hazard Detection
 Check when using instruction is decoded
in ID stage
 ALU operand register numbers in ID stage
are given by
 IF/ID.RegisterRt, IF/ID.RegisterRs
 Load-use hazard when
 ID/EX.MemRead and
((ID/EX.RegisterRt = IF/ID.RegisterRs) or
(ID/EX.RegisterRt = IF/ID.RegisterRt))
 If detected, stall and insert bubble

How to Stall the Pipeline
 Force control values in ID/EX register
to 0
 EX, MEM and WB do nop (no-operation)
 Prevent update of PC and IF/ID register
 Using instruction is decoded again
 Following instruction is fetched again
 1-cycle stall allows MEM to read data for LDUI
 Can subsequently forward to EX stage

Load-Use Data Hazard
Stall inserted here

Datapath with Hazard Detection

Stalls and Performance
The BIG Picture
 Stalls reduce performance
 But are required to get correct results
 Compiler can arrange code to avoid
hazards and stalls
 Requires knowledge of the pipeline structure

§4.8 Control Hazards
Branch Hazards
 If branch outcome determined in MEM
Flush these
instructions
(Set control
values to 0)
PC

Reducing Branch Delay
 Move hardware to determine outcome to ID
stage
 Target address adder
 Register comparator
 Example: branch taken
36: SUB X10, X4, X8
40: beq X1, X3, 7 //PC relative branching 40+4 + 7*4 =72
44: AND X12, X2, X5

48: ORR X13, X2, X6
52: ADD X14, X4, X2
56: SUB X15, X6, X7
...
72: LDUR X4, [X7,#50]

Example: Branch Taken

Example: Branch Taken

Dynamic Branch Prediction
 In deeper and superscalar pipelines, branch
penalty is more significant
 Use dynamic prediction
 Branch prediction buffer (aka branch history table)
 Indexed by recent branch instruction addresses
 Stores outcome (taken/not taken)
 To execute a branch
 Check table, expect the same outcome
 Start fetching from fall-through or target
 If wrong, flush pipeline and flip prediction

1-Bit Predictor: Shortcoming
 Inner loop branches mispredicted twice!
outer: …
…
inner: …
…
beq …, …, inner
…
beq …, …, outer
 Mispredict as taken on last iteration of inner

loop
 Then mispredict as not taken on first
iteration of inner loop next time around
2-Bit Predictor
 Only change prediction on two successive
mispredictions

Calculating the Branch Target
 Even with predictor, still need to calculate
the target address
 1-cycle penalty for a taken branch
 Branch target buffer
 Cache of target addresses
 Indexed by PC when instruction fetched
 If hit and instruction is branch predicted taken, can
fetch target immediately

§4.9 Exceptions
Exceptions and Interrupts
 “Unexpected” events requiring change
in flow of control
 Different ISAs use the terms differently
 Exception
 Arises within the CPU
 e.g., undefined opcode, overflow, syscall, …
 Interrupt
 From an external I/O controller
 Dealing with them without sacrificing
performance is hard

Handling Exceptions
 Save PC of offending (or interrupted) instruction
 In Exception Link Register (ELR)
 Save indication of the problem

 In Exception Syndrome Rregister (ESR)
 We’ll assume 1-bit
 0 for undefined opcode, 1 for overflow

An Alternate Mechanism
 Vectored Interrupts
 Handler address determined by the cause
 Exception vector address to be added to a
vector table base register:
 Unknown Reason: 00 0000two
 Overflow: 10 1100two
 …: 11 1111two
 Instructions either
 Deal with the interrupt, or
 Jump to real handler
Handler Actions
 Read cause, and transfer to relevant
handler
 Determine action required
 If restartable
 Take corrective action
 use EPC (Exception Program Counter) to
return to program
 Otherwise
 Terminate program
 Report error using EPC, cause, …

Exceptions in a Pipeline
 Another form of control hazard
 Consider overflow on add in EX stage
ADD X1, X2, X1
 Prevent X1 from being clobbered
 Complete previous instructions
 Flush add and subsequent instructions
 Set ESR and ELR register values
 Transfer control to handler
 Similar to mispredicted branch

 Use much of the same hardware
Pipeline with Exceptions

Exception Properties
 Restartable exceptions
 Pipeline can flush the instruction
 Handler executes, then returns to the
instruction
 Refetched and executed from scratch
 PC saved in ELR register
 Identifies causing instruction
 Actually PC + 4 is saved
 Handler must adjust

Exception Example
 Exception on ADD in
40 SUB X11, X2, X4
44 AND X12, X2, X5
48 ORR X13, X2, X6
4C ADD X1, X2, X1
50 SUB X15, X6, X7
54 LDUR X16, [X7,#100]
…
 Handler
80000180 SW $26, [X0,#1000]
80000184 Sw X27, [X0,#1008]
…

Exception Example

Exception Example

Multiple Exceptions
 Pipelining overlaps multiple instructions
 Could have multiple exceptions at once
 Simple approach: deal with exception from
earliest instruction
 Flush subsequent instructions
 “Precise” exceptions
 In complex pipelines
 Multiple instructions issued per cycle
 Out-of-order completion
 Maintaining precise exceptions is difficult!

Imprecise Exceptions
 Just stop pipeline and save state
 Including exception cause(s)
 Let the handler work out
 Which instruction(s) had exceptions
 Which to complete or flush
 May require “manual” completion
 Simplifies hardware, but more complex handler
software
 Not feasible for complex multiple-issue
out-of-order pipelines

§4.10 Parallelism via Instructions
Instruction-Level Parallelism (ILP)
 Pipelining: executing multiple instructions in
parallel
 To increase ILP
 Deeper pipeline
 Less work per stage  shorter clock cycle
 Multiple issue
 Replicate pipeline stages  multiple pipelines
 Start multiple instructions per clock cycle
 CPI < 1, so use Instructions Per Cycle (IPC)
 E.g., 4GHz 4-way multiple-issue
 16 BIPS, peak CPI = 0.25, peak IPC = 4
 But dependencies reduce this in practice

Multiple Issue
 Static multiple issue
 Compiler groups instructions to be issued together
 Packages them into “issue slots”
 Compiler detects and avoids hazards
 Dynamic multiple issue
 CPU examines instruction stream and chooses
instructions to issue each cycle
 Compiler can help by reordering instructions
 CPU resolves hazards using advanced techniques at
runtime

Speculation
 “Guess” what to do with an instruction
 Start operation as soon as possible
 Check whether guess was right
 If so, complete the operation
 If not, roll-back and do the right thing
 Common to static and dynamic multiple issue
 Examples
 Speculate on branch outcome
 Roll back if path taken is different
 Speculate on load
 Roll back if location is updated

Compiler/Hardware Speculation
 Compiler can reorder instructions
 e.g., move load before branch
 Can include “fix-up” instructions to recover
from incorrect guess
 Hardware can look ahead for instructions
to execute
 Buffer results until it determines they are
actually needed
 Flush buffers on incorrect speculation

Speculation and Exceptions
 What if exception occurs on a
speculatively executed instruction?
 e.g., speculative load before null-pointer check
 Static speculation
 Can add ISA support for deferring exceptions
 Dynamic speculation
 Can buffer exceptions until instruction
completion (which may not occur)

Static Multiple Issue
 Compiler groups instructions into “issue
packets”
 Group of instructions that can be issued on a
single cycle
 Determined by pipeline resources required
 Think of an issue packet as a very long
instruction
 Specifies multiple concurrent operations
  Very Long Instruction Word (VLIW)

Scheduling Static Multiple Issue
 Compiler must remove some/all hazards
 Reorder instructions into issue packets
 No dependencies with a packet
 Possibly some dependencies between
packets
 Varies between ISAs; compiler must know!
 Pad with nop if necessary

Static Dual Issue
 Two-issue packets
 One ALU/branch instruction
 One load/store instruction
 64-bit aligned
 ALU/branch, then load/store
 Pad an unused instruction with nop
Address Instruction type Pipeline Stages
n ALU/branch IF ID EX MEM WB
n+4 Load/store IF ID EX MEM WB

Static Multiple Issue

Hazards in the Multiple-Issue
 More instructions executing in parallel
 EX data hazard
 Forwarding avoided stalls with single-issue
 Now can’t use ALU result in load/store in same packet
 ADD X0, X0, X1
LDUR X2, [X0,#0]
 Split into two packets, effectively a stall
 Load-use hazard
 Still one cycle use latency, but now two instructions
 More aggressive scheduling required

Scheduling Example
Loop: LDUR X0, [X20,#0] // X0=array element
ADD X0, X0,X21 // add scalar in X21
STUR X0, [X20,#0] // store result
SUBI X20, X20,#4 // decrement pointer
CMP X20, X22 // branch $s1!=0
BGT Loop
ALU/branch Load/store cycle
Loop nop LDUR X0, [X20,#0] 1

:
 IPC =SUBI
7/6X20,
= 1.17
X20,#4
(c.f.noppeak IPC = 2) 2
Loop Unrolling
 Replicate loop body to expose more
parallelism
 Reduces loop-control overhead
 Use different registers per replication
 Called “register renaming”
 Avoid loop-carried “anti-dependencies”
 Store followed by a load of the same register
 Aka “name dependence”
 Reuse of a register name

Loop Unrolling Example
ALU/branch Load/store cycle
Loop: SUBI X20, X20,#32 LDUR X0, [X20,#0] 1
 IPC = nop
15/8 = 1.875 LDUR X1, [X20,#24] 2
 Closer to 2, but at cost of registers and code size
ADD X0, X0, X21 LDUR X2, [X20,#16] 3

Dynamic Multiple Issue
 “Superscalar” processors
 CPU decides whether to issue 0, 1, 2, …
each cycle
 Avoiding structural and data hazards
 Avoids the need for compiler scheduling
 Though it may still help
 Code semantics ensured by the CPU

Dynamic Pipeline Scheduling
 Allow the CPU to execute instructions out
of order to avoid stalls
 But commit result to registers in order
 Example
LDUR X0, [X21,#20]
ADD X1, X0, X2
SUB X23,X23,X3
ANDI X5, X23,#20
 Can start sub while ADD is waiting for LDUI

Dynamically Scheduled CPU
Preserves
dependencies
Hold pending
operands
Results also sent

to any waiting
reservation stations
Reorders buffer for

register writes
Can supply
operands for
issued instructions

Register Renaming
 Reservation stations and reorder buffer
effectively provide register renaming
 On instruction issue to reservation station
 If operand is available in register file or reorder
buffer
 Copied to reservation station
 No longer required in the register; can be
overwritten
 If operand is not yet available
 It will be provided to the reservation station by a
function unit
 Register update may not be required
Speculation
 Predict branch and continue issuing
 Don’t commit until branch outcome determined
 Load speculation
 Avoid load and cache miss delay
 Predict the effective address
 Predict loaded value
 Load before completing outstanding stores
 Bypass stored values to load unit
 Don’t commit load until speculation cleared

Why Do Dynamic Scheduling?
 Why not just let the compiler schedule
code?
 Not all stalls are predicable
 e.g., cache misses
 Can’t always schedule around branches
 Branch outcome is dynamically determined
 Different implementations of an ISA have
different latencies and hazards

Does Multiple Issue Work?
The BIG Picture
 Yes, but not as much as we’d like
 Programs have real dependencies that limit ILP
 Some dependencies are hard to eliminate
 e.g., pointer aliasing
 Some parallelism is hard to expose
 Limited window size during instruction issue
 Memory delays and limited bandwidth
 Hard to keep pipelines full
 Speculation can help if done well
Power Efficiency
 Complexity of dynamic scheduling and
speculations requires power
 Multiple simpler cores may be better
Microprocessor Year Clock Rate Pipeline

Stages Issue
width Out-of-order/
Speculation Cores Power
i486 1989 25MHz 5 1 No 1 5W
Pentium 1993 66MHz 5 2 No 1 10W

§4.11 Real Stuff: The ARM Cortex-A8 and Intel Core i7 Pipelines
Cortex A53 and Intel i7
Processor ARM A53 Intel Core i7 920
Market Personal Mobile Device Server, cloud
Thermal design power (1100

coremilliWatts
@ 1 GHz) 130 Watts
Clock rate 1.5 GHz Chapter 42.66 GHz

— The Processor — 125

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Unit 2

Chapter 4 — The Processor — 2

Chapter 4 — The Processor — 3

Chapter 4 — The Processor — 4

Chapter 4 — The Processor — 5

Control unit has

Chapter 4 — The Processor — 8

Chapter 4 — The Processor — 9

Chapter 4 — The Processor — 10

No feedback with in the same

Chapter 4 — The Processor — 12

Chapter 4 — The Processor — 14

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Chapter 4 — The Processor — 17

16 32 Replacing lower 28 bits of PC

Chapter 4 — The Processor — 18

Chapter 4 — The Processor — 19

Chapter 4 — The Processor — 20

Chapter 4 — The Processor — 21

ALU control Function

Chapter 4 — The Processor — 22

opcode ALUOp Operation Funct field ALU function ALU control

LW 00 load register XXXXXX add 0010

SW 00 store register XXXXXX add 0010

Branch equal 01 Branch equal XXXXXX subtract 0110

Chapter 4 — The Processor — 24

Then turned into gates – Completely

Observations on the Instruction format (MIPS)

Chapter 4 — The Processor — 27

Chapter 4 — The Processor — 29

Chapter 4 — The Processor — 30

 Jump uses word address

PC+4 [31– 28] M M

Instruction [25– 21] Read

Chapter 4 — The Processor — 32

Chapter 4 — The Processor — 33

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Chapter 4 — The Processor — 35

Instr Instr fetch Register

LW 200ps 100 ps 200ps 200ps 100 ps 800ps

SW 200ps 100 ps 200ps 200ps 700ps

Chapter 4 — The Processor — 36

Pipelined (Tc= 200ps)

Chapter 4 — The Processor — 37

Chapter 4 — The Processor — 38

 Few and regular instruction formats

Chapter 4 — The Processor — 39

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LDUR X1, [X0,#0] LDUR X1, [X0,#0]

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