CDC 3217G-C Automotive Controller: Micronas

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ADVANCE INFORMATION

CDC 3217G-C
Automotive Controller

Edition Feb. 18, 2005


6251-670-1AI MICRONAS

Downloaded from Arrow.com.


CDC 3217G-C ADVANCE INFORMATION

Contents

Page Section Title

3 1. Introduction
3 1.1. Features
6 1.2. Abbreviations
7 1.3. Block Diagram

9 2. Packages and Pins


9 2.1. Package Outline Dimensions
10 2.2. Pin Assignment
10 2.3. Pin Function Description
11 2.4. External Components

13 3. Electrical Data
13 3.1. Absolute Maximum Ratings
14 3.2. Recommended Operating Conditions
15 3.3. Characteristics
17 3.4. Recommended Quartz Crystal Characteristics

19 4. CPU and Clock System

21 5. Memory and Special Function ROM (SFR) System

23 6. Core Logic
23 6.1. Control Word (CW)

25 7. Hardware Options
25 7.1. Functional Description

26 8. Data Sheet History

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ADVANCE INFORMATION CDC 3217G-C

1. Introduction
The chip contains timer/counters, an interrupt controller, a
multichannel A/D converter, a stepper motor and LCD driver,
CAN interfaces, PWM outputs and a crystal clock multiplying
PLL.
The device is a microcontroller for use in automotive applica-
tions. The on-chip CPU is an ARM processor ARM7TDMI This document provides MCM Flash hardware-specific infor-
with 32-bit data and address bus, which supports Thumb mation. General information on operating the IC can be
format instructions. found in the document “CDC32xxG-C Automotive Controller
- Family User Manual, CDC3205G-C Automotive Controller”
(6251-579-1DS)”.

1.1. Features

Table 1–1: CDC32xxG-C Family Feature List

This
Device:

Item CDC3205G- CDC3207G- CDC3217G- CDC3257G- CDC3272G- CDC3231G-


C C C C2 C C
EMU MCM Flash MCM Flash MCM Flash Mask ROM Mask ROM

Core

CPU 32-bit ARM7TDMI

CPU-active operation modes DEEP SLOW, SLOW, FAST and PLL

Power-saving operation modes IDLE, WAKE and STANDBY


(CPU inactive)

CPU clock multiplication PLL delivering up to 50 MHz

EMI reduction mode selectable in PLL mode

Oscillators 4 to 5 MHz quartz and 32 kHz internal RC

RAM, zero wait state, 32 bit wide 32 Kbyte 12 Kbyte 16 Kbyte 6 Kbyte

ROM ROMless, 512-Kbyte 1024-Kbyte 256-Kbyte 384 Kbyte 128 Kbyte


ext. up to Flash Flash Flash (96 K × 32/ (32 K × 32/
4 M × 32/ (256 K × 16) (512 K × 16) (128 K × 16) 192 K × 16) 64 K × 16)
8 M × 16 top-boot top-boot top-boot
conf. conf. conf.

Boot ROM 8 Kbyte (special function ROM)

Digital watchdog ✔

Central clock divider ✔

Interrupt controller expanding 40 inputs, 16 priority levels 26 inputs,


IRQ 16 priority
levels

Port interrupts including slope 6 inputs 5 inputs


selection

Port wake-up inputs including 10 inputs


slope/level selection

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CDC 3217G-C ADVANCE INFORMATION

Table 1–1: CDC32xxG-C Family Feature List

This
Device:

Item CDC3205G- CDC3207G- CDC3217G- CDC3257G- CDC3272G- CDC3231G-


C C C C2 C C
EMU MCM Flash MCM Flash MCM Flash Mask ROM Mask ROM

Patch module 10 ROM locations

Boot system allows in-system downloading of external code to Flash -


memory via JTAG

Device lock module inhibits access to internal firmware, lock can be set by -
customer

Analog

Reset/Alarm combined input for regulator input supervision

Clock and supply supervision ✔

10-bit ADC, charge balance type 16 channels (each selectable as digital input)

ADC reference VREF pin, P1.0 pin, P1.1 pin or VREFINT internal bandgap selectable

Comparators P06COMP with 1/2 AVDD reference,


WAITCOMP with internal bandgap reference

LCD internal processing of all analog voltages for the LCD driver

Communication

DMA 3 DMA channels, one each for serving the graphics bus interface, SPI0 -
and SPI1

UART 2: UART0 and UART1 UART0

Synchronous serial peripheral 2: SPI0 and SPI1, DMA supported


interfaces

Full CAN modules V2.0B 4: CAN0, CAN1, CAN2 and CAN3 2: CAN0 and CAN1 1: CAN0
with a 32-objects’-RAM each
(LCAN000E)

DIGITbus 1 master module -

I2C 2 master modules: I2C0 and I2C1 I2C0

Graphics bus interface 8-bit data bus, DMA supported, e.g., for connection of EPSON SED 1560 -
LCD controller

Input & Output

Universal ports selectable as up to 52 I/O or 48 LCD segment lines (= 192 segments), up to 50 I/O
4:1-mux LCD segment/back- individually configurable as I/O or LCD or 46 LCD
plane lines or digital I/O ports segment
lines (= 184
segments)

Universal port slew rate SW-selectable

Stepper motor control modules 7 modules, 4 modules


with high-current ports 32 dI/dt-controlled ports 23 dI/dt-
controlled
ports

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ADVANCE INFORMATION CDC 3217G-C

Table 1–1: CDC32xxG-C Family Feature List

This
Device:

Item CDC3205G- CDC3207G- CDC3217G- CDC3257G- CDC3272G- CDC3231G-


C C C C2 C C
EMU MCM Flash MCM Flash MCM Flash Mask ROM Mask ROM

PWM modules, each config- 6 modules: PWM0/1, PWM2/3, PWM4/5, PWM6/7, PWM8/9 and PWM10/ 5 modules:
urable as two 8-bit PWMs or one 11 PWM0/1,
16-bit PWM PWM2/3,
PWM4/5,
PWM6/7,
PWM8/9

Pulse/frequency modulator 2: PFM0 and PFM1 -

Audio module with auto-decay ✔

SW-selectable clock outputs 2

Polling/flash timer output 1 high-current port output operable in power-saving operation modes

Timers & Counters

16-bit free-running counters with CCC0 with 4 CAPCOM CCC0 with


capture/compare modules CCC1 with 2 CAPCOM 4 CAPCOM

16-bit timers 1: T0

8-bit timers 4: T1, T2, T3 and T4

Real-time clock, delivering ✔


hours, minutes and seconds

Miscellaneous

Scalable layout in CAN, RAM - ✔


and ROM

Various HW options selectable set by copy from user program storage during system start-up
at random

JTAG interface allows Flash programming ✔ ✔

On-chip debug aids Embedded JTAG


trace mod-
ule, JTAG

Core bond-out ✔ -

Supply voltage 3.5 to 5.5 V (limited I/O performance below 4.5 V)

Case temperature range 0 °C to −40 °C to +105 °C


+70 °C

Package

Type ceramic plastic 128QFP


257PGA 0.5 mm pitch

Bonded pins 256 128 128 128 126 111

ARM and Thumb are the registered trademarks of ARM Limited.


ARM7TDMI is the trademark of ARM Limited.

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CDC 3217G-C ADVANCE INFORMATION

1.2. Abbreviations

ADC Analog-to-Digital Converter


AM Audio Module
CAN Controller Area Network
CAPCOM Capture/Compare
CCC Capture/Compare Counter
CPU Central Processing Unit
DMA Direct Memory Access
ERM EMI Reduction Mode
ETM Embedded Trace Module
I2C I2C Bus Interface
LCD Liquid Crystal Display
P06COMP P0.6 Alarm Comparator
PWM Pulse Width Modulator
SM Stepper Motor Control Module
SPI Serial Synchronous Peripheral Interface
T Timer
UART Universal Asynchronous Receiver/Transmitter
WAITCOMP Wait Comparator

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ADVANCE INFORMATION CDC 3217G-C

1.3. Block Diagram

FVDD UVDD VDD


FVSS UVSS VSS
Reset/Alarm RESETQ

3.3 V Reg. 2.5 V Reg. Test TEST


Watchdog TEST2
Clock
XTAL1
PLL/ERM XTAL2
RC Oscillator
WAIT 40-Input
WAITH Interrupt RTC
VREFINT ARM7TDMI Controller Power
VREF CPU Saving
AVDD 2.5 V Reg.
AVSS
BVDD JTAG Test
SRAM and Debug 5
8K x 32 Interface
PPort0

8
DMA Logic
PPort1

Flash

UPort0
8 32 16 512K x 16 8
Bridge
Memory
Controller Special
PPort2

Wait Comp.
2 Function
ROM

UPort1
4K x 16 8
P06 Comp.
Patch
10 Locations
HPort0

4 Bandgap Ref.

UPort2
Device Lock 7
10-bit ADC Bridge
Module
HPort1

4 8

UPort3
HPort2

UART 0 Stepper Motor 16-bit Timer 0 16-bit CCC 0 8


4 LCD Control
Control
UART 1 8-bit Timer 1 CAPCOM 0
Audio Module 8-bit PWM 0
HPort3

UPort4
4 SPI 0 8-bit Timer 2 CAPCOM 1
8/16-bit PWM 1 4
Clock Out 0 CAPCOM 2
SPI 1 8-bit PWM 2 8-bit Timer 3
HPort4

CAPCOM 3
4 Clock Out 1 8/16-bit PWM 3
CAN 0 8-bit Timer 4
UPort5

16-bit CCC 1 4
Pulse/Freq. 8-bit PWM 4
HPort5

CAN 1
4 Modulator 0 CAPCOM 4
8/16-bit PWM 5
CAN 2 Pulse/Freq. CAPCOM 5
UPort6

Modulator 1 8-bit PWM 6


HPort6

3
4 CAN 3
8/16-bit PWM 7

DIGITbus
8-bit PWM 8
HPort7

UPort7

4 I2 C 0 8/16-bit PWM 9 4

I2 C 1 8-bit PWM 10
HVDD0
HVSS0 8/16-bit PWM 11
UPort8

Graphics Bus
HVDD1 6
HVSS1
HVDD2
HVSS2
HVDD3
HVSS3

Fig. 1–1: CDC3217G-C block diagram

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CDC 3217G-C ADVANCE INFORMATION

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ADVANCE INFORMATION CDC 3217G-C

2. Packages and Pins


2.1. Package Outline Dimensions

Fig. 2–1:
PMQFP128-2: Plastic Metric Quad Flat Package, 128 leads, 14 × 20 × 2.7 mm3
Ordering code: MF
Weight approximately 1.8 g

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CDC 3217G-C ADVANCE INFORMATION

2.2. Pin Assignment

Pin Functions Not Pin Pin Not Pin Functions


LCD Port Port Basic e No. No. e Basic Port Port LCD
Mode Special Out Special In Function Function Special In Special Out Mode
SEG3.1 CC1-OUT CC1-IN / TMS U3.1 116 115 U3.2 CC0-IN / TCK CC0-OUT SEG3.2
SEG3.0 CC2-OUT CC2-IN / TDI U3.0 117 114 U3.3 CO0/TDO SEG3.3
TEST2 118 113 U3.4 SPI0-CLK-IN SPI0-CLK-OUT SEG3.4
UVDD 119 112 U3.5 SPI0-D-IN TO3 SEG3.5
UVSS 120 111 U3.6 SPI0-D-OUT SEG3.6
SEG2.6 DIGIT-OUT DIGIT-IN U2.6 121 110 U3.7 SPI1-CLK-IN SPI1-CLK-OUT SEG3.7
SEG2.5 CC1-OUT UART0-RX U2.5 122 109 U4.0 SPI1-D-IN CC0-OUT BP0
SEG2.4 UART0-TX DIGIT-IN/CC1-IN U2.4 123 108 U4.1 CC0-IN SPI1-D-OUT BP1
SEG2.3 CC2-OUT UART1-RX U2.3 124 107 U4.2 CAN0-TX BP2
SEG2.2 UART1-TX CC2-IN U2.2 125 106 U4.3 CAN0-RX/WP5 TO2 BP3
SEG7.7 CO0 U7.7/GD7 1,2 126 105 1,2 U8.0 CC4-OUT SEG8.0
SEG7.6 CO1 U7.6/GD6 1,2 127 104 1,2 U8.1 CC3-OUT SEG8.1
SEG7.5 LCK/PFM1 U7.5/GD5 1,2 128 103 1,2 U8.2 LCD-CLK-IN CAN3-TX SEG8.2
SEG7.4 CC5-OUT CC5-IN U7.4/GD4 1,2 1 102 1,2 U8.3 CAN3-RX/WP9 LCD-CLK-OUT SEG8.3
FVDD 1,2 2 101 1,2 U8.4 LCD-SYNC-IN CAN2-TX SEG8.4
FVSS 1,2 3 100 1,2 U8.5 CAN2-RX/PINT3/ LCD-SYNC-OUT SEG8.5
SEG5.3 CC4-OUT CC4-IN U5.3/GD3 1 4 WP8
SEG5.2 SDA1 SDA1 U5.2/GD2 1 5 99 1 U6.0 CAN1-TX SEG6.0
SEG5.1 SCL1 SCL1 U5.1/GD1 1 6 98 1 U6.1 CAN1-RX/WP7 GOEQ SEG6.1
SEG5.0 PFM0 U5.0/GD0 1 7 97 1 U6.2 GWEQ SEG6.2
SEG2.1 SDA0 WP6/SDA0/CAN0- U2.1 8 96 1 P2.0
RX 95 P2.1
SEG2.0 SCL0/CAN0-TX SCL0 U2.0 9 94 P0.0 CC4-IN
SEG1.7 PFM0 WP0/PINT0 U1.7 10 93 P0.1
SEG1.6 INTRES/CO0 PINT1 U1.6 11 92 P0.2
128 116 115 103
SEG1.5 CO1/CO0Q PINT2 U1.5 12 91 P0.3
TEST 13 1 102 90 P0.4
RESETQ/ALARMQ 14 89 P0.5
XTAL2 15 88 P0.6 P0.6 Comp.
XTAL1 16 87 P0.7
VSS 17 86 WAITH
VDD 18 85 WAIT
SEG1.4 ITSTOUT/AM-OUT U1.4 19 84 BVDD
SEG1.3 MTO/AM-PWM WP3 U1.3 20 83 AVSS
SEG1.2 INTRES/T0-OUT MTI/ITSTIN U1.2 21 82 AVDD
SEG1.1 T1-OUT U1.1 22 81 VREFINT
SEG1.0 T2-OUT U1.0 23 80 VREF
SEG0.7 T3-OUT WP4 U0.7 24 79 P1.0 VREF0/WP1
38 65
SEG0.6 CC3-OUT/T4-OUT CC3-IN U0.6 25 78 P1.1 VREF1/WP2
SEG0.5 CC3-OUT PINT4 U0.5 26 39 51 52 64 77 P1.2 PINT0
SEG0.4 CO1 PINT5 U0.4 27 76 P1.3 PINT1
SEG0.3 PWM0 U0.3 28 75 P1.4 PINT2
SEG0.2 PWM1 U0.2 29 74 P1.5 PINT3
SEG0.1 PWM2 U0.1 30 73 P1.6 PINT4
SEG0.0 PWM3 U0.0 31 72 P1.7 PINT5
SME1+/PWM4 SME-COMP3 H7.3 1 32 71 1 H0.0 SMG-COMP0 SMG2-/PWM7
SME1-/PWM6 SME-COMP2 H7.2 1 33 70 1 H0.1 SMG-COMP1 SMG2+/PWM5
SME2+/PWM8 SME-COMP1 H7.1 1 34 69 1 H0.2 SMG-COMP2 SMG1-/PWM3/POL
SME2-/PWM9 SME-COMP0 H7.0 1 35 68 1 H0.3 SMG-COMP3 SMG1+/PWM1
HVDD2 1,2 36 67 1,2 HVSS3
HVSS2 1,2 37 66 1,2 HVDD3
PWM8 H6.3 1,2 38 65 1,2 H1.0 SMF-COMP0 SMF2-
PWM9 H6.2 1,2 39 64 1,2 H1.1 SMF-COMP1 SMF2+
PWM10 H6.1 1,2 40 63 1,2 H1.2 SMF-COMP2 SMF1-
PWM11 H6.0 1,2 41 62 1,2 H1.3 SMF-COMP3 SMF1+
SMD1+ SMD-COMP3 H5.3 42 61 H2.0 SMC-COMP0 SMC2-
SMD1- SMD-COMP2 H5.2 43 60 H2.1 SMC-COMP1 SMC2+
HVDD0 44 59 HVSS1
HVSS0 45 58 HVDD1
SMD2+ SMD-COMP1 H5.1 46 57 H2.2 SMC-COMP2 SMC1-
SMD2- SMD-COMP0 H5.0 47 56 H2.3 SMC-COMP3 SMC1+
SMA1+ SMA-COMP3 H4.3 48 NC = not connected, 55 H3.0 SMB-COMP0 SMB2-
SMA1- SMA-COMP2 H4.2 49 leave vacant 54 H3.1 SMB-COMP1 SMB2+
SMA2+ SMA-COMP1 H4.1 50 53 H3.2 SMB-COMP2 SMB1-
(...) = future usage
SMA2- SMA-COMP0 H4.0 51 52 H3.3 SMB-COMP3 SMB1+

Fig. 2–2: Pin assignment for PQFP128 package


Note 1 denotes pins that will not be available in future 88-pin versions.
Note 2 denotes pins that will not be available in future 104-pin versions.

2.3. Pin Function Description


(differing from document “CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller”
(6251-579-1DS))
TEST2
For normal operation with internal code connect TEST2 to
System Ground (no internal pull-down).

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ADVANCE INFORMATION CDC 3217G-C

2.4. External Components

FVDD
3.3 µ 470 n
Tantal Ceramic 3.3 V
ESR < 14 Ω X7R
FVSS Flash
5V

+5 V UVDD +5 V
Supply HVDD0 to 3 Supply
100 n to 150 n 4 x 100 n to 150 n
System 5V System
UVSS HVSS0 to 3
Ground Ground
2.5 V
VDD
220 n
10 µ Ceramic
Tantal X7R AVDD Analog
Low ESR VSS Supply
100 n to 150 n

XTAL1 VREFINT
5V
18 p
10 n, Ceramic
2.5 V AVSS Analog
Ground
+5 V Supply
18 p 150 n
BVDD Ceramic, X7R
4.7 k XTAL2
Resetq RESETQ
System
Ground 47 n

Fig. 2–3: Recommended external supply and quartz connection.

To provide effective decoupling and to improve EMC behav-


ior, the small decoupling capacitors must be located as close
to the supply pins as possible. The self-inductance of these
capacitors and the parasitic inductance and capacitance of
the interconnecting traces determine the self-resonant fre-
quency of the decoupling network. Too low a frequency will
reduce decoupling effectiveness, will increase RF emissions
and may adversely affect device operation.
XTAL1 and XTAL2 quartz connections are especially sensi-
tive to capacitive coupling from other PC board signals. It is
strongly recommended to place quartz and oscillation capac-
itors as close to the pins as possible and to shield the XTAL1
and XTAL2 traces from other signals by embedding them in a
VSS trace.
The RESETQ pin adjacent to XTAL2 should be supplied with
a 47 nF capacitor, to prevent fast RESETQ transients from
being coupled into XTAL2, to prevent XTAL2 from coupling
into RESETQ, and to guarantee a time constant of ≥200 µs
sufficient for proper wake reset functionality.

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CDC 3217G-C ADVANCE INFORMATION

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ADVANCE INFORMATION CDC 3217G-C

3. Electrical Data

3.1. Absolute Maximum Ratings

Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum ratings condi-
tions for extended periods will affect device reliability.
This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; how-
ever, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated volt-
ages to this high-impedance circuit.

Table 3–1: All voltages listed are referenced to ground (UVSS = HVSSn = AVSS = 0 V), except where noted. All ground pins
except VSS must be connected to a low-resistive ground plane close to the IC.

Symbol Parameter Pin Name Min. Max. Unit

VSUP Main supply voltage UVDD −0.3 6.0 V


Analog supply voltage AVDD
SM supply voltage HVDD0 .. HVDD3

VREG Flash supply voltage FVDD −0.3 4.0 V

Core supply voltage VDD −0.3 3.0 V


PLL supply voltage BVDD

ISUP Core supply current VDD, VSS, −100 100 mA


Main supply current UVDD, UVSS

Analog supply current AVDD, AVSS −20 20 mA

SM supply current HVDD0 .. HVDD3 −250 250 mA


@TCASE = 105 °C, duty factor = 0.71 1) HVSS0 .. HVSS3

Flash supply current FVDD, FVSS −50 50 mA

PLL supply current BVDD −20 20 mA

Vin Input voltage U ports, UVSS − 0.5 UVDD + 0.7 V


XTAL,RESETQ,
TEST, TEST2

P ports UVSS − 0.5 AVDD + 0.7 V


VREF

H ports HVSS − 0.5 HVDD + 0.7 V

Iin Input current all inputs 0 2 mA

Io Output current U ports, −5 5 mA


RESETQ, WAITH

H ports −60 60 mA

toshsl Duration of short circuit to UVSS or U ports, except in indefinite s


UVDD, Port SLOW mode enabled DP mode

Tj Junction temperature under bias −45 115 °C

Ts Storage temperature −45 125 °C

Pmax Maximum power dissipation 0.8 W


1) This condition represents the worst case load with regard to the intended application.

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CDC 3217G-C ADVANCE INFORMATION

3.2. Recommended Operating Conditions

Do not insert the device into a live socket. Instead, apply power by switching on the external power supply.
Keep UVDD=AVDD during all power-up and power-down sequences.
Failure to comply with the above recommendations will result in unpredictable behavior of the device and may result in device
destruction.
Functional operation of the device beyond those indicated in the “Recommended Operating Conditions” of this specification is not
implied, may result in unpredictable behavior of the device and may reduce reliability and lifetime.

Table 3–2: All voltages listed are referenced to ground (UVSS = HVSSn = AVSS = 0 V), except where noted. All ground pins
except VSS must be connected to a low-resistive ground plane close to the IC.

Symbol Parameter Pin Name Min. Typ. Max. Unit

VSUP Main supply voltage UVDD = AVDD 3.5 5 5.5 V


Analog supply voltage

HVSUP SM supply voltage HVDDn 4.75 5 5.25 V

dVDD Ripple, peak-to-peak UVDD 200 mV


AVDD
BVDD
FVDD
VDD

dVDD/dt Supply voltage up/down ramping UVDD 20 V/µs


rate AVDD

fXTAL XTAL clock frequency XTAL1 4 4 5 MHz

fSYS CPU clock frequency, PLL on For a list of available settings see Table 4–1.

fBUS Program storage clock frequency,


PLL on

Vil 1) Automotive low input voltage U ports 0.5 × V


H ports xVDD
P ports

CMOS low input voltage U ports, TEST, 0.3 × V


TEST2 xVDD
H ports
P ports

Vih 1) Automotive high input voltage U ports 0.86 × V


H ports xVDD
P ports

CMOS high input voltage U ports,TEST, 0.7 × V


TEST2 xVDD
H ports
P ports

RVil Reset active input voltage RESETQ 0.75 V

WRVil Reset active input voltage during RESETQ 0.4 V


power-saving modes and wake
reset

RVim Reset inactive and alarm active RESETQ 1.5 2.3 V


input voltage
1)
For a list of input types and their supply voltages see Table 2-2 of document “CDC32xxG-C Automotive Controller - Family
User Manual, CDC3205G-C Automotive Controller” (6251-579-1DS).

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ADVANCE INFORMATION CDC 3217G-C

Table 3–2: All voltages listed are referenced to ground (UVSS = HVSSn = AVSS = 0 V), except where noted. All ground pins
except VSS must be connected to a low-resistive ground plane close to the IC.

Symbol Parameter Pin Name Min. Typ. Max. Unit

RVih Reset inactive and alarm inactive RESETQ 3.2 V


input voltage

WRVih Reset inactive input voltage during RESETQ UVDD V


power-saving modes and wake − 0.4 V
reset

VREFi Ext. ADC reference input voltage VREF 2.56 AVDD V

PVi ADC port input voltage referenced P ports 0 VREFi V


to ext. VREF reference
ADC port input voltage referenced 0 VREFINT
to int. VREFINT reference

3.3. Characteristics

Listed are only those characteristics that differ from Chapter 3.3 of Document “CDC32xxG-C Automotive Controller - Family User
Manual, CDC3205G-C Automotive Controller” (6251-579-1DS). All not differing characteristics, that are not listed here, apply, but
in a TCASE temperature range extended to −40 °C to +105 °C.

Table 3–3: UVSS = FVSS = HVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD < 5.5 V, 4.75 V < HVDDn < 5.25 V, TCASE = −40 °C to
+105 °C, fXTAL = 5 MHz, external components according to Fig. 2–3 (unless otherwise noted).

Symbol Parameter Pin Na. Min. Typ. 1) Max. Unit Test Conditions

Package

Rthjc Thermal resistance from 9 K/W measured on Micronas


junction to case typical 2-layer board,
1s1p, described in docu-
Rthja Thermal resistance from 31 K/W ment “Integrated Circuits
junction to ambient - Thermal Characteriza-
tion of Packages” (6200-
266-1E) (modified
JESD-51.3)

Supply Currents (CMOS levels on all inputs, i.e., Vil = xVSS ± 0.3 V and Vih = xVDD ± 0.3 V, no loads on outputs)

UIDDp UVDD PLL mode supply UVDD 65 mA fSYS = 24 MHz


current 120 fSYS = 50 MHz

UIDDprog UVDD Flash program UVDD 45 mA Flash Write/Erase,


supply current all modules off, 2)

UIDDf UVDD FAST mode supply UVDD 18 mA all modules off, 2)


current

UIDDs UVDD SLOW mode supply UVDD see 1.4 mA all modules off, 2) 3)
current Fig. 3–1

1)
Typical values describe typical behavior at room temperature (25 °C, unless otherwise noted), with typical
Recommended Operating Conditions applied, and are not 100% tested.
2)
Value may be exceeded with unusual hardware option setting.
3)
Measured with external clock. Add typically 120 µA for operation on quartz with SR0.XTAL=0 (Oscillator RUN mode).

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CDC 3217G-C ADVANCE INFORMATION

Table 3–3: UVSS = FVSS = HVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD < 5.5 V, 4.75 V < HVDDn < 5.25 V, TCASE = −40 °C to
+105 °C, fXTAL = 5 MHz, external components according to Fig. 2–3 (unless otherwise noted).

Symbol Parameter Pin Na. Min. Typ. 1) Max. Unit Test Conditions

UIDDd UVDD DEEP SLOW mode UVDD see 0.9 mA all modules off, 3)
supply current Fig. 3–1

UIDDw UVDD WAKE mode supply UVDD 0 20 50 µA RC and XTAL oscillators


current off

UIDDst UVDD STANDBY mode UVDD 35 75 µA RC oscillator on, XTAL


supply current off

UVDD 60 100 µA XTAL oscillator on, RC


off 3)

UIDDi UVDD IDLE mode supply UVDD 50 475 µA RC oscillator on, XTAL
current off

see 500 µA XTAL oscillator on, RC


Fig. 3–1 off 3)

AIDDa AVDD active supply current AVDD 0.35 0.6 mA ADC on, PLL off

2 mA ADC, buffer and PLL on

AIDDq Quiescent supply current AVDD 0 1 10 µA ADC and PLL off

HIDDq Sum of 0 1 40 µA no output activity,


all SM module off
HVDDn

Inputs

Ii Input leakage current TEST2 −1 1 µA 0 < Vi < UVDD


1)
Typical values describe typical behavior at room temperature (25 °C, unless otherwise noted), with typical
Recommended Operating Conditions applied, and are not 100% tested.
2) Value may be exceeded with unusual hardware option setting.
3) Measured with external clock. Add typically 120 µA for operation on quartz with SR0.XTAL=0 (Oscillator RUN mode).

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ADVANCE INFORMATION CDC 3217G-C

µA
900

800

700
UIDDs (SLOW mode)
600
UIDD
500

400
UIDDd (DEEP SLOW mode)
300

200
UIDDi (IDLE mode)
100

0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 °C

TCASE

Fig. 3–1: Typical UIDD characteristics over temperature @ fXTAL = 4 MHz, 5 V

3.4. Recommended Quartz Crystal Characteristics

See Chapter 3.4 of document “CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller”
(6251-579-1DS).

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CDC 3217G-C ADVANCE INFORMATION

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ADVANCE INFORMATION CDC 3217G-C

4. CPU and Clock System

4.1. Recommended Register Settings Suppression Strength (SUP) and Clock Tolerance (TOL)
may be varied between zero and the values for strong set-
Settings for PMF, IOP and WSR differing from those given in tings according to the rules in Section 4.4.2 of the document
Table 4–1 must not be used and may result in undefined “CDC32xxG-C Automotive Controller - Family User Manual,
behavior. It is required not to operate I/O faster than Flash. CDC3205G-C Automotive Controller” (6251-579-1DS). The
given limits must not be exceeded.

Table 4–1: PLL and ERM modes: Recommended settings and resulting operating frequencies (MHz)

fXTAL CPU Flash I/O ERMC.EOM = 1 ERMC.EOM = 2 or 3

Weak Normal Strong Weak Normal Strong

SUP

SUP

SUP

SUP

SUP

SUP
TOL

TOL

TOL

TOL

TOL

TOL
fSYS PLLC. fBUS WSR fIO= IOC.
PMF f0 IOP

4 16 3 8 0x11 8 1 0 8 0 14 0 15 8 4 14 7 22 11

24 5 8 0x22 8 2 0 12 0 15 0 15 12 6 21 11 31 12

12 0x11 0 10 0 10 0 10 12 2 21 2 33 2

32 7 8 0x33 8 3 0 12 0 12 0 12 16 8 28 12 31 12

10.67 0x22 0 12 0 12 0 12 16 8 19 9 19 9
23 7 23 7
28 6 37 6

40 9 10 0x33 8 4 0 6 0 6 0 6 21 6 35 6 37 6

48 11 12 0x33 8 5 0 1 0 1 0 1 25 1 42 1 42 1

5 10 1 10 0x00 10 0 0 5 0 8 0 14 5 3 8 4 14 7

20 3 10 0x11 10 1 0 10 0 15 0 15 10 5 17 8 28 8

30 5 10 0x22 10 2 0 14 0 14 0 14 15 8 24 12 28 10
26 11 30 9
35 8

40 7 10 0x33 10 3 0 6 0 6 0 6 21 6 35 6 37 6

50 9 12.5 0x33 10 4 set ERMC.EOM=0 set ERMC.EOM=0

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CDC 3217G-C ADVANCE INFORMATION

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ADVANCE INFORMATION CDC 3217G-C

5. Memory and Special Function ROM (SFR) System

address range RESETQ = 1 RESETQ = 0


(16M) CR.MAP = 00 CR.MAP = 01 CR.MAP = 1x TEST2-Pin = 0 TEST2-Pin = 1
00FF.FFFF
.5M I/O I/O I/O
F8.0000

.5M
F0.0000 SFR SFR SFR
rsvd
E0.0000
debug

2M
C0.8000
RAM RAM RAM
32KB 32KB 32KB
C0.0000

A0.0000

The device contains a 1024-KByte Flash


EEPROM of the SPANSION S29AL008D-
8M 01 type (top boot configuration). This
device exhibits electrical byte program and
sector erase functions. Refer to the SPAN-
SION data sheet for details.

30.0000

Flash Flash
1MB 1MB

20.0000

10.0000
2M
8000
Flash Flash
RAM 1MB 1MB
32KB
0 SFR SFR

Fig. 5–1: Address map. Most common settings

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CDC 3217G-C ADVANCE INFORMATION

Warning:
Since only a 24-bit address space is supported, do not use
addresses outside this range when debugging this device.

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ADVANCE INFORMATION CDC 3217G-C

6. Core Logic

6.1. Control Word (CW)

A number of important system configuration properties are As Table 6–1 shows, the device disables external access
selectable during device start-up by means of a unique con- (through the multifunction port) to internal code, as long as
trol word (CW). MFPLR.MFPL is 1 (= state after UVDD power-up). Setting it
to 0 requires internal SW. By this means, an effective device
lock mechanism is implemented, which prevents unautho-
6.1.1. Reset Active rized access to internal SW.
At the end of the reset period, the device fetches this CW In ROM parts, flag MFPLR.MFPL is available, but does not
from address locations 0x20 to 0x23 of a source that is lock the multifunction port. Thus Table 6–1 reduces to Table
determined by the state of pins TEST and TEST2 and flag 6–2.
MFPLR.MFPL, see Table 6–1 for MCM parts, Table 6–2 for
ROM parts. Table 6–2: CW fetch in ROM parts (QFP128)
Table 6–1: CW fetch in MCM parts (QFP128) “Control Word Fetch” desired Necessary Reset
from config. of pins
“Control Word Fetch” Necessary Reset Con-
desired from figuration TEST2 TEST
TEST2 TEST MFPL Internal ROM 0 0
Int. Flash 0 0 x External via multifunction port 0 1
Int. Flash 0 1 1 Int. special-function ROM 1 x
Ext. via multifunction port 0 1)
6.1.2. Reset Inactive
Int. special-function ROM 1 x x
When exiting Reset, the CW is read and stored in the control
1)
Only available after a non-power-on RESET with MFPL register (CR) and the system will start up according to the
= 0 set before configuration defined therein.
Normally the CW is fetched from the same memory that the
system will start executing code from. Table 6–3 gives fixed
CWs for a list of the most commonly used configurations.

Table 6–3: Some common system configurations and the corresponding CW setting

Part “Program Start” desired from Additional desired properties Necessary CW


Type
31:16 15:0

MCM int. 16-bit Flash - Don’t care 0x7F5F

ROM int. 16-bit ROM - Don’t care 0x7F5F

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CDC 3217G-C ADVANCE INFORMATION

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ADVANCE INFORMATION CDC 3217G-C

7. Hardware Options

7.1. Functional Description

Hardware options are available in several areas to adapt the


IC function to the host system requirements. For details see
the document “CDC32xxG-C Automotive Controller - Family
User Manual, CDC3205G-C Automotive Controller” (6251-
579-1DS).
Setting hardware options is carried out in two steps:
1. selection is effected by programming dedicated address
locations in the HW options field with the desired options’
code.
2. activation is effected by copying the HW options field to
the corresponding HW options’ registers at least once after
each reset.
In EMU and MCM devices, all hardware options are soft-
ware-progammable.
In mask ROM derivatives, the clock options and the watch-
dog, clock and supply monitors are hard-wired, according to
the HW options field of the ROM code hex file. Those options
can only be altered by changing a production mask.
To ensure compatible option settings in this IC and mask
ROM derivatives when run with the same ROM code, it is
mandatory to always write the HW options field to the HW
option registers directly after reset.

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CDC 3217G-C ADVANCE INFORMATION

8. Data Sheet History

1. Advance Information: “CDC3217G-C Automotive


Controller Specification”, Feb. 18, 2005, 6251-670-1AI.
First release of the advance information.
Originally created for HW version CDC3217G-C1.

Micronas GmbH All information and data contained in this data sheet are without any
Hans-Bunte-Strasse 19 commitment, are not to be considered as an offer for conclusion of a
D-79108 Freiburg (Germany) contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
P.O. Box 840 and delivery are exclusively subject to our respective order confirmation
D-79008 Freiburg (Germany) form; the same applies to orders based on development samples deliv-
Tel. +49-761-517-0 ered. By this publication, Micronas GmbH does not assume responsibil-
Fax +49-761-517-2174 ity for patent infringements or other rights of third parties which may
E-mail: docservice@micronas.com result from its use.
Internet: www.micronas.com Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
Printed in Germany No part of this publication may be reproduced, photocopied, stored on a
Order No. 6251-670-1AI retrieval system, or transmitted without the express written consent of
Micronas GmbH.

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