CDC 3217G-C Automotive Controller: Micronas
CDC 3217G-C Automotive Controller: Micronas
CDC 3217G-C Automotive Controller: Micronas
CDC 3217G-C
Automotive Controller
Contents
3 1. Introduction
3 1.1. Features
6 1.2. Abbreviations
7 1.3. Block Diagram
13 3. Electrical Data
13 3.1. Absolute Maximum Ratings
14 3.2. Recommended Operating Conditions
15 3.3. Characteristics
17 3.4. Recommended Quartz Crystal Characteristics
23 6. Core Logic
23 6.1. Control Word (CW)
25 7. Hardware Options
25 7.1. Functional Description
1. Introduction
The chip contains timer/counters, an interrupt controller, a
multichannel A/D converter, a stepper motor and LCD driver,
CAN interfaces, PWM outputs and a crystal clock multiplying
PLL.
The device is a microcontroller for use in automotive applica-
tions. The on-chip CPU is an ARM processor ARM7TDMI This document provides MCM Flash hardware-specific infor-
with 32-bit data and address bus, which supports Thumb mation. General information on operating the IC can be
format instructions. found in the document “CDC32xxG-C Automotive Controller
- Family User Manual, CDC3205G-C Automotive Controller”
(6251-579-1DS)”.
1.1. Features
This
Device:
Core
RAM, zero wait state, 32 bit wide 32 Kbyte 12 Kbyte 16 Kbyte 6 Kbyte
Digital watchdog ✔
This
Device:
Device lock module inhibits access to internal firmware, lock can be set by -
customer
Analog
10-bit ADC, charge balance type 16 channels (each selectable as digital input)
ADC reference VREF pin, P1.0 pin, P1.1 pin or VREFINT internal bandgap selectable
LCD internal processing of all analog voltages for the LCD driver
Communication
DMA 3 DMA channels, one each for serving the graphics bus interface, SPI0 -
and SPI1
Full CAN modules V2.0B 4: CAN0, CAN1, CAN2 and CAN3 2: CAN0 and CAN1 1: CAN0
with a 32-objects’-RAM each
(LCAN000E)
Graphics bus interface 8-bit data bus, DMA supported, e.g., for connection of EPSON SED 1560 -
LCD controller
Universal ports selectable as up to 52 I/O or 48 LCD segment lines (= 192 segments), up to 50 I/O
4:1-mux LCD segment/back- individually configurable as I/O or LCD or 46 LCD
plane lines or digital I/O ports segment
lines (= 184
segments)
This
Device:
PWM modules, each config- 6 modules: PWM0/1, PWM2/3, PWM4/5, PWM6/7, PWM8/9 and PWM10/ 5 modules:
urable as two 8-bit PWMs or one 11 PWM0/1,
16-bit PWM PWM2/3,
PWM4/5,
PWM6/7,
PWM8/9
Polling/flash timer output 1 high-current port output operable in power-saving operation modes
16-bit timers 1: T0
Miscellaneous
Various HW options selectable set by copy from user program storage during system start-up
at random
Core bond-out ✔ -
Package
1.2. Abbreviations
8
DMA Logic
PPort1
Flash
UPort0
8 32 16 512K x 16 8
Bridge
Memory
Controller Special
PPort2
Wait Comp.
2 Function
ROM
UPort1
4K x 16 8
P06 Comp.
Patch
10 Locations
HPort0
4 Bandgap Ref.
UPort2
Device Lock 7
10-bit ADC Bridge
Module
HPort1
4 8
UPort3
HPort2
UPort4
4 SPI 0 8-bit Timer 2 CAPCOM 1
8/16-bit PWM 1 4
Clock Out 0 CAPCOM 2
SPI 1 8-bit PWM 2 8-bit Timer 3
HPort4
CAPCOM 3
4 Clock Out 1 8/16-bit PWM 3
CAN 0 8-bit Timer 4
UPort5
16-bit CCC 1 4
Pulse/Freq. 8-bit PWM 4
HPort5
CAN 1
4 Modulator 0 CAPCOM 4
8/16-bit PWM 5
CAN 2 Pulse/Freq. CAPCOM 5
UPort6
3
4 CAN 3
8/16-bit PWM 7
DIGITbus
8-bit PWM 8
HPort7
UPort7
4 I2 C 0 8/16-bit PWM 9 4
I2 C 1 8-bit PWM 10
HVDD0
HVSS0 8/16-bit PWM 11
UPort8
Graphics Bus
HVDD1 6
HVSS1
HVDD2
HVSS2
HVDD3
HVSS3
Fig. 2–1:
PMQFP128-2: Plastic Metric Quad Flat Package, 128 leads, 14 × 20 × 2.7 mm3
Ordering code: MF
Weight approximately 1.8 g
FVDD
3.3 µ 470 n
Tantal Ceramic 3.3 V
ESR < 14 Ω X7R
FVSS Flash
5V
+5 V UVDD +5 V
Supply HVDD0 to 3 Supply
100 n to 150 n 4 x 100 n to 150 n
System 5V System
UVSS HVSS0 to 3
Ground Ground
2.5 V
VDD
220 n
10 µ Ceramic
Tantal X7R AVDD Analog
Low ESR VSS Supply
100 n to 150 n
XTAL1 VREFINT
5V
18 p
10 n, Ceramic
2.5 V AVSS Analog
Ground
+5 V Supply
18 p 150 n
BVDD Ceramic, X7R
4.7 k XTAL2
Resetq RESETQ
System
Ground 47 n
3. Electrical Data
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum ratings condi-
tions for extended periods will affect device reliability.
This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; how-
ever, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated volt-
ages to this high-impedance circuit.
Table 3–1: All voltages listed are referenced to ground (UVSS = HVSSn = AVSS = 0 V), except where noted. All ground pins
except VSS must be connected to a low-resistive ground plane close to the IC.
H ports −60 60 mA
Do not insert the device into a live socket. Instead, apply power by switching on the external power supply.
Keep UVDD=AVDD during all power-up and power-down sequences.
Failure to comply with the above recommendations will result in unpredictable behavior of the device and may result in device
destruction.
Functional operation of the device beyond those indicated in the “Recommended Operating Conditions” of this specification is not
implied, may result in unpredictable behavior of the device and may reduce reliability and lifetime.
Table 3–2: All voltages listed are referenced to ground (UVSS = HVSSn = AVSS = 0 V), except where noted. All ground pins
except VSS must be connected to a low-resistive ground plane close to the IC.
fSYS CPU clock frequency, PLL on For a list of available settings see Table 4–1.
Table 3–2: All voltages listed are referenced to ground (UVSS = HVSSn = AVSS = 0 V), except where noted. All ground pins
except VSS must be connected to a low-resistive ground plane close to the IC.
3.3. Characteristics
Listed are only those characteristics that differ from Chapter 3.3 of Document “CDC32xxG-C Automotive Controller - Family User
Manual, CDC3205G-C Automotive Controller” (6251-579-1DS). All not differing characteristics, that are not listed here, apply, but
in a TCASE temperature range extended to −40 °C to +105 °C.
Table 3–3: UVSS = FVSS = HVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD < 5.5 V, 4.75 V < HVDDn < 5.25 V, TCASE = −40 °C to
+105 °C, fXTAL = 5 MHz, external components according to Fig. 2–3 (unless otherwise noted).
Symbol Parameter Pin Na. Min. Typ. 1) Max. Unit Test Conditions
Package
Supply Currents (CMOS levels on all inputs, i.e., Vil = xVSS ± 0.3 V and Vih = xVDD ± 0.3 V, no loads on outputs)
UIDDs UVDD SLOW mode supply UVDD see 1.4 mA all modules off, 2) 3)
current Fig. 3–1
1)
Typical values describe typical behavior at room temperature (25 °C, unless otherwise noted), with typical
Recommended Operating Conditions applied, and are not 100% tested.
2)
Value may be exceeded with unusual hardware option setting.
3)
Measured with external clock. Add typically 120 µA for operation on quartz with SR0.XTAL=0 (Oscillator RUN mode).
Table 3–3: UVSS = FVSS = HVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD < 5.5 V, 4.75 V < HVDDn < 5.25 V, TCASE = −40 °C to
+105 °C, fXTAL = 5 MHz, external components according to Fig. 2–3 (unless otherwise noted).
Symbol Parameter Pin Na. Min. Typ. 1) Max. Unit Test Conditions
UIDDd UVDD DEEP SLOW mode UVDD see 0.9 mA all modules off, 3)
supply current Fig. 3–1
UIDDi UVDD IDLE mode supply UVDD 50 475 µA RC oscillator on, XTAL
current off
AIDDa AVDD active supply current AVDD 0.35 0.6 mA ADC on, PLL off
Inputs
µA
900
800
700
UIDDs (SLOW mode)
600
UIDD
500
400
UIDDd (DEEP SLOW mode)
300
200
UIDDi (IDLE mode)
100
0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 °C
TCASE
See Chapter 3.4 of document “CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller”
(6251-579-1DS).
4.1. Recommended Register Settings Suppression Strength (SUP) and Clock Tolerance (TOL)
may be varied between zero and the values for strong set-
Settings for PMF, IOP and WSR differing from those given in tings according to the rules in Section 4.4.2 of the document
Table 4–1 must not be used and may result in undefined “CDC32xxG-C Automotive Controller - Family User Manual,
behavior. It is required not to operate I/O faster than Flash. CDC3205G-C Automotive Controller” (6251-579-1DS). The
given limits must not be exceeded.
Table 4–1: PLL and ERM modes: Recommended settings and resulting operating frequencies (MHz)
SUP
SUP
SUP
SUP
SUP
SUP
TOL
TOL
TOL
TOL
TOL
TOL
fSYS PLLC. fBUS WSR fIO= IOC.
PMF f0 IOP
4 16 3 8 0x11 8 1 0 8 0 14 0 15 8 4 14 7 22 11
24 5 8 0x22 8 2 0 12 0 15 0 15 12 6 21 11 31 12
12 0x11 0 10 0 10 0 10 12 2 21 2 33 2
32 7 8 0x33 8 3 0 12 0 12 0 12 16 8 28 12 31 12
10.67 0x22 0 12 0 12 0 12 16 8 19 9 19 9
23 7 23 7
28 6 37 6
40 9 10 0x33 8 4 0 6 0 6 0 6 21 6 35 6 37 6
48 11 12 0x33 8 5 0 1 0 1 0 1 25 1 42 1 42 1
5 10 1 10 0x00 10 0 0 5 0 8 0 14 5 3 8 4 14 7
20 3 10 0x11 10 1 0 10 0 15 0 15 10 5 17 8 28 8
30 5 10 0x22 10 2 0 14 0 14 0 14 15 8 24 12 28 10
26 11 30 9
35 8
40 7 10 0x33 10 3 0 6 0 6 0 6 21 6 35 6 37 6
.5M
F0.0000 SFR SFR SFR
rsvd
E0.0000
debug
2M
C0.8000
RAM RAM RAM
32KB 32KB 32KB
C0.0000
A0.0000
30.0000
Flash Flash
1MB 1MB
20.0000
10.0000
2M
8000
Flash Flash
RAM 1MB 1MB
32KB
0 SFR SFR
Warning:
Since only a 24-bit address space is supported, do not use
addresses outside this range when debugging this device.
6. Core Logic
A number of important system configuration properties are As Table 6–1 shows, the device disables external access
selectable during device start-up by means of a unique con- (through the multifunction port) to internal code, as long as
trol word (CW). MFPLR.MFPL is 1 (= state after UVDD power-up). Setting it
to 0 requires internal SW. By this means, an effective device
lock mechanism is implemented, which prevents unautho-
6.1.1. Reset Active rized access to internal SW.
At the end of the reset period, the device fetches this CW In ROM parts, flag MFPLR.MFPL is available, but does not
from address locations 0x20 to 0x23 of a source that is lock the multifunction port. Thus Table 6–1 reduces to Table
determined by the state of pins TEST and TEST2 and flag 6–2.
MFPLR.MFPL, see Table 6–1 for MCM parts, Table 6–2 for
ROM parts. Table 6–2: CW fetch in ROM parts (QFP128)
Table 6–1: CW fetch in MCM parts (QFP128) “Control Word Fetch” desired Necessary Reset
from config. of pins
“Control Word Fetch” Necessary Reset Con-
desired from figuration TEST2 TEST
TEST2 TEST MFPL Internal ROM 0 0
Int. Flash 0 0 x External via multifunction port 0 1
Int. Flash 0 1 1 Int. special-function ROM 1 x
Ext. via multifunction port 0 1)
6.1.2. Reset Inactive
Int. special-function ROM 1 x x
When exiting Reset, the CW is read and stored in the control
1)
Only available after a non-power-on RESET with MFPL register (CR) and the system will start up according to the
= 0 set before configuration defined therein.
Normally the CW is fetched from the same memory that the
system will start executing code from. Table 6–3 gives fixed
CWs for a list of the most commonly used configurations.
Table 6–3: Some common system configurations and the corresponding CW setting
7. Hardware Options
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