Flybac Circuit Special

LT3748
100V Isolated
Flyback Controller
Features Description
nn 5V to 100V Input Voltage Range The LT®3748 is a switching regulator controller specifically
nn 1.9A Average Gate Drive Source and Sink Current designed for the isolated flyback topology and capable of
nn Boundary Mode Operation high power. It drives a low side external N-channel power
nn No Transformer Third Winding or Opto-Isolator MOSFET from an internally regulated 7V supply. No third
Required for Regulation winding or opto-isolator is required for regulation as the
nn Primary-Side Winding Feedback Load Regulation part senses the isolated output voltage directly from the
nn V
OUT Set with Two External Resistors primary-side flyback waveform.
nn INTV
CC Pin for Control of Gate Driver Voltage The LT3748 utilizes boundary mode to provide a small
nn Programmable Soft Start
magnetic solution without compromising load regulation.
nn Programmable Undervoltage Lockout
Operating frequency is set by load current and transformer
nn Available in MSOP Package
magnetizing inductance. The gate drive of the LT3748
combined with a suitable external MOSFET allow it to
Applications deliver load power up to several tens of watts from input
voltages as high as 100V.
nn Isolated Telecom Converters
nn High Power Automotive Supplies The LT3748 is available in a high voltage 16-lead MSOP
nn Isolated Industrial Power Supplies package with four leads removed.
nn Military and High Temperature Applications L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5438499 and 7471522.
Typical Application
25W, 12V Output, Isolated Telecom Supply
Output Load and Line Regulation
4:1 VOUT+
VIN 12.6
12V
36V TO 72V 2A
10µF 412k
60.8µH 3.8µH 100µF 12.4
VIN
EN/UVLO
243k
15.4k RFB VOUT– 12.2
VOUT (V)
RREF
12.0
LT3748 6.04k
11.8
TC GATE
11.6 VIN = 72V

SS SENSE
VIN = 48V
VC GND INTVCC 0.033Ω VIN = 36V
11.4
56.2k 2nF 10k 0 0.5 1.0 1.5 2.0
3748 TA01a
LOAD CURRENT (A)
4700pF 4.7µF
3748 TA01b
3748fb
For more information www.linear.com/LT3748 1

LT3748
Absolute Maximum Ratings Pin Configuration
(Note 1)
VIN, RFB....................................................................100V TOP VIEW
VIN to RFB...................................................................±5V VIN 1 16 RFB
EN/UVLO.......................................................–0.3V, 100V EN/UVLO 3 14 RREF
INTVCC.....................................................VIN + 0.3V, 20V INTVCC

GATE
5
6
12
11
TC
VC
SS, VC, TC, RREF..........................................................6V SENSE
GND
7
8
10
9
SS
GND
SENSE.......................................................................0.4V MS PACKAGE
Operating Junction Temperature Range (Note 2) 16 (12)-LEAD PLASTIC MSOP
LT3748E/LT3748I................................ –40°C to 125°C TJMAX = 150°C, θJA = 90°C/W
LT3748H............................................. –40°C to 150°C

LT3748MP.......................................... –55°C to 150°C
Storage Temperature Range................... –65°C to 150°C
order information
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3748EMS#PBF LT3748EMS#TRPBF 3748 16-Lead Plastic MSOP –40°C to 125°C
LT3748IMS#PBF LT3748IMS#TRPBF 3748 16-Lead Plastic MSOP –40°C to 125°C
LT3748HMS#PBF LT3748HMS#TRPBF 3748 16-Lead Plastic MSOP –40°C to 150°C
LT3748MPMS#PBF LT3748MPMS#TRPBF 3748 16-Lead Plastic MSOP –55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Electrical
Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 10V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Voltage Range l 5 100 V
Quiescent Current Not Switching 1.3 1.75 mA
VEN/UVLO = 0.2V 0 1 µA
VIN Quiescent Current, INTVCC Overdriven VINTVCC = 10V 300 450 µA
INTVCC Voltage Range l 4.5 20 V
INTVCC Pin Regulation Voltage 6.8 7 7.2 V
INTVCC Dropout (VIN – VINTVCC), IINTVCC = 10mA, VIN = 5V 0.7 V
INTVCC Undervoltage Lockout Falling Threshold l 3.45 3.6 3.75 V
EN/UVLO Pin Threshold EN/UVLO Pin Voltage Rising l 1.19 1.223 1.25 V
EN/UVLO Pin Hysteresis Current EN/UVLO = 1V 1.9 2.4 2.9 µA
Soft-Start Current VSS = 0.4V (Note 3) 5 µA
Soft-Start Threshold 0.65 V
Soft-Start Reset Current 3 mA
3748fb
2 For more information www.linear.com/LT3748

LT3748
Electrical
Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 10V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Maximum SENSE Current Limit Threshold VC = 2.2V 95 100 105 mV
l 90 100 110 mV
Minimum SENSE Current Limit Threshold VC = 0V 15 mV
Maximum to Minimum SENSE Threshold l 5.2 6.6 8.2 mV/mV
Ratio
SENSE Overcurrent Threshold VC = 2.2V 115 130 145 mV
SENSE Input Bias Current VSENSE = 10mV (Note 3) 10 15 20 µA
RREF Voltage VC = 1.1V 1.20 1.223 1.24 V
l 1.195 1.245 V
RREF Voltage Line Regulation 5V < VIN < 100V 0.005 0.025 %/V
RREF Pin Bias Current (Note 3) l 35 500 nA
TC Current into RREF RTC = 20k 27.5 µA
Error Amplifier Voltage Gain 115 V/V
Error Amplifier Transconductance ∆I = 10µA 155 µmhos
VC Source Current VC = 1.1V, VRREF = 0.5V –45 µA
VC Sink Current VC = 1.1V, VRREF = 2V 48 µA
Flyback Comparator Trip Current Current into RFB Pin, RREF = 6.04k 10 µA
Minimum GATE Off-Time 700 ns
Minimum GATE On-Time 250 ns
Maximum Discontinuous Off-Time VC = 0V 24 µs
Maximum GATE Off-Time VRREF = 0.5V 55 µs
Maximum GATE On-Time VSENSE = 0V 55 µs
GATE Output Rise Time CL = 3300pF, 10% to 90% 16 ns
GATE Output Fall Time CL = 3300pF, 10% to 90% 16 ns
GATE Output Low (VOL) 0.05 V
GATE Output High (VOH) VINTVCC – 0.05 V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings LT3748I is guaranteed over the full –40°C to 125°C operating junction
may cause permanent damage to the device. Exposure to any Absolute temperature range. The LT3748H is guaranteed over the full –40°C to
Maximum Rating condition for extended periods may affect device 150°C operating junction temperature range. The LT3748MP is guaranteed
reliability and lifetime. over the full –55°C to 150°C operating junction temperature range. High
Note 2: The LT3748E is guaranteed to meet performance specifications junction temperatures degrade operating lifetimes. Operating lifetime is
from 0°C to 125°C junction temperature. Specifications over the –40°C derated at junction temperatures greater than 125°C.
to 125°C operating junction temperature range are assured by design Note 3: Current flows out of the pin.
characterization and correlation with statistical process controls. The
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LT3748
Typical Performance Characteristics TA = 25°C, unless otherwise noted.
Output Regulation vs Temperature Quiescent Current vs Temperature Quiescent Current vs VIN Voltage
15.6 1.7 1.6
FIGURE 16 CIRCUIT VSS = 0V VSS = 0V
IOUT = 150mA ON EACH OUTPUT 1.6 INTVCC = OPEN 1.4 INTVCC = OPEN
15.4 VIN = 12V
QUIESCENT CURRENT (mA)

1.5 VIN = 72V
QUIESCENT CURRENT (mA)

1.2
15.2 1.4
VIN = 36V 1.0
VOUT (V)
1.3
15.0 0.8
1.2 VIN = 12V
0.6
14.8 1.1
VIN = 6V
0.4
1.0
14.6
0.9 0.2
14.4 0.8 0
–55 –25 0 25 50 75 100 125 150 –55 –25 0 25 50 75 100 125 150 0 20 40 60 80 100
TEMPERATURE (°C) TEMPERATURE (°C) VIN (V)
3748 G01 3748 G02 3748 G03
INTVCC Undervoltage Lockout

INTVCC Voltage vs Temperature INTVCC Voltage vs VIN Voltage vs Temperature
7.5 7.5 4.0
IINTVCC = 0mA
7.4
7.0 3.9
7.3 IINTVCC = 10mA
7.2 6.5 3.8

INTVCC VOLTAGE (V)
INTVCC UVLO (V)

7.1 IINTVCC = 0mA
VINTVCC (V)
6.0 3.7 RISING THRESHOLD

7.0
5.5 3.6
6.9 IINTVCC = 10mA FALLING THRESHOLD
6.8 5.0 3.5
6.7
4.5 3.4
6.6
6.5 4.0 3.3
–55 –25 0 25 50 75 100 125 150 4 6 8 10 20 40 60 80 100 –55 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) VIN VOLTAGE (V) TEMPERATURE (°C)
3748 G04 3748 G05 3748 G06
INTVCC Regulator Dropout

vs INTVCC Current INTVCC Dropout vs Temperature Soft-Start Current vs Temperature
3.0 3.0 6
VIN = 5V VIN = 5V
INTVCC REGULATOR DROPOUT (V)
2.5 2.5 5
SOFT-START CURRENT (µA)
INTVCC DROPOUT (V)
2.0 2.0 4
IINTVCC = 20mA
1.5 1.5 3
IINTVCC = 10mA
1.0 1.0 2
150°C
0.5 100°C 0.5 1
25°C IINTVCC = 5mA
–50°C
0 0 0
0 10 20 30 40 –55 –25 0 25 50 75 100 125 150 –55 –25 0 25 50 75 100 125 150
INTVCC CURRENT (mA) TEMPERATURE (°C) TEMPERATURE (°C)
3748 G07 3748 G08 3748 G09
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LT3748
Typical Performance Characteristics TA = 25°C, unless otherwise noted.
EN/UVLO Threshold
EN/UVLO Current vs Temperature vs Temperature TC Pin Voltage vs Temperature
3.0 1.40 0.9
1.35 0.8
2.5
VEN/UVLO = 1.1V 0.7
EN/UVLO THRESHOLD (V)

1.30
EN/UVLO CURRENT (µA)
2.0 0.6
TC VOLTAGE (V)
VEN/UVLO = 0.9V 1.25
0.5
1.5 1.20
0.4
1.15
1.0 0.3
1.10
0.2
0.5
1.05 0.1
VEN/UVLO = 1.3V
0 1.00 0
–55 –25 0 25 50 75 100 125 150 –55 –25 0 25 50 75 100 125 150 –55 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3748 G10 3748 G11 3748 G12
Error Amplifier Transconductance Error Amplifier Output Current SENSE Pin Threshold
vs Temperature vs RREF Pin Voltage vs Temperature
200 60 160
190 50
140 OVERCURRENT
40
TRANSCONDUCTANCE (µmhos)
180
30
SENSE THRESHOLD (mV)

120
170 20 VC = 2.2V
160 100
10
IVC (µA)
150 0 80
140 –10
60
–20
130
–30 150°C 40
120 100°C
–40 VC = 0.2V
110 VIN = 100V 25°C 20
–50
VIN = 6V –50°C
100 –60 0
–55 –25 0 25 50 75 100 125 150 0 0.5 1.0 1.5 2.0 2.5 –55 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) VREF (V) TEMPERATURE (°C)
3748 G13 3748 G14 3748 G15
Maximum Discontinuous Off-Time GATE Rise and Fall Time

vs Temperature GATE Rise and Fall Time vs Charge vs INTVCC Voltage
30 2.0 25
CGATE = 3.3nF
AVERAGE GATE SOURCE, SINK CURRENT (A)
MAXIMUM DISCONTINUOUS OFF-TIME (µs)
29 tr, tf 10% TO 90%

AVERAGE 1.5
GATE RISE AND FALL TIME (ns)
GATE RISE AND FALL TIME (ns)
28 CURRENT 20
FALLING
50 1.0
27
26 15 RISING
40 0.5
25 RISE TIME
30 0
24 10
FALL TIME
23 20
22 Q=C•V 5
10
21 VINTVCC = 7V
tr, tf 10% TO 90%
20 0 0
–55 –25 0 25 50 75 100 125 150 0 20 40 60 80 100 120 0 5 10 15 20
TEMPERATURE (°C) TOTAL GATE CHARGE (nC) VINTVCC (V)
3748 G16 3748 G17 3748 G18
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LT3748
Pin Functions
VIN (Pin 1) Input Voltage. This pin supplies current to the GND (Pins 8, 9): Ground.
internal start-up circuitry and is the reference voltage for
SS (Pin 10): Soft-Start Pin. This pin delays start-up and
the feedback circuitry connected to the RFB pin. This pin
clamps VC pin voltage. Soft-start timing is set by the size
must be locally bypassed with a capacitor. of the external capacitor at the pin. Switching starts when
EN/UVLO (Pin 3): Enable/Undervoltage Lockout. A resistor VSS reaches ~0.65V.
divider connected to VIN is tied to this pin to program the VC (Pin 11): Compensation Pin for the Internal Error
minimum input voltage at which the LT3748 will operate. Amplifier. Connect a series RC from this pin to ground to
At a voltage below ~0.5V, the part draws less than 1µA compensate the switching regulator. A 100pF capacitor
quiescent current. When below 1.223V but above ~0.5V, in parallel helps eliminate noise.
the part will draw quiescent current but will not regulate
the INTVCC supply or power the gate drive circuitry. Above TC (Pin 12): Output Voltage Temperature Compensation.
1.223V, all internal circuitry will start and the SS pin will Connect a resistor to ground to produce a current pro-
source 5μA. When EN/UVLO falls below 1.223V, 2.4μA is portional to absolute temperature to be sourced into the
sunk from the pin to provide programmable hysteresis RREF node. ITC = 0.55V/RTC.
for undervoltage lockout. RREF (Pin 14): Input Pin for the External Ground-Referred
INTVCC (Pin 5): Gate Driver Bias Voltage. This pin supplies Reference Resistor. The resistor at this pin should be 6.04k,
current to the internal gate driver circuitry of the LT3748. but for convenience in selecting a resistor divider ratio,
The INTVCC pin must be locally bypassed with a capacitor. the value may range from 5.76k to 6.34k. The resistor
This pin may also be connected to VIN if a third winding should be as close to the LT3748 as possible.
is not used and if VIN ≤ 20V. If a third winding is used, RFB (Pin 16): Input Pin for the External Feedback Resistor.
the INTVCC voltage should be lower than the input voltage This pin is connected to the transformer primary at the
for proper operation. external MOSFET power switch. The ratio of this resistor
GATE (Pin 6): N-Channel MOSFET Gate Driver Output. to the RREF resistor, times the internal bandgap reference,
Switches between INTVCC and GND. determines the output voltage (plus the effect of any
non-unity transformer turns ratio). The average current
SENSE (Pin 7): The Current Sense Input for the Control
through this resistor during the flyback period should be
Loop. Kelvin connect this pin to the positive terminal of
approximately 200μA. The resistor should be as close
the switch current sense resistor, RSENSE, in the source
to the LT3748 as possible.
of the N-channel MOSFET. The negative terminal of the
current sense resistor should be connected to the GND
plane close to the IC.
3748fb

LT3748
block diagram
T1 DOUT
NPS:1
VIN VOUT +
CIN
LPRI LSEC COUT
RFB
VOUT –
1 16
VIN RFB
TC
CURRENT –
Q1 Q2 BOUNDARY 1.223V
MODE DETECT +A4
TC INTVCC
12 –A1 5
RTC + CBIAS
20µA 6.04k
ERROR AMP
50µs MAX
1.223V + OFF TIMER
RREF gm
14 – MASTER
RREF LATCH
VARIABLE S S GATE
Q A4 6 NMOS
DELAY TIMER R R
R1 1.223V + INTERNAL
50µs MAX GND
EN/UVLO A3 ON TIMER
3 – REFERENCE 5µA 8, 9
AND
REGULATORS A2
R2 ––+
2.4µA SENSE
100mV 7
CURRENT RSENSE
LIMIT
SS VC
10 11
CSS RC
3748 BD
CC
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LT3748
Operation
The LT3748 is a current mode switching regulator con- Boundary Mode Operation
troller designed specifically for the isolated flyback topol- Boundary mode is a variable frequency, current mode
ogy. The special problem normally encountered in such switching scheme. The external N-channel MOSFET turns
circuits is that information relating to the output voltage on and the inductor current increases until it reaches the VC
on the isolated secondary side of the transformer must pin-controlled current limit. After the external MOSFET is
be communicated to the primary side in order to maintain turned off, the voltage on the drain of the MOSFET rises to
regulation. Historically, this has been done with opto- the output voltage multiplied by the primary-to-secondary
isolators or extra transformer windings. Opto-isolator transformer turns ratio plus the input voltage. When the
circuits waste output power and the extra components secondary current through the output diode falls to zero,
increase the cost and physical size of the power supply. the voltage on the drain of the MOSFET falls below VIN . A
Opto-isolators can also exhibit trouble due to limited boundary mode detection comparator detects this event
dynamic response, nonlinearity, unit-to-unit variation and turns the external MOSFET back on.
and aging over life. Circuits employing extra transformer
Boundary mode returns the secondary current to zero every
windings also exhibit deficiencies. Using an extra wind-
cycle, so the parasitic resistive voltage drops do not cause
ing adds to the transformer’s physical size and cost, and
load regulation errors. Boundary mode also allows the use
dynamic response is often mediocre.
of a smaller transformer compared to continuous conduc-
The LT3748 derives its information about the isolated tion mode and does not exhibit subharmonic oscillation.
output voltage by examining the primary-side flyback At low output currents the LT3748 delays turning on the
pulse waveform. In this manner, no opto-isolator nor external MOSFET and thus operates in discontinuous mode.
extra transformer winding is required for regulation. The Unlike traditional flyback converters, the external MOSFET
output voltage is easily programmed with two resistors. has to turn on to update the output voltage information.
The LT3748 features a boundary mode control method, Below 0.6V on the VC pin, the current comparator level
(also called critical conduction mode) where the part decreases to its minimum value and a variable delay timer
operates at the boundary between continuous conduc- waits to reset before turning on the external MOSFET. With
tion mode and discontinuous conduction mode. Due to the addition of delay before turning the MOSFET back
the boundary control mode operation, the output voltage on, the part starts to operate in discontinuous mode. The
can be calculated from the transformer primary voltage average output current is able to decrease while still allow-
when the secondary current is almost zero. This method ing a minimum off-time for the error amplifier sampling
improves load regulation without external resistors and circuitry. The typical maximum discontinuous off-time
capacitors. with VC equal to 0V is 24µs.
The Block Diagram shows an overall view of the system.
Many of the blocks are similar to those found in traditional
switching regulators, including current comparators, inter-
nal reference and regulators, logic, timers and an N‑channel
MOSFET gate driver. The novel sections include a special
sampling error amplifier and a temperature compensation
circuit.
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LT3748
Applications Information
Pseudo-DC Theory of Operation Combining with the previous VFLBK expression yields an
expression for VOUT, in terms of the internal reference,
The RREF and RFB resistors as depicted in the Block Diagram
programming resistors, transformer turns ratio and diode
are external resistors used to program the output voltage.
forward voltage drop:
The LT3748 operates much the same way as traditional
current mode switchers with the exception of the unique  R  1 
error amplifier which derives its feedback information VOUT = VBG  FB    − V −I (ESR)
R  N  F SEC
from the flyback pulse.  REF  PS 
Operation is as follows: when the NMOS output switch Additionally, it includes the effect of nonzero secondary
turns off, its drain voltage rises above VIN. The amplitude output impedance (ESR). This term can be assumed to
of this flyback pulse (i.e., the difference between it and be zero in boundary control mode.
VIN) is given as:
VFLBK = (VOUT + VF + ISEC • ESR) • NPS Temperature Compensation
VF = DOUT forward voltage The first term in the VOUT equation does not have a tem-
perature dependence, but the diode forward drop, VF , has a
ISEC = Transformer secondary current significant negative temperature coefficient. To compensate
ESR = Total impedance of secondary circuit for this, a positive temperature coefficient current source
is internally connected to the RREF pin. The current is set
NPS = Transformer effective primary-to-secondary
by resistor RTC to ground connected between the TC pin
turns ratio
and ground. To cancel the temperature coefficient, the
The flyback voltage is converted to a current by RFB and following equation is used:
Q2. Nearly all of this current flows through resistor RREF to
form a ground-referred voltage. This voltage is fed into the
dVF R FB 1 dVTC
=− • • or,
flyback error amplifier. The flyback error amplifier samples dT RTC NPS dT
this output voltage information when the secondary-side R FB
−RFB 1 dV
winding current reaches zero. The error amplifier uses a RTC = • • TC ≈
bandgap voltage, 1.223V, as the reference voltage. NPS dVF / dT dT NPS

The relatively high gain in the overall loop will then cause (dVF /dT) = Diode’s forward voltage temperature coef-
the voltage at the RREF resistor to be nearly equal to the ficient
bandgap reference voltage, VBG. The relationship between
VFLBK and VBG may then be expressed as: (dVTC /dT) = 1.85mV/°C
 VFLBK  VBG VTC = 0.55V
 
 R = R or The resistor value given by this equation should also
 FB  REF be verified experimentally and adjusted, if necessary, to
R  achieve optimal regulation over temperature.
VFLBK = VBG  FB  The revised output voltage is as follows:
 R REF 
 R  1 
VBG = Internal bandgap reference VOUT = VBG  FB   − V
R N  F
 REF   PS 
 VTC  R
−   • FB – ISEC (ESR)
 TC  NPS
R
3748fb

LT3748
Selecting Actual RREF , RFB and RTC Resistor Values With a new value of RFB selected, the temperature co-
efficient of the output diode in the application can be
The preceding equations define how the LT3748 would
tested to verify the nominal RTC value. The RTC resistor
regulate the output voltage if the system had no time delays
should be removed from the circuit under test (this will
and no error sources. However, there are a number of
cause VOUT to increase for this step) and VOUT should
repeatable delays and parasitics in each application which
be measured over temperature at a desired target output
will affect the output voltage and force a re-evaluation of
load. It is very important for this evaluation that uniform
the RFB and RTC component values. The following approach
is the best method for selecting the correct values. temperature be applied to both the output diode and the
LT3748—if freeze spray or a heat gun is used there can
The expression for VOUT, developed in the Operation sec- be a significant mismatch in temperature between the
tion, can be rearranged to yield the following expression two devices that causes significant error. Attempting to
for RFB: extrapolate the data from a diode datasheet or assuming
the nominal RTC value may yield a better result if there is
RREF • NPS ( VOUT + VF ) + VTC 
R FB = no method to apply uniform heat or cooling such as an
VBG oven. With at least two data points (although more data

points from hot to cold are recommended), the change
where: in V/°C can be determined by:
VOUT = Output voltage ∆VOUT V –V
= OUT1 OUT2
VF = Output diode forward voltage ∆TEMP TEMP1– TEMP2
NPS = Effective primary-to-secondary turns ratio Using the measured VOUT temperature coefficient, an exact
RTC value can be selected using the following equation:
VTC = 0.55V
RFB 1.85mV/°C
The equation assumes the temperature coefficients of the RTC = •
NPS ∆VOUT
output diode and VTC are equal and substitutes RFB/NPS for
∆TEMP
the value of RTC. This is a good first order approximation
but will be revisited later. If the value of RTC has changed significantly, which can
First, the value of RREF should be approximately 6.04k happen with the use of some output diodes that have
since the LT3748 is trimmed and specified using this a very low forward drop, the RFB value may need to be
value. If the impedance of RREF varies considerably from changed to restore VOUT to the desired value. As in the
6.04k, additional errors will result. However, a variation in previous iteration, after measuring VOUT , a new RFB can
RREF of several percent is acceptable. This yields a bit of once again be selected using:
freedom in selecting standard 1% resistor values to yield VOUT(DESIRED)
nominal RFB /RREF ratios. RFB(NEW) = • RFB(OLD)
VOUT(MEASURED)
With starting values for RFB and RTC, an initial iteration
of the application should be built with final selections of Once the values of RFB and RTC are selected, the regulation
all external components (transformer, diode, MOSFET, accuracy from board to board for a given application will be
etc.). The resulting VOUT should be measured and used very consistent, typically under ±5% when including device
to re-evaluate the value of RFB due to non-idealities in the variation of all the components in the system (assuming
sampling system: resistor tolerances and transformer windings matching
of 1% or better). However, if the transformer, the output
VOUT(DESIRED) diode or MOSFET switch are changed or the layout is
RFB(NEW) = • RFB(OLD)
VOUT(MEASURED) dramatically altered, there may be some change in VOUT .

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LT3748
Minimum Primary Inductance Requirements Output Power
The LT3748 obtains output voltage information from the Because the MOSFET power switch is located outside the
external MOSFET drain voltage when the secondary winding LT3748, the maximum output power is primarily limited
conducts current. The sampling circuitry needs a minimum by external components. Output power limitations can
of 400ns to settle and sample the output voltage while the be separated into three categories—voltage limitations,
MOSFET switch is off. This required settle and sample current limitations and thermal limitations.
time is controlled by external components independent of
The voltage limitations in a flyback design are primar-
the minimum off-time of the GATE pin as specified in the ily the MOSFET switch VDS(MAX) and the output diode
Electrical Characteristics table. The electrical specification reverse-bias rating. Increasing the voltage rating of either
minimum off-time is based on an internal timer and acts component will typically decrease application efficiency if
as a maximum frequency clamp. The following equation all else is equal and the voltage requirements on each of
gives the minimum value for primary-side magnetizing those components will be directly related to the windings
inductance: ratio of the transformer, the input and output voltages
LPRI ≥
( VOUT + VF(DIODE) ) • RSENSE • tSETTLE(MIN) • NPS and the use of any additional snubbing components.
The MOSFET VDS(MAX) must theoretically be higher than
VSENSE(MIN) VIN(MAX) + (VOUT • NPS) and the output diode reverse bias
VSENSE(MIN) = 15mV must be higher than VOUT + (VIN(MAX)/NPS), though leak-
tSETTLE(MIN) = 400ns age inductance spikes on both the drain of the MOSFET
NPS = Ratio of primary windings to secondary windings and the anode of the output diode may more than double
that requirement (see section on leakage inductance for
In addition to the primary inductance requirement for more details on snubbers). Figure 1 illustrates the effect
minimum settling and sampling time, the LT3748 has on available output power for several MOSFET voltage
internal circuit constraints that prevent it from setting the ratings while continuously maximizing windings ratio
GATE node high for shorter than approximately 250ns. for input voltage with a fixed MOSFET current limit and
If the inductor current exceeds the desired current limit output voltage. Increasing the MOSFET rating increases
during that time oscillation may occur at the output as the possible windings ratio and or maximum input voltage
the current control loop will lose its ability to regulate. and can increase the available output power for a given
Therefore, the following equation relating to maximum application. Both figures assume no leakage inductance
input voltage must also be followed in selecting primary- and high efficiency.
side magnetizing inductance:
50
VIN(MAX) • RSENSE • tON(MIN) VDS = 200V
LPRI ≥ VDS = 150V
VSENSE(MIN)
MAXIMUM OUTPUT POWER (W)
40
tON(MIN) = 250ns 30
The last constraint on minimum inductance value would VDS = 100V

20
relate to minimum full-load operating frequency, fSW(MIN),
and is derived from fSW = 1/(tON + tOFF): 10
LPRI ≤ VIN(MIN) • (VOUT + VF(DIODE)) • NPS/(fSW(MIN) • ILIM •

((VOUT + VF(DIODE)) • NPS + VIN(MIN))) 0
0 20 40 60 80 100
The minimum operating frequency may be lower than INPUT VOLTAGE (V)
the calculated number due to delays in detecting current 3748 F01
limit and detecting boundary mode that are specific to Figure 1. Maximum Output Power at 12VOUT with a
3A ILIM and Maximum VDS = 100V, 150V, 200V
each application.
3748fb

LT3748
The current limitation on output power delivery is gen- increasing as a percentage basis of loss as the output
erally constrained by transformer saturation current in voltage is increased. As power levels increase the output
higher power applications, although the MOSFET switch diode and transformer may exceed their rated temperature
and output diode will need to be rated for the desired specifications. Minimizing RMS output diode current,
currents, as well. Increasing the peak current on the pri- selecting a diode with minimal forward drop at expected
mary side of the flyback by reducing the RSENSE resistor currents and minimizing parasitic resistances and leakage
is the primary way to increase output power, and power inductance in the transformer will keep those components
delivered increases fairly linearly with current limit as below their maximum temperatures while maximizing
shown in Figure 2, until parasitic losses begin to dominate. efficiency. The following section discussing transformer
However, once the saturation current of the transformer selection will further help focus on how to minimize losses
is exceeded the energy coupling between the primary and in the output diode.
the secondary will be reduced and incremental power will While quiescent current in the LT3748 itself is low (ap-
not be delivered to the output. In addition, the primary proximately 300µA from VIN and 1mA from INTVCC), the
inductance will drop, the SENSE pin overcurrent threshold current required to drive the external MOSFET (fSW • QG),
may trip due to a corresponding rapid rise in current, and if drawn from VIN through the LT3748 INTVCC LDO, dis-
the transformer will have to absorb the energy that is not sipates (VIN – INTVCC) • fSW • QG. If that power is high
transferred through the saturated core, leading to heating. enough to cause significant heating of the LT3748 the
Some manufacturers may not specify the rated saturation current may need to be drawn from a third winding. Doing
current but it is a necessary specification when trying to so will push all thermal limitations outside of the LT3748.
minimize transformer size and maximize output power
and efficiency. Also necessary for proper design is data Selecting a Transformer
on saturation current over temperature—the saturation
of typical power ferrites may reduce by over 20% from Transformer specification and design is perhaps the most
25°C to 100°C. critical part of successfully applying the LT3748. In addi-
tion to the usual list of caveats dealing with high frequency
The thermal limitation in flyback applications for lower isolated power supply transformer design, the following
output voltages will be dominated by losses in the output information should be carefully considered.
diode, with resistive and leakage losses in the transformer
First and most importantly, since the voltage on the sec-
50 ondary side of the transformer is inferred by the voltage
ILIM = 3A sampled on the primary, the transformer turns ratio must
40 be tightly controlled to ensure a consistent output volt-

ILIM = 2A
age. A tolerance of ±5% in turns ratio from transformer
30
to transformer could result in a variation of more than
±5% in output regulation. Fortunately, most magnetic
20 ILIM = 1A component manufacturers are capable of guaranteeing a
turns ratio tolerance of 1% or better.
10
Linear Technology has worked with several leading mag-
0
0 20 40 60 80 100
netic component manufacturers to produce predesigned
INPUT VOLTAGE (V) flyback transformers for use with the LT3748. Table 1
3748 F02 shows the details of several of these transformers.
Figure 2. Maximum Output Power at 12VOUT
with 150V VDS(MAX) and ILIM = 1A, 2A, 3A
3748fb

LT3748
Table 1. Pre-Designed Transformers—Typical Specifications Unless Otherwise Noted
TRANSFORMER LPRI LLEAK NPS ISAT RPRI RSEC TARGET APPLICATION†
PART NUMBER Size (W x L x H) mm (µH) (nH) (NP:NS) (A) (mΩ) (mΩ) MANUFACTURER INPUT (V) OUTPUT
750311424 17.7 × 14.0 × 12.7 100 844 3:1 3 180 29 Würth Electronics 40 to 75 12V/1A
750311456* 17.7 × 14.0 × 12.7 100 900 3:1 2.4 225 31 Würth Electronics 40 to 75 12V/1A
750311439 17.7 × 14.0 × 12.7 37 750 2:1 2.8 89 28 Würth Electronics 30 to 75 12V/1A
750311458* 17.7 × 14.0 × 12.7 15 175 3:1 5 35 6 Würth Electronics 10 to 40 5V/2.5A
750311624 17.7 × 14.0 × 12.7 9 150 1.5:1 8 34 21 Würth Electronics 10 to 40 15V/1A
750311604 29.08 × 23.11 × 11.43 8 300 1:1 9.5 30 12 Würth Electronics 10 to 40 24V/1.3A
750311608 29.08 × 23.11 × 11.43 12 500 1.5:1 9 30 20 Würth Electronics 20 to 75 24V/1.3A
750311607 29.08 × 23.11 × 11.43 14 500 2.5:1 9.5 40 10 Würth Electronics 20 to 75 12V/2.5A
750311590 32.31 × 27.03 × 13.69 8 200 2:1 18 15 8 Würth Electronics 10 to 40 12V/3.8A
750311592 32.31 × 27.03 × 13.69 8 200 1:1 18 15 20 Würth Electronics 10 to 40 24V/1.9A
PA2367NL 17.7 × 14.0 × 12.7 85 750 2.7:1 1.7 325 26 Pulse Engineering 20 to 75 12V/1A
PA1276NL 17.7 × 14.0 × 12.7 77.4 800 1.47:1 1.6 100 75 Pulse Engineering 20 to 75 12V/1A
PA2467NL 17.7 × 14.0 × 12.7 37 750 2:1 2.9 89 28 Pulse Engineering 20 to 75 12V/1A
PA1260NL 17.7 × 14.0 × 12.7 77.4 800 3.67:1 1.5 220 18 Pulse Engineering 20 to 75 5V/2A
PA3177NL 29.21 × 21.84 × 11.43 8.3 100 2:1 8.6 10 7 Pulse Engineering 10 to 40 10V/2.5A
*2.5k isolation, others are rated for 1.5kV isolation.
†TARGET APPLICATION, NOT GUARANTEED.
Turns Ratio and RMS Diode Current efficiency and better utilize the saturation current of a
given transformer. Figure 3 shows the maximum output
Note that when using an RFB/RREF resistor ratio to set
power using three transformers with different windings
output voltage, the user has relative freedom in selecting
ratios that have the same output inductance and peak
a transformer turns ratio to suit a given application. In
output current, illustrating that increasing current while
contrast, simpler ratios of small integers (e.g., 1:1, 2:1,
decreasing turns ratio can deliver more power.
3:2, etc.) can be employed to provide more freedom in
setting total turns and mutual inductance. There are two significant constraints on the turns ratio.
First, as described in the previous section on limitations
While the turns ratio can be selected to maximize output
to output power, the drain of the MOSFET switch will
power for a given current limit, minimizing the turns
see a voltage equal to the maximum input supply plus
ratio and increasing the current limit will often increase
3748fb

LT3748
the output voltage multiplied by the windings ratio plus 25
NPS = 2:1
some amount of overshoot caused by leakage inductance. ILIM = 3A
Second, increasing the turns ratio will increase the peak 20
current seen on the output diode generally increasing the
OUTPUT POWER (W)

RMS diode current thereby lowering the efficiency. This 15
NPS = 3:1
efficiency limitation is worse at lower output voltages when ILIM = 2A
NPS = 6:1
the diode forward voltage is significant compared to the 10
ILIM = 1A
output voltage. In a typical application such as the 5V, 2A
5
output shown on the back page, the diode losses dominate
all the other losses, as shown in Figure 4. To calculate 0
RMS diode current, two equations are needed—the first 0 20 40 60 80 100
INPUT VOLTAGE (V)
for calculating duty cycle, D, and the second to calculate 3748 F03
the RMS current of a triangle waveform: Figure 3. Maximum Output Power at 12V Out Using Three
D=
( VOUT + VF(DODE) ) • NPS Transformers with Equal Peak Output Current and Secondary
Inductance
VIN + ( VOUT + VF(DIODE) ) • NPS 100
VIN = 12V
(ILIM • NPS ) • (1– D)

2
95
IDIODE(RMS) = DOUT
EFFICIENCY LOSS (%)
3 90
For a more general analysis, Figure 5 illustrates a sweep 85
of windings ratio on the x-axis while comparing output 80

fSW • QG + IQ
power and estimated efficiency for a 5V output using a FET RDS(ON)

48V input. If the desired application required 20W, the 75
maximum power curve indicates that a winding ratio of TRANSFORMER I • R + LEAKAGE

70
12:1 would be sufficient at a current limit of 2A (RSENSE = 0.2A MIN 2A MAX
0.05Ω), while a winding ratio of 5:1 would deliver the same IOUT (A)
3748 F03
power at 3A. However, when examining the corresponding

Figure 4. Sources of Loss In 5V, 2A Out Typical Application
efficiency at max load for those two windings ratios and
current limits, the 5:1, 3A selection is clearly the superior 100 32
solution with an estimated efficiency of 85% compared to ILIM = 3A
ESTIMATED MAX LOAD EFFICIENCY (%)
95 ILIM = 2A 28
78% for the 12:1, 2A application.
OUTPUT
90 POWER 24
There are several caveats to this evaluation. First, as the
85 20
diode forward voltage becomes a smaller percentage of
total loss at higher output voltages (>12V) the RMS current 80 16
becomes less of a concern and minimizing it will have a 75 12
much smaller impact on efficiency. More significantly, if 70 8

EFFICIENCY
a lower turns ratio forces the use of a diode with a larger 65 4
forward drop to obtain a higher reverse voltage rating, 60 0
any gains from minimizing current might be lost. For low 0 3 6 9 12 15 18
NPS
output voltages (3.3V or 5V) or high input voltages (>48V), 3748 F05
a turns ratio greater than one can be used with multiple

Figure 5. Estimated Efficiency and Output Power at 5VOUT from
primary windings relative to the secondary to maximize 48VIN vs Windings Ratio, NPS, at 2A and 3A Current Limits
the transformer’s current gain.
3748fb

LT3748
Saturation Current series resistance using the observed periods (tPERIOD, and
As discussed earlier in the Maximum Output Power sec- tPERIOD(SNUBBED)) and snubber capacitance (CSNUBBER) is
tion, because the core of the transformer is being used for below, and the resultant waveforms are shown in Figure 6.
energy storage in a flyback, the current in the transformer CSNUBBER
CPAR =
windings should not exceed their rated saturation current  tPERIOD(SNUBBED) 2
as energy injected once the core is saturated will not be   –1
transferred to the secondary and will instead be dissipated  tPERIOD 
in the core. Information on saturation current should be tPERIOD2
provided by the transformer manufacturers and Table 1 LPAR =
CPAR • 4π2
lists the saturation current of the transformers designed
for use with the LT3748. LPAR
RSNUBBER =
CPAR
Leakage Inductance and Snubbers
Transformer leakage inductance (on either the primary 90
or secondary) causes a voltage spike to appear at the 80
primary after the MOSFET switch turns off. This spike is 70
increasingly prominent at higher load currents where more 60
stored energy must be dissipated. Transformer leakage
VDRAIN (V)
50
inductance should be minimized.
40
In most cases, proper selection of the external MOSFET 30
NO SNUBBER
and a well designed transformer will eliminate the need for 20 WITH SNUBBER
CAPACITOR
snubber circuitry, but in some cases the optimal MOSFET 10 WITH RESISTOR
may require protection from this leakage spike. An RC 0
AND CAPACITOR
(resistor capacitor) snubber may be sufficient in applica- 0 0.05 0.10 0.15 0.20 0.25 0.30
TIME (µs)
tions where the MOSFET has significant margin beyond 3748 F06
the predicted DC drain voltage applied in flyback while a

Figure 6. Observed Waveforms at MOSFET Drain when
clamp using an RCD (resistor capacitor diode) or a Zener Iteratively Implementing an RC Snubber
might be a better option when using a MOSFET with very
little margin for leakage inductance spiking.
Note that energy absorbed by a snubber will be converted
The recommended approach for designing an RC snubber to heat and will not be delivered to the load. In high volt-
is to measure the period of the ringing at the MOSFET age or high current applications, the snubber may need to
drain when the MOSFET turns off without the snubber be sized for thermal dissipation. To determine the power
and then add capacitance—starting with something in dissipated in the snubber resistor from capacitive losses,
the range of 100pF—until the period of the ringing is 1.5 measure the drain voltage immediately before the MOSFET
to 2 times longer. The change in period will determine turns on and use the following equation relating that volt-
the value of the parasitic capacitance, from which the age and the MOSFET switching frequency to determine
parasitic inductance can be determined from the initial the expected power dissipation:
period, as well. Similarly, initial values can be estimating
PSNUBBER = fSW • CSNUBBER • VDRAIN2/2
using stated switch capacitance and transformer leakage
inductance. Once the value of the drain node capacitance Decreasing the value of the capacitor will reduce the dis-
and inductance is known, a series resistor can be added to sipated power in the snubber at the expense of increased
the snubber capacitance to dissipate power and critically peak voltage on the MOSFET drain, while increasing the
dampen the ringing. The equation for deriving the optimal value of the capacitance will decrease the overshoot.
3748fb

LT3748
Although it typically does not decrease efficiency, leakage ring beyond that expected reverse voltage. An RC snubber
inductance energy that would normally have been dis- or RCD clamp may be implemented to reduce the voltage
sipated in the switch or transformer is also dissipated in spike if it is desirable to use a lower reverse voltage diode.
the RC snubber resistor and can be calculated as:
Secondary Leakage Inductance
PSNUBBER = fSW • LLEAK • ILIM2/2
In addition to the previously described effects of leakage
An RCD clamp, shown in Figure 7, also prevents the
inductance in general, leakage inductance on the sec-
leakage inductance spike from exceeding the breakdown ondary in particular exhibits an additional phenomena. It
voltage of the MOSFET switch. In most applications, there forms an inductive divider on the transformer secondary
will be a very fast voltage spike caused by a slow clamp that effectively reduces the size of the primary-referred
diode. Once the diode clamps, the leakage inductance flyback pulse used for feedback. This will increase the
current is absorbed by the clamp capacitor. This period
output voltage target by a similar percentage. Note that,
should not last longer than 200ns so as not to interfere
unlike leakage spike behavior, this phenomena is load
with the output regulation. The clamp diode turns off after
independent. To the extent that the secondary leakage
the leakage inductance energy is absorbed and the switch
inductance is a constant percentage of mutual inductance
voltage is then equal to:
VDS = VIN + NPS • (VOUT + VF(DIODE)) 200
180
Schottky diodes are typically the best choice for use in a
160
snubber, but some PN diodes can be used if they turn on 140
DRAIN VOLTAGE (V)
fast enough to limit the leakage inductance spike. Figures 8 120

and 9 show the waveform at the drain of the MOSFET 100
switch for the 48V output application shown in Figure 17 80
at maximum rated load and maximum input voltage with 60 VIN = 96V
an RC snubber and RCD clamp, respectively. Both solu- 40
VOUT = 48V
IOUT = 0.5A
tions limit the leakage spike to less than 190V, below the 20 R = 66Ω
C = 150pF
200V VDS(MAX) rating of the Si7464DP MOSFET. 0
0 50 100 150 200 250 300
TIME (ns) 3748 F08
LLEAK
VIN VOUT+
Figure 8. Waveform of MOSFET Drain During Normal Operation
+ C R of Figure 19 with RC Snubber (as Drawn)
200
D
VOUT– 180
160
GATE NMOS
140
DRAIN VOLTAGE (V)
3748 F07
120
Figure 7. RCD Clamp 100

80
VIN = 96V
Leakage Inductance and Output Diode Stress 60 VOUT = 48V
IOUT = 0.5A
40
R = 4.99k
The output diode may also see increased reverse voltage 20 C = TDK 0.22µF 250V
stresses from leakage inductance. While it nominally sees 0
D = CMR1U-02M-LTC
0 50 100 150 200 250 300
a reverse voltage of the input voltage divided by the wind- TIME (ns) 3748 F08
ings ratio plus the output voltage when the MOSFET power
Figure 9. Waveform of MOSFET Drain During Normal Operation
switch turns on, the capacitance on the output diode and of Figure 19 Using RCD Clamp with Central Semiconductor
the leakage inductance will cause an LC tank which may CMR1U-02M-LTC Instead of RC Snubber
3748fb

LT3748
(over manufacturing variations), this can be accommodated GATE pin is near its final value, or until at least 150ns
by adjusting the RFB /RREF resistor ratio. has passed, whichever occurs more slowly. This should
be entirely sufficient for most applications but premature
Winding Resistance Effects tripping of the SENSE comparator may occur in cases
Resistance in either the primary or secondary will reduce where a MOSFET with very high QG is used with a series
overall efficiency (POUT /PIN). Good output voltage regula- resistor at the GATE pin.
tion will be maintained independent of winding resistance
Output Short Circuits and SENSE Pin Over Current
due to the boundary mode operation of the LT3748.
The LT3748 has an internal threshold to detect when
Bifilar Winding primary inductor current exceeds the programmed range.
A bifilar, or similar winding technique, is a good way to This can result from an inductive output short-circuit and
minimize troublesome leakage inductances. However, re- an output voltage below zero, reflecting a voltage back to
member that this will also increase primary-to-secondary the primary side of the transformer which, in turn, causes
capacitance and limit the primary-to-secondary breakdown the LT3748 to turn the external MOSFET on before the
voltage, so, bifilar winding is not always practical. The secondary current has discharged. When the voltage at
Linear Technology Applications group is available and the SENSE pin exceeds approximately 130mV—equiva-
extremely qualified to assist in the selection and/or design lent to 30% higher than the programmed ILIM(MAX) in
of the transformer. the RSENSE resistor—the SS pin will be reset, stopping
switching. Once the soft-start capacitor is recharged and
Selecting a Current Sense Resistor the soft-start threshold is reached, switching will resume
at the minimum current limit.
The external current sense resistor allows the user to
optimize the current limit behavior for the particular ap- High Drain Capacitance and Low Current Operation
plication under consideration. As the current sense resistor
is varied from several ohms down to tens of milliohms, When designing applications with some combination of a
peak switch current goes from a fraction of an ampere low current limit (ILIM < 1A), a high secondary-to-primary
to tens of amperes. Care must be taken to ensure proper turns ratio (NPS << 1), multiple output windings, or very
circuit operation, especially with small current sense capacitive output diodes, it is important to minimize the
resistor values. capacitance reflected onto the primary winding and on the
drain of the external MOSFET. After the MOSFET turns off
For example, a peak MOSFET switch current of 4A requires during each switching cycle, the primary current charges
a sense resistor of 0.025Ω. Note that the instantaneous that capacitance to slew the MOSFET drain until the second-
peak power in the sense resistor is 1W, and it must be ary begins to deliver power, and if the drain node does not
rated accordingly. The LT3748 has only a single sense line slew and remain above VIN within approximately 200ns
to this resistor. Therefore, any parasitic resistance in the once the GATE pin goes low and the MOSFET turns off,
ground side connection of the sense resistor will increase the LT3748 may detect that the current in the secondary
its apparent value. In the case of a 0.025Ω sense resistor, is zero and turn the MOSFET back on prematurely, caus-
1mΩ of parasitic resistance will cause a 4% reduction in ing the LT3748 to switch continuously while delivering
peak switch current. Therefore, resistance of printed circuit very little power to the output. The result will be droop of
copper traces and vias cannot necessarily be ignored. the output voltage at lighter loads and oscillation at the
Another issue for proper operation of the current sense VC node. This problem can be prevented by maximizing
circuitry is avoiding prematurely tripping the SENSE NPS (minimizing ratio of secondary windings to primary
threshold while slewing the MOSFET drain when the GATE windings), increasing the peak drain current (minimizing
pin goes high. The LT3748 does not begin to compare RSENSE), and minimizing the output diode and transformer
the SENSE pin voltage with the target threshold until the capacitance.
3748fb

LT3748
Soft-Start Minimum Load Requirement
The LT3748 contains an optional soft-start function that The LT3748 recovers output voltage information using
is enabled by connecting an explicit external capacitor the flyback pulse that occurs once the external MOSFET
between the SS pin and ground. Internal circuitry prevents turns off and the secondary winding conducts current. In
the control voltage at the VC pin from exceeding that on order to regulate the output voltage, the LT3748 needs to
the SS pin. sample the flyback pulse. The LT3748 delivers a minimum
The soft-start function is engaged whenever power at VIN amount of energy even during light load conditions to
is removed, or as a result of either undervoltage lockout, ensure accurate output voltage information. The minimum
overcurrent in the sense resistor or thermal (overtempera- delivery of energy creates a minimum load requirement
ture) shutdown. The SS node is then discharged to roughly on the output of approximately 2% of maximum load.
600mV. When this condition is removed, a nominal 5µA The minimum operating frequency at minimum load is
current acts to charge up the SS node towards roughly approximately 42kHz.
2.2V. For example, a 0.1µF soft-start capacitor will place Alternatively, a Zener diode sufficiently rated to handle the
a 0.05V/ms limit on the turn-on ramp rate at the VC node. minimum load power can be used to provide a minimum
load without decreasing efficiency in normal operation.
ENABLE and Undervoltage Lockout (UVLO) In selecting a Zener diode for this purpose, the Zener
A resistive divider from VIN to the EN/UVLO pin implements voltage should be high enough that the diode does not
undervoltage lockout (UVLO). The EN/UVLO pin threshold become the load path during transient conditions but the
is set at 1.223V. In addition, the EN/UVLO pin draws 2.4µA voltage must still be low enough that the MOSFET and
when the voltage at the pin is below 1.223V. This current output voltage ratings are not exceeded when the Zener
provides user programmable hysteresis based on the value functions as the minimum load.
of R1. The effective UVLO thresholds are:
INTVCC Pin Considerations
1.223V • (R1+ R2)
VIN(UVLO,RISING) = + 2.4µA • R1 The INTVCC pin powers the internal circuitry and gate
R2 driver of the LT3748. Three unique configurations exist
1.223V • (R1+ R2) for regulation of the INTVCC pin as shown in Figure 11. In
VIN(UVLO,FALLING) = the first configuration, the internal LDO drives the INTVCC
R2
pin internally from the VIN supply. In the second configura-
Figure 10 shows the implementation of external shutdown tion, the VIN supply directly drives the INTVCC pin through
control while still using the UVLO function. The NMOS a direct connection bypassing the internal LDO. Use this
grounds the EN/UVLO pin when turned on, and puts the optional configuration for voltages lower than 20V. In the
LT3748 in shutdown with a quiescent current draw of third configuration, an external supply or third winding
less than 1µA. drives the INTVCC pin. Use this option when a voltage
supply exists lower than the input supply but higher than
VIN
the regulated INTVCC voltage. Using a lower voltage sup-
ply provides a more efficient source of power for internal
R1
circuitry and reduces power dissipation in the LT3748.
EN/UVLO
RUN/STOP
When calculating the minimum input voltage required for
LT3748 R2 CONTROL
(OPTIONAL)
a valid INTVCC , or the power dissipated in the LT3748, it is
useful to know how much current will be drawn from the
GND
INTVCC LDO during normal operation. The easiest way to
3748 F10
calculate this current is to use the gate charge (QG) for the
Figure 10. Undervoltage Lockout (UVLO) selected MOSFET switch at the expected VIN and INTVCC
3748fb

LT3748
3.0
LT3748 VIN 5V TO 100V VIN = 5V
2.5
LDO
INTVCC DROPOUT (V)

2.0
(VIN – DROPOUT) TO 7V INTVCC UVLO = 3.6V
INTVCC 1.5
1.0
IINTVCC = 20mA
LT3748 VIN 5V TO 20V 0.5
0
LDO –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C)
3748 F12
INTVCC Figure 12. INTVCC Current at Low VIN Can Cause the LT3748
OPTIONAL
to Stop Switching Due to INTVCC Undervoltage Lockout
temperature, but when the dropout for the same current

LT3748 5V TO 100V
VIN
exceeds 1.4V and trips the UVLO at higher temperatures
the LT3748 will stop switching.
LDO
3.6V < BIAS < 20V,
VIN > BIAS
EXTERNAL SUPPLY
Overdriving INTVCC with a Third Winding
INTVCC OR THIRD WINDING
The LT3748 provides excellent output voltage regulation
without the need for an opto-coupler or third winding, but for
3748 F09
Figure 11. INTVCC Pin Configurations

some applications with input voltages greater than 20V, an
additional winding may improve overall system efficiency.
voltages and multiply that charge required with each The third winding should be designed to output a voltage be-
turn-on event by the maximum operating frequency. The tween 7.2V and 20V. A resistor in series with the rectifier is
maximum operating frequency in a given application can recommended to absorb leakage spikes. For a typical 48VIN,
be approximated from the primary transformer inductance, 10W application, overdriving the INTVCC pin may improve
the windings ratio (NPS), the nominal output voltage and efficiency by several percent at maximum load and as
the maximum input voltage. Unless the part is limited by much as 30% at light loads.
minimum on- or off-times, this maximum frequency will
occur when the part is regulating in boundary mode at the Loop Compensation
minimum peak switch current, and can be derived from: The LT3748 is compensated using an external resistor-
fSW(MAX) ≈
(
VIN(MAX) • VOUT + VF(DIODE) • NPS ) capacitor network on the VC pin. Typical values are in the
range of RC = 50k and CC = 1nF (see the numerous sche-
(( )
LPRI •ILIM(MIN) • VOUT + VF(DIODE) • NPS + VIN(MAX) ) matics in the Typical Applications section for other possible
values). If too large of an RC value is used, the part will be
With the maximum INTVCC current calculated, the expected more susceptible to high frequency noise and jitter. If too
dropout when VIN drops below 7V can be extracted from small of an RC value is used, the transient performance will
the curves in the Typical Performance Characteristics suffer. The value choice for CC is somewhat the inverse
section. The LT3748 is tested as low as VIN = 5V but of the RC choice: if too small a CC value is used, the loop
the hard limit on minimum VIN operation is the INTVCC may be unstable and if too large a CC value is used, the
regulator dropout and the 3.6V under voltage lockout. transient performance will also suffer. Transient response
Figure 12 illustrates an example where operation with VIN plays an important role for any DC/DC converter.
= 5V and IINTVCC = 20mA might be fully functional at room
3748fb

LT3748
Synchronous Secondary Applications 100
PRIMARY SIDE
Using a synchronous secondary controller such as the 80 DRAIN VOLTAGE
LT8309 with the LT3748 is an excellent method to boost
converter efficiency and minimize heat, especially for lower BODY DIODE
VOLTAGE (V)
60
CONDUCTION
output voltages and higher output currents. However,
there are some important details to understand when 40
designing a synchronous application. First, although the LT8309

VGATE
LT8309 controls a synchronous MOSFET in place of the 20
standard output rectifier, when properly configured that

synchronous MOSFET must turn off before the end of 0
0 1 2 3 4 5 6 7 8
the secondary conduction time. This ensures that there TIME (µs)
LT3748 F13
is no reverse current sending power back to the primary

side of the transformer and no cross conduction once the Figure 13. Waveforms at LT3748 Primary Side MOSFET
LT3748 GATE pin goes high on the next switching cycle. Drain and LT8309 GATE Pin During Operation Illustrating
Optimum Body Diode Conduction Time
As a result, the forward voltage drop of the secondary
MOSFET body diode is reflected back to the primary side
and sampled by the LT3748. In order to guarantee an
accurate sample and to maintain excellent line and load
regulation, the RDRAIN resistor of the LT8309 must be
optimized to allow the body diode to conduct long enough
to provide an accurate reflected voltage. To ensure ac-
curate output regulation the secondary MOSFET should
turn off at least 180ns before the secondary current goes
to zero. Figure 13 illustrates the expected waveform at
the primary side drain node and the LT8309 GATE pin us-
ing the circuit from Figure 21 with sufficient body diode
conduction time marked.
Because the body diode is conducting at the sampling
point for the LT3748 when the secondary current goes
to zero, the temperature coefficient of this body diode
should be compensated using the TC pin using the same
procedures outlined when a normal rectifier is used on the
secondary. The silicon junction of the body diode has a
negative temperature coefficient comparable to a standard
or Schottky diode and standard values specified earlier in
the applications section should be a good starting point.
3748fb

LT3748
DESIGN EXAMPLE: 12VIN to 5V, 2A OUT Evaluating the results of the table, the 1:2 turns ratio looks
demanding in terms of diode reverse-voltage requirements
The first example is an automotive application shown on
(a diode with higher reverse bias capability generally will
the back page of this data sheet—a nominal 12VIN, 5VOUT
at 2A with an operating input voltage range of 6V to 45V have a larger forward drop and therefore lower application
with a design focus of maximizing efficiency. efficiency) and primary side currents and only decreases
the output diode RMS current by 13% from the 1:1 case.
1. Select Transformer Turns Ratio However, on evaluating the minimum and maximum in-
ductance requirements in Step 3, even the 1:1 case does
Transformer turns ratio will affect the requirements for the not allow for enough on-time from maximum VIN for the
MOSFET switch VDS rating, the output diode reverse bias range of inductance that provides sufficient off-time.
rating, the output power capability, and the efficiency of For that reason, a 2:1 turns ratio is selected, easing the
the overall converter. Because the output voltage is low requirement on the output diode reverse voltage rating
compared to the forward drop on the output diode and in the process.
the currents are high in this application, efficiency can be
optimized by minimizing the RMS diode current. Typical 2. Calculate Sense Resistor Value
efficiency in a variety of applications will be 85% to 90%
The sense resistor can be calculated by the following
and due to compromises made for the wide input voltage
equation:
range and the low output voltage in this specific applica-
tion, an efficiency of 85% is assumed for calculating 100mV
RSENSE =
output power. This assumption can be revised once the ILIM
application is tested. Equations for evaluating each of the
important criteria are: The desired 5.8A current limit leads to an unusual value of
0.0172Ω, so the current limit is increased to use a more
NPS = NP/NS standard 0.016Ω value and ILIM of 6.25A.
VDS(MAX) ≥ VIN(MAX) + VOUT • NPS
3. Select a Transformer Based on Inductance and
VR(DIODE) ≥ VIN(MAX)/NPS + VOUT
Saturation Current Requirements
IOUT(MAX) ≈ 0.85 • (1 – D) • NPS • ILIM/2
The transformer in this application will be selected to
D = (VOUT + VF(DIODE)) • NPS/(VIN + (VOUT + VF(DIODE)) optimize efficiency at a 80kHz minimum switching fre-
• NPS) quency at maximum load from the nominal input voltage.
IDIODE(RMS) = √(ILIM • NPS)2 • (1 – D)/3 In applications where transformer size is the primary
The equation for output power can be rearranged to solve requirement, reducing the current limit or increasing the
for the current limit, ILIM, which can be solved at the switching frequency may be required. The following equa-
nominal or the minimum VIN depending on application tions select the inductance required for a given switching
requirements. In this application the 2A load requirement frequency at max load and then verify that the inductance
will be set at VIN = 7.5V to reduce operating stresses at is large enough to satisfy the minimum on and minimum
higher input voltages. The results of the aforementioned sampling times of the LT3748.
equations in this application are found in Table 2.
Table 2. Voltage Stresses, Output Capability and Diode Current vs Turns Ratio in 12VIN to 5V, 2A Application
NPS VDS(MAX) VR(DIODE) D (VIN = 12V) D (VIN = 7.5V) ILIM (2A OUT AT VIN = 7.5V) IDIODE(RMS) (VIN = 12V)
0.5 47.5 95 0.19 0.27 12.9 3.3
1 50 50 0.31 0.42 8.2 3.9
2 55 27.5 0.48 0.59 5.8 4.8
3 60 20 0.58 0.69 5.0 5.6
3748fb

LT3748
LPRI ≤ VIN(MIN) • (VOUT + VF(DIODE)) • NPS/(fSW(MIN) • ILIM • squared and multiplied by the RDS(ON) to calculate losses
(VOUT + VF(DIODE)) • NPS + VIN(MIN))) and the current required to drive the FET at frequency can
LPRI ≥ (VOUT + VF(DIODE)) • RSENSE • 400ns • NPS/15mV be determined, by the following equations:
LPRI ≥ VIN(MAX) • RSENSE • 200ns/15mV IMOSFET(RMS) = √ILIM2 • D/3

IINTVCC = fSW • QG
For this application, the primary inductance with a 2:1
transformer and a 0.016Ω sense resistor for an 6.25A PINTVCC = IINTVCC • (VIN – VINTVCC)
current limit is bounded by the minimum desired switch- In this application the MOSFET RMS current at maximum
ing frequency and the minimum off time requirement to
load is about 2.7A, which into the 0.038Ω RDS(ON) will be
be between 9.6µH and 11.5µH. Looking at Table 1, there 0.28W, or on the order of 2% loss in efficiency. Assum-
are no transformers that fit that exact requirement. For the ing that the maximum operating frequency is around four
sake of prototyping, a transformer with slightly less than the times higher than the maximum load frequency (at about a
desired primary inductance is selected with the PA3177NL. quarter the output load) and reading the approximate QG at
The application will need to be tested thoroughly for sta- 7V operation from the Vishay data sheet, the approximate
bility at higher input voltages and when the current limit
INTVCC current is likely close to 8mA, dissipating 0.04W
is at a minimum (in the middle of the output load range). when the load is on the order of 2.5W, or less than 2%,
The easiest solution to ease the requirement on minimum and much less at maximum load.
on-time is to reduce the maximum VIN voltage although
alternatively NPS could be increased at the expense of ef- 5. Select the Output Diode
ficiency (and requiring a more thorough redesign).
The output diode reverse voltage, as calculated earlier, is
4. Select a MOSFET Switch the first important specification for the output diode. As with
The selected 2:1 transformer requires a nominal 55V rating the MOSFET, choosing a diode with enough margin should
on the MOSFET switch, assuming no leakage inductance. preclude the use of a snubber. The second criterion is the
However, even a small amount of leakage inductance may power requirement of the diode which is more difficult to
cause the drain to ring to double the anticipated voltage, correctly ascertain—some manufacturers give direct data
and generally this needs to be verified in the final design. about power dissipation versus duty cycle, which can be
However, at currents below 10A it is fairly easy to find a used with the data from the table to determine. To avoid
MOSFET with sufficiently low RDS(ON) to be a very small using a snubber, a diode with a 60V reverse-bias capabil-
contributor to maximum load efficiency losses while ity and minimal forward drop was selected—in this case,
similarly having a low enough QG to require minimum the Diodes Inc. SBR 8U60P5. In this particular application
current and minimal losses when driving the MOSFET at where maximizing efficiency is the goal, minimizing the
lighter loads. Also, while considering the efficiency gains maximum voltage requirement on VIN may allow the use
and losses with a given MOSFET, it is important to real- of a diode with a lower reverse bias rating and a lower
ize that a trade-off in RDS(ON) for VDS(MAX) may backfire forward drop which could further increase efficiency. Al-
if a snubber needs to be added to the circuit to meet the ternatively, if no efficient diode is available for a particular
voltage requirements and dissipates more energy than the reverse bias rating, it may be more beneficial to increase
difference in switch resistance. For that reason, a Vishay the windings ratio until a diode with low forward drop can
Si7738 is selected to give lots of margin with its 150V be selected and then reevaluate whether that solution with
rating. The RMS current in the MOSFET can be calculated, higher RMS diode current is beneficial.
3748fb

LT3748
6. Select the Feedback Resistor for Proper Output was considered in order to maximize efficiency but was
Voltage unable to turn on fast enough to sufficiently clamp the very
Using the iterative process laid out earlier in the Applications fast leakage spike. The final solution is an RC snubber,
Information section, select the feedback resistor RFB and implemented iteratively, that decreases efficiency by less
program the output voltage to 5V. Adjust the RTC resistor than 1% across the majority of the output load range while
for temperature compensation of the output voltage. RREF reducing the worst-case drain voltage spike to just 80V.
is selected as 6.04k. Similarly, the anode of the output diode is probed to look
at potential ringing when the MOSFET switch turns on and
7. Select the Output Capacitor a peak of 45V is measured across the diode. Therefore,
no snubber circuitry is required.
The output capacitor should be chosen to minimize the
output voltage ripple while considering the increase in 9. Optimize the Compensation Network
size and cost of a larger capacitor. The following equation
calculates the output voltage ripple: To set the compensation, the application is first configured
with a 22nF capacitor and 10k resistor as a starting point. A
LPRI • ILIM2 load step is applied at both light and heavy loads at the 60V
∆VMAX =
2 • COUT • VOUT maximum input voltage and the capacitance is decreased

until damping decreases to the desired limit, in this case
8. Add Snubber Circuitry as Necessary with a compensation capacitance of 2.2nF and a response
implying about 60˚ of phase margin. After verifying stability
With the primary components selected, the application at the minimum input voltage, as well, the compensation
should be constructed to evaluate ringing at the drain of the capacitance is doubled for safety margin. The series resis-
MOSFET switch and to evaluate step response to optimize tance is varied from 5k to 50k but the optimal response is
the compensation network. If using an RC snubber, the observed with 24.7k. For best ripple performance, select
equations from the Applications Information section can a compensation capacitor not less than 1nF, and select a
be used or a rough estimate of component values may compensation resistor not greater than 50k.
come from using the published leakage inductance of the
transformer and selecting a snubber capacitor ranging 10. Soft-Start Capacitor and UVLO Resistor Divider
from 1 to 3 times larger than the published MOSFET output A soft-start capacitor helps during the start-up of the
capacitance. In this application, the peak MOSFET drain flyback converter. Select the UVLO resistor divider for
voltage was measured at maximum load from minimum VIN the intended input operation range. These equations are
and exceeded the 150V rating of the Si7738. A DZ clamp aforementioned.
3748fb

LT3748
DESIGN EXAMPLE: 48VIN to 12V, 2A OUT The output diode only nominally has 30V of reverse bias
but a B360 diode is selected to ensure enough margin that
The second example is a telecom application shown on
a snubber will not be required. A more expensive diode
the front page of the datasheet. The focus of this applica-
tion is a cheap, small and simple solution. Table 3 shows with lower forward drop might recover several percent
the results of the initial step for selecting the turns ratio. efficiency and if high temperature operation is required
a diode rated for more average current at temperature
In this example, the output diode is a much smaller ef- might be needed, but the B360 is small and inexpensive.
ficiency loss due to the smaller voltage drop across it in
ratio to VOUT so minimizing output diode current is not The rest of the design and component selection is straight-
forward.
as important. Of greater importance is minimizing the
stresses on the MOSFET and output diode and the 4:1 Suggested Layout
case seems to be the best compromise for that to avoid
using a snubber on either device. See Figures 14 and 15 for the DC1557A demo board lay-
out. Note the proximity of the RREF and RFB resistors (R9,
20µH of primary inductance is required for minimum R5) to the LT3748 for optimal regulation. The location of
off-time while selecting the transformer, but in order to these two resistors as close to the physical pins of the
minimize output ripple at maximum load a 60.8µH trans- LT3748 is critical for accurate regulation. In addition, the
former is selected. To meet the saturation current (12A,
high frequency current path from the VIN bypass capacitor
peak, on the secondary windings), a Versa-Pak VP4-0047-R (C2) through the primary-side winding, the MOSFET switch
provides a compact and efficient solution. and sense resistor (R10) is a very tight loop. Similarly,
For the MOSFET switch, since the input voltage is so high, the high frequency current path for the MOSFET gate
resistive losses on the primary side will be very low so switching from the INTVCC capacitor through the source of
minimizing RDS(ON) is of minimum benefit. However, since the MOSFET and sense resistor is similarly small in area.
the current for the gate drive is pulled from a high VIN, For improved regulation it is recommended that the user
minimizing both QG and operating frequency is essential ensure that the high current ground is kept separate or
unless a third winding is added. The Vishay Si7464DP, with at least physically isolated from the small-signal ground
a 200V VDS(MAX) and low gate charge, keeps the INTVCC used by the other ground-referenced pins.
current to just over 3mA, worst-case, which when added
to quiescent current will keep power dissipation in the
LT3748 to just over 1/4W at 72V VIN.
Table 3. Voltage Stresses, Output Capability and Diode Current vs Turns Ratio in 48VIN to 12V, 2A Application
NPS VDS(MAX) VR(DIODE) D (VIN = 48V) D (VIN = 36V) ILIM (2A OUT AT VIN = 36V) IDIODE(RMS) (VIN = 48V)
1 84 84 0.21 0.26 6 3.3
2 96 48 0.34 0.41 4 3.7
4 120 30 0.51 0.58 3 4.6
6 144 24 0.61 0.68 2 5.2
3748fb

LT3748
Figure 14. Demo Board Topside Silkscreen
Figure 15. Demo Board Topside Metal
3748fb

LT3748
typical Applications
T1 320V
1:1:1:1:1 VO1
VIN IGBT
12V TYP DRIVER
10µF 1µF 825k D1
VIN 6µH 15V C1 Z1
EN/UVLO 300mA
71.5k
150k RFB
RREF VO2
IGBT
6.04k DRIVER
D2
LT3748 15V C2 Z1
M1 300mA
TC GATE
VO3
SS SENSE IGBT
DRIVER
VC GND INTVCC 0.0125Ω D3
15V C3 Z1
133k 2nF 10k 300mA
4700pF 4.7µF
VO4 3-PHASE
IGBT MOTOR
C1-C4: 22µH 25V X7R ×2 D4 49.9k CATHODE DRIVER
15V C4
D1-D4: DIODES INC. PDS3100
300mA REF
M1: VISHAY Si7898DP
T1: COILTRONICS VERSA-PAC VP4-0075-R 9.09k TL431ACD
Z1: DIODES INC. DFLZ18-7 ANODE
0V
Figure 16. Automotive IGBT Controller Supply 3748 F16
17.0
16.5
VO4 (NO LOAD)
OUTPUT VOLTAGE (V)
16.0
VO3(100mA)
15.5
15.0
VO1 (300mA) VO2 (SWEPT)

14.5
14.0
0 200 400 600 800
LOAD CURRENT (mA)
LT3748 F17
Figure 17. Cross Regulation Performance of the Supply in Figure 16 with VO1 and VO3 Loaded with VO2 Swept
3748fb

LT3748
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY

T1
D1 VOUT+
VIN 1:10:10
300V
7V TO 15V 8mA
C1 C2 C8
R5 R7
10µF 1µF 0.22µF C5
10k 600k
R1 50V
357k D3
VIN R3 VOUT–
EN/UVLO
140k D2
R2 RFB VOUT+
93.1k 300V
RREF 8mA
C6 R8
R4
LT3748 600k
SS 6.04k
VOUT–
TC GATE M1
SENSE
C7 VC GND INTVCC 50mΩ
0.1µF
3748 F18
C9 R6
100pF 24.9k C3
C4 4.7µF
2.2nF
C5, C6: 0.1µF 600V ×2

D1, D2: CENTRAL SEMICONDUCTOR CMR1U-06M LTC
M1: FAIRCHILD FDM3622
T1: WÜRTH ELEKTRONIK 750311486
D3: CENTRAL SEMICONDUCTOR CMMR1U-02
Figure 18. ±300V Isolated Flyback Converter
3748fb

LT3748
T1 D1 VOUT+
VIN 1:1 48V
48V TYP 0.5A
4.7µF 0.22µF 4.7µF
66Ω
825k 44.1µH 100V
VIN ×3
150pF
EN/UVLO VOUT–
226k
49.9k RFB
RREF
LT3748 6.04k
TC GATE M1
SS SENSE
VC GND INTVCC 0.030Ω
2nF 10k 3748 F19
4700pF 4.7µF
D1: CENTRAL SEMICONDUCTOR CMR5U-02-LTC

M1: VISHAY Si7464DP
T1: COILTRONICS VERSA-PAC VP4-0060-R
Figure 19. 48V, 0.5A Supply from 24V to 96V Input
100
95
VIN = 24V
90
EFFICIENCY (%)
85
VIN = 48V
80
VIN = 96V
75
70
65
60
0 0.1 0.2 0.3 0.4 0.5
OUTPUT CURRENT (A)
3748 F20
Figure 20. Efficiency of 48V Supply of Figure 17
3748fb

LT3748
PA1735NL
VIN 5.33:1:2.67
36V TO VOUT+
72V 5V, 8A
62µF D1 100Ω •
1.2M 910µF
VIN D2 120pF • D4 3Ω
EN/UVLO VCC
51k 147k 1µF D6
LT3748 RFB LT8309
RREF
2.15k D5
6.04k
DRAIN
TC INTVCC
GATE GATE
28k M1 M2
SS GND
D1: SMBJ85A-13-F SENSE
0.22µF VC GND INTVCC 4.7µF
D2: CMMRIU-02 0.012Ω
D3: BAV20W-7-F VOUT–
D3 68Ω
D4: BAV20W-7-F
D5: CMZ5919B 470pF 12.1k 3784 TA21
4.7nF
D6: CMHZ5258B •
M1: BSC320N20NS3G 15nF 4.7µF
M2: BSC028N06NS
Figure 21. 5V, 8A Isolated Supply with Synchronous Secondary-Side Rectification Using LT8309
92
90
88
LT8309 & MOSFET
EFFICIENCY (%)
86
84
82 PDS760
DIODE
80
VIN = 36V
78 VIN = 48V
VIN = 72V
76
0 1 2 3 4 5 6 7 8 9
ILOAD (A)
Figure 22. Efficiency of the Supply in Figure 21 as well as Performance Using a Conventional PDS760 Schottky Rectifier
3748fb

LT3748
Figure 23 Thermal Image of the Supply in Figure 21 Using a PDS760 Instead of the LT8309 and Synchronous Switch at 5V/5A Output
Figure 24 Thermal Image of the Supply in Figure 21 with Synchronous Secondary-Side at 5V/5A Output with Much Lower Temperatures
3748fb

LT3748
PA1477NL
8:1.4
VIN VOUT+
36V TO 3.3V, 10A
72V 62µF D1 100Ω •
1.2M 1500µF
VIN D2 120pF • D4 3Ω
EN/UVLO VCC
51k 158k 1µF D6
LT3748 RFB LT8309
RREF
2k D5
6.04k
DRAIN
INTVCC
TC GATE GATE
M1 M2
19.1k GND
D1: SMBJ85A-13-F SS SENSE
D2: CMMRIU-02 VC GND INTVCC 4.7µF
0.22µF 0.015Ω
D3: BAV20W-7-F D3
D4: BAV20W-7-F 68Ω VOUT–
D5: CMZ5914 B 470pF 15k •
3748 F25
D6: CMHZ5258B 4.7nF

M1: BSC320N20NS3G 4.7µF
22nF
M2: BSC016N04LS
Figure 25. 3.3V, 10A Isolated, Synchronous Flyback Converter
100
95
90
EFFICIENCY (%)
85
80
75 VIN = 36V
VIN = 48V
VIN = 72V
70
0 200 400 600 800 10
LOAD CURRENT (A)
LT3748 F26
Figure 26. Efficiency of the Supply in Figure 25
3748fb

LT3748
Package Description
MS Package
Varitation: MS16 (12)
16-Lead Plastic MSOP with 4 Pins Removed
(Reference LTC DWG # 05-08-1847 Rev A)
1.0
(.0394) 0.889 ± 0.127
BSC (.035 ± .005)
5.23
(.206) 3.20 – 3.45
(.126 – .136) 4.039 ± 0.102
MIN
(.159 ± .004)
(NOTE 3) 0.280 ± 0.076
16 14 121110 9 (.011 ± .003)
REF
0.305 ± 0.038 0.50
(.0120 ± .0015) (.0197)
TYP BSC
3.00 ± 0.102
4.90 ± 0.152
RECOMMENDED SOLDER PAD LAYOUT (.118 ± .004)
(.193 ± .006)
(NOTE 4)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
1 3 567 8
GAUGE PLANE 1.0
(.0394)
0.53 ± 0.152 BSC
(.021 ± .006) 1.10 0.86
(.043) (.034)
DETAIL “A” REF
MAX
0.18
(.007)
SEATING
PLANE 0.17 – 0.27 0.1016 ± 0.0508
(.007 – .011) (.004 ± .002)
TYP 0.50
NOTE: (.0197)
MSOP (MS12) 0510 REV A
1. DIMENSIONS IN MILLIMETER/(INCH) BSC

2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3748fb

LT3748
Revision History
REV DATE DESCRIPTION PAGE NUMBER
A 10/10 Added H-grade information to Absolute Maximum Ratings, Pin Configuration, Order Information, and Electrical 2, 3
Characteristics sections.
Revised text and Table 2 in the Applications Information section. 15, 16, 20, 22
Revised Figures 10 and 17 in the Applications Information section. 26, 27
Revised Typical Application drawing. 30
B 2/15 Added MP-grade device. 2, 3
Added Synchronous Secondary Applications paragraphs 20
Added Figures 21, 22, 23, 24, 25 and 26 29, 30, 31
3748fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection information
of its circuits www.linear.com/LT3748
as described herein will not infringe on existing patent rights. 33
LT3748
Typical Application
5V, 2A Output from Automotive Input with Continuous Operation from 6V to 45V
T1 D1
VIN 2:1 VOUT+
12V TYP 5V, 2A
10µF 18.2Ω 100µF
10V D2
8.3µH
825k 330pF
VIN VOUT–
EN/UVLO
48.7k
215k RFB
RREF
6.04k
LT3748
D1: DIODES INC. SBR8U60P5
D2: DIODES INC. BZT52C5V6
TC GATE M1 M1: Si7738DP
T1: PULSE PA3177NL
SS SENSE
VC GND INTVCC 0.016Ω
86.6k 47nF 24.7k 3748 TA02
2.2nF 4.7µF
Related Parts
PART NUMBER DESCRIPTION COMMENTS
LT8300 100VIN Micropower Isolated Flyback Converter with Low IQ Monolithic No-Opto Flybacks, 5-Lead TSOT-23
150V/260mA Switch
LT8301 42VIN Micropower Isolated Flyback Converter with Low IQ Monolithic No-Opto Flybacks, 5-Lead TSOT-23
65V/1.2A Switch
LT8302 42VIN Micropower Isolated Flyback Converter with Low IQ Monolithic No-Opto Flybacks, 8-Lead SO-8E
65V/3.6A Switch
LT8309 Secondary-Side Synchronous Rectifier Driver 4.5V ≤ VCC ≤ 40V, Fast Turn-On and Turn-Off, 5-Lead TSOT-23
LT3573 40V Isolated Flyback Converter Monolithic No-Opto Flyback with Integrated 1.25A, 60V Switch
LT3574/LT3575 40V Isolated Flyback Converters Monolithic No-Opto Flybacks with Integrated 0.65A / 2.5A 60V Switch
LT3757/LT3758 40V/100V Flyback, Boost Controllers Universal Controllers with Small Package and Powerful Gate Drive
LT3957/LT3958 40V/100V Flyback, Boost Converters Monolithic with Integrated 5A/3.3A Switch
LT1725 20V Isolated Flyback Controller Controller with Load Compensation Circuitry
LT1737 20V Isolated Flyback Controller No Opto-Isolator or Third Winding Required, Up to 50W Output
LTC 3803/LTC3803-3
®
200kHz/300kHz Flyback DC/DC Controllers VIN and VOUT Limited Only by External Components
LTC3803-5
LTC3805/LTC3805-5 Adjustable Frequency Flyback Controllers VIN and VOUT Limited Only by External Components
3748fb
34 Linear Technology Corporation

LT 0215 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/LT3748
(408) 432-1900 ●● FAX: (408)
(408) 434-0507
434-0507 ●● www.linear.com/LT3748
www.linear.com  LINEAR TECHNOLOGY CORPORATION 2010

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LT3748

11.6 VIN = 72V

For more information www.linear.com/LT3748 1

VIN to RFB...................................................................±5V VIN 1 16 RFB

EN/UVLO.......................................................–0.3V, 100V EN/UVLO 3 14 RREF

INTVCC.....................................................VIN + 0.3V, 20V INTVCC

LT3748E/LT3748I................................ –40°C to 125°C TJMAX = 150°C, θJA = 90°C/W

LT3748H............................................. –40°C to 150°C

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QUIESCENT CURRENT (mA)

QUIESCENT CURRENT (mA)

INTVCC Undervoltage Lockout

7.2 6.5 3.8

INTVCC UVLO (V)

6.0 3.7 RISING THRESHOLD

INTVCC Regulator Dropout

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EN/UVLO THRESHOLD (V)

SENSE THRESHOLD (mV)

Maximum Discontinuous Off-Time GATE Rise and Fall Time

29 tr, tf 10% TO 90%

GATE RISE AND FALL TIME (ns)

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The last constraint on minimum inductance value would VDS = 100V

LPRI ≤ VIN(MIN) • (VOUT + VF(DIODE)) • NPS/(fSW(MIN) • ILIM •

the calculated number due to delays in detecting current 3748 F01

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40 be tightly controlled to ensure a consistent output volt-

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current seen on the output diode generally increasing the

OUTPUT POWER (W)

(ILIM • NPS ) • (1– D)

For a more general analysis, Figure 5 illustrates a sweep 85

of windings ratio on the x-axis while comparing output 80

power and estimated efficiency for a 5V output using a FET RDS(ON)

maximum power curve indicates that a winding ratio of TRANSFORMER I • R + LEAKAGE

power at 3A. However, when examining the corresponding

becomes less of a concern and minimizing it will have a 75 12

much smaller impact on efficiency. More significantly, if 70 8

a turns ratio greater than one can be used with multiple

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the predicted DC drain voltage applied in flyback while a

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fast enough to limit the leakage inductance spike. Figures 8 120

Figure 7. RCD Clamp 100

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INTVCC DROPOUT (V)

LT3748 VIN 5V TO 20V 0.5

temperature, but when the dropout for the same current

Figure 11. INTVCC Pin Configurations

fast enough to limit the leakage inductance spike. Figures 8 120