Published in the 1998 IEEE Frequency Control Symposium.

SINE OUTPUT DDSs A SURVEY OF THE STATE OF THE ART

Kenneth A. Essenwanger
Raytheon Systems Company
P.O. Box 2999, TO/231/ 2011
Torrance, CA 90509-2999
and
Victor S. Reinhardt
Hughes Space and Communications Company
P.O. Box 92919, SC/S12/W320
Los Angeles, CA 90009

Abstract Introduction
This paper presents a survey of the latest techniques Sine output direct digital synthesizers (DDSs) digitally
and hardware advances in sine output direct digital generate a stepped sine wave at an output frequency fo
synthesizers (DDSs). from a clock frequency fc (figure 1). These DDSs have
First, a brief description of the theory of sine output been in use since the late 1960s [Gillette, 1969] and have
DDSs is presented. A sine output DDS has the advantage become more and more popular as digital logic has
of being able to synthesize high spectral purity sine wave advanced in complexity and performance. Sine output
signals over a wide range of frequencies utilizing compact DDSs are not the only type of DDSs [Reinhardt, 1985], but
digital integrated circuits containing an accumulator, a sine have become the most widely used because of their high
look-up table, and a digital-to-analog converter (DAC). spectral purity and all digital implementation. This paper
(The DDS is completed with an output filter.) The DDS surveys the latest developments in the state of the art of
can produce an output frequency from zero to a maximum sine output DDSs and discusses the direction of future
frequency that is on the order of 1/3 of the clock frequency advances. To simplify terminology in the remainder of this
of the digital components. The principal advances in DDSs paper, we will refer to sine output DDSs as DDSs with the
have been in increasing the maximum frequency (clock implication that we are discussing only the sine output
speed) and in increasing the spectral purity (spur type.
reduction). F re q u e n c y W o rd K (N -b its )

Second, sine output DDS designs are examined that C lo c k P h a s e

fall into two broad categories: designs for high speed and fc G e n e ra to r
M -b its
spectrally clean performance and designs for applications
S in e W a v e
that require special features. Results are presented showing G e n e ra to r
how the spectral purity of the DDS is related to the L -b its
complexity and performance parameters of the digital
D ig ita l D /A
components. Recent advances in architectural techniques A p p lic a tio n D -b its
are described that are designed to optimize spectral A n ti-A lia s in g
performance while minimizing architectural complexity. F ilte r
fo = (K /2 N ) fc
Finally, a survey of the latest DDSs and components A n a lo g
developed by several manufacturers are described A p p lic a tio n

presenting key performance parameters such as clock Figure 1. Conceptual Block Diagram of a (Sine Output)
speed, spectral purity, frequency resolution, DC power DDS. The analog application requiring the DAC is the
consumption, and special features. A plot of reported focus of this paper as both the digital and DAC
spurious performance on DDSs (or DACs for DDSs) is imperfections are discussed.
presented revealing a performance barrier that designers
are striving to break. The advances necessary to break this In addition, three techniques for the digital generation
barrier will be discussed. of a sine output are shown in figure 2. The digital signal
processor (DSP) computes the sine output but is typically
slow compared to the DDS. The waveform generator reads
sine-output data from previously written random access

For research purposes. This material is copyrighted by the IEEE.

memory (RAM). This technique is widely used in test the phase generator increments the phase φ n by an amount
equipment for radar and communications applications. The
given by
scope of this paper is limited to the accumulator based
K
sine-output DDS. ∆φ = 2π
Direct Digital Waveform
Generator
Digital Signal 2N
Synthesizer Processor
K
where K is an N-bit frequency word. Since this occurs at
Pre-load Waveform K
Accumulator fc the clock rate, the phase steps through 2π radians at a
DSP Computes
RAM fc
Sine Output
fc frequency
Sine Generator K
fo = fc = F r f c
2N
Figure 2 Three methods for the digital generation of sine φ n is then truncated to M-bits and sent to the sine wave
output wavefroms are shown. The DSP is typically slow. generator, which generates an L-bit digital word
The waveform generator is widely used in test equipment proportional to sin(φ n ) .
pattern or arbitrary waveform generators in radar and If the DDS is utilized in a digital application as part of
communications applications. The phase accumulator a larger digital signal processor, the DDS is complete as
followed by a sine generator (phase-to-amplitude described. If an analog output is required, a digital-to-
translation) based DDS is the focus of this paper. analog converter (DAC) and an anti-aliasing filter are
required to complete the DDS. The DAC takes the sine
Id e a l S in e
O u tp u t output word truncated to D-bits and converts this into a
δ v (t)
t stepped voltage as shown in Figure 1. The anti-aliasing
filter, whose low pass knee is below fc/2, is required to
A c tu a l
O u tp u t smooth the output to improve the spectral purity.
v (t) According to the Sampling Theorem, a perfect sine wave
(a) with no phase jitter is recovered, if the process of
Spurs Principal Spur From generating the stepped sine voltage output were perfect.
1st Harmonic K (N -b its )
B=2N
Phase
f G e n e ra to r
T r u n c a t io n to M - B its
0 fo fc/2 fc-fo fc
S in e W a v e
(b) G e n e ra to r S in e A c c u r a c y
Many Harmonics Coalesce 2 M x L B it s
Spurs into a Few Spurs T r u n c a tio n to L -B its
fr=3/8 D /A
f
S ta t ic : T r u n c a t io n to D -B it s
0 fo fc A c c u ra c y
D y n a m ic : R o ll-O v e r G litc h
(c) N o n -lin e a r S le w R a te
Figure 3. (a) The uniformly stepped output is periodic with Figure 4. Some static errors are due to word length
period B (b) The Fourier harmonic expansion due to the truncations in the DDS and DAC, and some dynamic
perodicity of B results in B spurs from frequency 0 to Fc. errors are due to the roll-over glitch and non-linear slew
The non-ideal sine wave also has a Fourier harmonic rate. An in-depth description of how to linearly slew the
expansion. Aliasing moves these spurs from the harmonic DAC response is given by [Essenwanger, 1998].
locations to the B locations. (c) However, for the
normalized frequency (Fr =K/B), when K and B are not Imperfections in the sine generation process cause
relatively prime, the fraction is written as an irreducible spurious outputs to be generated (figure 3). Because of the
fraction (i.e. 3/8), and the multitude of B spurs are uniform sampling process involved, these imperfections
coalesced into a few spurs as shown. An in-depth can be aliased down to low frequency offset spurs, which
derivation is given by [Reinhardt, 1985]. can be as close as 2-Nfc from the carrier [Reinhardt, 1985].
These imperfections are caused by several factors
The conceptual block diagram of a (sine output) DDS [Reinhardt, 1985]. First, the truncation of the phase word
shown in Figure 1 consists of two components, a phase to M-bits, the sine generation accuracy and truncation to L-
generator and a sine wave generator. The phase generator bits cause imperfections in the sine output. Second, DAC
is driven by a clock frequency fc. At the nth clock period,

2
 q2
imperfections, which can be classed as static and dynamic E (ε )= 12
2

imperfections, also cause spurs (figure 4). The static

imperfections are due to the D-bit truncation of the DAC
word and the static inaccuracies of the DAC. Dynamic
noise rms
≈ E (ε ) =
2 q
12
=
1
12
for q normalized

imperfections are largely due to the non-linear slew rate of 2

k

signal =
the DAC [Essenwanger, 1998] and the fact that all the bits rms
2 2
of a DAC don’t switch at the same time, causing a glitch as  
the input word is changed (glitch area). Spur levels are  k 
 signal   2 
generally given by 6 dB per bit of accuracy, though the SNR = 20 log   = 20 log  
 noise  2 2
DAC imperfections can generate spurs at the 7-8.5 dB per  
 12 
bit level [Garvey, 1990]. The reader is referred to
[Reinhardt, 1985] for an in-depth derivation of the = 20 log (2 ) + 20 log  26  k

harmonic aliasing of spurious frequencies in DDS.  

≈ 20 log (2 ) + 1 . 761 = 20 log (2 ) + 1 . 7609
k 8
The 6-dB per bit rule-of-thumb is valid when the for an 8 - bit DAC
aliased spurious power is coalesced into one spur [Tierney, ≈ 48 . 1 + 1 . 8 = 49 . 9 dB
1971] or summed. The coalescing into a few spurs is This result, in close agreement with the typical level
shown in figure 3c, but the summation of spurious power shown in figure 5, confirms the practical usefulness of the
may also be computed for all output frequencies Fo as 6 dB per bit rule-of-thumb (the 1.8dB constant is
shown in figure 5, where all spurs are summed up to fc/2 or understood). The root-mean-squared (RMS) was also
200MHz for this example. At Fo=1/4 fc (100MHz) there studied instead of the RSS with similar results, except the
are no spurious. At Fo=1/8 fc and 3/8 fc worst case spurious RMS had slightly more variations (not as smooth) as
results. shown in figure 5.
100
90
dBc
80
.

70
Effective Number

60
of Spurs

50 E ffe c t. #
I d e a l F la t #
40
30
Probable Spur
20
Region
10
0
0 20 40 60 80 100
T h e o r e tic a l N u m b e r o f S p u r s
Fo MHz
Figure 5. The root-sum-square of spurious power as a Figure 6. The effective number of dominant spurs is
function of output frequency [Essenwanger, 1996]. The reduced from the theoretical spectrally flat number by the
response is searched for worst case start phase and post- coalesced spurs for DDSs.
compensated for sinc(πFr)sinc(πFr∆) [Essenwanger,
1998]. In figure 6, most of the power is divided among the
fewer dominant coalesced spurs. For the ideal flat spurious
The RSS of spurious is based on the following spectrum case, the spurious power is evenly divided among
equation [Essenwanger, 1996], after “total integrated all spurs. The 6 dB/Bit rule-of-thumb is approached as the
spurious” [Kent, 1995]: two curves converge and approach the one spur assumption
1 near the chart origin.
 i < Nyquist
(Cm i )
2

 i∑ =1 DDS Survey
RSS Spurious
= 20 log  
 Cm 0  Table 1 shows various phase-to-sine conversion
  architectures (or DDS back-end circuitry) for which
where Cmi = magnitude of power. i = 0 for the Vankka has simulated worst case spurious (algorithm
fundamental. i = 1,2,3,…,(<Nyquist Rate) for spurious, error) [Vankka, 1998]. Raytheon’s back-end (BE)
excluding the alias. The approximate variance power of the architecture is appended to the bottom of the table as well
errors for a uniform quantizer is well known [Rabiner, as the unmodified Sunderland BE. It is difficult to compare
1975], [Colotti, 1990] as architectures when new unconventional methods of
where q is the quantization. Thus, for uniform quantization performance are used without all parameters and
of a sine wave

3
conditions defined. The Vankka worst case spur was for the simulations, the same data is not available for the
reported to be simulated for the Nicholas phase Raytheon DDS; however, the unmodified Sunderland
accumulator. Because it is not clear all of the conditions architecture is 12-bits +/- 2 LSBs which has a worst case
spur of nearly 61.8dBc by the 6dB/Bit + 1.8dB rule-of-
thumb. Sunderland reports measured performance for
Fr=3/8 of 65.4dBc [Sunderland, 1984]. Simulations with
an ideal DAC model for Fr=11/32 gives -67dBc
[Essenwanger, 1987] (without a search routine for the
worst-case start phase).

Table 1. Modified Vankka’s Table [Vankka, 1998]: updated with the Raytheon [2] and unmodified Sunderland [26]
Direct Digital Synthesizer Back-End Sine-Output Architectures.
Worst Case
Algorithm
ROM Required Compression Significant Additional Error
Architecture [bits] Ratio Logic Circuits [dBc] Comments
Uncompressed
ROM 2 14 x 12 1:1 (none) -97.23 reference
Modified 28 x 9
Sunderland 28 x 4 59:1 adder -86.91 good spur level and simple
Nicholas Fine
8
Linear 2 x9
Interpolation 28 x 3 128:1 adder/subtract -88.94 best compression ratio
Conventional 2 7 x 14
Taylor Series 27 x 9 conventional multipliers are
Approximation 25 x 3 64:1 2 adders, multiplier -97.04 slow
14 pipelined stages, 18- slightly more circuitry needed,
Cordic (none) N/A bits wide -84.25 AM possible
7
Raytheon's Taylor 2 x 14 67:1 (w.r.t. optimized for performance,
Series 2 7 x 11 2^14x13 multiplier, multiplexer, 13-bits and cell reuse from a sine and
Approximation 25 x 7 ROM) adder +
/ - 1-bit cosine output capable design
Unmodified 2 8 x 11 12-bits
Sunderland 28 x 4 51:1 adder +
/ - 2-bits simple

SFDR Far Future Vankka also reports that the modified Sunderland is
5 to 10 years DDS 14 dB better than the unmodified Sunderland. Thus, the
Design
-90dB Goal Vankka simulation for the unmodified Sunderland DDS
Near Future should be about 14-86.91= -72.91dBc. Hence, there is
2 to 3 years about an 11dB discrepancy from worst case spurious
-70dB predictions by the rule-of-thumb for the conventional
Current Sunderland architecture and about a 6dB discrepancy (or
Technology more) from simulations. See [Sunderland et al., 1984] for a
(1998)
-50dB conventional calculation of DDS algorithm truncation in
terms of signal-to-noise ratio. On the other hand, the
Raytheon DDS performance is equivalently 13-bits +/- 1
1 MHz 1 GHz
LSB or the equivalent of a 12-bit linear DAC with nearly
Clock Rate ideal phase-to-sine conversion, similar to what a full ROM
BE would provide (approaching the -97.23 dB
Figure 7. DDS Technology Trends. The DDS Design Goal performance as read from Vankka’s table).
is High SFDR and High Speed to get Wide Bandwidth The trends and design goal of DDS technology are
such that signals can be synthesized at IF. The Current shown in figure 7. By innovative circuits and higher speed
Technology, Near Future, and Far Future Expectations IC processes, the goal should be attainable within about 10
are Shown [Estrick, 1995]. years.

4
The survey results are shown in table 2 and figures 8 and 9. the-art for high resolution DDSs and are often used along
Because of the limited number of parts that can reasonably with conventional direct and indirect synthesizers for wide
be shown on one chart, the list is not exhaustive. However, bandwidth and synthesis at IF frequencies. Figure 9 shows
this is representative of the state-of-the-art in DDS. the high speed (wide bandwidth) capable DDSs (and
Figure 8 shows the lower output frequency capable DACs) and reveals a barrier in performance, as the lower
DDS (and DACs useful for DDS). These are the state-of- right corner of the chart is clear. This barrier is attributed
to the high-speed performance limitations of the DAC.

B u rr-B ro w n , (1 )
S p u r io u s /H a r m o n ic s D A C 6 0 0 ,[ 2 2 ]

T I, [ 6 ]
-3 0
-3 5 S c ite q D D S - 1 ,[ 7 ]
-4 0
-4 5 Q u a lc o m m
-5 0 Q 2 3 3 4 ,[ 1 3 ] [ 1 4 ]

-5 5 Q u a lc o m m
Q 2 2 3 0 ,[ 1 3 ]
-6 0
-6 5 Q u a lc o m m
Q 2 2 2 0 (3 ),[ 1 6 ]
-7 0
-7 5 A n a lo g D e v i c e s
A D 7 0 0 8 ,[ 1 7 ]
-8 0
A n a lo g D e v i c e s ( 1 )
A D 9 7 2 0 ,[ 1 7 ]
25

55

0
2

3
12

10
29

.5

3. B ro a d C o m [1 2 ]
62

33
0.

Figure 8. The Survey Results for Lower Bandwidth DDSs and DACs useful for DDS. While the list is not exhaustive, it is
representative of typically commercially available and state-of-the-art prototype technology found in the literature [31].

S T E L -2 3 7 3 ,[1 ]

dBc S p u r io u s /H a r m o n ic s R a y th e o n [2 ]
-1 9
P le s s e y (4 ) S P 2 0 0 2 ,[3 ]

-2 9 R o c k w e ll,[4 ]

-3 9 T I / L in c o n L a b s L D D S ,[5 ]

S c ite q D C P -1 A ,[7 ]
-4 9
S c ite q A D S -4 3 x [7 ]
-5 9
S c ite q (5 ) A D S -6 3 x [7 ]
-6 9 H u g h e s S p a c e [8 ],[9 ]

-7 9 P h ilip s M ic ro w a v e
L im e il,T h o m s o n C N I[1 0 ]
T R W D D S /H D A C -1 ,[1 1 ]
25

0
29

12

33

19

24

29

45
0.

D A C T riq u e n t S C -0 8 0 6 -
C ,(1 )[2 1 ]
Sine Output Frequency MHz
Figure 9. The survey results for high-speed DDSs and DACs useful for DDS. The lower right corner of the chart is clear of
data points revealing a barrier in performance attributed to the DAC’s high-speed performance limitation. The table
captures the data to the authors’ best ability in interpreting the published information [31].

5
 Notes for Table 2 and Figures 8 and 9: (Table 2 Continued)
(1) DAC useful for DDS application. Result
Clock
Frequency Word(s) Phase Tech - Pow er
(2) Has noise reduction circuit that manufacturer shows Identifier Rate MHz
(max)
Resolution or DAC-
LFM Out
Offset
I/Q Out
nology Diss
Package
bits
reducing discrete spurious from -57dBc to -72 dBc for
approximately a 4 MHz output frequency. Qualcomm
50 32-bits 12 no 3-bits yes 0.67W
68-pin
Q2334,[13][14] PLCC
(3) The Q0320-1 DDS synthesizer card includes the
Q2220 DDS and Sony CXD1171M DAC. Qualcomm
Q2230,[13]
85 32-bits 12

(4) Internal divide-by-two cuts effective clock to half. Qualcomm

50 24-bits 10
(5) Uses Triquint's GaAs 14-bit DAC. Q2220 (3),[16]

(6) The reported typical SNR is about 6dB worse than the Analog Devices
50 32-bits 10 no 12-bits no
44-pin
AD7008,[17] PLCC
plotted "Peak Harmonic" for the 1st Image. It is
Analog Devices
unclear if the technique of [Hill,1993] is suggested. (1) 250 10
Dip and
LCC
AD9720,[17]
(7) Some manufacturers distinguish between spurious and
harmonics (e.g. Sciteq or Osicom), but often this Sandia,[18] 590 24-bits 8 yes 12-bits GaAs PWB

distinction is not made clear.

University of
Bradford UK 500 32-bits 8 GaAs
Table 2. Survey of DDS/DAC Features [31] DDS,[19]
Result
Clock
Frequency Word(s) Phase Tech - Power
Identifier Rate MHz LFM Out I/Q Out Package
Resolution or DAC- Offset nology Diss TMC2340 w / CMOS/
(max) 20 32-bits 12 no 32-bits yes
bits TDC1012,[20] bipolar
2" x1"
STEL-2373,[1] 1000 20.8023 Hz 8 no 2-bit no GaAs 12 W
hybrid DAC Triquent
SC-0806- 1000 14
IC/Modul C,(1)[21]
Raytheon [2] 1000 0.232 Hz 13 yes 32-bit no Bipolar 7.5 W
e
Burr-Brow n, (1)
256 12 Bipolar
DAC600,[22]
Plessey(4) monolithi
1600 0.5 Hz 8 no no yes 6W
SP2002,[3] c IC
HP(1),[23] 1000 12 GaAs
1.12"x2.
GaAs
Rockwell,[4] 500 28-bits 12 no 8-bits no 5.5 W 33" x0.2
HBT
" hybrid 48-pin
AD9830[17] 50 32-bit 10 no yes no CMOS 250Mw
TQFP

TI / Lincon Labs DAC

800 32-bits 10 1000 12 SiGe HBT
LDDS,[5] Rockw ell,(1)[24]

DAC Rockw ell

(1) RI61008 1200 10 GaAs
[25]
GaAs monolithi
TI,[6] 450 28-bits 8 yes no yes
HBT c IC

1.2" x5" x
Some surveyed wideband DACs do not show up on
Sciteq DCP-
1A,[7]
700 24-bits 12 yes 12-bit no 15 W 7.8"
module
the survey chart in figure 9 because no published data on
Sciteq VDS- 32-bits BCD
1.2"x7.8 the spurious performance was determined. However, they
20 12 no 3W " x5"
8,[7] 0.1 Hz exact
module are of particular interest because of the high clock rate or
Sciteq DDS-1
Hybrid/ novel architecture. For example, Rockwell has reported
25 32-bits 12 no 16-bit no CMOS 1.57W 74-pin
,[7]
LCC development of a 12-bit, 3-GHz DAC [Loring,1994]. For
Sciteq ADS-
1600 30-bits 8 no yes (6) Silicon 6W/8W
novel DAC architectures, see [Takakura et al., 1991],
43x[7]
[Hawksford, 1994], [Kim, 1993], [Essenwanger, 1998],
Sciteq (5) ADS-
500 14 4-bits GaAs
and others listed in the references and bibliography. An
63x [7]
example of a high-speed DDS/DAC is the Raytheon IC and
module design shown in figures 10 through 14.
P1
Hughes
1000 22 12 no no no InP HBT IC ••
•• Add BUS Add WAVEFORM 16 DDS
Space[8],[9] ••
•• I/F MEMORY CONTROLLER
•• Dat Dat 8
•• DPRAM FPGA
VME •• Cntl (freq., phase,
••
•• 20 slope, duration)
••
••
•• 16
•• CLK÷32

Philips
START/
Microwave GaAs STOP
1250 25-bits 12 yes no no 2.2W 6 ICs 5 16
Limeil,Thomson MESFET
CNI[10] GATE Add Dat Wr
Exe CLK÷32
Hold RFT LPF OUTPUT
DDS
CLK HYBRID
RFF
TRW Ext
HBT 1.4 cubic Ext Ext Ext OUTPUT
DDS/HDAC- 500 24-bits 12 no no no CLK Out Exe Add Dat Wr
GaAs in.
1,[11]
MOD 3 16
START/ P3
STOP Ext_Wr ••
+12V ••
Ext_Dat
•• EXT Freq/
+5V ••
P2 ••
•• Ext Phase
MODULATION Ext_Add ••
•• 32 ••
•• UPDATE ••
3W ••
•• POWER DPRAM DDS EXT
BroadCom [12] 800 32-bits 12 no 12-bits yes IC ••
•• CONDITIONING 15
+ DAC VME ••
(slope, ²ø, ²f)
CONTROLLER
•• FPGA
•• VOLTAGE
•• +3.3V
•• REGULATOR
••
••

Figure 10. Block Diagram of Raytheon DDS Module[2].

6
 Conclusions

There are major challenges in DDS designs,

particularly in the DAC, to achieve the design goal of
about –90dBc SFDR and GHz clock rates for wideband
output capability. The technology needed to achieve this
goal, through the use of advanced IC process technology
and novel circuits, was presented. The survey revealed a
barrier in performance attributed primarily to the dynamic
imperfections of high speed DACs. Standardization in the
specification and measurement of spurious performance is
Figure 11. Photograph of the Raytheon DDS Module. also needed.

References and Bibliography

S
Sin
inee Survey Chart References
S
Slo
loppee P
Phhase-to
ase-to-- 1. Zavrel, Robert J., Jr. and Edwards, Gwyn; Editors;
A The DDS Handbook. Second Edition, Stanford
Accu
ccum m uulato
latorr A
Amm pplitu
litu
litudddee Telecommunications, Inc., Custom & ASIC Products
FFro
ronnt-E
t-Enndd Group. July, 1990.
PPhhase
ase
D
DAAC C 2. Data Sheet RAP 1420830. "1 GHz DDS Module."
AA ccum
ccu m..
Raytheon Systems Company, Raytheon Advanced
Products, Torrance, CA, 1998.
R
REEFF
3. Plessey Data Book, Professional Products IC
Figure 12. The Raytheon IC chip. Handbook, GEC Plessey Semiconductors, June 1994.
dBc
0 4. Kent, Gary W.; Sheng, Neng-Haung; "A High Purity,
-10
High Speed Direct Digital Synthesizer." 1995 IEEE
-20
Frequency Control Symposium.
-30
-40
5. Kushner, Lawrence J.; Ainsworth, Marcus T.; "A
-50
-60
Spurious Reduction Technique for High-Speed Direct
-70
Digital Synthesizers", Lincoln Laboratory,
Massachusetts Institute of Technology. IEEE
0 100 20 0 3 00 4 00 500
International Frequency Control Symposium, 1996, pp
Fundamental Frequency MHz 920-927.
Figure 13. Typical worst case spurious performance of
the Raytheon DDS/DAC module [2]. 6. Andrews, G. Van; Chang, C. T. M.; Cayo, S. S.;
White, W. A..; Harris, M. P.; "A Monolithic Digital
dBc Carrier at 86 MHz Chirp Synthesizer Chip with I and Q Channels.' Texas
-60 Instruments Inc.,1991 IEEE GaAs IC Symposium,
-80 March 91, pp. 19-22.

-100 7. Sciteq Data Book, “Frequency Synthesis & RF

-120 Subsystems.” Sciteq Electronics, Inc., 1994.
-140 8. Schaffer, T. A.; Warren, H. P.; Bustamante, M. J., and
-160 Kong, K. W., "A 2 GHz 12-bit Digital-to-Analog
10 100 1K 10K 100K 1M 10M Converter for Direct Digital Synthesis Applications."
L(f) [dBc/Hz] vs f[Hz] Hughes Space and Communications, 1996 IEEE GaAs
Figure 14. Measured phase noise for the Raytheon IC Symposium, pp. 61-64.
DDS/DAC [2].

7
9. Private telephone conversation between Victor 20. --.1994 DATA BOOK, Raytheon Semiconductor
Reinhardt and Mario Bustamante, May, 1998. (Previously TRW LSI Products).

10. CAGLIO, Nathalie; DEGOUY, Jean-Luc; 21. Data Sheet SC-0806-C. "1GS/s 14 Bit Digital to
MEIGNANT, Didier; ROUSSEAU, Patrick; Analog Converter", TriQuent Semiconductor, Oct
LEROUX, Bruno; "An Integrated GaAs 1.25 GHz 1,94.
Clock Frequency FM-CW Direct Digital Synthesizer."
LEP/Philips Microwave Limeil, Thomson CNI, 1993 22. FAX, Burr-Brown Mktg, DAC600, "12-Bit 256Mhz
IEEE, GaAs IC Symposium, pp167-170. Monolithic Digital-to-Analog Converter", PDS1153
Data Sheet, Bur-Brown Corporation, Sept. 9. 1992.
11. Sharma, Arvind K.-Chairman,"Direct Digital
Synthesis and TRW Custom HBT Chips." 1995 IEEE, 23. Hsieh, Kuo-Chiang; Knotts, Thomas A.; Baldwin,
International Microwave Symposium, Workshop Gary L.; Hornak, Thomas, " A 12-bit 1-Gword/s GaAs
WFFD: Advances in Microwave and mm-Wave Digital-to-Analog Converter System." IEEE Journal of
Synthesizer Technology, May 19, 1995. Orlando, Solid-State Circuits, Vol. SC-22, NO. 6, Dec. 1987.
Florida
24. Goodenough, F., 12-Bit DAC Runs at 1 Ghz, Puts 20
12. Tan, Loke K.; Roth, Edward; Yee, Gordon E.; mA Into 50 (Ohms), Electronic Design, pp 47-52,
Samueli, Henry; "An 800MHz Quadrature Digital February 7, 1994.
Synthesizer with ECL-Compatible Output Drivers in
0.8µm CMOS." Broadcom Corporation, 1995 IEEE 25. Wirbel, Loring;"1.2-GHz GaAs D/A set." EE Times,
International Solid-State Circuits Conference, paper June 6, 94.
FA 15.1, pp258-259,198-199.
DDS Spurious Theory References and Bibliography
13. Qualcomm Data Book; “Master Selection Guide.”
Qualcomm VLSI Products, 80-3751 C, June, 1995. 26. Sunderland, D.A., et al., CMOS/SOS Frequency
Synthesizer LSI Circuit for Spread Spectrum
14. Qualcomm Data Book; “Q2334 Dual Direct Digital Communications, IEEE Journal of Solid-State Circuits
Synthesizer.” Qualcomm Inc., DL90-2334C, May Vol. SC-19, No. 4, pp 497-506, August 1984.
1995.
27. Essenwanger, K.A., Spurious Suppression in Direct
15. Hill, Allen; and Surber, Jim; “Using Aliased-Imaging Digital Frequency Synthesis by Combined Dithered
Techniques in DDS to Generate RF Signals.” RF Accumulator and Sine Approximation Techniques,
Design, Sept. 1993. Masters Thesis, Cal Poly, Pomona, May 1987.

16. Qualcomm Data Book; “Q2220 Direct Digital 28. J. F. Garvey and D. Babitch, “An Exact Analysis of a
Synthesizer.” Qualcomm Inc., DL80-3749-1C, Aug. Number controlled Oscillator Synthesizer,” IEEE
1993. Frequency Control Symposium, 1990.

17. G2132-150-5/96, Designer's Reference Manual, Data 29. G. C. Gillette, “Digiphase Principle,” Frequency
Converters." Analog Devvices Inc., 1996. Technology, August, 1969.

18. Remund, Brett L.; Srivatsa, Charkra R., "A 500 MHZ 30. V. S. Reinhardt, “Direct Digital Synthesizers,”
PHASE GENERATOR FOR SYNTHETIC Proceedings of the 17th NASA/DOD PTTI Planning
APERTURE RADAR WAVEFORM Meeting, Washington, D C., Dec., 1985.
SYNTHESIZERS", Sandia National Laboratories,
GaAs IC Symposium, IEEE 1991. Pp 349-352. 31. Estrick, Vaughn and Essenwanger, K. A.; “Direct
Digital Synthesizer Survey.” an internal for the RF
19. Benn, H.P.; Jones, W.J.; "A Fast Hopping Frequency Systems Technology Network (RFSTN) at Hughes
Synthesizer." University of Bradford UK,IEE Aircraft now known as Raytheon Systems Company,
Conference Pub. #303 2nd International Conference Nov. 8, 1995.
on Frequency Control and Synthesis, 1989, pp 10-13.

8
32. Tierney, Joseph, Rader, Charles M., and Gold, 43. Takkura, H.; Yokoyama, M.; and Yamaguchi, A.; “A
Bernard. “A Digital Frequency Synthesizer”, IEEE 10 bit 80MHz Glitchless CMOS D/A Converter.”
Transactions on Audio and Electroacoustics. Vol. Au- IEEE 1991 Custom Integrated Circuits Conference,
19. No. 1. March 1971. 48-57. pp. 26.5.1-26.5.4.

33. Nicholas, H.T. III, and Samueli H., Kim, B., The 44. Hawksford, M. A.; “Digital-to-Analog Converter with
Optimization of Direct Digital Frequency Synthesizer Low Intersample Transition Distortion and Low
Performance in the Presence of Finite Word Length Sensitivity to Sample Jitter and Transresistance
Effects, IEEE Annual Frequency Control Symposium, Amplifier Slew Rate.” J. Audio Eng. Soc., Vol. 42,
pp. 357-363, 1988. No. 11, Nov. 1994, pp. 901-916.

34. Nicholas, H.T. III, and Samueli H., An Analysis of the 45. Kim, O., et al., Settling Time Reduction Technique
Output Spectrum of Direct Digital Frequency for High Speed DACs, Electronics Letters, Vol. 29,
Synthesizers in the Presence of Phase-Accumulator No. 25, Dec. 9, 1993, pp. 2191-2192.
Truncation, IEEE 41st Annual Frequency Control
Symposium, pp. 495-502, 1987. 46. Mercer, D., A 16-bit Converter with Increased
Spurious Free Dynamic Range, IEEE Journal of
35. O’Leary, P., and Maloberti, F.; “A Direct-Digital Solid-State Circuits, Vol. 29, No. 10, Oct. 1994.
Synthesizer with Improved Spectral Performance.”
IEEE Trans. on Comm. Vol. 39, No. 7, July 1991. 47. Nakamura, Y., et. al., A 10-b 70-MS/s CMOS D/A
Converter, IEEE Journal of Solid-State Circuits. Vol.
36. Flanagan, M. J., and Zimmerman, G. A.; “Spur- 26, No. 4., pp. 637-642, April 1991.
Reduced Digital Sinusoid Synthesis.” IEEE Trans. on
Comm. Vol. 43, No. 7, July 1995, pp. 2254-2262. 48. Jensen, H T., and Galton, I.; “A Low-Complexity
Dynamic Element Matching DAC for Direct Digital
37. Vankka, J.; “Spur Reduction Techniques in Sine Synthesis.” IEEE Trans. on Circuits and Systems—II,
Output Direct Digital Synthesis.” 1996 IEEE Vol. 45. No.1, Jan. 1998.
International Frequency Control Symposium, pp.
951-959. 49. Spang, H. A. III; “Reduction of Quantizing Noise by
Use of Feedback.” IRE Trans. on Comm. Syst. Vol.
38. Karlquist, R. K.; “A 3 to 30 Mhz High-Resolution CS-10, pp 373-380, Dec. 1962. (reprinted in
Synthesizer Consisting of A DDS, Divide-and-Mix Waveform Quantization and Coding. Jayant N. S.
Modules, and a M/N Synthesizer.” 1996 IEEE Editor, IEEE Press, 1976).
International Frequency Control Symposium, pp.
928-933. 50. Chen, F., and Leung, B.; “A Mulit-Bit Σ∆ DAC with
Dynamic Element Matching Techniques.” IEEE 1992
39. Vankka, J., Waltri, M., Kosunen, M., and Halonen, Custom Integrated Circuits Conference, pp 16.2.1-
K. A. I.; “A Direct Digital Synthesizer with an On- 16.2.4.
Chip D/A-Converter.” IEEE Journal of Solid-State
Circuits, Vol. 33, No. 2, Feb. 1998. pp. 218-227. 51. Rabiner, L.R. and Gold B.; Theory and Application
of Digital Signal Processing. Prentice-Hall,
DAC References and Bibliography Englewood Cliffs, N.J. 1975, p. 330.
40. Colotti, J. J.; “Dynamic Evaluation of High Speed,
High Resolution D/A Converters.” RF Design, 1990, 52. Benz, S. P.; Hamilton, C. A.; Burroughs, Jr. C. J.;
pp. 51-64 Harvey, T. E.; Christian, L. A.; and Przybysz, J. X.;
“Pulse-Driven Josephson Digital/Analog Converter.”
41. Essenwanger, K. A, “Slewer Fractional-Order-Hold: IEEE Transactions on Applied Superconductivity,
The Ideal DAC Response for Direct Digital Vol. 8, No.2, June 1998, pp. 42-47.
Synthesizers.” The 1998 IEEE International
Frequency Control Symposium, May 1998. IC Process References and Bibliography
53. Eason, S. D.; “SiGe Stretches Limits of Silicon
42. Essenwanger, K. A.; “Final Report Evaluation of Applications.” Microwaves & RF, Dec. 1996, pp89-
Digital-to-Analog Converters…” under contract to 96.
Hughes Space and Communications, Sept. 13, 1996.