See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/339228509

Towards cloud energy metering system with 32 bit FPGA device architecture

Article  in  Journal of Computer Science and Its Application · February 2020

DOI: 10.4314/jcsia.v26i2.12

CITATIONS READS
0 123

3 authors:

Kennedy Chinedu Okafor Adaora Obayi

Federal University of Technology Owerri University of Nigeria
162 PUBLICATIONS   330 CITATIONS    19 PUBLICATIONS   23 CITATIONS   

SEE PROFILE SEE PROFILE

Ogbonna UkachukwuUkachukwu Oparaku

University of Nigeria
54 PUBLICATIONS   225 CITATIONS   

SEE PROFILE

Some of the authors of this publication are also working on these related projects:

Modeling and Detection of Criminal Networks View project

KenIoT:An Intelligent Cloud Infrastructure for Internet of Things Projects View project

All content following this page was uploaded by Kennedy Chinedu Okafor on 13 February 2020.

The user has requested enhancement of the downloaded file.

 https://dx.doi.org/10.4314/jcsia.v26i2.12

THE JOURNAL OF COMPUTER

SCIENCE AND ITS APPLICATIONS
Vol. 26, No. 2 December 2019

TOWARDS CLOUD ENERGY METERING SYSTEM

WITH 32 BIT FPGA DEVICE ARCHITECTURE

K. C. Okafor,1 A. A. Obayi2 and O. U. Oparaku3

1
Dept. of Mechatronics Engineering, Federal University of Technology Owerri, Nigeria
2
Dept. of Computer Science, University of Nigeria, Nsukka
3
Dept. of Electronic Engineering, University of Nigeria, Nsukka
1
[email protected], [email protected],3 [email protected]

ABSTRACT

Cloud based Advanced Metering Infrastructure (CAMI) is the next digital future for energy
management (EM). Various efforts on EM capabilities are mainly skewed towards embedded device
architectures that support non-concurrent execution. This paper presents cloud energy metering system
(CEMS) using high speed 32 bit field programmable gate array (FPGA) device. The architectural
framework for energy tracking and profile measurement in CEMS is presented. This aims at accurate
metering with demand side management (DSM). An application context that supports an EM
architecture is highlighted. The contextual CEMS features energy monitoring in distributed energy
utilities such as solar generators, wind and energy storage sources. Process integration with Cloud
based Internet for real-time energy reading is achieved through the FPGA synthesis to provide end-to-
end energy analytics. CEM prototype (Xilinx FPGA) running on a wireless open-access research
platform supports management of large historical data-sets from the current data up to the last granular
interval, hourly, daily, monthly and yearly dataset captures. The system provides the low latency
datasets in both tabular and graphical forms for end-user visualization of energy consumption patterns.
In the experimental setup, three case scenarios demonstrate how the metering system executes fast
edge computing profiling, thereby providing data-visualization services to end-users. The results show
the Avg. Latency time for CAMI household 1, 2 and 3 respectively. In case 1, the average latencies for
actual and measured (proposed CAMI) are 75% and 25% respectively. In case 2 and case 3, this gave
66.67% and 33.33% respectively. Clearly, the proposed CAMI offers lower latency for all scenarios of
energy consumption metering usage.

Keywords: Advanced Metering, Energy management, Cyber-physical systems, Cloud Computing,

IoT, Fog.

1.0 INTRODUCTION metering and billing systems [3][4]. Smart-

Cloud based metering technology with AMI have changed the way metering is done
FPGA’s is a disruptive technology that have by allowing customers participation in
recently gained attention in today’s energy making demand side management [5].
industry. Indeed, smart metering designs
In the world of cloud driven AMI found in
with FPGA devices [1] and digital inclusive
modern Smart Grids [6], [7], smart meters
technology such as the Internet cloud [2] are
combine highly intelligent electronic/digital
needed to provide new efficiency in energy
components with full duplex two-way
 Towards Cloud Energy Metering System With 32 Bit FPGA Device Architecture
K. C. Okafor, A. A. Obayi and O. U. Oparaku

communication to achieve seamlessness. The the low latency FPGA application specific
essence is to create efficient monitoring and circuit (ASIC) system on chip (SOC).
management of energy usage data. The
features of these meters include energy usage In the proposed system, the core is designed
monitoring for billing, power and theft to have little power drain while having
detection, anti-tampering feature, load characteristics like low delay real-time clock,
connect/disconnect detection, firmware up- signal conditional converter and other RF
gradations, demand side management, interfaces. These forms part of the ongoing
(DSM), and analytics, among others [8]. A research on CEMS/AMI concept. The system
functional SM can give unbiased split up has efficient latency and replaces the legacy
consumer energy usage at short intervals. alternative.
The benefit is that it automates the billing
system with very low cost overhead. In most [9] gave essential benefits of AMI for energy
SMs, there are two essential components viz: driven society. These include:
metering and communication modules [8].
i. It offers low latency energy data-stream
These components have specific controller
updates.
units relating seamlessly during its operation.
ii. It gives cumulative data-sets from
Also, these meters have load enable/disable
various home units’ sources while
switch, I/O control interfaces, with
performing data analytics at the cloud
embedded power storage subsystems, among
backend.
others.
iii. It gives secured data protection for user
With the global energy crisis, these features location, and other energy billing data-
can enhance energy efficiency, reduce sets.
wastages and control usage pattern by iv. It manages bandwidth sensitive
consumers. This is very useful in the workloads during its full duplex
generation; distribution and transmission of communication.
electrical energy where the traditional v. It provides trajectory data-mining using
electrical grids are revised with smart location and context-aware service
metering elements. The major difference provisioning. This reason is that by
between the recent smart metering systems staying closer to edge user location
and the legacy metering models is that the devices, more I/O streams (information
SM enforces active participation of data) can be acquired from user source
consumers in energy conservation through device and location.
real time feedback communication on their
The benefits of the proposed CEMS include
exact energy consumption profiles [5].
reduction in data collection costs, improved
Till date, most metering system in Nigeria reading precision, efficient and more
does not support full duplex communication organized billing process, significant
for real time energy feedback. Low increase in its operational efficiency through
latency/high speed processing capabilities is the provision of real time metering activities.
yet to be fully implemented and deployed. Essentially, the work presents the developed
This research presents Cloud based CEMS CEMs implementation architecture for the
which depends on high speed processor such distributed energy resources like solar, wind,
as FPGA. In this paper, various works on etc as highlighted in [4]. The design strategy
FPGA based processors and their various for achieving analog to digital conversion
categories are reviewed to provide clear module in a 32 bit FPGA driven smart
understanding of its application in CEMS. meters is considered. In this case, the
The main feature of the proposed CEMS is metering filters in FPGA ADC is
122
The Journal of Computer Science and its Applications Vol. 26, No. 2, December 2019

programmed with VHDL to deliver a architecture whose power calculation theory

System-On-a-Programmable Chip (SOPC) was verified with IEEE 1459-2010 Standard.
based model. In future, a smart Sigma delta HDL was used to synthesize the design.
ADC will be introduced as an IP core in the Their approach satisfied windowing
Altera FPGA component library while specifications established for power quality
leveraging it as a platform in the proposed measurement methods [14].
AMI.
In terms of FPGA processor architectures,
2.0 RELATED WORKS various works have been carried out to
address speed performance issues. For
In this Section, related works on smart
instance [15] presented an FPGA 32
metering systems relying on FPGA
bit extended arithmetic logic unit (ALU)
technology are discussed. The work [8],
architecture simulated in Xilinx Vivado 14.4
presented an implementation of FPGA sigma
tool and implemented on 28nm zynq 7000
delta architecture for the analog to digital
FPGA board. [16] presented a 32-bit MIPs
conversion module in smart meters. [10]
FPGA-Based pipelined microprocessor with
presented a transceiver architecture that
Very high speed hardware descriptive
depicts resource estimations for ASIC and
language (VHDL), [17]. The system executes
FPGA adapted to an AMI. The work
instructions in single cycle, and also
developed an integrated multi-rate and multi-
improves performance with pipelining
regional frequency shift keying (MR-FSK)
techniques. Xilinx FPGA was used as the
transceiver compliant with IEEE 802.15.4g
implementation platform and was verified
standard for smart metering utility networks.
using Xilinx assembly programs. [18]
[11] presented a typical power measurement
presented the implementation of a 32-bit
device whose computational units are
MIPS (Microprocessor without Interlocked
embedded in an FPGA device. This was
Pipeline Stage) processor based on QR
developed for analyzing 4-wire three-phase
decomposition (QRD) using Givens rotation
systems based on IEEE 1459-2010 standard,
algorithm. Their design has modified
considering under sinusoidal, non-sinusoidal,
hardware that reduces the latency of QRD
balanced and/or unbalanced condition. The
processes. It was realized with Xilinx 14.7
system was built on a synthesized
ISE simulator while its code was done in
programmable logic device (PLD) using
Verilog HDL language and implemented on
hardware description language (HDL)
Virtex - 7 FPGA kit. Other similar works on
alongside with digital signal processing
32 bit FPGA designs have been studied and
schemes.
presented in [19], [20], [21], [22], [23], [24]
[12] demonstrated a prototype [25], [26], [27] and [28].
implementation of an MR-OFDM baseband
With the FPGA device board [29], the design
modem (with FPGA compliant
can be used create, implement, and test CEM
IEEE802.15.4g standard) adapted to smart
AMI design using programmable logic.
metering utility networks. The work used
Figure 1 shows the I/O ports in DE2 -115
VHDL while prototyping with Altera's
highlighting the board layout with
device 5CGXFCC5C6F27C7N having
indications on the location and connections
maximum seed of 65.16MHz. The modem
of various components.
parameters that were analyzed for the energy
meter include active power, reactive power,
3.0 FPGA DEVICE ARCHITECTURES
current, voltage and frequency. [13]
presented an electric power measurement Clearly, the FPGA device architecture is
implementation in a three-phase power perceived to have strong potential for
system by using an FPGA device optimal design of AMIs. This is further
123
 Towards Cloud Energy Metering System With 32 Bit FPGA Device Architecture
K. C. Okafor, A. A. Obayi and O. U. Oparaku

buttressed in [30] where the authors  High level integration in FPGAs reduces
identified the merits of using FPGA-ASIC. power consumption/dissipation.
These were summarized as follows:
Reduces component counts significantly.
 Using FPGAs offers re-programmability Hence, using FPGA with an isolated CPU
for bugs’ correction. chip often yield cost savings, miniaturized
 FPGA development allows shorter time system, and reliability.
to market and reduces unnecessary costs.

Figure 1: ALTERA FPGA Development Board (DE2-115 T-Pad) [31].

Table 1 show the features of commercial FPGAs which could be used in any CEMs.

Table 1: Soft Processor Cores for FPGAs [32],[33]

Features Nios II 5.0 Micro-Blaze 4.0
FPGA Gate Count 26,000-72,000 30,000-60,000
FPGA Frequency 50-200MHz 50-200MHz
FPGA Datapath Width 32bits 32bits
FPGA Pipeline Stages 1-6 3
FPGA Register File 32 general purpose with 6 special 32 general purpose &
Purpose 32 special Purpose
FPGA Instruction Word 32bits 32bits
FPGA Instruction Cache Optional Optional
FPGA Hardware Multiply & Optional Optional
Divide

In this work, to achieve CEMS considering programmable-chip (SoPC) design. This

low latency FPGA design, this will require a comprises the legacy design process used in
leverage on electronic digital automation FPGA-device architectures. It supports the
process (EDA) as found in [34], [35], [36], inclusion of the processor core configuration
and [37]. Figure 2 shows the proposed CAD and software design tools.
EDA process framework for CEMS-on-a

124
The Journal of Computer Science and its Applications Vol. 26, No. 2, December 2019

Figure 2: Proposed CEMS CAD tool flow for 32 bit FPGA SoPC design

The established CEMS uses high deployment as depicted in Figure 3.

performance FPGA (Xilinx) variant referred Depending on the consumption rate of end
to as application specific integrated circuit user n+1, the AMI collects data locally and
(ASIC) circuit. This is explored to achieve transmits into the cloud. As highlighted in
efficient performance in the cloud domain. the work, this transmission occurs as often as
The choice of the processor for the system 1sec or as infrequently as daily, according to
implementation is influenced by cost and the usage of power. The collector retrieves
availability in the market. This work also the data, process it or simply pass it on for
aims at developing an integrated framework processing upstream in the cloud. The energy
for soft core processor used in embedded data is transmitted to the utility central
CEMS, (Xilinx FPGA). collection point for processing and use by
business applications. Since the communica-
4.0 CEMS DESCRIPTION tions path is two way, signals or commands
In this Section, a high speed 3 phase power can be sent directly to the meters, customer
micro-grid solar utility described by [5], premise or distribution device.
serves as the application context for

125
 Towards Cloud Energy Metering System With 32 Bit FPGA Device Architecture
K. C. Okafor, A. A. Obayi and O. U. Oparaku

Figure 3: Proposed Cloud Energy Management Infrastructure

5.0 SMART METER ARCHITECTURE modular and scalable in its architecture. In

Figure 4 is currently being developed for the the implementation phase, the CEMS SOC
32 bit FPGA low latency Silicon-on-Chip will satisfy the requirements previously
(SOC) architecture. It shows the CEMS with highlighted in Figure 3 and 4. The CEMS
TCP/IP interface. This is the core of the support core energy measurement and
CEMS. The low latency FPGA device runs calculation functions. Specialized co-
on a 32 bit microprocessor with a digital processor with additional peripherals for data
signal processor (DSP) for handling signal exchange and communication is used in this
processing functions especially for power regard. The hardware architecture supports
quality measurement features. This is an sufficient flash and internal memory. This
efficient feature since the multi-core executes the real time operating system
processor SOC runs on low latency shared which can support most of the commercially
peripheral and memory interface bus. This available or open source protocol stacks for
method of interconnection of resources in a Wi-Fi, Modem (2G/3G), TCP/IP, Zigbee,
CEMS SOC makes the system design to be Bluetooth Peripherals, Wimax, etc.

Figure 4: FPGA CEMS Architecture

126
The Journal of Computer Science and its Applications Vol. 26, No. 2, December 2019

6. SYSTEM IMPLEMENTATION core) into the data-center server provides

The initial model of the FPGA CEM has in significant benefits for Figure 3. Real-time
its implementation on the peripheral interface data provides a greater understanding of the
controller (PIC). However, the CEMS dynamic response characteristics of energy
leveraging low latency Xilinx FPGA ASIC usage. Acquiring real-time data enables
processor as depicted in Figure 5. As proactive management. Most importantly,
discussed by [38], two basic sensors (voltage the system’s ability to send frequent reports
and current) are employed for energy has no impact on communication costs,
computation in Figure 5. But acquiring data unlike the telephone-modem based meters.
in real time from CEM meter (32 bit FPGA

Figure 5: An FPGA powered CEMS with Consumer loads

As discussed in an earlier work [5], the  Programmable demand (kW) threshold.

energy metering and reporting features in the Meter sends email when exceeded.
FPGA based CEMS include:  Programmable daily reporting of peak
demand, consumption and previous
 kW, kWh, kVARh, voltage, current, month’s energy usage.
power factor, frequency.  Programmable reporting of load profile
 kWh & kVARh (delivered, received, data at end of interval or at fixed
sum, net - Instantaneous). intervals, (total kWh, last interval's kW,
 Configurable demand reset date and load voltage, current, power factor values by
profile logging interval. phase and frequency).
 Internet connectivity via dynamically  Client report data to be sent every 1 to 15
assigned IP address or static IP address. minutes or daily.
 Data transfer via TCP/IP RF protocol.
 CEMS sending load profile, demand and Figure 6 shows the implementation of the
consumption summary details. CEMS with its application program interface
 Low latency timing synchronization. (API) called enterprise energy tracking
 Log-in to web server is authenticated. analytic cloud portal (EETACP) application.
 Data encapsulation format - XML. These are built with C and JAVA languages
 Programmable alpha-numeric meter ID respectively.
and meter serial number.

127
 Towards Cloud Energy Metering System With 32 Bit FPGA Device Architecture
K. C. Okafor, A. A. Obayi and O. U. Oparaku

measure the energy consumption of complex

household processing tasks. Evidently, the
metering system synchronizes with the cloud
architecture whose computing resources are
leveraged to store captured datasets. Hence,
the metering system executes fast edge
computing profiling, thereby providing data-
visualization services to end-users.

Figure 7, 8 and 9 shows the Avg. Latency

time for CAMI household 1, 2 and 3
respectively. In case 1 (shown in Figure 7),
the average latencies for actual and measured
are 75% and 25% respectively.
Figure 6: CEMS Prototype test-bed environ-
ment. In case 2 and case 3, this gave 66.67% and
33.33% respectively. Clearly, the proposed
Service oriented programming approach CAMI offers lower latency for all scenarios
(SOPA) was employed in API design. Also, of energy consumption metering usage. This
the EETACP application was realized so as has been validated for over 3 case scenarios
to capture energy data from the CEMS and in this work.
store it in MySQL database server every
second based on 24 hour scale of daily
energy supply. At the hardware layer, the
CEMS was achieved using embedded digital
hardware implementation (HDEI) for Cloud
interfacing. The economic relevance of
system lies on its low cost, high performance,
security and flexibility characteristics.
Interested readers can study more about the
base-system in [4].

7. 0 EVALUATION/RESULTS
IMPLEMENTATION Figure 7. Avg. Latency time for CAMI
household 1
In the experimental setup of the CEMS,
energy consumption considering low latency
processing was investigated. This focused on
the average power consumption during four
weeks’ timeframe. A three case scenario for
household loads are metered using Figure 6.
Figure 7 shows the energy consumption
according to CAMI computing operation
discussed previously. The experiment was
conducted focusing on the energy
consumption required for all sorts of
household devices. To achieve this, various
load demands were metered while using a Figure 8. Avg. Latency time for CAMI
trans-coded resolution of 250p and 1080p to household 2
128
The Journal of Computer Science and its Applications Vol. 26, No. 2, December 2019

function virtualization (NFV). These

will reduce computational workload
across heterogeneously interconnected
devices on the metering cloud.
vi. Deployment of AMI data-centre servers
must be done in such a way as to deliver
maximum quality of service at all
layers.
vii. Training of young African digital
workforce with supports from the
industry, government and international
organizations. There is an urgent need
Figure 9. Avg. Latency time for CAMI for training, re-training and capacity
household 3. building efforts while encouraging
policy initiatives that will facilitate
Consequently, a low latency FPGA based energy innovation. This should go
metering system provides satisfactory beyond the conventional academic
response to energy data-stream updates. It research and innovation while
provides aggregate data-sets from diverse expanding a vibrant ecosystem for
home units while allowing data analytics at disruptive energy technologies, via
the cloud. It can manage bandwidth sensitive support of smart grid tech innovation
workloads during its full duplex hubs.
communication. Besides, trajectory data-
mining using location and context-aware 9.0 CONCLUSION/FUTURE WORK
service provisioning is feasible. In this paper, Cloud Energy Metering System
using 32 bit FPGA device architecture is
8.0 RECOMMENDATIONS presented. The system supports bi-directional
Some few recommendations for full Cloud data communication for cost efficient AMI
based FPGA metering in any digitally system. Low latency FPGA ASIC
inclusive society will include: implementation was employed during the
design phase. The functionalities of CEMS
i. Establishing strong regulatory reforms have been highlighted while enumerating the
with appropriate legal enforcements to benefits. This edge model is expected to
eradicate inefficiencies and minimize eliminate all forms of energy frauds and as
corruption in the energy value chain. well as the corruption in the existing
ii. Encouraging energy Internet of Things metering model. The next generation AMI
(e-IoT) computing service providers for will be highly dependent high performance
energy automation. processing and security layers. Hence, the
iii. Investing in network infrastructure for next research direction will focus on:
6G/4G-LTE. The attention should be on
providing high-speed networks for  Investigating on AMI reliability
ubiquitous energy services. constraints at the Edge, Fog, and cloud,
iv. Training experts and end-users on the using previous dynamic modelling efforts
existing IoT-edge smart metering in [39], [40] & [41].
technologies.  Carrying performance evaluation on both
v. Supporting disruptive energy FPGAs and embedded controllers in the
ecosystems by introducing software context of data acquisition latency
defined networks (SDN) and network effects.

129
 Towards Cloud Energy Metering System With 32 Bit FPGA Device Architecture
K. C. Okafor, A. A. Obayi and O. U. Oparaku

10. ACKNOWLEDGEMENT [5] Okafor, K. C. (2017b). Development

This research was carried out as an extended of a Model for Smart Green Energy
work on SGEMS/EETACP project Management Using Distributed Cloud
commissioned by the Department of Computing Network”, Ph.D. Thesis,
Electronic Engineering, University of University of Nigeria Nsukka.
Nigeria Nsukka. Many thanks to Mr. Jim [6] Yujae Song, Peng-Yong Kong,
Ovia who supported this research via Nigeria Yongjae Kim, Seungjae Baek,
Computer Society. TETFund (FUT/DVC Yonghoon Choi (2019). Cellular-
(Acad.)/GEN 92/II/90) also deserves our Assisted D2D Communications for
appreciation for partly sponsoring this work. Advanced metering Infrastructure in
Smart Grid”, IEEE Systems J., pp.1-
REFERENCES 12.
[7] Kaveh Dehghanpour, Yuxuan Yuan,
[1] Zaheer Khan; Janne J. Lehtom•ki Zhaoyu Wang, Fankun Bu (2019). A
Ekram Hossain,; Matti Latva-Aho, Game-Theoretic Data-Driven Approach
Alan Marshal, (2018). An FPGA- for Pseudo-Measurement Generation
Based Implementation of a in Distribution System State
Multifunction Environment Sensing Estimation. IEEE Trans. on Smart
Device for Shared Access With Grid, pp.1-1.
Rotating Radars. IEEE Trans., on [8] Padmaprabha V.R; D. S. Divya ; K.
Instr. & Measur, 67(11), pp. 2561 – Jiju, (2017). SOPC based sigma delta
2578, DOI: ADC IP core for smart energy meter.
10.1109/TIM.2018.2828718. IEEE International Conference on
[2] Yiming Wang, Zhiyuan Ren, Hailin Circuits and Systems (ICCS), India,
Zhang; Xiangwang Hou ; Yao Xiao, Pp. 140-144.
(2018). Combat Cloud-Fog Network doi: 10.1109/ICCS1.2017.8325979.
Architecture for Internet of Battlefield [9] Ndinechi, Michael C. & Okafor K. C.
Things and Load Balancing (2019). Towards Smart Society with
Technology. IEEE International Intelligent Fog (i-Fog) Computing,
Conference on Smart Internet of Accepted at 2nd Int’l Conf. on Elect.,
Things (SmartIoT), Xi'an, China, & Elect., Eng., (ICEEE), Rome, Italy
pp. 263-268. DOI: July, 22-23,. https://scientific
10.1109/SmartIoT.2018.00054 federation.com/iceee-
[3] Yuanqi Gao, Brandon Foggo, Nanpeng 2019/program.php
Yu, (2019). A Physically Inspired [10] Jessica A. J. de Oliveira, Augusto F. R.
Data-driven Model for Electricity Queiroz, E. R. de Lima, J. Mertes,
Theft Detection with Smart Meter (2015). An MR-FSK transceiver
Data”, IEEE Transactions on compliant to IEEE802.15.4g for smart
Industrial Informatics, pp.1–1, DOI: metering utility applications: FPGA
10.1109/TII.2019.2898171 implementation and ASIC resource
[4] Okafor, K. C., G. C. Ononiwu, J. A. estimation”, 7th IEEE Latin-American
Okoye, M. U. Ndubuaku, (2017a). Conference on Communications
Enterprise Energy Analytic Cloud (LATINCOM), Peru, pp.1-4, DOI:
Metering Portal for On Demand 10.1109/LATINCOM.2015.7430144
Service Provisioning. Indian J. of Science [11] Luis De Oro Arenas; Guilherme A.
and Tech. (IJST), 10(36), Pp.1-13, DOI: Melo; Carlos A. Canesin (2018).
10.17485/ijst/2017/v10i36/111913. Power quantities calculation by using
an FPGA device, applying IEEE 1459-
130
The Journal of Computer Science and its Applications Vol. 26, No. 2, December 2019

2010 standard”, IEEE Simposio DOI:

Brasileiro de Sistemas Eletricos 10.1109/ICCCEEE.2018.8515875.
(SBSE), Niteroi, Brazil,Pp.1 – 6. DOI: [17] Okafor K.C., Guinevere, E.C.,
10.1109/SBSE.2018.8395626. Akinyele, O.O. (2011e). Hardware
[12] Augusto F. R. Queiroz, Gabriel S. da Description Language (HDL): An
Silva, Cesar G. Chaves, Tiago D. Efficient Approach to Device
Perez, Daniel G. Urdanetta, Denise C. Independent Designs for VLSI
Alves, Maique C. Garcia, Eduardo R. Market Segments. Proc 3rd IEEE
de Lima (2015). Demo: FPGA International Conference Adaptive
implementation of an IEEE802.15.4g Science and Technology (ICAST),
MR-OFDM baseband modem for Abuja, pp. 262-267.
Smart metering utility networks”, [18] Safaa S. Omran, Ahmed K. Abdul-
IEEE 4th Global Conference on abbas (2018a). Design and
Consumer Electronics (GCCE), Japan, implementation of 32-Bits MIPS
pp. 125-126. DOI: processor to Perform QRD Based on
10.1109/GCCE.2015.7398736. FPGA, IEEE Int’l Conf. on
[13] Luis De Oro Arenas; Guilherme A. Engineering Technology and their
Melo; Carlos A. Canesin, (2017). Appls, (IICETA), Iraq, pp. 36-41,
FPGA-based power meter implement- DOI: 10.1109/IICETA.2018.8458073.
tation for three-phase three-wire and [19] Safaa S. Omran; Ahmed K. Abdul-
four-wire power systems, according to abbas (2018b). Design of 32-bits RISC
IEEE 1459-2010 standard. IEEE processor for hardware efficient QR
Brazilian Power Electronics Conf. decomposition. Int’l Conf. on Advance
(COBEP), Juiz de Fora, Brazil, pp.1-6, of Sustainable Engineering & its
DOI: 10.1109/COBEP.2017.8257373. Application (ICASEA), pp. 69-73.
[14] Radek Sedl„ček, Josef Vedral, J„n [20] Jie Bai; Liji Wu, Niu Yun, Yang
Tomlain (2013). Wideband partial Liu, Xiangmin Zhang (2013). A
discharge meter using FPGA. IEEE 10Gbps in-line Network Security
9th IEEE Int’l Symposium on Processor with a 32-bit embedded
Diagnostics for Electric Machines, CPU, IEEE 22nd Wireless and Optical
Power Electronics and Drives Comm Conf., pp. 616-619.
(SDEMPED), Spain, pp. 396-401. [21] J. Rohit, M. Raghavendra (2017).
DOI: Implementation of 32-bit RISC
10.1109/DEMPED.2013.6645746. processors without interlocked
[15] Nidhi Gaur; Anu Mehra, Deepika Pipelining on Artix-7 FPGA board.
Kamboj, Devyani Tyagi (2016). A IEEE Int’l Conf. on Circuits, Controls,
novel implementation of 32 bit and Communications (CCUBE), pp.
extended ALU Architecture at 28nm 105-108.
FPGA”, IEEE Int’l Conf. on Emerging [22] Xiuze Dong, Xiaonan Zhang (2016). A
Trends in Comm. Technologies high performance FPGA implement-
(ETCT), India, 2016, pp. 1-4. DOI: tation of 256-bit Modular multiplica-
10.1109/ETCT.2016.7882932 tion processor over GF (p), 2nd IEEE
[16] Wael Saad Osman; Samah Mohamed Int’l Conf. on Comp. and Comms
Hashim (2018). FPGA-Based (ICCC), pp. 961-965.
Pipelined Microprocesor, IEEE [23] Sujay Pandit, Prateek Sikka (2018).
International Conference on Design and Implementation of Power
Computer, Control, Electrical, and Optimized Dual Core and Single Core
Electronics Engineering (ICCCEEE), DLX Processor on FPGA, IEEE 9th
Khartoum, Sudan, pp. 1-4, Int’l Conf. on Computing, Comm &
131
 Towards Cloud Energy Metering System With 32 Bit FPGA Device Architecture
K. C. Okafor, A. A. Obayi and O. U. Oparaku

Networking Tech (ICCCNT), pp.1-5. Electricity Sector in African Markets.

[24] Don Kurian Dennis, Ayushi CGD Policy Paper. Washington, DC:
Priyam, Sukhpreet Singh Virk, Sajal Center for Global Development.
Agrawal, Tanuj Sharma, Arijit [Online]. Available:
Mondal, Kailash Chandra Ray (2017).
Single cycle RISC-V micro https://www.cgdev.org/publication/cha
architecture processor and its FPGA llenges-and-solutions-electricity-
prototype. IEEE 7th Int’l Symp. on sector-africanmarkets.
Embedded Comp., & System Design [32] J. O. Hamblen, (2006). Using System-
(ISED), pp. 1-5. on-a-Programmable-Chip Technology
[25] Malik Imran; Muhammad Rashid, to Design Embedded Systems, IJCA,
Imran Shafi (2018). Lopez Dahab 13(3).
based elliptic crypto processor (ECP) [33] Christophersen, H, R. Pickell, J.
over GF(2163) for low-area applications Neidhoefer, A. Koller, S. Kannan, and
on FPGA”, IEEE Int’l Conf. on Eng., E. Johnson (2006). A Compact
& Emerging Tech.,(ICEET), pp. 1-6. Guidance, Navigation, and Control
[26] Mirosław Chmiel, Wojciech System for Unmanned Aerial Vehicles.
Kloska, Dariusz Polok; Jan Mocha, Journal of Aerospace Computing,
(2016a). FPGA-based two-processor Information, and Communication.
CPU for PLC”, IEEE International [34] Jad G. Atallah (2018). EDA Tools
Conference on Signals and Electronic Usage and Tutorial Authoring for
Systems (ICSES), pp. 247-252. Basic Electronic Circuits Education.
[27] Miroslaw Chmiel, Jan Mocha, Artur IEEE 12th European Workshop on
Lech (2018b). Implementation of a Microelectronics Education (EWME),
Two-Processor CPU for a pp. 51-54.
Programmable Logic Controller [35] Kunal Promode Ghosh; Anagha K
Designed on FPGA Chip, IEEE Int’l Ghosh (2018). Technology mediated
Conf. on Signals & Electronic Sys. tutorial on RISC-V CPU core
(ICSES), pp. 13-18. implementation and sign-off using
[28] Wael M. ElMedany, Khalid A. Al- revolutionary EDA management
Kooheji (2019). Design and system (EMS) – VSDFLOW. IEEE
Implementation of a 32bit RISC China Semiconductor Technology
Processor on Xilinx FPGA”, [Online]. International Conference (CSTIC),
Available: pp. 1-3.
[36] Sidina Wane, Ruska Patton, Nicolas
http://www.ursi.org/proceedings/proc Gross (2018). Unification of
GA08/papers/DP1p2.pdf, 11/02/2019. Instrumentation and EDA Tooling
[29] Ankita Goel, Hamid, Manhood, Platforms for Enabling Smart Chip-
Embedded System Design Flow, using Package-PCB-Probe Arrays Co-
ALTERA FPGA Development Board Design Solutions using Advanced
(DE2-115 T-Pad). RFIC Technologies, IEEE Conf. on
[30] McConnel, Toni. EETimes (2010). Antenna Measurements & Appl.
ESC - Xilinx All Programmable (CAMA), pp. 1-4.
System on a Chip combines best of [37] Ilya Tuzov, David de Andr‡s, Juan-
serial and parallel processing. April 28. Carlos Ruiz, (2018). DAVOS:
[31] Ijeoma Onyeji-Nwogu, Morgan EDA Toolkit for Dependability
Bazilian, and Todd Moss. (2017). Assessment, Verification, Optimisa-
Challenges and Solutions for the tion and Selection of Hardware
132
 The Journal of Computer Science and its Applications Vol. 26, No. 2, December 2019

Models, IEEE 48th Annual IEEE/IFIP

Int’l Conf. on Dependable Systems & [41] Okafor, K. C., I.E Achumba, G.A
Networks (DSN), pp. 322-329. Chukwudebe, G.C Ononiwu (2017).
[38] Ndinechi, M.C, O.A. Ogungbenro, Leveraging Fog Computing For
Okafor, K.C. (2011). Digital Metering Scalable IoT Datacenter Using Spine-
System: a better alternativefor Leaf Network Topology”, Journal of
electromechanical energy meter in Electrical and Computer Engineering,
Nigeria, Int’l J. of Academic Research, Vol.2017, Article ID 2363240, Pp.1-11
3(5) 2011, pp.189-194. ISSN: 2090-0147. USA.
[39] Okafor, K. C. (2019). Dynamic DOI:10.1155/2017/2363240.
Reliability Modelling of Cyber-
Physical Edge Computing Network.
Int’l J. of Comp & Appl, (IJCA), SI-
Sustainable Computing for Intelligent
Systems, pp. 1-10. DOI:
10.1080/1206212X.2019.1600830
40] Okafor, K. C, G.C. Ononiwu, Sam G.,
Chijindu, V.C., C. C. Udeze (2018d).
Towards Complex Dynamic Fog
Network Orchestration Using
Embedded Neural Switch. Int’l J. of
Compt, &Appl, IJCA) SI- Internet of
Everything, Networks, Application,
and Computing Systems, 40 (4), pp.1-
18.DOI:
10.1080/1206212X.2018.1517440.

133

View publication stats