Code:1

module prg1();
reg [7:0]a;
initial
begin
a = "A";
$display("Value of a %o",a);
end
endmodule
Ans: 101
Q2:
Write a Verilog code for +ve edge triggered flip-flop with asynchronous ve reset
with non-blocking assignment?
Q3:
In a pure combinational logic, is it necessary to mention all the inputs in
the sensitivity list?

pre and post synthesis simulation results will mismatch.

Q4:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Wildcard operator in a sensitivity list.
ANSI C style port declaration
Power off operator (square)
Automatic task

Q5:
What is the data type of y_out for the following statment? assign y_out =
a_in & b_in;

Net type,
it can be possible reg also if we write assign in procedural block(not
recomanded)

Q6:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Wildcard operator in a sensitivity list.
ANSI C style port declaration
Power off operator (square)
Automatic task

Q7:
reg rega [1:n]; represents?

(a) array of n, 1 bit registers: ANS

(b) n bit register
(c) array of (n-1), 1 bit registers
(d) array of (n+1), 1 bit registers
Q8:
Wire y_out;
initial
begin
x = 4'b1011;
y_out = &x;
end
What is the value of y_out.?
ANS: error, because y_out is a net type.if it is reg type then the output is 0

Q9:
What is the output of the following Verilog code with y = 3, a = 2,b = 1.
initial
begin
y = a + b;
z = y + a;
end
ANS: y = 3, z = 5

Q10: what is the output of the following code having initial values at 0ns
for y = 6, a = 3,b = 1 .
initial
begin
#10 ;
y <= a + b;
z <= y + a;
end

a) y = 4, z = 9
Q11:
Write a verilog code to swap contents of two registers without a
temporary register?

ANS: always @ (posedge clock)

begin
a <= b;
b <= a;
end

Q12:
Write a Verilog code to generate race condition?

ANS: reg data = 1b0;

initial
begin
data = 1b1;
end

Q13:
Write a Verilog code to generate clock?(consider time period is 10ns)
`timescale 1ns/1ns

ANS: initial
begin
clk = 1b0;
forever
begin
#5 clk = ~clk;
end
end

Q14:
What is the difference between task and function?

ANS:
Function
It execute in one simulation time
unit
function cannot enable a task
and it can enable function
function shall have at least one
input type argument and shall
not have an output or inout type
argument;
function shall return a single
value;

Task
It can contain time-controlling
statements.
task can enable other tasks or
functions.
task can have zero or more
arguments of any type.

task shall not return a value. But

it can update a value

Q15:
What is the difference between the following two lines of Verilog code?
#5 a = b;
a = #5 b;
ANS: #5 a = b; Wait five time units before doing the action for "a = b;". The value
assigned to a will be the value of b 5 time units hence. a = #5 b; The value of b is
calculated and stored in an internal temp
register. After five time units, assign this stored value to a.

Q16:
What is the difference between the following two codes
c = foo ? a : b;

|
if(foo)
|
c = a;
|
else
|
c = b;
ANS: The ? merges answers if the condition is "x", so for instance if foo = 1'bx, a = 'b10,
and b = 'b11,
you'd get c = 'b1x. On the other hand, if treats Xs or Zs as FALSE, so you'd always get c = b.

Q17:
Which one of the following is procedural statement?
1. initial
2. always

ANS: Both

Q18:
How do you override parameters during instantiation?

ANS: counter #(8) DUT(clk,rst_n,count);

Q19:
Difference between `define and parameter?

ANS: `define fifo_depth 16usage: if (depth <= `fifo_depth)

Parameter fifo_depth 16
usage: if (depth <= fifo_depth)
`define
Parameter
Basically a text substitution
It is used to specify the
macro
constants over code
Cant be override by any
Parameters can be overridden
mechanism

Q20:
Tell me some net types in Verilog?

ANS: wire, tri, tri0, supply0, wand, triand, tri1, supply1, wor, trior,
trireg, uwire

Q21:
Can you write the Truth table for wor and trior nets?

ANS: for both truth table is same

Q22:
Is reg creates flip-flop

wor/trio
r
0
1
X
Z

0
1
X
0

1
1
1
1

X
1
X
X

0
1
X
Z

all the time ?

ANS: no, because when we assign a value inside a procedural block

it requires the LHS variable to be reg type and also it depends on
the sensitivity if we menction * it means combination logic.

Q23:
What are the Verilog predefined primitives that you know?

ANS:
and
nand
nmos

or
nor
cmos

xor
not
pullup

xnor
pmos
pulldo
wn

Q24:
What is the difference between $stop and $finish?

ANS: $stop will interrupt the program where as $finish terminates

the program.
Q25:
Write a Verilog code for asynchronous active low reset d-flip-flop?

ANS:
module d_ff ( input clk, rst_n, d, output reg q);
always @ (posedge clk, negedge rst_n)
begin
if(!rst_n)
q <= 1b0;
else
q <= d;
end
endmodule

Q26:

What are the different levels of abstractions support by verilog.

ANS: switch level, gate level, behavioral level, data flow level
Q27:
Do you know Verilog standards? If you know what are they?

ANS: 1995, 2001, 2005

Q28:
What are the different Register Data Types?

ANS: reg, integer, time, real

Q29:
How to read memory from a file(data is in hexadecimal format),file name
is mem.txt?

ANS:
$readmemh("mem.txt",memory);
Q30:
Which procedural block can be synthesis (always, initial)?

ANS: always procedural block will synthesizable, initial procedural

block is not because in will executes only once.

Q31:
How many levels can be nested using `include?

ANS: we can nest `include compiler directive up to

at least 16 levels.

Q32:
Does all the constructs in Verilog will synthesizable? If yes ok or not
listout some non-synthesizable constructs?

ANS: No, (initial, fork, join, real, delays(#10), UDPs, system tasks )

Q33:
How to generate a random number in verilog?

ANS: $random();

Q34:
How to generate random number which is between 0 to 100?

ANS: variable_1 = {$random} % 100;

Q35:
What is the advantage of named port connection over ordered port
connections?

ANS: less possibility of mismatch (if we follow the ordered ports we

may mention the order may be false like clock in place of reset)

Q36:
list out some of enhancements in Verilog 2001?

Automatic task

Q37:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q38:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q39:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q40:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q41:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q42:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q43:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q44:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q45:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q46:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q47:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q48:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q49:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q50:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q51:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q52:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q53:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q54:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q55:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q56:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q57:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q58:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q59:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q60:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q61:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q62:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q63:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q64:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q65:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q66:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q67:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q68:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q69:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q70:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q71:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q72:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q73:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q74:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q75:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q76:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q77:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q78:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q79:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q80:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q81:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q82:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q83:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q84:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q85:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q86:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q87:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q88:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q89:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q90:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q91:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q92:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q93:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q94:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q95:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q96:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q97:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q98:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q99:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list

Q100:
list out some of enhancements in Verilog 2001?

Comma operator in sensitivity list