High Frequency Voltage Controlled Ring

Oscillators in Standard CMOS

Yalcin Alper Eken

PhD Candidate in School of ECE
GaTech

July 7th , 2003

1

Agenda

§ Integrated VCO types

§ Ring oscillator theory
§ Important characteristics of ring oscillators
§ Frequency
§ Noise
§ High frequency low noise ring oscillators
§ Prototype Chip
§ Performance Comparison
§ Applications/Summary/Conclusions
2

1
 Integrated VCO Types

§ LC Oscillator

§ Ring Oscillator

VCO Types : LC

LC Oscillator
§ High Q resonant element
Resonator
§ Expensive to implement
§ Require more die area
§ Reduce integration density
§ Extra steps
§ Secondary effects
§ Eddy currents
§ Magnetic coupling
Amplifier

2
 VCO Types : Ring
Ring
Oscillator

§ Less expensive to implement

§ Wider tuning range
§ Multiple output phases
§ Low Q
5

Ring Oscillator Theory

3
 Ring Oscillator Operation in Time Domain

X1 X2 X3

At t = t 1
Vinitial
At t = t 1+Td At t = t 1+3Td
Gnd Vdd At t = t 1+2Td Vdd
Vinitial
Vinitial
Gnd Gnd

§ Odd number of inversions

§ T = 6*Td or 2N*Td for N stage
§ fosc = 1/(6*Td) or 1/(2N*Td) for N stage
7

S-domain Analysis : Ring Oscillator

X(s) Amplifier Y(s)

A(s)

Frequency
Selective Network
α (s)

L(s) = A1(s)A2(s)...A N(s)

= A N (s) assuming that A1(s) = A2(s) = ... = AN (s)

Barkhausen Criterion :
2 kπ N
∠A( jω0 ) = θ = and A( jω0 ) = 1
N
at the oscillation frequency
8

4
 Ring Oscillator Linear Model

φ =0 φ =π +θ φ = 2π + 2θ φ = N (π + θ )
π
= N (π + )
N
=0
 − gm R  π for odd # of stages
Stage transfer function A ( j ω) =   θ=
1 + RCjω  N
tan θ
Frequency : ω 0 = 1
RC Gain requirement : g m R ≥
cosθ
For 3 - stage ω0 = 3 For 3 - stage g m R ≥ 2
RC
For 4 - stage ω0 = 1 For 4 - stage gm R ≥ 2
RC
9

Differential Ring Oscillators

+ - + - + - + -
A1 A2 A3 A4
- + - + - + - +

§ Better immunity to common-

mode disturbance
§ 50% duty cycle
§ Improved spectral purity
§ Even/Odd number of stages

10

5
 Important Characteristics of Ring VCOs

§ Frequency

11

Frequency Tuning - I
Current
Load Control
Control -I Drive
Strength
Control

Load
Control - II
C LVswing
Td =
I control
I control
f osc =
2 NCLVswing

12

6
 Frequency Tuning - II

Feedback Coupling
Control Control

13

Frequency Increase : Multipliers

14

7
 Frequency Increase : Subfeedback Loops1

Implementation 5-Stage Main-Loop

with N = 5, i = 2
X1 X2 X3 X4 X5

3-Stage Subfeedback Loop

1 L. Sun, T. Kwasniewski, and K. Iniewski, “A Quadrature Output Voltage Controlled Ring Oscillator Based on Three-Stage
Subfeedback Loops,” Proc. Int. Symp. Circuits and Systems, Orlando, FL, 1999, vol. 2, pp. 176 -179. 15

Important Characteristics of Ring VCOs

§ Noise

16

8
 Phase Noise : Leeson’s Model

2
Single Sideband Oscillator 2 FkT  ω0 
Phase Noise in Leeson’s Model L{∆ ω} =  
PS  2Q∆ ω 

Q of LC Oscillators Q ≤ 10
(standard CMOS)

Q of a ring oscillator?

17

Ring Oscillator Q : Razavi

ω  dA   dφ 
2 2
Q of a ring oscillator Q= 0   + 
2  dω   dω 

2
Modified Leeson’s 2 NFkT  ω0 
L{∆ω} =  
PS  2Q∆ω 
equation

3 - stage Q : 3 3 4 ≅ 1.3
4 - stage Q : 2 ≅ 1. 4

18

9
 Phase Noise : Harjani
Application of Harjani's Equation

Sine Curvefit
Output Signal

Swing (V)

Vdd
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

Vpp

Time (nsec)

 64 FkTR ω0 2  8 * Vdd 
 9V 2 ( ∆ω )  for V pp << 
  3π  2SRMAX
L{∆ω} = 
pp
V pp =
 512 FkTRVdd ( ω 0 ) 2  8 * Vdd  ω0
 for V pp >> 
 27 πV pp
3
∆ω  3π 

Equation from : L. Dai, and R. Harjani, “Design of Low-Phase-Noise CMOS Ring-Oscillators,” IEEE Trans. Circuits Sys. II, vol. 49,
pp. 328 -338, May 2002. 19

Ring Oscillator Q : Harjani

9 π dv / dt max
Q of a 3-stage ring Qeff =
oscillator 8 ω0Vdd

3 .63 in TSMC 0.18um


Qeff (3 - stage rings, at 900 MHz) = 3 .02 in TSMC 0.25um
 2.51 in TSMC 0.35um


§ Clipped Signals
Better NOISE
§ Sharper transition
performance!!
§ Full-switching

20

10
 Ring Oscillator Gain Stages
Analog Saturated
Gain Stage Gain Stage

§ Stage gain dependence for § Latching characteristics

switching speed-up signal transitions
§ Inferior noise performance § Good noise characteristics
§ Continuous conduction § Full Switching
§ Cascaded connections § Rail-to-rail outputs
21

High Frequency Low Noise

Ring Oscillators

22

11
 Multiple-Pass Loop Architecture
3-Stage 1 § Auxiliary loops nested
inside main-loop
§ Frequency Improvement
§Effective stage delay
reduced
§ Noise Improvement
General § Slew Rate increase

23

Saturated Gain Stage with Regenerative Elements

§ Used in our designs

§ Frequency control by
varying latch strength

§ Two sets of inputs for

multiple-pass architecture

§ Tuning range control by

varying sizes of M3 and M4.

Delay Stage : C.H. Park, and B. Kim, “A Low-Noise, 900-MHz VCO in 0.6-µ m CMOS,” IEEE J. Solid State Circuits, vol. 34, pp.
586 -591, May 1999. 24

12
 Multiple-Pass Ring Oscillator with
Saturated Gain Stage – Frequency/Noise Performance
Number of Technology, Frequency Range Phase Noise at 1
Stages CMOS (GHz) MHz (-dBc/Hz)
3 0.25 um 4.15-5.30 -105.2 (5.07 GHz)
4 0.25 um 2.50-3.68 -110.28 (3.42 GHz)
3 0.18 um 8.10-9.50 -99.2 (9.05GHz)
4 0.18 um 5.56-6.66 -104.66 (6.35 GHz)
4 0.18 um 4.11-6.53 -104.21 (5.29 GHz)
5 0.18 um - -113.46 (4.33 GHz)
3 0.13 um 8.75-14.4 -90.49 (10.97 GHz)

25

Prototype Chip

§ 0.18 µm TSMC CMOS

§ 1.8 V main supply
§ Parts
§ 9-stage ring oscillator
§ 3-stage ring oscillator
§ Integrated LC oscillator
§ Charge-pump circuits
§ PFD networks
§ MOSIS SCMOS rules for
ring oscillators : 0.20 µm
minimum drawn channel
length
26

13
Three-Stage Multiple-Pass Ring Oscillator

Simulations

Measurements

§ Simulations : 5.18-6.11 GHz

§ Measurements : 5.16-5.93 GHz
§ Linear characteristics
§ Possible operation up to 7.7 GHz
27

Nine-Stage Multiple-Pass Ring Oscillator

§ Simulations : 1.16-1.93 GHz

§ Measurements : 1.10-1.86 GHz
§ Linear characteristics
28

14
 Phase Noise Simulations

§ Spectre RF
§ Models with thermal noise, no 1/f noise
§ 3-stage : -99.5 dBc/Hz (foff = 1 MHz, f0 = 5.79 GHz)
§ 9-stage : -112.8 dBc/Hz (foff = 1 MHz, f0 = 1.82 GHz)
29

Phase Noise Measurements

Power Spectrum at 1:2 Output of 9-Stage Ring § Spectrum analyzer

§ 9-Stage ring oscillator :
§ -105.5 dBc/Hz phase noise at
(1MHz offset, 1.8 GHz center)
L{∆ ω} = SBmeas − 10 log( RBW )
− 20 log( ∆ω / ∆ωmeas ) + 20 log( ω0 / ω meas )

§ Larger result due to power-

supply/ground noise + 1/f noise
§ Low frequency noise

30

15
 Performance Comparison

31

Frequency Performance Comparison

32

16
 Phase Noise Performance Comparison

33

Applications
Possible Applications Need LC Oscillators
§ CPU, DSP, DRAM clock generation §Wired transceivers
§ SONET, STS-768 2
§ System synchronization (deskewing ) :
Zero delay clock buffers § Wireless transceivers
§ Bluetooth3 (power)
§ Oversampling A/D converters
§ HomeRF4 (power)
§ Wired transceivers § Wireless LAN (IEEE
§ Gigabit Ethernet 802.11a)5
§ 10 Gigabit Ethernet (IEEE 802.3ae) § HiperLAN
§ GSM6
§ SONET, STS-192 1 , STS-96, STS-48,
STS-36, STS-24, STS-18,… § DECT7
1[Mukherjee at al., 2002] : at 10 GHz, -90 dBc/Hz at a 1 MHz offset is
required for a loop bandwidth of 10 MHz.
2 ~40 GHz operation frequency required (for serial transmission)
3 at 2.44 GHz, -119 dBc/Hz is required at 3 MHz offset
4 at 2.404-2.478 GHz, -77 dBc/Hz is required at 3 MHz offset
5 at 5.15 -5.35 GHz, -110 dBc/Hz is required at a 1 MHz offset
6 at 0.9/1.8 GHz, -138/-145 dBc/Hz is required at 3 MHz offset
7 at 2.4 GHz, -134 dBc/Hz is required at 5.128 MHz offset 34

17
 Summary and Conclusions

§ Ring oscillator analysis (time, s-domain)

§ How to improve characteristics of ring oscillators
§ Multiple-pass architecture with latching saturated stages
for high frequency, low-noise in CMOS
§ Estimations :
§ Up to 9.5 GHz in 0.18 µm CMOS, -99.2 dBc/Hz Phase Noise
§ Up to 14 GHz in 0.13 µm CMOS, -90.5 dBc/Hz Phase Noise
§ Suggestion of practical applications
§ Results suggest that it is not always necessary to resort to
integrated LC networks for high-frequency low-noise
VCO/CCO modules
35

Questions

?
36

18