IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 67, NO.

1, JANUARY 2020 9

Efficient Supply Modulator for Wide-Band Envelope

Elimination and Restoration Power Amplifiers
Ahmed Mamdouh, Member, IEEE, Mohamed Aboudina , Senior Member, IEEE,
Faisal Hussien, Senior Member, IEEE, and Ahmed Nader Mohieldin , Senior Member, IEEE

Abstract—A fast transient response supply modulator has

been realized and verified in envelope elimination and restora-
tion (EER) power amplifier. The analysis and detailed design
of the proposed architecture is presented. Simulation results, in
130-nm CMOS technology, show that the proposed supply mod-
ulator achieves better linearity and efficiency compared to the
conventional hybrid mode supply modulators or hybrid EER
when signal frequency increases. Adjacent channel leakage ratio
requirements are met for an LTE signal with 5 MHz, 10 MHz,
and 20 MHz BW with error vector magnitude less than 3% and
efficiency of 79%, 73%, and 67%, respectively at an output power
of 0.45 W. Post-layout simulations are performed across different
process corners and the effects of real off-chip components and
routes are taken into consideration to verify the robustness of
the proposed solution.
Index Terms—Class-E power amplifier, supply modulator, Fig. 1. Block diagram of dual switch controlled hybrid supply modulator.
envelope elimination and restoration, wide-band.

A conventional hybrid converter is shown in Fig. 1. It con-

I. I NTRODUCTION sists of a linear path and a switching path (excluding the extra
LASS-E power amplifiers (PA) show excellent efficiency path). The switches of the switching path are controlled by
C as well as capability to provide power amplification for
RF signals up to multiple GHz. However, a linearization tech-
the comparator’s output through some buffers. The compara-
tor forces Mp to conduct when the output needs to charge (the
nique is essential if the input RF signal contains amplitude voltage across Rsense is positive due to the direction of the cur-
information. The output of a class-E PA is proportional to the rent), and forces Mn to conduct when the output load needs
value of the applied supply voltage Vout = γ VDD where γ is to discharge. The comparator together with the large buffers
constant [1]. Thus, one of the most commonly used techniques and the big switches form a very slow long loop that is not
to linearize class-E PA is envelope elimination and restoration able to track fast changes in the envelope signal.
(EER). Phase signal is applied directly to the input, while the In order to facilitate tracking of the fast envelope signals,
envelope containing amplitude information is fed through the the linear amplifier with class-AB push pull stage is added.
supply of the PA. Using this approach, the linearity require- The linear stage will push more current Ilin into the load such
ment is shifted from the high frequency of the carrier to the that the output maintains the envelope if the switching stage
low frequency of the baseband signal; consequently supply is not able to track the fast envelope. The linear amplifier
modulation process should be done with highly linear and forms a low-efficiency path which is responsible for tracking
efficient amplifiers. The most commonly used supply mod- fast changes of envelope signal, while the switching path is
ulators, are switching mode regulators. However, they are not responsible for high-current Isw low-speed changes. This sup-
fast enough to amplify the baseband signal; accordingly lin- ply modulator is very efficient for low speed envelopes, while
ear regulators are usually used together with switching mode it can track fast changes with more losses in the linear ampli-
regulators (the hybrid supply modulator [2], [3]). fier; thus lower efficiency [4]. In [5], an extra path has been
added as shown in Fig. 1. In case of high output power where
Manuscript received February 1, 2019; accepted February 11, 2019. Date the envelope signal voltage is higher than a certain threshold
of publication February 21, 2019; date of current version December 26, 2019. (Vref ), switch Mp2 will supply the required current through LB2
This brief was recommended by Associate Editor S. C. Wong. (Corresponding even if the main switching stage is not responding yet due to
author: Ahmed Nader Mohieldin.)
The authors are with the Electronics and Electrical Communications the loop delay. Efficiency enhancement of 5% to 9% has been
Engineering, Cairo University, Giza 12613, Egypt (e-mail: reported compared to the conventional H-EER. However, dual
[email protected]). switch supply modulator has some drawbacks. First, it uses
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. two inductors, thus bulky and more expensive. Second, it does
Digital Object Identifier 10.1109/TCSII.2019.2900596 not solve the fundamental speed/efficiency trade-off of H-EER,
1549-7747 c 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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 10 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 67, NO. 1, JANUARY 2020

Fig. 3. Output voltage ripples of replica circuit.

Fig. 2. Architecture of the proposed hybrid supply modulator.

i.e., if high-speed envelope signal is applied, more current is

needed from the linear stage. Fig. 4. Rising step response of replica circuit & switching path.

II. P ROPOSED E NHANCED S UPPLY M ODULATOR A. Design of the Proposed Supply Modulator
The architecture of the proposed hybrid supply modulator 1) Estimating Switching Frequency of the Replica: In order
is shown in Fig. 2. It enhances the speed of the switching to achieve appropriate linearity performance, the switching
path; and thus improves the overall efficiency. The idea of the frequency FSW should be much higher than the signal band-
proposed architecture is developed as follows: width FENV as shown in Section III-A. This is also desirable to
1) The loop controlling the switching path has been reduce the size of the external inductor LB but results in larger
removed; and an additional control circuit is used in switching losses. The value of FSW is chosen as a trade-off
an open-loop configuration. The switching path consists between linearity and efficiency.
of digital buffers, non-overlapping circuit, switches MP In order to find an estimate FSW , the ripples of Vout−rep
and MN , inductor LB and capacitor CB . are assumed very small (Vout−rep  0) and thus the cur-
2) The proposed control circuit is a replica circuit for the rent across R1 , R2 and C1 is approximately constant. It is also
switching path. The replica circuit consists of two MOS assumed that the envelope Venv is constant for the sake of sim-
switches MP−rep and MN−rep that charge and discharge plifying the calculations. Thus, as shown in Fig. 3, a constant
capacitor C1 through resistor R1 . The effect of resistor current charges and discharges C1 , where tcomp1,2 represents
R2 is to emulate the load seen by the switching path. In the required time for the comparator to be able to flip its polar-
the current design, R2 has been made programmable to ity, while tbuff is the constant delay of the buffers following the
account for potential variations in the load. comparator. The term tcharge,discharge is the charging and dis-
3) Since the switching path is an open-loop path, it is charging time until Vout−rep reaches Venv . The time required
required to include a feedback path to correct any errors to charge C1 through MP−rep and fully invert the polarity
introduced by the control circuit. The feedback path is of the comparator is T1 = tcomp1 + tcharge + tbuff . Similarly,
a high-speed path that consists of a low-power linear the discharging time of C1 is T2 = tcomp2 + tdischarge +
OTA followed by a class-AB output stage. The linear tbuff . Thus, Vout−rep = T1 Slopeup = T2 Slopedown , where
stage should have minimum hit on efficiency, thus it is Slopeup = CV1DD R1 − Vout−rep ( C1 R1 + C1 R2 ) and Slopedown =
1 1

designed with small current (< 10% of the total output −Vout−rep ( C1 R1 + C1 R2 ).
1 1

current). FSW = 1/(T1 + T2 ) = 1/Tloop . For Venv = VDD /4 with

It shall be noted that proposed design uses two versions of R1 = R2 , Slopeup = Slopedown , and tcomp1 = tcomp2 , results
the envelope signal. The delay between the two envelope signal in Tloop = 4(tcomp + tbuff ). The delay of the comparator is
paths should be accurately calibrated from the digital domain. simulated for a differential input amplitude swept from 10 mV
The delay does not depend on the instantaneous value of the to 200 mV with three values of the bias current IB . For V1,2
amplitude so it does not introduce additional AM-PM distor- of 50 mV, the output of the comparator becomes a healthy rail-
tion. Similar calibration procedures are widely performed in to-rail signal after tcomp of about 13nsec, 7.5nsec, and 3.8nsec
many H-EER systems to adjust the delay between the envelope for IB of 0.5 mA, 1 mA, and 2 mA, respectively. tbuff is a
and phase signal paths [1]. The effect of this delay between minor contributor of about 1nsec.
the two envelope signals on linearity performance (IM3) is 2) Design Considerations for Switching Path: In order
studied in Section III-A. to achieve good rejection of the switching frequency and

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 MAMDOUH et al.: EFFICIENT SUPPLY MODULATOR FOR WIDE-BAND EER PA 11

Fig. 5. Circuit implementation of the comparator in replica circuit and the Linear stage.

TABLE I
yet allow the envelope signal to pass with no significant atten- I NITIAL C OMPONENT VALUES F ROM A NALYTIC S OLUTION
uation, the LC filter is designed to have a cut-off frequency
close to the signal bandwidth as shown in eq. (1).
1
4π 2 FENV
2
= (1)
LB CB
Since the switching path is designed to work in continuous
current mode (CCM), the value of LB is chosen sufficiently parameters obtained in the first step to obtain similar dynamic
large to avoid large current ripples that leads to losses due performance. This is measured through the step response of
to discharge of the output capacitor [6]. The value of CB each loop and the resulting IM3 by combining the two loops
affects the voltage ripples on Vout ; accordingly it is chosen together. Fig. 4 shows the rising step response of the replica
large enough for low voltage ripples. Equivalent series resis- circuit and the switching path for the case of 5 MHz signal
tance (ESR) of CB degrades efficiency, so it should be chosen BW. A good agreement between the two responses for both
as minimal as possible. cases (rising and falling) is achieved for R1,2 = 10k and
3) Design Parameters for Replica Circuit: First, analytic C1 = 25pF. In Fig. 4, IM3 drawn versus C1 and R1,2 is taken
expressions are found to equate the parameters of the replica as a norm to verify achieving the best solution.
circuit with that of the switching path under the assumption Since the components of the replica circuit are prone to
that both have constant average output voltage, i.e., Vout  0 process and temperature variations, the response of the replica
and Vout−rep  0. The voltage ripples of the replica circuit circuit can deviate. The linear stage in the proposed architec-
and the switching path can be expressed as: ture (Fig. 2) is designed to track very fast envelope changes
VDD 1 1 with minimal degradation of the overall efficiency, in addition
Vout−rep = T1 [ − Vout−rep ( + )] (2) to maintaining good performance in the presence of process
C1 R1 C1 R1 C1 R2
VDD − Vout Vout variations. Performance enhancement due to the linear stage,
Vout = T12 ( ) − T1 (3) even in the presence of process variations, has been verified
2LB CB RL CB
through simulations as shown in Section III-B.
In order to simplify the solution, R1 is chosen to be equal to
R2 and it is assumed that T1 = T2 = Tloop /2. Voltage division
between R1 and R2 in the replica circuit results in halving B. Circuit Implementation of the Proposed Design
Vout−rep . Equating both voltage ripples leads to: In Fig. 5a the detailed structure of the used comparator is
Tloop /2 1 shown. It consists of a high speed cascode differential ampli-
Coeff (VDD ) = = (2) (4) fier stage followed by a differential to single-ended rail to rail
2LB CB R1 C1
grep Tloop /2 1 output stage. A cascode amplifier is used to achieve high gain
Coeff (Vout ) = (2)( )= + (5) and thus good accuracy. The speed of the comparator is a cru-
C1 2LB CB RL CB
cial requirement for achieving good performance; and thus the
where grep = R11
+ R2
1
= R2 . cascode stage consumes about 0.5 mA to 2 mA for different
Equations (1) and (4)-(5) are then solved to find the design signal BW. The input headroom issue is relaxed using R1 = R2
parameters as summarized in Table I for three different values halving the signal swing at input of the comparator.
of signal BW. RL is chosen to be 2.5  to emulate PA loading. The linear stage is shown in Fig. 5b. It consists of a single-
It is noted that the replica circuit is a first-order system ended cascode amplifier followed by a class-AB stage that
while the switching path is a second-order system. Thus, provides the required current for the load. A Miller capacitor
matching the ripple magnitude analytically does not guaran- CC and resistor RZ are added to enhance stability of the linear
tee matching the dynamic behavior. Second, the fine tuning path. The loading effect of the switching stage is added in
step, where the values of C1 and R1,2 are swept around the simulations. RL is the equivalent load resistance in the

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 12 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 67, NO. 1, JANUARY 2020

Fig. 6. Simulation results (IM3 and Transient Response).

Fig. 7. Simulation results (HD, IM3, Power Consumption and Efficiency).

range of few s, thus CB has non-dominant effect on the case of non-ideal alignment between the two envelope signals,
overall stability. The BW of the linear stage is chosen slightly the IM3 for different delay mismatch is reported as shown
higher than the switching frequency to be able to track the in Fig. 6a. IM3 has been simulated across different technol-
replica circuit. Cascode amplifier consumes about 1.5 mA. The ogy corners including the effect of mismatch. Since we have
linear stage has one dominant pole (wp1  1/rota Cc ), one non- off-chip components (LB and CB ) and on-chip components,
dominant pole (wp2 =1/RL CB ) and one Zero (wz =Cc (1/gmab − so the worst case mismatch is simulated where the off-chip
Rz )). Where rota is the output resistance of the cascade stage components are maximum and on-chip components are mini-
which is in range of 100 k and Cc is about 16pF. Class-AB mum and vice versa as shown in Fig. 6b. The slow corner is
stage has small attenuation (about -2dB gain) due to the small an indication of slow on-chip components while the off-chip
output resistance. gmab is the transconductance of the class- components have minimum values, i.e., worst case mismatch
AB stage, and Rz is 150 . The simulated BW of the linear between replica and switching path. The fast corner has oppo-
stage is 49 MHz with open loop gain of 54dB, wz is located site conditions. The slow corner has been simulated without
at 60 MHz to guarantee good phase margin. the linear path, shown in Fig. 6b, indicating that the linear
stage enhances IM3 about 6dB at 5MHz.
III. S IMULATION R ESULTS
The layout of the proposed architecture in 0.13µm CMOS B. Linear Stage Contribution to Harmonic Distortion
technology is shown in Fig. 9. It occupies an area of Harmonic distortion (HD) test has been performed using a
1000µmx450µm. Post-layout simulations results are shown single tone signal at 2 MHz and 1.8Vpp amplitude. Figure 6c
with a conventional class-E PA used to test the performance shows that the amplitude of ripples at the output is less than
of the supply modulator in EER system. 55 mV. The effect of FSW is also simulated as shown in Fig. 7a.
It is noted that the linear stage enhances HD about 3dB when
A. Two Tone Test FSW is low. When FSW is high, the linear stage has lower
Two tones are applied to the input of the supply modula- contribution due to its bandwidth limitation.
tor. Figure 6a shows the simulated third-order intermodulation
(IM3). It can be noted that the proposed supply modulator C. Efficiency Test
maintains IM3 better than 40dBc for input signal frequencies Fig. 7b shows the efficiency as well as power consumption
up to 5 MHz, while the conventional H-EER can only achieve of the linear path. The efficiency of the conventional H-EER
3 MHz. In order to study the performance degradation in is higher than the proposed design when the signal frequency

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 MAMDOUH et al.: EFFICIENT SUPPLY MODULATOR FOR WIDE-BAND EER PA 13

TABLE II TABLE III

P OWER B UDGET C OMPARISON W ITH S TATE - OF - THE -A RT

reported peak efficiency is tested. The HD is reported only

in [9] and [10], where the signal applied to the supply modu-
lator is defined by the frequency Ffund and swing App . It can
be noted that the proposed design provides good efficiency
Fig. 8. PSD using the proposed supply modulator. while achieving the highest signal BW with good linearity.

IV. C ONCLUSION
The architecture of an efficient supply modulator for wide-
band EER PAs has been proposed. Design equations and trade-
offs have been presented. The design is implemented using
0.13µm CMOS technology. Post-layout simulations using LTE
signals have been performed showing that the proposed sup-
ply modulator is a good candidate for modern communication
systems supporting wide-band signals.
Fig. 9. Layout of the proposed supply modulator.
R EFERENCES
[1] C.-J. Li, C.-T. Chen, T.-S. Horng, J.-K. Jau, and J.-Y. Li, “High average-
is less than 2 MHz due to lower switching losses. However it efficiency multimode RF transmitter using a hybrid quadrature polar
modulator,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 3,
degrades quickly with signal frequency due to higher contribu- pp. 249–253, Mar. 2008.
tion of the linear stage. The efficiency of the proposed design [2] J. Kim et al., “Highly efficient RF transmitter over broad average power
is almost constant since the power contribution of the linear range using multilevel envelope-tracking power amplifier,” IEEE Trans.
Circuits Syst. I, Reg. Papers, vol. 6, no. 62, pp. 1648–1657, Jun. 2015.
path is much smaller. Efficiency versus output power is shown [3] K. Oishi et al., “A 1.95 GHz fully integrated envelope elimination and
in Fig. 7c for three different signal BW (5 MHz, 10 MHz restoration CMOS power amplifier using timing alignment technique
and 20 MHz). Simulations results of IM3 versus output power for WCDMA and LTE,” IEEE J. Solid-State Circuits, vol. 49, no. 12,
pp. 2915–2924, Dec. 2014.
shows an acceptable linearity performance for power levels up [4] J. Ham et al., “CMOS power amplifier integrated circuit with dual-mode
to 650 mW (28 dBm). Power budget is shown in Table II. supply modulator for mobile terminals,” IEEE Trans. Circuits Syst. I,
Reg. Papers, vol. 63, no. 1, pp. 157–167, Jan. 2016.
[5] H. S. Son et al., “A hybrid envelope amplifier with switching-controlled
D. Simulation Results Using LTE Signal structure for EDGE/WCDMA/LTE reconfigurable transmitters,” in Proc.
A real LTE signal has been used in order to validate the IEEE/MTT-S Int. Microw. Symp., 2012, pp. 1–3.
[6] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics.
performance of the supply modulator design. The channel New York, NY, USA: Kluwer, 2004.
spacing is 15kHz, while the constellation scheme is 16- [7] H. Holma and A. Toskala, LTE for UMTS-OFDMA and SC-FDMA
QAM [7]. ACLR has been tested for different LTE signal BW. Based Radio Access. Hoboken, NJ, USA: Wiley, 2009.
[8] J. Choi, D. Kim, D. Kang, and B. Kim, “A polar transmitter with CMOS
The RF power spectral density (PSD) for 20 MHz is shown programmable hysteretic-controlled hybrid switching supply modulator
in Fig. 8 and the corresponding scatter plot shows EVM less for multistandard applications,” IEEE Trans. Microw. Theory Techn.,
than 3%. vol. 57, no. 7, pp. 1675–1686, Jul. 2009.
[9] P. Y. Wu and P. K. Mok, “A two-phase switching hybrid supply modu-
lator for RF power amplifiers with 9% efficiency improvement,” IEEE
E. Comparison With State-of-the-Art J. Solid-State Circuits, vol. 45, no. 12, pp. 2543–2556, Dec. 2010.
[10] M. Tan and W.-H. Ki, “A 100 MHz hybrid supply modulator with ripple-
A comparison is shown in Table III with different liter- current-based PWM control,” IEEE J. Solid-State Circuits, vol. 52, no. 2,
ature work. Pout represents the output power at which the pp. 569–578, Feb. 2017.

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