Improved Second Source

to the EL2020
ADEL2020
FEATURES CONNECTION DIAGRAMS
Ideal for Video Applications
0.02% Differential Gain 8-Lead PDIP (N) 20-Lead SOIC (R)
0.04
Differential Phase
0.1 dB Bandwidth to 25 MHz (G = +2)
High Speed BAL 1 8 DISABLE NC 1 20 NC

90 MHz Bandwidth (–3 dB) –IN 2 7 V+ BAL 2 ADEL2020 19 DISABLE

TOP VIEW
500 V/s Slew Rate +IN 3 6 OUTPUT NC 3 18 NC

60 ns Settling Time to 0.1% (VO = 10 V Step) V– 4 ADEL2020 5 BAL –IN 4 17 V+

TOP VIEW
Low Noise NC 5 16 NC

2.9 nV/√Hz Input Voltage Noise +IN 6 15 OUTPUT

Low Power NC 7 14 NC

6.8 mA Supply Current V– 8 13 BAL

2.1 mA Supply Current (Power-Down Mode) NC 9 12 NC

High Performance Disable Function NC 10 11 NC

Turn-Off Time of 100 ns NC = NO CONNECT

Input to Output Isolation of 54 dB (Off State)

GENERAL DESCRIPTION The ADEL2020 offers other significant improvements. The

The ADEL2020 is an improved second source to the EL2020. most important is lower power supply current (33% less than the
This op amp improves on all the key dynamic specifications competition) with higher output drive. Important specifications
while offering lower power and lower cost. The ADEL2020 like voltage noise and offset voltage are less than half of those
offers 50% more bandwidth and gain flatness of 0.1 dB to for the EL2020. The ADEL2020 also provides an improved
beyond 25 MHz. In addition, differential gain and phase are disable feature. The disable time (to high output impedance) is
less than 0.05% and 0.05° while driving one back terminated 100 ns with guaranteed break before make. The ADEL2020 is
cable (150 Ω). offered for the industrial temperature range of –40°C to +85°C
and comes in both PDIP and SOIC packages.
+0.1
RL = 150 0.10 0.20
0 GAIN = +2
15V 0.09 RF = 750 0.18
RL = 150
–0.1

DIFFERENTIAL PHASE – Degrees

5V
0.08 fC = 3.58MHz 0.16
NORMALIZED GAIN – dB

100 IRE
DIFFERENTIAL GAIN – %

0.07 MODULATED RAMP 0.14

0.06 0.12
+0.1
RL = 1k 0.05 0.10
0 0.04 0.08
15V GAIN PHASE
–0.1 0.03 0.06
5V
0.02 0.04

0.01 0.02

100k 1M 10M 100M 0 0

FREQUENCY – Hz 5 6 7 8 9 10 11 12 13 14 15
SUPPLY VOLTAGE – V
Figure 1. Fine-Scale Gain (Normalized) vs. Frequency
for Various Supply Voltages, RF = 750 Ω, Gain = +2 Figure 2. Differential Gain and Phase vs. Supply Voltage

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com
registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
ADEL2020–SPECIFICATIONS (@ T = 25
C, V = 15 V dc, R = 150 Ω, unless otherwise noted.)
A S L

ADEL2020A
Parameter Conditions Temperature Min Typ Max Unit

INPUT OFFSET VOLTAGE 1.5 7.5 mV

TMIN to TMAX 2.0 10.0 mV
Offset Voltage Drift 7 µV/°C
COMMON-MODE REJECTION VCM = ± 10 V
VOS TMIN to TMAX 50 64 dB
± Input Current TMIN to TMAX 0.1 1.0 µA/V
POWER SUPPLY REJECTION VS = ± 4.5 V to ± 18 V
VOS TMIN to TMAX 65 72 dB
± Input Current TMIN to TMAX 0.05 0.5 µA/V
INPUT BIAS CURRENT –Input TMIN to TMAX 0.5 7.5 µA
+Input TMIN to TMAX 1 15 µA
INPUT CHARACTERISTICS
+Input Resistance 1 10 MΩ
–Input Resistance 40 Ω
+Input Capacitance 2 pF
OPEN-LOOP TRANSRESISTANCE VO = ± 10 V
RL = 400 Ω TMIN to TMAX 1 3.5 MΩ
OPEN-LOOP DC VOLTAGE GAIN RL = 400 Ω, VOUT = ± 10 V TMIN to TMAX 80 100 dB
RL = 100 Ω, VOUT = ± 2.5 V TMIN to TMAX 76 88 dB
OUTPUT VOLTAGE SWING RL = 400 Ω TMIN to TMAX ± 12.0 ± 13.0 V
Short-Circuit Current 150 mA
Output Current TMIN to TMAX 30 60 mA
POWER SUPPLY
Operating Range ± 3.0 ± 18 V
Quiescent Current TMIN to TMAX 6.8 10.0 mA
Power-Down Current TMIN to TMAX 2.1 3.0 mA
Disable Pin Current Disable Pin = 0 V TMIN to TMAX 290 400 µA
Min Disable Pin Current to Disable TMIN to TMAX 30 µA
DYNAMIC PERFORMANCE
3 dB Bandwidth G = +1; RFB = 820 90 MHz
G = +2; RFB = 750 70 MHz
G = +10; RFB = 680 30 MHz
0.1 dB Bandwidth G = +2; RFB = 750 25 MHz
Full Power Bandwidth VO = 20 V p-p,
RL = 400 Ω 8 MHz
Slew Rate RL = 400 Ω, G = +1 500 V/µs
Settling Time to 0.1% 10 V Step, G = –1 60 ns
Differential Gain f = 3.58 MHz 0.02 %
Differential Phase f = 3.58 MHz 0.04 Degree
INPUT VOLTAGE NOISE f = 1 kHz 2.9 nV/√Hz
INPUT CURRENT NOISE –IIN, f = 1 kHz 13 pA/√Hz
+IIN, f = 1 kHz 1.5 pA/√Hz
OUTPUT RESISTANCE Open Loop (5 MHz) 15 Ω
Specifications subject to change without notice.

–2– REV. A
 ADEL2020
ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V The maximum power that can be safely dissipated by the
Internal Power Dissipation2 . . . . . . . Observe Derating Curves ADEL2020 is limited by the associated rise in junction tempera-
Output Short Circuit Duration . . . . Observe Derating Curves ture. For the plastic packages, the maximum safe junction
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . ± VS temperature is 145°C. If the maximum is exceeded momen-
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ± 6 V tarily, proper circuit operation will be restored as soon as the
Storage Temperature Range die temperature is reduced. Leaving the device in the over-
PDIP and SOIC . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C heated condition for an extended period can result in device
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C burnout. To ensure proper operation, it is important to observe
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C the derating curves in figure 4.
While the ADEL2020 is internally short circuit protected, this
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma- may not be sufficient to guarantee that the maximum junction
nent damage to the device. This is a stress rating only and functional operation of temperature is not exceeded under all conditions.
the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating 2.4
conditions for extended periods may affect device reliability.
2.2
2
8-Lead PDIP: θJA = 90°C/W
20-Lead SOIC Package: θJA = 150°C/W

TOTAL POWER DISSIPATION – W

2.0

+VS 1.8
20-LEAD SOIC
0.1F 1.6

1.4
10k
7 1.2
2 – 1 8-LEAD PDIP
5 1.0
ADEL2020 6
0.8
3 +
4
0.1F 0.6

0.4
–VS –40 –20 0 20 40 60 80 100
AMBIENT TEMPERATURE –
C
Figure 3. Offset Null Configuration
Figure 4. Maximum Power Dissipation vs. Temperature

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

ADEL2020AN –40°C to +85°C 8-Lead PDIP N-8

ADEL2020AR-20 –40°C to +85°C 20-Lead SOIC R-20
ADEL2020AR-20-REEL –40°C to +85°C 20-Lead SOIC R-20

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADEL2020 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. A –3–
ADEL2020–Typical Performance Characteristics
GAIN = +1 GAIN = +1
RL = 150 0 RL = 1k 0

–45 –45
PHASE PHASE VS = 15V
CLOSED-LOOP GAIN – dB

CLOSED-LOOP GAIN – dB
PHASE SHIFT – Degrees

PHASE SHIFT – Degrees

–90 –90
VS = 15V
1 –135 1 –135
5V
0 –180 0 –180
5V
–1 –225 –1 –225
GAIN GAIN
–2 –270 –2 –270
VS = 15V VS = 15V
–3 –3
5V 5V
–4 –4

–5 –5
1 10 100 1000 1 10 100 1000
FREQUENCY – MHz FREQUENCY – MHz

TPC 1. Closed-Loop Gain and Phase vs. Frequency, TPC 4. Closed-Loop Gain and Phase vs. Frequency,
G = + 1, RL = 150 Ω, RF = 1 kΩ for ± 15 V, 910 Ω for ± 5 V G = +1, RL = 1 kΩ, RF = 1 kΩ for ± 15 V, 910 Ω for ± 5 V

110 110
GAIN = +1 GAIN = –1
100 RL = 150 100 RL = 150
VO = 250mV p-p VO = 250mV p-p
PEAKING < 1.0dB
90 90
RF = 750 RF = 499 PEAKING < 1.0dB
–3dB BANDWIDTH – MHz

–3dB BANDWIDTH – MHz

80 80

70 70

60 60
RF = 1k PEAKING < 0.1dB RF = 681 PEAKING < 0.1dB
50 50

40 40

30 30
RF = 1.5k RF = 1k
20 20

10 10
0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
SUPPLY VOLTAGE – V SUPPLY VOLTAGE – V

TPC 2. –3 dB Bandwidth vs. Supply Voltage, TPC 5. –3 dB Bandwidth vs. Supply Voltage,
Gain = +1, RL = 150 Ω Gain = –1, RL = 150 Ω

GAIN = –1 GAIN = –1
RL = 150 180 RL = 1k 180

135 135
PHASE PHASE
CLOSED-LOOP GAIN – dB

CLOSED-LOOP GAIN – dB
PHASE SHIFT – Degrees

PHASE SHIFT – Degrees

VS = 15V 90 VS = 15V 90

1 45 1 45

0 0 0 0
5V 5V
–1 –45 –1 –45
GAIN GAIN
–2 –2
VS = 15V VS = 15V
–3 –3
5V 5V
–4 –4

–5 –5
1 10 100 1000 1 10 100 1000
FREQUENCY – MHz FREQUENCY – MHz

TPC 3. Closed-Loop Gain and Phase vs. Frequency, TPC 6. Closed-Loop Gain and Phase vs. Frequency,
G = –1, RL = 150 Ω, RF = 680 Ω for ± 15 V, 620 Ω for ± 5 V G = –1, RL = 1 kΩ, RF = 680 Ω for VS = ± 15 V, 620 Ω
for ± 5 V

–4– REV. A
 ADEL2020
GAIN = +2 GAIN = +2
RL = 150 0 RL = 1k 0

–45 –45
PHASE PHASE
CLOSED-LOOP GAIN – dB

CLOSED-LOOP GAIN – dB
PHASE SHIFT – Degrees

PHASE SHIFT – Degrees

VS = 15V –90 VS = 15V –90

7 –135 7 –135

6 –180 6 –180
5V 5V
5 –225 5 –225
GAIN GAIN
4 –270 4 –270
VS = 15V VS = 15V
3 3
5V 5V
2 2

1 1
1 10 100 1000 1 10 100 1000
FREQUENCY – MHz FREQUENCY – MHz

TPC 7. Closed-Loop Gain and Phase vs. Frequency, TPC 10. Closed-Loop Gain and Phase vs. Frequency,
G = +2, RL = 150 Ω, RF = 750 Ω for ± 15 V, 715 Ω for ± 5 V G = +2, RL = 1 kΩ, RF = 750 Ω for ± 15 V, 715 Ω for ± 5 V

110 110
GAIN = +2 GAIN = +10
100 RL = 150 100 RL = 150
VO = 250mV p-p VO = 250mV p-p
PEAKING < 1.0dB
90 90
RF = 500

–3dB BANDWIDTH – MHz

–3dB BANDWIDTH – MHz

80 80

70 70
PEAKING < 0.5dB
60 60
PEAKING < 0.1dB RF = 232
RF = 750
50 50

40 40 RF = 442 PEAKING < 0.1dB

RF = 1k
30 30
RF = 1k
20 20

10 10
0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
SUPPLY VOLTAGE – V SUPPLY VOLTAGE – V

TPC 8. –3 dB Bandwidth vs. Supply Voltage, TPC 11. –3 dB Bandwidth vs. Supply Voltage,
Gain = +2, RL = 150 Ω Gain = +10, RL = 150 Ω

GAIN = +10 GAIN = +10

RF = 270 0 RF = 270 0
RL = 150 RL = 1k
–45 –45
PHASE PHASE
CLOSED-LOOP GAIN – dB

CLOSED-LOOP GAIN – dB
PHASE SHIFT – Degrees

PHASE SHIFT – Degrees

–90 –90
VS = 15V VS = 15V
21 –135 21 –135

20 –180 20 –180

19 –225 19 –225
GAIN 5V GAIN 5V
18 –270 18 –270
VS = 15V VS = 15V
17 17
5V 5V
16 16

15 15
1 10 100 1000 1 10 100 1000
FREQUENCY – MHz FREQUENCY – MHz

TPC 9. Closed-Loop Gain and Phase vs. Frequency, TPC 12. Closed-Loop Gain and Phase vs. Fre-
G = +10, RL = 150 kΩ quency, G = +10, RL = 1 kΩ

REV. A –5–
ADEL2020
30 10
GAIN = +2
VS = 15V RF = 715

CLOSED-LOOP OUTPUT RESISTANCE – 

25 VS = 5V
OUTPUT VOLTAGE – V p-p

20 1

OUTPUT LEVEL FOR 3% THD

15 VS = 15V

10 0.1
VS = 5V

0 0.01
100k 1M 10M 100M 10k 100k 1M 10M 100M
FREQUENCY – Hz FREQUENCY – Hz

TPC 13. Maximum Undistorted Output Voltage TPC 16. Closed-Loop Output Resistance vs. Frequency
vs. Frequency

80 10
RF = 715
AV = +2
70
9
POWER SUPPLY REJECTION – dB

60 VS = 15V
SUPPLY CURRENT – mA
VS = 15V 8
50
VS = 5V VS = 5V
40 7

30
CURVES ARE FOR WORST-CASE 6
CONDITION WHERE ONE
20
SUPPLY IS VARIED WHILE THE
OTHER IS HELD CONSTANT 5
10

0 4
10k 100k 1M 10M 100M –60 –40 –20 0 20 40 60 80 100 120 140
FREQUENCY – Hz JUNCTION TEMPERATURE –
C

TPC 14. Power Supply Rejection vs. Frequency TPC 17. Supply Current vs. Junction Temperature

100 100 1200

VS = 5V TO 15V RL = 400
1100

1000
GAIN = –10
CURRENT NOISE – pA/ Hz
VOLTAGE NOISE – nV/ Hz

900
SLEW RATE – V/s

INVERTING INPUT 800

CURRENT
GAIN = +10
10 10 700

600

500
VOLTAGE NOISE GAIN = +2
400
NONINVERTING
INPUT CURRENT 300

1 1 200
10 100 1k 10k 100k 0 2 4 6 8 10 12 14 16 18 20
FREQUENCY – Hz SUPPLY VOLTAGE – V

TPC 15. Input Voltage and Current Noise vs. Frequency TPC 18. Slew Rate vs. Supply Voltage

–6– REV. A
 ADEL2020
1k 750
+VS +VS
0.1F 0.1F

7 750 7
2 – 2 –

ADEL2020 6 VO ADEL2020 6 VO
RL RL
VIN 3 + VIN 3 +
4 4
RT 0.1F RT 0.1F

–VS –VS

Figure 5. Connection Diagram for AVCL = +1 Figure 7. Connection Diagram for AVCL = +2

681 270
+VS +VS
0.1F 0.1F

681 7 30 7
VIN 2 – 2 –

ADEL2020 6 VO ADEL2020 6 VO
RL RL
3 + VIN 3 +
4 4
0.1F RT 0.1F

–VS –VS

Figure 6. Connection Diagram for AVCL = –1 Figure 8. Connection Diagram for AVCL = +10

REV. A –7–
ADEL2020
GENERAL DESIGN CONSIDERATIONS DISABLE MODE
The ADEL2020 is a current feedback amplifier optimized for By pulling the voltage on Pin 8 to common (0 V), the ADEL2020
use in high performance video and data acquisition systems. can be put into a disabled state. In this condition, the supply
Since it uses a current feedback architecture, its closed-loop current drops to less than 2.8 mA, the output becomes a high
bandwidth depends on the value of the feedback resistor. The impedance, and there is a high level of isolation from input to
–3 dB bandwidth is also somewhat dependent on the power output. In the case of a line driver, for example, the output
supply voltage. Lowering the supplies increases the values of impedance will be about the same as that for a 1.5 kΩ resistor
internal capacitances, reducing the bandwidth. To compen- (the feedback plus gain resistors) in parallel with a 13 pF capacitor
sate for this, smaller values of feedback resistors are used at (due to the output), and the input to output isolation will be
lower supply voltages. better than 50 dB at 10 MHz.
Leaving the disable pin disconnected (floating) will leave the
POWER SUPPLY BYPASSING part in the enabled state.
Adequate power supply bypassing can be critical when optimiz-
ing the performance of a high frequency circuit. Inductance in In cases where the amplifier is driving a high impedance load,
the power supply leads can contribute to resonant circuits that the input to output isolation will decrease significantly if the
produce peaking in the amplifier’s response. In addition, if large input signal is greater than about 1.2 V p–p. The isolation can
current transients must be delivered to the load, then bypass be restored to the 50 dB level by adding a dummy load (say 150 Ω)
capacitors (typically greater than 1 µF) will be required to at the amplifier output. This will attenuate the feedthrough
provide the best settling time and lowest distortion. Although signal. (This is not an issue for multiplexer applications where the
the recommended 0.1 µF power supply bypass capacitors will outputs of multiple ADEL2020s are tied together as long as at
be sufficient in most applications, more elaborate bypassing least one channel is in the ON state.) The input impedance of
(such as using two paralleled capacitors) may be required in the disable pin is about 35 kΩ in parallel with a few pF. When
some cases. grounded, about 50 µA flows out of the disable pin for ±5 V supplies.
Break-before-make operation is guaranteed by design. If driven
CAPACITIVE LOADS by standard CMOS logic, the disable time (until the output is
When used with the appropriate feedback resistor, the ADEL2020 high impedance) is about 100 ns and the enable time (to low
can drive capacitive loads exceeding 1000 pF directly without impedance output) is about 160 ns. Since it has an internal pull-
oscillation. Another method of compensating for large load up resistor of about 35 kΩ, the ADEL2020 can be used with
capacitance is to insert a resistor in series with the loop output. open drain logic as well. In that case, the enable time increases
In most cases, less than 50 Ω is all that is needed to achieve an to about 1 µs.
extremely flat gain response.
If there is a nonzero voltage present on the amplifier’s output
at the time it is switched to the disabled state, some additional
OFFSET NULLING
decay time will be required for the output voltage to relax to
A 10 kΩ pot connected between Pins 1 and 5, with its wiper con-
zero. The total time for the output to go to zero will normally
nected to V+, can be used to trim out the inverting input current
be about 250 ns; it is somewhat dependent on the load impedance.
(with about ±20 µA of range). For closed-loop gains above about
5, this may not be sufficient to trim the output offset voltage to
zero. Tie the pot’s wiper to ground through a large value resistor
(50 kΩ for ±5 V supplies, 150 kΩ for ±15 V supplies) to trim the
output to zero at high closed-loop gains.

OPERATION AS A VIDEO LINE DRIVER

The ADEL2020 is designed to offer outstanding performance at
closed-loop gains of 1 or greater. At a gain of 2, the ADEL2020
makes an excellent video line driver. The low differential gain
and phase errors and wide –0.1 dB bandwidth are nearly inde-
pendent of supply voltage and load. For applications requiring
widest 0.1 dB bandwidth, it is recommended to use 715 Ω feed-
back and gain resistors. This will result in about 0.05 dB of
peaking and a –0.1 dB bandwidth of 30 MHz on ± 15 V supplies.

–8– REV. A
 ADEL2020
OUTLINE DIMENSIONS

8-Lead Plastic Dual-in-Line Package [PDIP]

(N-8)
Dimensions shown in inches and (millimeters)

0.375 (9.53)
0.365 (9.27)
0.355 (9.02)

8 5 0.295 (7.49)
0.285 (7.24)
1 4 0.275 (6.98)
0.325 (8.26)
0.310 (7.87)
0.100 (2.54) 0.150 (3.81)
0.300 (7.62)
BSC
0.135 (3.43)
0.015 0.120 (3.05)
0.180
(4.57) (0.38)
MAX MIN
0.015 (0.38)
0.150 (3.81) SEATING 0.010 (0.25)
0.130 (3.30) PLANE 0.008 (0.20)
0.110 (2.79) 0.060 (1.52)
0.022 (0.56) 0.050 (1.27)
0.018 (0.46) 0.045 (1.14)
0.014 (0.36)

COMPLIANT TO JEDEC STANDARDS MO-095AA

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

20-Lead Standared Small Outline Pacakge [SOIC]

Wide Body
(R-20)
Dimensions shown in millimeters and (inches)

13.00 (0.5118)
12.60 (0.4961)

20 11
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
1 10
10.00 (0.3937)

2.65 (0.1043) 0.75 (0.0295)

2.35 (0.0925)  45

0.30 (0.0118) 0.25 (0.0098)
0.10 (0.0039)

8

COPLANARITY 1.27 0.51 (0.0201) SEATING 0
1.27 (0.0500)
(0.0500) PLANE 0.32 (0.0126)
0.10 0.33 (0.0130) 0.40 (0.0157)
BSC 0.23 (0.0091)

COMPLIANT TO JEDEC STANDARDS MS-013AC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

REV. A –9–
ADEL2020
Revision History
Location Page
1/03—Data Sheet changed from REV. 0 to REV. A.
Format updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
8-Lead PDIP (N) and 20-Lead SOIC (R) updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
OUTLINE DIMENSIONS updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

–10– REV. A
–11–
–12–
PRINTED IN U.S.A. C03445–0–1/03(A)