PD - 97061B

IRFB4110PbF
Applications
HEXFET® Power MOSFET
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply VDSS 100V
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
RDS(on) typ. 3.7m:
max 4.5m:
ID 180A
Benefits
l Improved Gate, Avalanche and Dynamic dv/dt
D
Ruggedness D
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
G S
D
G
S TO-220AB

G D S
Gate Drain Source

Absolute Maximum Ratings

Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 180c A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 130c
IDM Pulsed Drain Current d 670
PD @TC = 25°C Maximum Power Dissipation 370 W
Linear Derating Factor 2.5 W/°C
VGS Gate-to-Source Voltage ± 20 V
dv/dt Peak Diode Recovery f 5.3 V/ns
TJ Operating Junction and -55 to + 175 °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300
(1.6mm from case)
Mounting torque, 6-32 or M3 screw 10lbxin (1.1Nxm)
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy e 210 mJ
IAR Avalanche Currentc 75 A
EAR Repetitive Avalanche Energy g 37 mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Case k ––– 0.402
RθCS Case-to-Sink, Flat Greased Surface 0.50 ––– °C/W
RθJA Junction-to-Ambient j ––– 62

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This datasheet has been downloaded from http://www.digchip.com at this page 2/21/06
IRFB4110PbF

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.108 ––– V/°C Reference to 25°C, ID = 5mAd
RDS(on) Static Drain-to-Source On-Resistance ––– 3.7 4.5 mΩ VGS = 10V, ID = 75A g
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 100V, VGS = 0V
––– ––– 250 VDS = 100V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 160 ––– ––– S VDS = 50V, ID = 75A
Qg Total Gate Charge ––– 150 210 nC ID = 75A
Qgs Gate-to-Source Charge ––– 35 ––– VDS = 50V
Qgd Gate-to-Drain ("Miller") Charge ––– 43 ––– VGS = 10V g
RG Gate Resistance ––– 1.3 ––– Ω
td(on) Turn-On Delay Time ––– 25 ––– ns VDD = 65V
tr Rise Time ––– 67 ––– ID = 75A
td(off) Turn-Off Delay Time ––– 78 ––– RG = 2.6Ω
tf Fall Time ––– 88 ––– VGS = 10V g
Ciss Input Capacitance ––– 9620 ––– pF VGS = 0V
Coss Output Capacitance ––– 670 ––– VDS = 50V
Crss Reverse Transfer Capacitance ––– 250 ––– ƒ = 1.0MHz
Coss eff. (ER) Effective Output Capacitance (Energy Related)i ––– 820 ––– VGS = 0V, VDS = 0V to 80V j
Coss eff. (TR) Effective Output Capacitance (Time Related)h ––– 950 ––– VGS = 0V, VDS = 0V to 80V h

Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 170c A MOSFET symbol D

(Body Diode) showing the

ISM Pulsed Source Current ––– ––– 670 integral reverse G

(Body Diode)di p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 75A, VGS = 0V g
trr Reverse Recovery Time ––– 50 75 ns TJ = 25°C VR = 85V,
––– 60 90 T J = 125°C I F = 75A
Qrr Reverse Recovery Charge ––– 94 140 nC TJ = 25°C di/dt = 100A/µs g
––– 140 210 TJ = 125°C
IRRM Reverse Recovery Current ––– 3.5 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Calculated continuous current based on maximum allowable junction † Coss eff. (TR) is a fixed capacitance that gives the same charging time
temperature. Package limitation current is 75A. as Coss while VDS is rising from 0 to 80% VDSS.
‚ Repetitive rating; pulse width limited by max. junction ‡ Coss eff. (ER) is a fixed capacitance that gives the same energy as
temperature. Coss while VDS is rising from 0 to 80% VDSS.
ƒ Limited by TJmax, starting TJ = 25°C, L = 0.074mH ˆ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
RG = 25Ω, IAS = 75A, VGS =10V. Part not recommended for use mended footprint and soldering techniques refer to application note #AN-994.
above this value. ‰ Rθ is measured at TJ approximately 90°C.
„ ISD ≤ 75A, di/dt ≤ 630A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
… Pulse width ≤ 400µs; duty cycle ≤ 2%.

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 IRFB4110PbF
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V
ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

6.0V 6.0V
5.5V 5.5V
5.0V 5.0V
4.8V 4.8V
BOTTOM 4.5V BOTTOM 4.5V 4.5V

100 4.5V 100

≤60µs PULSE WIDTH ≤60µs PULSE WIDTH

Tj = 25°C Tj = 175°C
10 10
0.1 1 10 100 0.1 1 10 100
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 3.0
ID = 75A

RDS(on) , Drain-to-Source On Resistance

VGS = 10V
ID, Drain-to-Source Current (A)

2.5
100

2.0
(Normalized)

10 T J = 25°C

1.5
T J = 175°C

1
1.0
VDS = 25V
≤60µs PULSE WIDTH
0.1 0.5
1 2 3 4 5 6 7 -60 -40 -20 0 20 40 60 80 100120140160180

VGS, Gate-to-Source Voltage (V) T J , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

100000 12.0
VGS = 0V, f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
ID= 75A
Crss = C gd 10.0
VGS, Gate-to-Source Voltage (V)

Coss = Cds + Cgd VDS= 80V

VDS= 50V
C, Capacitance (pF)

10000 Ciss 8.0

6.0
Coss

1000 4.0
Crss
2.0

100 0.0
1 10 100 0 50 100 150 200
VDS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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 IRFB4110PbF
1000 10000

OPERATION IN THIS AREA

LIMITED BY R DS(on)

ID, Drain-to-Source Current (A)

ISD, Reverse Drain Current (A)

T J = 175°C
100 1000

T J = 25°C 100µsec

10 100

10msec

DC 1msec
1 10
Tc = 25°C
Tj = 175°C
VGS = 0V Single Pulse
0.1 1
0.0 0.5 1.0 1.5 2.0 0 1 10 100 1000
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area

V(BR)DSS , Drain-to-Source Breakdown Voltage (V)

180 125
Id = 5mA
160
Limited By Package 120
140
115
ID, Drain Current (A)

120

100 110

80 105

60
100
40
95
20

0 90
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180
T C , Case Temperature (°C) T J , Temperature ( °C )

Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Drain-to-Source Breakdown Voltage

5.0 900
ID
EAS , Single Pulse Avalanche Energy (mJ)

4.5 800
TOP 17A
4.0 26A
700
BOTTOM 75A
3.5
600
3.0
Energy (µJ)

500
2.5
400
2.0
300
1.5

1.0 200

0.5 100

0.0 0
0 20 40 60 80 100 120 25 50 75 100 125 150 175

VDS, Drain-to-Source Voltage (V) Starting T J , Junction Temperature (°C)

Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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 IRFB4110PbF
1

D = 0.50
Thermal Response ( Z thJC )

0.1 0.20
0.10
0.05
τi (sec)
R1 R2 R3
0.01 0.02 R1 R2 R3 Ri (°C/W)
τJ τC
0.01 τJ
τ1
τC 0.09876251 0.000111
τ2 τ3
τ1 τ2 τ3 0.2066697 0.001743
C i= τi/R i 0.09510464 0.012269
C i= τi/Ri
0.001 SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000
Allowed avalanche Current vs avalanche
Duty Cycle = Single Pulse
pulsewidth, tav, assuming ∆ Tj = 150°C and
Tstart =25°C (Single Pulse)
100
Avalanche Current (A)

0.01
0.05
10
0.10

1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth

250 Notes on Repetitive Avalanche Curves , Figures 14, 15:

TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 1.0% Duty Cycle 1. Avalanche failures assumption:
200 ID = 75A Purely a thermal phenomenon and failure occurs at a temperature far in
EAR , Avalanche Energy (mJ)

excess of Tjmax. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
150 4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
100 6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
50 tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)

0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25 50 75 100 125 150 175
Iav = 2DT/ [1.3·BV·Zth]
Starting T J , Junction Temperature (°C) EAS (AR) = PD (ave)·tav

Fig 15. Maximum Avalanche Energy vs. Temperature

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IRFB4110PbF
4.0 25
IF = 30A
V R = 85V
VGS(th) , Gate threshold Voltage (V)

3.5
20
TJ = 25°C
3.0 TJ = 125°C
15
2.5

IRR (A)
ID = 250µA
2.0 ID = 1.0mA 10
ID = 1.0A
1.5
5
1.0

0.5 0
-75 -50 -25 0 25 50 75 100 125 150 175 200 0 200 400 600 800 1000
T J , Temperature ( °C ) diF /dt (A/µs)

Fig 16. Threshold Voltage vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt

25 560
IF = 45A IF = 30A
V R = 85V 480 V R = 85V
20
TJ = 25°C TJ = 25°C
TJ = 125°C TJ = 125°C
400
15
QRR (A)
IRR (A)

320

10
240

5
160

0 80
0 200 400 600 800 1000 0 200 400 600 800 1000
diF /dt (A/µs) diF /dt (A/µs)

Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt

560
IF = 45A

480 V R = 85V
TJ = 25°C
TJ = 125°C
400
QRR (A)

320

240

160

80
0 200 400 600 800 1000
diF /dt (A/µs)

Fig. 20 - Typical Stored Charge vs. dif/dt

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 IRFB4110PbF
Driver Gate Drive
P.W.
D.U.T P.W.
Period D=
Period
+

ƒ VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG VDD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• ISD controlled by Duty Factor "D" - Inductor Current
Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

V(BR)DSS
15V
tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS

Fig 21a. Unclamped Inductive Test Circuit Fig 21b. Unclamped Inductive Waveforms

LD
VDS VDS
90%
+
VDD -

D.U.T 10%
VGS VGS
Pulse Width < 1µs
Duty Factor < 0.1% td(on) tr td(off) tf

Fig 22a. Switching Time Test Circuit Fig 22b. Switching Time Waveforms
Id
Vds

Vgs

L
VCC
DUT Vgs(th)
0
1K

Qgs1 Qgs2 Qgd Qgodr

Fig 23a. Gate Charge Test Circuit Fig 23b. Gate Charge Waveform
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IRFB4110PbF

TO-220AB Package Outline (Dimensions are shown in millimeters (inches))

TO-220AB Part Marking Information

(;$03/( 7+,6,6$1,5)
/27&2'(
$66(0%/('21:: ,17(51$7,21$/ 3$57180%(5
,17+($66(0%/</,1(& 5(&7,),(5
/2*2
Note: "P" in assembly line
position indicates "Lead-Free" '$7(&2'(
$66(0%/< <($5 
/27&2'( :((.
/,1(&

TO-220AB packages are not recommended for Surface Mount Application.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 02/06
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