LAB 09

RISC-V Assembly (Part I: Introduction)

EE-222 Microprocessors Systems
April 11, 2019

Contents
1 Administrivia 2
1.1 Learning Outcomes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Deliverable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 RISC-V 3
2.1 RISC-V Instruction Set Architecture . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.3 RISC-V Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 RISC-V Assembly 5
3.1 Venus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Writing Assembly Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 Memory Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.4 Assembler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.5 Environment Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Lab Tasks 8
4.1 Task A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.1 Answer the given questions . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Task B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 Task C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

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1 Administrivia
1.1 Learning Outcomes
By the end of this lab you will be able to;

1. Write programs in RISC-V assembly.

2. Get familiarized with RISC-V ISA.

3. Understand the concept of pseudo instructions.

4. Understand memory segments of a program.

1.2 Deliverable
You are required to submit

• Appropriately Commented Code

• Issues in Developing the Solution and your Response

in the beginning of next lab

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2 RISC-V
RISC-V is an open source architecture based on reduced instruction set computing. In
contrast to most ISAs, the RISC-V ISA is free and can be used royalty-free for any purpose,
permitting anyone to design, manufacture and sell RISC-V chips and software.

2.1 RISC-V Instruction Set Architecture

The most basic form of RISC-V ISA is base integer ISA (written as RV32I or RV64I for
32-bit address space and 64-bit address space respectively). Further extensions to the base
integer ISA are also available.

Extension Functionality
RV32I Base 32-bit integer
RV64I Instructions to manipulate 64-bit data chunks are added
M Multiply and Divide instructions are added
F Single precision floating point instructions added
D Double precision floating point instructions added
A Atomic instruction for concurrent processing

2.2 Register File

RV32G (G = IMAFD) has 32-bit wide 32 general purpose registers. The first register x0 is
hard wired to zero. There are 12 callee saved registers s0-s11, 7 registers to hold temporaries
t0-t6, 8 function arguments/return value registers a0-a7 and a register dedicated to return
address, stack pointer, global pointer and thread pointer each.

Here is a link to RISC-V Reference Card1

1
http://inst.eecs.berkeley.edu/ cs61c/fa17/img/riscvcard.pdf

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2.3 RISC-V Instruction Format
RISC-V is a load-store architecture. All instructions are 32-bits wide and divided into four
categories.
Instruction Type Usage Format Example
Register-register
R-Type name dest, src1, src2 add s0, s1, s2
ALU instruction
ALU Instructions
I-Type with immediates name dest, src1, imm addi s0, s1, 9
(including Loads)
Compare and branch
S-Type name src1, src2, imm beq s0, s1, label
(including Stores)
U-Type Jump and Link name dest, imm jal ra, label
Jump and Link
UJ-Type name dest, src1, imm jalr ra, s1, label
Register

2.4 Data Types

The data types are 8-bit byte, 16-bit half word, 32-bit word and 64-bit double word. In ISA
there are different instructions present to manipulate these data types.

2.5 Addressing Modes

RV32G uses a byte addressable memory model with 32-bit address and little endian byte
numbering. As it is a load-store architecture, all references between memory and GPRs
are through loads or stores. The only data addressing mode in RV32G ISA is through
displacement. The base address is saved in some register and immediate offset is used to
address memory. For example if a words is to be fetched from address 1000, we will save this
address in some register say s0, and load the value into s1 through “lw s1, 0(s0)”. Similarly
for fetching the next word “lw s1, 4(s0)” and so on.

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 3 RISC-V Assembly
In this lab we will deal with RISC-V assembly. It is a convention to end assembly program
files with .s extension. To run RISC-V assembly we will use Venus simulator developed by
UC Berkeley.

3.1 Venus
Venus is a RISC-V (32-bit address space) instruction set simulator build for education pur-
pose available online here2
Follow the given instructions to properly use the simulator.
• Editor tab is for writing assembly code.
• Programs start at the first line regardless of the label. That means, the main function
must be put first.
• Once Venus is loaded into your browser, don’t refresh the page. You may lose your
code.
• When you are done editing, click the “Simulator” tab to prepare for execution.
• The right pannel in simulator shows the contents of general purpose registers and
memory.
• The rest is for you to explore.

3.2 Writing Assembly Programs

Write the following program in the Venus editor. Click on the “Simulator” tab, click “As-
semble & Simulate from Editor”, click “Run” to execute the whole program at once or click
“Step” to execute instructions one by one. See the output on the console below.
1 . text # Code Segment
2 . g l o b l main # d e c l a r i n g main a s g l o b a l
3 main : # main f u n c t i o n s t a r t s
4 a d d i a0 , z e r o , 4 # l o a d 4 i n r e g a0
5 la a1 , msg # l o a d a d d r e s s o f msg i n a1
6 ecall
7
8 end : # end o f program
9 a d d i a0 , z e r o , 10 # l o a d 10 i n a0
10 ecall
11
12 . data # data segment
13
14 msg : . a s c i i z ” H e l l o World ! ”
In the above program, “#” indicate comment, “.text”, “.globl”, etc are assembler directives,
“main” and “msg” are labels and ecall is environment call.
2
https://thaumicmekanism.github.io/venus/

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3.3 Memory Allocation
When a program is run, the operating system creates specialized memory segments in the
main memory specific to that program.
Generally, four segments are created,

1. Text Segment: The part of memory where instructions (code) is stored.

2. Data (Static) Segment: Where static data is stored.

3. Stack: Grows downward, stores local data.

4. Heap: Grows upward, stores dynamic data.

3.4 Assembler Directives

These are not part of the code. They help assembler to identify different parts of the program.

Directive Function
.data Store subsequent items in the static segment at the next available address.
.text Store subsequent instructions in the text segment at the next available address.
.byte Store listed values as 8-bit bytes.
.asciiz Store subsequent string in the data segment and add null-terminator.
.word Store listed values as unaligned 32-bit words.
.globl Makes the given label global.

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3.5 Environment Call
These are calls to the operating system requesting specific services. Generally they are
associated with I/O. To issue an environment call we load register a0 with specific ecall
code.

code (a0) Name Description

1 print int prints integer in a1
4 print string prints the null-terminated string whose address is in a1
9 sbrk allocates a1 bytes on the heap, returns pointer to start in a0
10 exit ends the program
11 print character prints ASCII character in a1

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 4 Lab Tasks
4.1 Task A
Update the displacement in instructions “ lb dest, displacement(base) ” in the code
given below such that the program prints “SURPRISE”. You are not allowed to change
anything else in the code.
1 . data
2 . byte 7 3 , 4 9 , 5 6 , 85
3 n: . word 1 2 2 , 8 3 , 5 5 , 9 8 , 8 0
4 . a s c i i z ”R”
5 . byte 1 1 4 , 6 9
6 . text
7 . g l o b l main
8 main :
9 la s0 , n
10 a d d i a0 , z e r o , 11
11 lb a1 , 4( s0 )
12 ecall
13 lb a1 , 8( s0 )
14 ecall
15 lb a1 , 12( s0 )
16 ecall
17 lb a1 , 0( s0 )
18 ecall
19 lb a1 , 22( s0 )
20 ecall
21 lb a1 , 4( s0 )
22 ecall
23 lb a1 , 23( s0 )
24 ecall
25 lb a1 , 16( s0 )
26 ecall
27 end :
28 a d d i a0 , z e r o , 10
29 ecall

4.1.1 Answer the given questions

1. What does the line 10 specify in the above program?

2. What is present at a displacement 21 bytes from n?

4.2 Task B
Complete the .text section of program given below, compute the following algebraic equation
and place your result in register a1. Your code must not exceed 20 lines, no register other
than a1, a2, a3, a4, a5 should be used and you are allowed to use variants of addition,
subtraction, shift, load and store instructions only.
Z = (A + B ∗ 8) − {(C + D)/4 + E ∗ 2} + {A/2 − D + (B − E)}

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 1 . data
2 A: . word 240
3 B: . word 50
4 C: . word 80
5 D: . word 32
6 E: . word 100
7 . text
8 . g l o b l main
9 main :
10 #−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
11 # Your Code Here
12 #−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
13
14 a d d i a0 , z e r o , 1 # p r i n t i n t e g e r
15 ecall
16 end :
17 a d d i a0 , z e r o , 10
18 ecall

4.3 Task C
Pseudo-instructions are made to create ease for assembly programmers. RISC-V ISA offers
some standard pseudo-instruction which can be used in Venus. Each pseudo-instruction can
be mapped to basic assembly instructions which is done behind the curtains by the assembler.
Write the basic assembly instructions to which the following pseudo-instructions are mapped.
You can take help from RISC-V Reference Card and RISC-V ISA Manual3

1. load address (la)

Loads absolute address in destination register.
la dest, symbol

2. load immediate (li)

Loads immediate value directly to a register.
li dest, imm

3. set if equal to zero (seqz)

If operand register is equal to zero, loads 1 in destination register else loads zero.
seqz dest, src1

4. negate (neg)
Loads destination register with 2’s complement of source.
neg dest, src1

5. move (mv)
Move data from one register to another
mv dest, src1

3
https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf