ABOUT THE I2C BUS

HISTORICAL BACKGROUND
The I2C bus was developed in the early 1980's by Philips semiconductors.
Its purpose was to provide an easy way to connect a CPU to peripheral chips in a
TV-set.
Normal Computer systems use ByteWide buses to accomplish this task. This
result in lots of copper tracks on PCB's to route the Address and datalines. Not to
mention a bunch of address decoders and glue logic to connect everything. In
mass production items such as TV-sets, VCR's and audio equipment this is not
acceptable. Furthermore lots of control lines implies that the systems is more
susceptible to disturbances by EMC and ESD. The research done by Philips Labs in
Eindhoven (The Netherlands) resulted in a 2 wire communication bus called the
I2C bus.
I2C is an acronym for Inter-IC bus. Its name literally explains it's purpose: to
provide a communication link between Integrated Circuits.
Nowadays the extent of the bus goes much further than Audio and Video
equipment. The bus is generally accepted in industry. Offspring like D2B and
ACCESS bus find their ways into computer peripherals like keyboards, mice,
printers, monitors, etc. The I2C BUs has been adopted by several leading chip
manufacturers like Xicor, SGS-Thomson, Siemens, Intel, TI, Maxim, Atmel, and
Analog Devices.




I2C BUS PROTOCOL
The BUS physically consists of 2 active wires and a ground connection. The
active wires, SDA and SCL, are both bidirectional. Where SDA is the Serial DAta
line and SCL is the Serial CLock line.
Every component hooked up to the bus has its own unique address
whether it is a CPU, LCD driver, memory, or complex function chip. Each of these
chips can act as a receiver and/or transmitter depending on its functionality.
Obviously an LCD driver is only a receiver, while a memory or I/O chip can both be
transmitter and receiver. Furthermore there may be one or more BUS MASTER's.
The BUS MASTER is the chip issuing the commands on the BUS. In the I2C
protocol specification it is stated that the IC that initiates a data transfer on the
bus is considered the BUS MASTER. At that time all the others are regarded to as
the BUS SLAVEs.
As mentioned before, the IC bus is a Multi-MASTER BUS. This means that
more than one IC capable of initiating data transfer can be connected to it. As
MASTERs are generally microcomputers let's take a look at a general 'inter-IC
chat' on the bus.

FEATURES
Only two bus lines are required: a serial data line (SDA) and a serial clock
line (SCL).
There is exits synchronous communication where clock frequency is
maintained by the master controller.



THE I2C-BUS BENEFITS DESIGNERS AND MANUFACTURERS
In consumer electronics, telecommunications and industrial electronics,
there are often many similarities between seemingly unrelated designs. For
example, nearly every system includes:
Some intelligent control, usually a single-chip microcontroller.
General-purpose circuits like LCD drivers, remote I/O ports, RAM, EEPROM,
or data converters.
Application-oriented circuits such as digital tuning and signal processing
circuits for radio and video systems, or DTMF generators for telephones
with tone dialling.
To exploit these similarities to the benefit of both systems designers and
equipment manufacturers, as well as to maximize hardware efficiency and circuit
simplicity, Philips developed a simple bi-directional 2-wire bus for efficient inter-
IC control. This bus is called the Inter IC or I2C-bus. At present, Philips IC range
includes more than 150 CMOS and bipolar I2C-bus compatible types for
performing functions in all three of the previously mentioned categories. All I2C
bus compatible devices incorporate an on-chip interface which allows them to
communicate directly with each other via the I2C-bus. This design concept solves
the many interfacing problems encountered when designing digital control
circuits.
Here are some of the features of the I2C-bus:
Only two bus lines are required; a serial data line (SDA) and a serial clock
line (SCL).
Each device connected to the bus is software addressable by a unique
address and simple master/slave relationships exist at all times; masters
can operate as master-transmitters or as master-receivers.
Its a true multi-master bus including collision detection and arbitration to
prevent data corruption if two or more masters simultaneously initiate data
transfer.
Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100
kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, or up to 3.4
Mbit/s in the High-speed mode.
On-chip filtering rejects spikes on the bus data line to preserve data
integrity.
The number of ICs that can be connected to the same bus is limited only by
a maximum bus capacitance of 400 pF.
Figure 1 shows two examples of I2C-bus applications.

DESIGNER BENEFITS
I2C-bus compatible ICs allow a system design to rapidly progress directly
from a functional block diagram to a prototype. Moreover, since they clip
directly onto the I2C-bus without any additional external interfacing, they allow a
prototype system to be modified or upgraded simply by clipping or unclipping
ICs to or from the bus. Here are some of the features of I2C-bus compatible ICs
which are particularly attractive to designers:
Functional blocks on the block diagram correspond with the actual ICs;
designs proceed rapidly from block diagram to final schematic.
No need to design bus interfaces because the I2C-bus interface is already
integrated on-chip.
Integrated addressing and data-transfer protocol allow systems to be
completely software-defined.
The same IC types can often be used in many different applications.
Design-time reduces as designers quickly become familiar with the
frequently used functional blocks represented by I2C-bus compatible ICs.
ICs can be added to or removed from a system without affecting any other
circuits on the bus.
Fault diagnosis and debugging are simple; malfunctions can be immediately
traced.
Software development time can be reduced by assembling a library of
reusable software modules.
In addition to these advantages, the CMOS ICs in the I2C-bus compatible
range offer designers special features which are particularly attractive for
portable equipment and battery-backed systems.

They all have:
Extremely low current consumption.
High noise immunity.
Wide supply voltage range.
Wide operating temperature range.

MANUFACTURER BENEFITS
I2C-bus compatible ICs dont only assist designers, they also give a wide
range of benefits to equipment manufacturers because:
The simple 2-wire serial I2C-bus minimizes interconnections so ICs have
fewer pins and there are not so many PCB tracks; result - smaller and less
expensive PCBs
The completely integrated I2C-bus protocol eliminates the need for address
decoders and other glue logic
The multi-master capability of the I2C-bus allows rapid testing and
alignment of end-user equipment via external connections to an assembly-
line
The availability of I2C-bus compatible ICs in SO (small outline), VSO (very
small outline) as well as DIL packages reduces space requirements even
more.
These are just some of the benefits. In addition, I2C-bus compatible ICs
increase system design flexibility by allowing simple construction of equipment
variants and easy upgrading to keep designs up-to-date. In this way, an entire
family of equipment can be developed around a basic model. Upgrades for new
equipment, or enhanced-feature models (i.e. extended memory, remote control,
etc.) can then be produced simply by clipping the appropriate ICs onto the bus. If
a larger ROM is needed, its simply a matter of selecting a micro-controller with a
larger ROM from our comprehensive range. As new ICs supersede older ones, its
easy to add new features to equipment or to increase its performance by simply
unclipping the outdated IC from the bus and clipping on its successor.

INTRODUCTION TO THE I2C-BUS SPECIFICATION
For 8-bit oriented digital control applications, such as those requiring
microcontrollers, certain design criteria can be established:
A complete system usually consists of at least one microcontroller and
other peripheral devices such as memories and I/O expanders
The cost of connecting the various devices within the system must be
minimized
A system that performs a control function doesnt require high-speed data
transfer
Overall efficiency depends on the devices chosen and the nature of the
interconnecting bus structure.
To produce a system to satisfy these criteria, a serial bus structure is
needed. Although serial buses dont have the throughput capability of parallel
buses, they do require less wiring and fewer IC connecting pins. However, a bus is
not merely an interconnecting wire, it embodies all the formats and procedures
for communication within the system.
Devices communicating with each other on a serial bus must have some
form of protocol which avoids all possibilities of confusion, data loss and blockage
of information. Fast devices must be able to communicate with slow devices. The
system must not be dependent on the devices connected to it, otherwise
modifications or improvements would be impossible. A procedure has also to be
devised to decide which device will be in control of the bus and when. And, if
different devices with different clock speeds are connected to the bus, the bus
clock source must be defined. All these criteria are involved in the specification of
the I2C-bus.

THE I2C-BUS CONCEPT
The I2C-bus supports any IC fabrication process (NMOS, CMOS, bipolar).
Two wires, serial data (SDA) and serial clock (SCL), carry information between the
devices connected to the bus. Each device is recognized by a unique address
(whether its a microcontroller, LCD driver, memory or keyboard interface) and
can operate as either a transmitter or receiver, depending on the function of the
device. Obviously an LCD driver is only a receiver, whereas a memory can both
receive and transmit data. In addition to transmitters and receivers, devices can
also be considered as masters or slaves when performing data transfers (see
Table 1). A master is the device which initiates a data transfer on the bus and
generates the clock signals to permit that transfer. At that time, any device
addressed is considered a slave.

The I2C-bus is a multi-master bus. This means that more than one device
capable of controlling the bus can be connected to it. As masters are usually
micro-controllers, lets consider the case of a data transfer between two
microcontrollers connected to the I2C-bus (see Fig.2). This highlights the master
slave and receiver-transmitter relationships to be found on the I2C-bus. It should
be noted that these relationships are not permanent, but only depend on the
direction of data transfer at that time. The transfer of data would proceed as
follows:
1. Suppose microcontroller A wants to send information to microcontroller B:
Microcontroller A (master), addresses microcontroller B (slave)
Microcontroller A (master-transmitter), sends data to microcontroller
B (slave- receiver)
Microcontroller A terminates the transfer
2. If microcontroller A wants to receive information from microcontroller B:
Microcontroller A (master) addresses microcontroller B (slave)
Microcontroller A (master- receiver) receives data from
microcontroller B (slave- transmitter)
Microcontroller A terminates the transfer.
Even in this case, the master (microcontroller A) generates the timing and
terminates the transfer.
The possibility of connecting more than one microcontroller to the I2C-bus
means that more than one master could try to initiate a data transfer at the same
time. To avoid the chaos that might ensue from such an event - an arbitration
procedure has been developed. This procedure relies on the wired-AND
connection of all I2C interfaces to the I2C-bus.
If two or more masters try to put information onto the bus, the first to
produce a one when the other produces a zero will lose the arbitration. The
clock signals during arbitration are a synchronized combination of the clocks
generated by the masters using the wired-AND connection to the SCL line (for
more detailed information concerning arbitration see Section 8).

Generation of clock signals on the I2C-bus is always the responsibility of
master devices; each master generates its own clock signals when transferring
data on the bus. Bus clock signals from a master can only be altered when they
are stretched by a slow-slave device holding-down the clock line, or by another
master when arbitration occurs.

GENERAL CHARACTERISTICS
Both SDA and SCL are bi-directional lines, connected to a positive supply
voltage via a current-source or pull-up resistor (see Fig.3). When the bus is free,
both lines are HIGH. The output stages of devices connected to the bus must have
an open-drain or open-collector to perform the wired-AND function. Data on the
I2C-bus can be transferred at rates of up to 100 kbit/s in the Standard-mode, up
to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode. The
number of interfaces connected to the bus is solely dependent on the bus
capacitance limit of 400 pF. For information on High-speed mode master devices,
see Section 13.































I2C COMMUNICATION PROCEDURE
One IC that wants to talk to another must:
1. Wait until it sees no activity on the I
2
C bus. SDA and SCL are both high. The
bus is 'free'.
2. Put a message on the bus that says 'its mine' - I have STARTED to use the
bus. All other ICs then LISTEN to the bus data to see whether they might be
the one who will be called up (addressed).
3. Provide on the CLOCK (SCL) wire a clock signal. It will be used by all the ICs
as the reference time at which each bit of DATA on the data (SDA) wire will
be correct (valid) and can be used. The data on the data wire (SDA) must be
valid at the time the clock wire (SCL) switches from 'low' to 'high' voltage.
4. Put out in serial form the unique binary 'address' (name) of the IC that it
wants to communicate with.
5. Put a message (one bit) on the bus telling whether it wants to SEND or
RECEIVE data from the other chip. (The read/write wire is gone!)
6. Ask the other IC to ACKNOWLEDGE (using one bit) that it recognized its
address and is ready to communicate.
7. After the other IC acknowledges all is OK, data can be transferred.
8. The first IC sends or receives as many 8-bit words of data as it wants. After
every 8-bit data word the sending IC expects the receiving IC to
acknowledge the transfer is going OK.
9. When all the data is finished the first chip must free up the bus and it does
that by a special message called 'STOP'. It is just one bit of information
transferred by a special 'wiggling' of the SDA/SCL wires of the bus.
Originally, the I
2
C bus was designed to link a small number of devices on a
single card, such as to manage the tuning of a car radio or TV. The maximum
allowable capacitance was set at 400 pF to allow proper rise and fall times for
optimum clock and data signal integrity with a top speed of 100 kbps. In 1992 the
standard bus speed was increased to 400 kbps, to keep up with the ever-
increasing performance requirements of new ICs. The 1998 I
2
C specification,
increased top speed to 3.4 Mbits/sec. All I
2
C devices are designed to be able to
communicate together on the same two-wire bus and system functional
architecture is limited only by the imagination of the design

I2C BUS SOFTWARE
Simple procedures that allow communication to start, to achieve data
transfer, and to stopDescribed in the Philips protocol (rules)Message
serial data format is very simpleOften generated by simple software in
general purpose microDedicated peripheral devices contain a complete
interfaceMulti-master capable with arbitration feature.
Each IC on the bus is identified by its own address codeAddress has to be
unique.
The master IC that initiates communication provides the clock signal (SCL)
There is a maximum clock frequency but NO MINIMUM SPEED.

HOW ARE THE CONNECTED DEVICES RECOGNIZED?
Master device polls used a specific unique identification or addresses
that the designer has included in the system
Devices with Master capability can identify themselves to other specific
Master devices and advise their own specific address and functionality
Allows designers to build plug and play systemsBus speed can be
different for each device, only a maximum limit
Only two devices exchange data during one conversation


Any device with the ability to initiate messages is called a master. It might
know exactly what other chips are connected, in which case it simply addresses
the one it wants, or there might be optional chips and it then checks whats there
by sending each address and seeing whether it gets any response (acknowledge).

I2C BUS TERMINOLOGY
Transmitter - the device that sends data to the bus. A transmitter can either be a
device that puts data on the bus of its own accord (a master-transmitter), or in
response to a request from data from another devices (a slave-transmitter).
Receiver - the device that receives data from the bus.
Master - the component that initializes a transfer, generates the clock signal, and
terminates the transfer. A master can be either a transmitter or a receiver.
Slave - the device addressed by the master. A slave can be either receiver or
transmitter.
Multi-master - the ability for more than one master to co-exist on the bus at the
same time without collision or data loss.
Arbitration - the prearranged procedure that authorizes only one master at a
time to take control of the bus.
Synchronization - the prearranged procedure that synchronizes the clock signals
provided by two or more masters.
SDA - data signal line (Serial DAta)
SCL - clock signal line (Serial CLock)

I2C ADDRESS
Each device is addressed individually by software
Unique address per device: fully fixed or with a programmable part through
hardware pin(s)
Programmable pins mean that several same devices can share the same
bus
Address allocation coordinated by the I2C-bus committee
112 different types of devices max with the 7-bit format (others reserved)

START AND STOP CONDITIONS
Within the procedure of the I
2
C bus, unique situations arise which are
defined as START (S) and STOP (P) conditions.
START: A HIGH to LOW transition on the SDA line while SCL is HIGH
STOP: A LOW to HIGH transition on the SDA line while SCL is HIGH
The master always generates START and STOP conditions. The bus is
considered to be busy after the START condition. The bus is considered to be free
again a certain time after the STOP condition. The bus stays busy if a repeated
START (Sr) is generated instead of a STOP condition. In this respect, the START (S)
and repeated START (Sr) conditions are functionally identical. The S symbol will be
used as a generic term to represent both the START and repeated START
conditions, unless Sr is particularly relevant. However, microcontrollers with no
such interface have to sample the SDA line at least twice per clock period to sense
the transition.

LIMITATION OF I2C PROTOCOL
Synchronization of the clock is required.
Data is transferred serially hence the system becomes slow.
Master slave configuration is strictly maintained.
Slaves cannot transfer data directly among each other as data transfer has
to take place through master itself.