Ddr4 Sdram Lrdimm: MTA72ASS8G72LZ - 64GB Features

64GB (x72, ECC, QR) 288-Pin DDR4 LRDIMM
Features
DDR4 SDRAM LRDIMM

MTA72ASS8G72LZ – 64GB
Features Figure 1: 288-Pin LRDIMM (MO-309, R/C-E2)

Module height: 31.25mm (1.23in)
• DDR4 functionality and operations supported as
defined in the component data sheet
• 288-pin, command/address/control-registered, da-
ta-buffered, load-reduced dual in-line memory
module (LRDIMM)
• Fast data transfer rates: PC4-2933, PC4-2666, or
PC4-2400 Figure 2: 288-Pin LRDIMM (MO-309, R/C-E2)
• 64GB (8 Gig x 72)
Module height: 31.25mm (1.23in)
• VDD = 1.20V (NOM)
• VPP = 2.5V (NOM)
• VDDSPD = 2.5V (NOM)
• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
Options Marking
• Low-power auto self refresh (LPASR) • Operating temperature
• On-die internal, adjustable V REFDQ generation – Commercial (0°C ≤ T OPER ≤ 95°C) None
• Quad-rank, using 16Gb TwinDie DDR4 • Package
• On-board I2C temperature sensor with integrated – 288-pin DIMM (halogen-free) Z
serial presence-detect (SPD) EEPROM • Frequency/CAS latency
• 16 internal banks; 4 groups of 4 banks each – 0.682ns @ CL = 21 (DDR4-2933) -2G9
– 0.75ns @ CL = 19 (DDR4-2666) -2G6
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
– 0.83ns @ CL = 17 (DDR4-2400) -2G3
via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Multiplexed command and address bus
• Terminated control, command, and address bus
Table 1: Key Timing Parameters
Data Rate (MT/s)

CL =
Speed
Grade
20\ 18\ 16\ 14\ 12\ 10\ tRCD tRP tRC
PC4- 24 22 21 19 17 15 13 11 9 ns ns ns
-3G2 3200 3200, 3200, 2933 2666\ 2400\ 2133\ 1866\ 1600\ 1333\ 13.75 13.75 45.75
2933 2933 2666 2400 2133 1866 1600 –
-2G9 2933 – 2933 2933 2666\ 2400\ 2133\ 1866\ 1600\ 1333\ 14.32 14.32 46.32
2666 2400 2133 1866 1600 – (13.75)1 (13.75)1 (45.75)1
CCMTD-1725822587-9934
ass72c8gx72lz.pdf - Rev. G 8/19 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Features
Table 1: Key Timing Parameters (Continued)
Data Rate (MT/s)

CL =
Speed
Grade
20\ 18\ 16\ 14\ 12\ 10\ tRCD tRP tRC
PC4- 24 22 21 19 17 15 13 11 9 ns ns ns
-2G6 2666 – – – 2666\ 2400\ 2133\ 1866\ 1600\ 1333\ 14.25 14.25 46.25
2666 2400 2133 1866 1600 – (13.75)1 (13.75)1 (45.75)1
-2G3 2400 – – – – 2400\ 2133\ 1866\ 1600\ 1333\ 14.16 14.16 46.16
2400 2133 1866 1600 – (13.75)1 (13.75)1 (45.75)1
-2G1 2133 – – – – – 2133\ 1866\ 1600\ 1333\ 14.06 14.06 47.06
2133 1866 1600 1333 (13.5)1 (13.5)1 (46.5)1
Note: 1. Down-bin timing, refer to component data sheet Speed Bin Tables for details.
Table 2: Addressing
Parameter 64GB
Row address 128K A[16:0]
Column address 1K A[9:0]
Device bank group address 4 BG[1:0]
Device bank address per group 4 BA[1:0]
Device configuration 16Gb TwinDie (4 Gig x 4), 16 banks
Module rank address 4 CS_n[3:0]
Table 3: Part Numbers and Timing Parameters – 64GB Modules

Base device: MT40A4G4,1 16Gb TwinDie DDR4 SDRAM
Module Module Memory Clock/ Clock Cycles
Part Number2 Density Configuration Bandwidth Data Rate (CL-nRCD-nRP)
MTA72ASS8G72LZ-2G9__ 64GB 8 Gig x 72 23.47 GB/s 0.682ns/2933 MT/s 21-21-21
Notes: 1. The data sheet for the base device can be found on micron.com.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MTA72ASS8G72LZ-2G9J1.
CCMTD-1725822587-9934
Important Notes and Warnings
Important Notes and Warnings

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CCMTD-1725822587-9934
Pin Assignments
Pin Assignments
Table 4: Pin Assignments
288-Pin DDR4 LRDIMM Front 288-Pin DDR4 LRDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 NC 37 VSS 73 VDD 109 Vss 145 NC 181 DQ29 217 VDD 253 DQ41
2 VSS 38 DQ24 74 CK0_t 110 DQS14_t 146 VREFCA 182 VSS 218 CK1_t 254 VSS
3 DQ4 39 VSS 75 CK0_c 111 DQS14_c 147 VSS 183 DQ25 219 CK1_c 255 DQS5_c
4 VSS 40 DQS12_t 76 VDD 112 VSS 148 DQ5 184 VSS 220 VDD 256 DQS5_t
5 DQ0 41 DQS12-c 77 VTT 113 DQ46 149 VSS 185 DQS3_c 221 VTT 257 VSS
6 VSS 42 VSS 78 EVENT_n 114 VSS 150 DQ1 186 DQS3_t 222 PARITY 258 DQ47
7 DQS9_t 43 DQ30 79 A0 115 DQ42 151 VSS 187 VSS 223 VDD 259 VSS
8 DQS09_c 44 VSS 80 VDD 116 VSS 152 DQS0_c 188 DQ31 224 BA1 260 DQ43
9 VSS 45 DQ26 81 BA0 117 DQ52 153 DQS0_t 189 VSS 225 A10_AP 261 VSS
10 DQ6 46 VSS 82 RAS_n/ 118 VSS 154 VSS 190 DQ27 226 VDD 262 DQ53
A16
11 VSS 47 CB4 83 VDD 119 DQ48 155 DQ7 191 VSS 227 NC 263 VSS
12 DQ2 48 VSS 84 S0_n 120 VSS 156 VSS 192 CB5 228 WE_n/ 264 DQ49
A14
13 VSS 49 CB0 85 VDD 121 DQS15_t 157 DQ3 193 VSS 229 VDD 265 VSS
14 DQ12 50 VSS 86 CAS_n/ 122 DQS15_c 158 VSS 194 CB1 230 NC 266 DQS6_c
A15
15 VSS 51 DQS17_t 87 ODT0 123 VSS 159 DQ13 195 VSS 231 VDD 267 DQS6_t
16 DQ8 52 DQS17_c 88 VDD 124 DQ54 160 VSS 196 DQS8_c 232 A13 268 VSS
17 VSS 53 VSS 89 S1_n 125 VSS 161 DQ9 197 DQS8_t 233 VDD 269 DQ55
18 DQS10_t 54 CB6 90 VDD 126 DQ50 162 VSS 198 VSS 234 A17 270 VSS
19 DQS10_c 55 VSS 91 ODT1 127 VSS 163 DQS1_c 199 CB7 235 NF 271 DQ51
20 VSS 56 CB2 92 VDD 128 DQ60 164 DQS1_t 200 VSS 236 VDD 272 VSS
21 DQ14 57 VSS 93 S2_n 129 VSS 165 VSS 201 CB3 237 S3_n 273 DQ61
22 VSS 58 RESET_n 94 VSS 130 DQ56 166 DQ15 202 VSS 238 SA2 274 VSS
23 DQ10 59 VDD 95 DQ36 131 VSS 167 VSS 203 CKE1 239 VSS 275 DQ57
24 VSS 60 CKE0 96 VSS 132 DQS16_t 168 DQ11 204 VDD 240 DQ37 276 VSS
25 DQ20 61 VDD 97 DQ32 133 DQS16_c 169 VSS 205 NC 241 VSS 277 DQS7_c
26 VSS 62 ACT_n 98 VSS 134 VSS 170 DQ21 206 VDD 242 DQ33 278 DQS7_t
27 DQ16 63 BG0 99 DQS13_t 135 DQ62 171 VSS 207 BG1 243 VSS 279 VSS
28 VSS 64 VDD 100 DQS13_c 136 VSS 172 DQ17 208 ALERT_n 244 DQS4_c 280 DQ63
29 DQS11_t 65 A12 101 VSS 137 DQ58 173 VSS 209 VDD 245 DQS4_t 281 VSS
30 DQS11_c 66 A9 102 DQ38 138 VSS 174 DQS2_c 210 A11 246 VSS 282 DQ59
31 VSS 67 VDD 103 Vss 139 SA0 175 DQS2_t 211 A7 247 DQ39 283 VSS
32 DQ22 68 A8 104 DQ34 140 SA1 176 VSS 212 VDD 248 VSS 284 VDDSPD
33 VSS 69 A6 105 VSS 141 SCL 177 DQ23 213 A5 249 DQ35 285 SDA
34 DQ18 70 VDD 106 DQ44 142 VPP 178 VSS 214 A4 250 VSS 286 VPP
35 VSS 71 A3 107 VSS 143 VPP 179 DQ19 215 VDD 251 DQ45 287 VPP
36 DQ28 72 A1 108 DQ40 144 NC 180 VSS 216 A2 252 VSS 288 VPP
CCMTD-1725822587-9934
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for DDR4
modules. All pins listed may not be supported on this module. See Functional Block Di-
agram for pins specific to this module.
Table 5: Pin Descriptions
Symbol Type Description

Ax Input Address inputs: Provide the row address for ACTIVATE commands and the column address for
READ/WRITE commands in order to select one location out of the memory array in the respec-
tive bank (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, and RAS_n/A16 have additional functions;
see individual entries in this table). The address inputs also provide the op-code during the
MODE REGISTER SET command. A17 is only defined for x4 SDRAM.
A10/AP Input Auto precharge: A10 is sampled during READ and WRITE commands to determine whether an
auto precharge should be performed on the accessed bank after a READ or WRITE operation
(HIGH = auto precharge; LOW = no auto precharge). A10 is sampled during a PRECHARGE com-
mand to determine whether the precharge applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank
addresses.
A12/BC_n Input Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if burst
chop (on-the-fly) will be performed (HIGH = no burst chop; LOW = burst chopped). See Com-
mand Truth Table in the DDR4 component data sheet.
ACT_n Input Command input: ACT_n defines the ACTIVATE command being entered along with CS_n. The
input into RAS_n/A16, CAS_n/A15, and WE_n/A14 are considered as row address A16, A15, and
A14. See Command Truth Table.
BAx Input Bank address inputs: Define the bank (with a bank group) to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be
accessed during a MODE REGISTER SET command.
BGx Input Bank group address inputs: Define the bank group to which a REFRESH, ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be
accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8 configura-
tions. x16-based SDRAM only has BG0.
C0, C1, C2 Input Chip ID: These inputs are used only when devices are stacked; that is, 2H, 4H, and 8H stacks for
(RDIMM/LRDIMM on- x4 and x8 configurations using through-silicon vias (TSVs). These pins are not used in the x16
ly) configuration. Some DDR4 modules support a traditional DDP package, which uses CS1_n,
CKE1, and ODT1 to control the second die. All other stack configurations, such as a 4H or 8H,
are assumed to be single-load (master/slave) type configurations where C0, C1, and C2 are used
as chip ID selects in conjunction with a single CS_n, CKE, and ODT. Chip ID is considered part of
the command code.
CKx_t Input Clock: Differential clock inputs. All address, command, and control input signals are sampled
CKx_c on the crossing of the positive edge of CK_t and the negative edge of CK_c.
CKEx Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, device
input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and
SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is
asynchronous for self refresh exit. After VREFCA has become stable during the power-on and ini-
tialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE
must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK_t,
CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE
and RESET_n) are disabled during self refresh.
CSx_n Input Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides external
rank selection on systems with multiple ranks. CS_n is considered part of the command code
(CS2_n and CS3_n are not used on UDIMMs).
CCMTD-1725822587-9934
Pin Descriptions
Table 5: Pin Descriptions (Continued)

ODTx Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the
DDR4 SDRAM. When enabled, ODT (RTT) is applied only to each DQ, DQS_t, DQS_c, DM_n/
DBI_n/TDQS_t, and TDQS_c signal for x4 and x8 configurations (when the TDQS function is ena-
bled via the mode register). For the x16 configuration, RTT is applied to each DQ, DQSU_t,
DQSU_c, DQSL_t, DQSL_c, UDM_n, and LDM_n signal. The ODT pin will be ignored if the mode
registers are programmed to disable RTT.
PARITY Input Parity for command and address: This function can be enabled or disabled via the mode
register. When enabled in MR5, the DRAM calculates parity with ACT_n, RAS_n/A16, CAS_n/A15,
WE_n/A14, BG[1:0], BA[1:0], A[16:0]. Input parity should be maintained at the rising edge of the
clock and at the same time as command and address with CS_n LOW.
RAS_n/A16 Input Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n) define the com-
CAS_n/A15 mand and/or address being entered and have multiple functions. For example, for activation
WE_n/A14 with ACT_n LOW, these are addresses like A16, A15, and A14, but for a non-activation com-
mand with ACT_n HIGH, these are command pins for READ, WRITE, and other commands de-
fined in Command Truth Table.
RESET_n CMOS Input Active LOW asynchronous reset: Reset is active when RESET_n is LOW and inactive when RE-
SET_n is HIGH. RESET_n must be HIGH during normal operation.
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range
SAx Input
on the I2C bus.
Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to
SCL Input
and from the temperature sensor/SPD EEPROM on the I2C bus.
DQx, CBx I/O Data input/output and check bit input/output: Bidirectional data bus. DQ represents
DQ[3:0], DQ[7:0], and DQ[15:0] for the x4, x8, and x16 configurations, respectively. If cyclic re-
dundancy checksum (CRC) is enabled via the mode register, the CRC code is added at the end of
the data burst. Any one or all of DQ0, DQ1, DQ2, or DQ3 may be used for monitoring of inter-
nal VREF level during test via mode register setting MR[4] A[4] = HIGH; training times change
when enabled.
DM_n/DBI_n/ I/O Input data mask and data bus inversion: DM_n is an input mask signal for write data. Input
TDQS_t (DMU_n, data is masked when DM_n is sampled LOW coincident with that input data during a write ac-
DBIU_n), (DML_n/ cess. DM_n is sampled on both edges of DQS. DM is multiplexed with the DBI function by the
DBIl_n) mode register A10, A11, and A12 settings in MR5. For a x8 device, the function of DM or TDQS
is enabled by the mode register A11 setting in MR1. DBI_n is an input/output identifying
whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/
output after inversion inside the DDR4 device and not inverted if DBI_n is HIGH. TDQS is only
supported in x8 SDRAM configurations (TDQS is not valid for UDIMMs).
SDA I/O Serial Data: Bidirectional signal used to transfer data in or out of the EEPROM or EEPROM/TS
combo device.
DQS_t I/O Data strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
DQS_c tered-aligned with write data. For x16 configurations, DQSL corresponds to the data on
DQSU_t DQ[7:0], and DQSU corresponds to the data on DQ[15:8]. For the x4 and x8 configurations, DQS
DQSU_c corresponds to the data on DQ[3:0] and DQ[7:0], respectively. DDR4 SDRAM supports a differen-
DQSL_t tial data strobe only and does not support a single-ended data strobe.
DQSL_c
ALERT_n Output Alert output: Possesses functions such as CRC error flag and command and address parity error
flag as output signal. If a CRC error occurs, ALERT_n goes LOW for the period time interval and
returns HIGH. If an error occurs during a command address parity check, ALERT_n goes LOW un-
til the on-going DRAM internal recovery transaction is complete. During connectivity test mode,
this pin functions as an input. Use of this signal is system-dependent. If not connected as signal,
ALERT_n pin must be connected to VDD on DIMMs.
EVENT_n Output Temperature event: The EVENT_n pin is asserted by the temperature sensor when critical tem-
perature thresholds have been exceeded. This pin has no function (NF) on modules without
temperature sensors.
CCMTD-1725822587-9934
Pin Descriptions
Table 5: Pin Descriptions (Continued)

TDQS_t Output Termination data strobe: When enabled via the mode register, the DRAM device enables the
TDQS_c same RTT termination resistance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c.
When the TDQS function is disabled via the mode register, the DM/TDQS_t pin provides the da-
(x8 DRAM-based ta mask (DM) function, and the TDQS_c pin is not used. The TDQS function must be disabled in
RDIMM only) the mode register for both the x4 and x16 configurations. The DM function is supported only in
x8 and x16 configurations. DM, DBI, and TDQS are a shared pin and are enabled/disabled by
mode register settings. For more information about TDQS, see the DDR4 DRAM component da-
ta sheet (TDQS_t and TDQS_c are not valid for UDIMMs).
VDD Supply Module power supply: 1.2V (TYP).
VPP Supply DRAM activating power supply: 2.5V –0.125V/+0.250V.
VREFCA Supply Reference voltage for control, command, and address pins.
VSS Supply Ground.
VTT Supply Power supply for termination of address, command, and control VDD/2.
VDDSPD Supply Power supply used to power the I2C bus for SPD.
RFU – Reserved for future use.
NC – No connect: No internal electrical connection is present.
NF – No function: May have internal connection present, but has no function.
CCMTD-1725822587-9934
DQ Map
DQ Map
Table 6: Component-to-Module DQ Map, Front
Component Component
Reference Component Module Pin Reference Component Module Pin
Number DQ Module DQ Number Number DQ Module DQ Number
U1 0 7 155 U2 0 15 166
1 5 148 1 13 159
2 6 10 2 14 21
3 4 3 3 12 14
U3 0 23 177 U4 0 31 188
1 21 170 1 29 181
2 22 32 2 30 43
3 20 25 3 28 36
U5 0 CB7 199 U7 0 39 247
1 CB5 192 1 37 240
2 CB6 54 2 38 102
3 CB4 47 3 36 95
U8 0 47 258 U9 0 55 269
1 45 251 1 53 262
2 46 113 2 54 124
3 44 106 3 52 117
U10 0 63 280 U12 0 2 12
1 61 273 1 1 150
2 62 135 2 3 157
3 60 128 3 0 5
U13 0 8 16 U14 0 16 27
1 10 23 1 18 34
2 9 161 2 17 172
3 11 168 3 19 179
U15 0 26 45 U16 0 CB2 56
1 25 183 1 CB1 194
2 27 190 2 CB3 201
3 24 38 3 CB0 49
U17 0 34 104 U18 0 42 115
1 32 97 1 40 108
2 35 249 2 43 260
3 33 242 3 41 253
U19 0 50 126 U20 0 56 130
1 48 119 1 58 137
2 51 271 2 57 275
3 49 264 3 59 282
CCMTD-1725822587-9934
DQ Map
Table 7: Component-to-Module DQ Map, Back
Component Component
Reference Component Module Pin Reference Component Module Pin
Number DQ Module DQ Number Number DQ Module DQ Number
U21 0 61 273 U22 0 53 262
1 63 280 1 55 269
2 60 128 2 52 117
3 62 135 3 54 124
U23 0 45 251 U24 0 37 240
1 47 258 1 39 247
2 44 106 2 36 95
3 46 113 3 38 102
U25 0 CB5 192 U26 0 29 181
1 CB7 199 1 31 188
2 CB4 47 2 28 36
3 CB6 54 3 30 43
U27 0 21 170 U28 0 13 159
1 23 177 1 15 166
2 20 25 2 12 14
3 22 32 3 14 21
U29 0 5 148 U30 0 58 137
1 7 155 1 56 130
2 4 3 2 59 282
3 6 10 3 57 275
U31 0 48 119 U32 0 40 108
1 50 126 1 42 115
2 49 264 2 41 253
3 51 271 3 43 260
U33 0 32 97 U34 0 CB1 194
1 34 104 1 CB2 56
2 33 242 2 CB0 49
3 35 249 3 CB3 201
U35 0 25 183 U36 0 18 34
1 26 45 1 16 27
2 24 38 2 19 179
3 27 190 3 17 172
U37 0 10 23 U38 0 1 150
1 8 16 1 2 12
2 11 168 2 0 5
3 9 161 3 3 157
CCMTD-1725822587-9934
Functional Block Diagram
Functional Block Diagram
Figure 3: Functional Block Diagram

CS0A, CS0B
CS1A, CS1B
CS2A, CS2B
CS3A, CS3B
Data Buffers CS2A CS0A CS3A CS1A Data Buffers CS2B CS0B CS3B CS1B
U11
DQS0_t DQS0_t DQS4_t DQS4_t
DQS0_c DQS0_c DQS4_c DQS4_c
CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS0 CS0A/B: Rank 0
DQS9_t DQ DQ DQS13_t DQ DQ
DQ0 DQ DQ DQ32 DQ DQ CS1 CS1A/B: Rank 1
DQS9_c DQS13_c
DQ1 DQ U12b DQ U12t DQ U38b DQ U38t DQ33 DQ U17b DQ U17t DQ U33b DQ U33t CS2 CS2A/B: Rank 2
U47 DQ2 DQ DQ DQ DQ U42 DQ34 DQ DQ DQ DQ
CS3 CS3A/B: Rank 3
DQ3 DQ DQ DQ DQ DQ35 DQ DQ DQ DQ R
DQ0 DQ32 BA[1:0] BA[1:0]A/B: DDR4 SDRAM
ZQ ZQ ZQ ZQ ZQ ZQ ZQ ZQ E
DQ1 DQ33 BG[1:0] BG[1:0]A/B: DDR4 SDRAM
DQS9_t
VSS VSS VSS VSS
DQS13_t
VSS VSS VSS VSS G
DQ2 DQ34 ACT_n ACTA/B: DDR4 SDRAM
DQ3 DQS9_c DQ35 DQS13_c I
CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c A[17,13:0] A[17,13:0]A/B: DDR4 SDRAM
DQ4
CS_n DQS_t DQS_c CS_n DQS_t DQS_c
DQ36
CS_n DQS_t DQS_c CS_n DQS_t DQS_c S
DQ4 DQ DQ DQ DQ DQ36 DQ DQ DQ DQ RAS_n/A16 RAS_n/A16A/B: DDR4 SDRAM
DQ5 DQ37 T
DQ5 DQ U1b DQ U1t DQ U29b DQ U29t DQ37 DQ U7b DQ U7t DQ U24b DQ U24t CAS_n/A15 CAS_n/A15A/B: DDR4 SDRAM
DQ6
DQ6 DQ DQ DQ DQ
DQ38
DQ38 DQ DQ DQ DQ WE_n/A14
E WE_n/A14A/B: DDR4 SDRAM
DQ7 DQ39 R
DQ7 DQ DQ DQ DQ DQ39 DQ DQ DQ DQ CKE0 CKE0A/B: Rank 0, Rank 2
ALERT_N ZQCAL ALERT_N ZQCAL
VSS
ZQ ZQ ZQ ZQ
VSS
ZQ ZQ ZQ ZQ CKE1 – CKE1A/B: Rank 1, Rank 3
VDD VDD
VSS VSS VSS VSS VSS VSS VSS VSS P
ODT0 ODT0A/B: Rank 0, Rank 2 tied to VSS
DQS1_t DQS1_t DQS5_t DQS5_t ODT1 L ODT1A/B: Rank 1, Rank 3 tied to VSS
DQS1_c DQS5_c
DQS1_c
CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c
DQS5_c
CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c PAR_IN L PARA/B: DDR4 SDRAM
DQS10_t DQ DQ DQS14_t DQ DQ C[2:0] – C[2:0]: DDR4 SDRAM
DQ8 DQ DQ DQ40 DQ DQ
DQS10_c DQS14_c B
DQ9 DQ U13b DQ U13t DQ U37b DQ U37t DQ41 DQ U18b DQ U18t DQ U32b DQ U32t ALERT_CONN_N ALERT_N: DDR4 SDRAM
U46 DQ10 DQ DQ DQ DQ U41 DQ42 DQ DQ DQ DQ U
DQ11 DQ DQ DQ DQ DQ43 DQ DQ DQ DQ SA0 F BCOM0: DATA BUFFERS
DQ8 ZQ ZQ ZQ ZQ
DQ40 ZQ ZQ ZQ ZQ
DQ9 VSS VSS VSS VSS DQ41 VSS VSS VSS VSS
SA1 F BCOM1: DATA BUFFERS
DQ10 DQS10_t DQ41 DQS14_t SA2 E BCOM2: DATA BUFFERS
DQ11 DQS10_c DQ43 DQS14_c SCL BCOM3: DATA BUFFERS
CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c
R
DQ12 DQ44 SDA
DQ12 DQ DQ DQ DQ DQ44 DQ DQ DQ DQ
DQ13 DQ45 BODT: DATA BUFFERS
DQ14
DQ13 DQ U2b DQ U2t DQ U28b DQ U28t DQ46
DQ45 DQ U8b DQ U8t DQ U23b DQ U23t C
DQ14 DQ DQ DQ46 DQ DQ BCKE: DATA BUFFERS
DQ15
DQ DQ
DQ47
DQ DQ O
DQ15 DQ DQ DQ DQ DQ47 DQ DQ DQ DQ VREFCA: DDR4 SDRAM
ALERT_N ZQCAL ALERT_N ZQCAL VREFCA_CONN N
ZQ ZQ ZQ ZQ ZQ ZQ ZQ ZQ BVREF: DATA BUFFERS
VDD VSS
VSS VSS VSS VSS
VDD VSS
VSS VSS VSS VSS
T
DQS2_t DQS6_t
R
DQS2_t DQS6_t
DQS2_c DQS6_c O CK0[A:D]_t
DDR4 SDRAM
DQS2_c DQS6_c
DQS11_t
CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c
DQS15_t
CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c L (U1–U5, U7–U15, U17–U38)
DQ16 DQ DQ DQ DQ DQ48 DQ DQ DQ DQ CK0t CK0[A:D]_c
DQS11_c DQS15_c
DQ17 DQ U14b DQ U14t DQ U36b DQ U36t DQ49 DQ U19b DQ U19t DQ U31b DQ U31t CK0c CKDB_c
U45 DQ18 DQ DQ DQ DQ U40 DQ50 DQ DQ DQ DQ DATA BUFFERS
DQ19 DQ DQ DQ DQ DQ51 DQ DQ DQ DQ (U39–U47)
DQ16 DQ48 CKDB_t
ZQ ZQ ZQ ZQ ZQ ZQ ZQ ZQ
DQ17 VSS VSS VSS VSS DQ49 VSS VSS VSS VSS
DQ18 DQS11_t DQ50 DQS15_t RESET_CONN_N QRST_N: DDR4 SDRAM
DQ19 DQS11_c DQ51 DQS15_c
DQ20 DQ52 ZQCAL
DQ21 DQ53 VSS
DQ22
DQ53 DQ U9b DQ U9t DQ U22b DQ U22t
DQ23 DQ55 CK1t
ALERT_N ZQCAL ALERT_N ZQCAL CK1c
VDD VSS VDD VSS
VSS VSS VSS VSS VSS VSS VSS VSS
DQS3_t DQS3_t DQS7_t DQS7_t
DQS3_c DQS3_c DQS7_c DQS7_c
DQS12_t DQ DQ DQS16_t DQ DQ
DQ24 DQ DQ DQ56 DQ DQ
DQS12_c DQS16_c
DQ25 DQ U15b DQ U15t DQ U35b DQ U35t DQ57 DQ U20b DQ U20t DQ U30b DQ U30t U6
U44 DQ26 DQ DQ DQ DQ U39 DQ58 DQ DQ DQ DQ
SPD EEPROM/
DQ24 ZQ ZQ ZQ ZQ
DQ56 ZQ ZQ ZQ ZQ SCL Temperature SDA
DQ25 VSS VSS VSS VSS DQ57 VSS VSS VSS VSS sensor
DQ26 DQS12_t DQ58 DQS16_t
EVT A0 A1 A2
DQ27 DQS12_c DQ59 DQS16_c
CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c SA0 SA1 SA2
DQ28 DQ60
DQ29 DQ61 EVENT_N
DQ30
DQ61 DQ U10b DQ U10t DQ U21b DQ U21t
DQ31 DQ63
ALERT_N ZQCAL ALERT_N ZQCAL
VDD VSS VDD VSS
VSS VSS VSS VSS VSS VSS VSS VSS
DQS8_t DQS8_t
DQS8_c DQS8_c
CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c Rank 0: U1t–U5t, U7t–U10t, U12t–U20t
DQS17_t DQ DQ Rank 1: U21t–U38t
CB0 DQ DQ
DQS17_c Rank 2: U1b–U5b, U7b–U10b, U12b–U20b Command, control, address, and clock line terminations:
CB1 DQ U16b DQ U16t DQ U34b DQ U34t
U43 CB2 DQ DQ DQ DQ Rank 3: U21b–U38b
CB3 DQ DQ DQ DQ DDR4
CB0 ZQ ZQ ZQ ZQ CS_n[3:0]A/B, BA[1:0]A/B, BG[1:0]A/B, SDRAM
CB1 VSS VSS VSS VSS ACT_nA/B, A[17, 13:0]A/B, RAS_n/A16A/B,
CB2 DQS17_t VTT
DQS17_c SPD EEPROM/Temp Sensor, CAS_n/A15A/B, WE_n/A14A/B,
CB3 VDDSPD
CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c CS_n DQS_t DQS_c Register CKE[1:0]A/B, ODT[1:0]A/B
CB4 DDR4
CB4 DQ DQ DQ DQ DDR4 SDRAMs, Register,
CB5 VDD SDRAM
CB6
CB5 DQ U5b DQ U5t DQ U25b DQ U25t Data Buffers
CB6 DQ DQ DQ DQ
CB7 Control, command and CK0[A:D]_t VDD
CB7 DQ DQ DQ DQ VTT
ALERT_N ZQCAL address termination CK0[A:D]_c
ZQ ZQ ZQ ZQ
VDD VSS
VSS VSS VSS VSS VREFCA DDR4 SDRAM, Register
BVREF Data Buffers
VPP DDR4 SDRAM
VSS DDR4 SDRAM, Register,
Data Buffer
Note: 1. The ZQ ball on each DDR4 component is connected to an external 240Ω ±1% resistor
that is tied to ground. It is used for the calibration of the component’s ODT and output
driver.
CCMTD-1725822587-9934
General Description
General Description
High-speed DDR4 SDRAM modules use DDR4 SDRAM devices with two or four internal
memory bank groups. DDR4 SDRAM modules utilizing 4- and 8-bit-wide DDR4 SDRAM
devices have four internal bank groups consisting of four memory banks each, provid-
ing a total of 16 banks. 16-bit-wide DDR4 SDRAM devices have two internal bank
groups consisting of four memory banks each, providing a total of eight banks. DDR4
SDRAM modules benefit from DDR4 SDRAM's use of an 8n-prefetch architecture with
an interface designed to transfer two data words per clock cycle at the I/O pins. A single
READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bit-
wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit-
wide, one-half-clock-cycle data transfers at the I/O pins.
DDR4 modules use two sets of differential signals: DQS_t and DQS_c to capture data
and CK_t and CK_c to capture commands, addresses, and control signals. Differential
clocks and data strobes ensure exceptional noise immunity for these signals and pro-
vide precise crossing points to capture input signals.
Fly-By Topology
DDR4 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, com-
mand, and address buses have been routed in a fly-by topology, where each clock, con-
trol, command, and address pin on each DRAM is connected to a single trace and ter-
minated (rather than a tree structure, where the termination is off the module near the
connector). Inherent to fly-by topology, the timing skew between the clock and DQS sig-
nals can be easily accounted for by using the write-leveling feature of DDR4.
Module Manufacturing Location

Micron Technology manufactures modules at sites world-wide. Customers may receive
modules from any of the following manufacturing locations:
Table 8: DRAM Module Manufacturing Locations
Manufacturing Site Location Country of Origin Specified on Label

Boise, USA USA
Aguadilla, Puerto Rico Puerto Rico
Xian, China China
Singapore Singapore
CCMTD-1725822587-9934
Address Mapping to DRAM
Address Mapping to DRAM

Address Mirroring
To achieve optimum routing of the address bus on DDR4 multi rank modules, the ad-
dress bus will be wired as shown in the table below, or mirrored. For quad rank mod-
ules, ranks 1 and 3 are mirrored and ranks 0 and 2 are non-mirrored. Highlighted ad-
dress pins have no secondary functions allowing for normal operation when cross-
wired. Data is still read from the same address it was written. However, Load Mode op-
erations require a specific address. This requires the controller to accommodate for a
rank that is "mirrored." Systems may reference DDR4 SPD to determine if the module
has mirroring implemented or not. See the JEDEC DDR4 SPD specification for more de-
tails.
Table 9: Address Mirroring
Edge Connector Pin DRAM Pin, Non-mirrored DRAM Pin, Mirrored

A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A4
A4 A4 A3
A5 A5 A6
A6 A6 A5
A7 A7 A8
A8 A8 A7
A9 A9 A9
A10 A10 A10
A11 A11 A13
A13 A13 A11
A12 A12 A12
A14 A14 A14
A15 A15 A15
A16 A16 A16
A17 A17 A17
BA0 BA0 BA1
BA1 BA1 BA0
BG0 BG0 BG1
BG1 BG1 BG0
CCMTD-1725822587-9934
Registering Clock Driver Operation
Registering Clock Driver Operation

Registered DDR4 SDRAM modules use a registering clock driver device consisting of a
register and a phase-lock loop (PLL). The device complies with the JEDEC DDR4 RCD
specification.
To reduce the electrical load on the host memory controller's command, address, and
control bus, Micron's RDIMMs utilize a DDR4 registering clock driver (RCD). The RCD
presents a single load to the controller while redriving signals to the DDR4 SDRAM de-
vices, which helps enable higher densities and increase signal integrity. The RCD also
provides a low-jitter, low-skew PLL that redistributes a differential clock pair to multiple
differential pairs of clock outputs.
Control Words
The RCD device(s) used on DDR4 RDIMMs, LRDIMMs, and NVDIMMs contain configu-
ration registers known as control words, which the host uses to configure the RCD
based on criteria determined by the module design. Control words can be set by the
host controller through either the DRAM address and control bus or the I2C bus inter-
face. The RCD I 2C bus interface resides on the same I2C bus interface as the module
temperature sensor and EEPROM.
Parity Operations
The RCD includes a parity-checking function that can be enabled or disabled in control
word RC0E. The RCD receives a parity bit at the DPAR input from the memory control-
ler and compares it with the data received on the qualified command and address in-
puts; it indicates on its open-drain ALERT_n pin whether a parity error has occurred. If
parity checking is enabled, the RCD forwards commands to the SDRAM when no parity
error has occurred. If the parity error function is disabled, the RCD forwards sampled
commands to the SDRAM regardless of whether a parity error has occurred. Parity is al-
so checked during control word WRITE operations unless parity checking is disabled.
Rank Addressing
The chip select pins (CS_n) on Micron's modules are used to select a specific rank of
DRAM. The RDIMM is capable of selecting ranks in one of three different operating
modes, dependant on setting DA[1:0] bits in the DIMM configuration control word lo-
cated within the RCD. Direct DualCS mode is utilized for single- or dual-rank modules.
For quad-rank modules, either direct or encoded QuadCS mode is used.
Data Buffer Operation and Description

Data buffers operate as 4-bit bidirectional data registers with differential strobes, de-
signed for 1.2 V DD operation. Each buffer has a dual 4-bit host bus interface connected
to the memory controller and a dual 4-bit DRAM interface connected to two x4 DRAM
devices. Each buffer has an input-only 4-bit control bus interface consisting of two
dedicated control signals, a voltage reference input, and a differential clock signal.
All DQ inputs are pseudo-differentiated with an internal voltage reference. All DQ out-
puts are V DD-terminated drivers that are optimized to drive single- or dual-terminated
traces in DDR4 LRDIMM applications. The differential DQS strobes are used to sample
the DQ inputs and are regenerated internally to drive the DQ outputs on the opposite
side of the device.
CCMTD-1725822587-9934
Data Buffer Operation and Description
Control inputs are sampled by the clock inputs, and each data buffer supports ZQ cali-
bration for parity (with dedicated pins) and sequence error alerts.
CCMTD-1725822587-9934
Temperature Sensor with SPD EEPROM Operation
Temperature Sensor with SPD EEPROM Operation

Thermal Sensor Operations
The integrated thermal sensor continuously monitors the temperature of the module
PCB directly below the device and updates the temperature data register. Temperature
data may be read from the bus host at any time, which provides the host real-time feed-
back of the module's temperature. Multiple programmable and read-only temperature
registers can be used to create a custom temperature-sensing solution based on system
requirements and JEDEC JC-42.2.
EVENT_n Pin
The temperature sensor also adds the EVENT_n pin (open-drain), which requires a pull-
up to V DDSPD. EVENT_n is a temperature sensor output used to flag critical events that
can be set up in the sensor’s configuration registers. EVENT_n is not used by the serial
presence-detect (SPD) EEPROM.
EVENT_n has three defined modes of operation: interrupt, comparator, and TCRIT. In
interrupt mode, the EVENT_n pin remains asserted until it is released by writing a 1 to
the clear event bit in the status register. In comparator mode, the EVENT_n pin clears
itself when the error condition is removed. Comparator mode is always used when the
temperature is compared against the TCRIT limit. In TCRIT only mode, the EVENT_n
pin is only asserted if the measured temperature exceeds the TCRIT limit; it then re-
mains asserted until the temperature drops below the TCRIT limit minus the TCRIT
hysteresis.
SPD EEPROM Operation

DDR4 SDRAM modules incorporate SPD. The SPD data is stored in a 512-byte, JEDEC
JC-42.4-compliant EEPROM that is segregated into four 128-byte, write-protectable
blocks. The SPD content is aligned with these blocks as shown in the table below.
Block Range Description
0 0–127 000h–07Fh Configuration and DRAM parameters
1 128–255 080h–0FFh Module parameters
2 256–319 100h–13Fh Reserved (all bytes coded as 00h)
320–383 140h–17Fh Manufacturing information
3 384–511 180h–1FFh End-user programmable
The first 384 bytes are programmed by Micron to comply with JEDEC standard JC-45,
"Appendix X: Serial Presence Detect (SPD) for DDR4 SDRAM Modules." The remaining
128 bytes of storage are available for use by the customer.
The EEPROM resides on a two-wire I2C serial interface and is not integrated with the
memory bus in any manner. It operates as a slave device in the I2C bus protocol, with all
operations synchronized by the serial clock. Transfer rates of up to 1 MHz are achieva-
ble at 2.5V (NOM).
Micron implements reversible software write protection on DDR4 SDRAM-based mod-
ules. This prevents the lower 384 bytes (bytes 0 to 383) from being inadvertently pro-
grammed or corrupted. The upper 128 bytes remain available for customer use and are
unprotected.
CCMTD-1725822587-9934
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in each device's data sheet is not implied. Exposure to ab-
solute maximum rating conditions for extended periods may adversely affect reliability.
Table 10: Absolute Maximum Ratings
Symbol Parameter Min Max Units Notes

VDD VDD supply voltage relative to VSS –0.4 1.5 V 1
VDDQ VDDQ supply voltage relative to VSS –0.4 1.5 V 1
VPP Voltage on VPP pin relative to VSS –0.4 3.0 V 2
VIN, VOUT Voltage on any pin relative to VSS –0.4 1.5 V
Table 11: Operating Conditions
Symbol Parameter Min Nom Max Units Notes

VDD VDD supply voltage 1.14 1.20 1.26 V 1
VPP DRAM activating power supply 2.375 2.5 2.75 V 2
VREFCA(DC) Input reference voltage – 0.49 × VDD 0.5 × VDD 0.51 × VDD V 3
command/address bus
IVTT Termination reference current from VTT –750 – 750 mA
VTT Termination reference voltage (DC) – 0.49 × VDD - 0.5 × VDD 0.51 × VDD + V 4
command/address bus 20mV 20mV
IIN Input leakage current; any input excluding ZQ; 0V < –5 – 5 µA 5, 8
VIN < 1.1V
IZQ Input leakage current; ZQ –50 – 10 µA 6
IOZpd Output leakage current; VOUT = VDD; DQ is High-Z – – 10 µA 7
IOZpu Output leakage current; VOUT = VSS; DQ is High-Z; –50 – – µA 7
ODT is disabled with ODT input HIGH
IVREFCA VREFCA leakage; VREFCA = VDD/2 (after DRAM is ini- –4.5 – 4.5 µA 8
tialized)
Notes: 1. VDDQ balls on DRAM are tied to VDD.

2. VPP must be greater than or equal to VDD at all times.
3. VREFCA must not be greater than 0.6 × VDD. When VDD is less than 500mV, VREF may be
less than or equal to 300mV.
4. VTT termination voltages in excess of specification limit adversely affect command and
address signals' voltage margins and reduce timing margins.
5. Command and address inputs are terminated to VDD/2 in the registering clock driver. In-
put current is dependent on termination resistance set in the registering clock driver.
6. Tied to ground. Not connected to edge connector.
7. Multiply by the number of module ranks and then times the number of die per package.
8. RCD input current
CCMTD-1725822587-9934
Table 12: Thermal Characteristics
Symbol Parameter/Condition Value Units Notes

TC Commercial operating case temperature 0 to 85 °C 1, 2, 3
TC >85 to 95 °C 1, 2, 3, 4
TOPER Normal operating temperature range 0 to 85 °C 5, 7
TOPER Extended temperature operating range (optional) >85 to 95 °C 5, 7
TSTG Non-operating storage temperature –55 to 100 °C 6
RHSTG Non-operating storage relative humidity (non-condensing) 5 to 95 %
NA Change rate of storage temperature 20 °C/hour
Notes: 1. Maximum operating case temperature; TC is measured in the center of the package.
2. A thermal solution must be designed to ensure the DRAM device does not exceed the
maximum TC during operation.
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC dur-
ing operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2X refresh, which is a 3.9µs
interval refresh rate.
5. The refresh rate must double when 85°C < TOPER ≤ 95°C.
6. Storage temperature is defined as the temperature of the top/center of the DRAM and
does not reflect the storage temperatures of shipping trays.
7. For additional information, refer to technical note TN-00-08: "Thermal Applications"
available at micron.com.
CCMTD-1725822587-9934
DRAM Operating Conditions
DRAM Operating Conditions

Recommended AC operating conditions are given in the DDR4 component data sheets.
Component specifications are available at micron.com. Module speed grades correlate
with component speed grades, as shown below.
Table 13: Module and Component Speed Grades

DDR4 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade Component Speed Grade
-3G2 -062E
-2G9 -068
-2G6 -075
-2G3 -083
-2G1 -093E
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully de-
signed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level. Mi-
cron encourages designers to simulate the signal characteristics of the system's memo-
ry bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the edge connector of the module, not at the DRAM.
Designers must account for any system voltage drops at anticipated power levels to en-
sure the required supply voltage is maintained.
IDD, I PP, and I DDQ Specifications

IDD and IPP values are only for the DDR4 SDRAM and are calculated from values in the
supporting component data sheet. IPP and IDDQ currents are not included in IDD cur-
rents. IDD and IDDQ currents are not included in IPP currents. Micron does not specify
IDDQ currents. In DRAM module application, IDDQ cannot be measured separately be-
cause V DD and V DDQ use a merged power layer in the module PCB.
Certain IDD/IPP conditions must be derated for optional modes of operation, such as CA
parity, DBI, write CRC, additive latency, geardown, CAL, 2X and 4X REF, and DLL disa-
bled. Refer to the base device data sheet IDD and IPP specification tables for derating val-
ues for the applicable die revision.
CCMTD-1725822587-9934
IDD Specifications
IDD Specifications
Table 14: DDR4 IDD Specifications and Conditions (0° ≤ TC ≤ 85°) – 64GB (Die Revision B)
Values are for the MT40A4G4 DDR4 TwinDie SDRAM only and are computed from values specified in the 16Gb (4 Gig x 4)
component data sheet
Parameter Symbol 2666 2400 Units
One bank ACTIVATE-PRECHARGE current ICDD0 2232 2178 mA
One bank ACTIVATE-PRECHARGE, wordline boost, IPP current ICPP0 216 216 mA
One bank ACTIVATE-READ-PRECHARGE current ICDD1 2448 2394 mA
Precharge standby current ICDD2N 1980 1962 mA
Precharge standby ODT current ICDD2NT 2250 2250 mA
Precharge power-down current ICDD2P 1800 1800 mA
Precharge quite standby current ICDD2Q 1890 1890 mA
Active standby current ICDD3N 2088 2034 mA
Active standby IPP current ICPP3N 216 216 mA
Active power-down current ICDD3P 1962 1926 mA
Burst read current ICDD4R 3582 3384 mA
Burst write current ICDD4W 3420 3258 mA
Burst refresh current (1x REF) ICDD5R 2358 2304 mA
Burst refresh IPP current (1x REF) ICPP5R 252 252 mA
Self refresh current: Normal temperature range (0°C to 85°C) ICDD6N 1980 1980 mA
Self refresh current: Extended temperature range (0°C to 95°C) ICDD6E 2160 2160 mA
Self refresh current: Reduced temperature range (0°C to 45°C) ICDD6R 1620 1620 mA
Auto self refresh current (25°C) ICDD6A 1209.6 1209.6 mA
Auto self refresh current (45°C) ICDD6A 1620 1620 mA
Auto self refresh current IPP current ICPP6X 288 288 mA
Bank interleave read current ICDD7 8100 7560 mA
Bank interleave read IPP current ICPP7 486 468 mA
Maximum power-down current ICDD8 1800 1800 mA
Note: 1. When TC > 85°C, the IDD and IPP values must be derated. Refer to the base device data
sheet IDD and IPP specification tables for derating values for the applicable die-revision.
CCMTD-1725822587-9934
IDD Specifications
Table 15: DDR4 IDD Specifications and Conditions (0° ≤ TC ≤ 85°) – 64GB (Die Revision D)
CCMTD-1725822587-9934
IDD Specifications
Table 16: DDR4 IDD Specifications and Conditions (0° ≤ TC ≤ 85°) – 64GB (Die Revision J)
CCMTD-1725822587-9934
Registering Clock Driver Specifications
Registering Clock Driver Specifications
Table 17: Registering Clock Driver Electrical Characteristics

DDR4 RCD01 devices or equivalent
Parameter Symbol Pins Min Nom Max Units
DC supply voltage VDD – 1.14 1.2 1.26 V
DC reference voltage VREF VREFCA 0.49 × VDD 0.5 × VDD 0.51 × VDD V
DC termination VTT – VREF - 40mV VREF VREF + 40mV V
voltage
High-level input VIH. CMOS DRST_n 0.65 × VDD – VDD V
voltage
Low-level input VIL. CMOS 0 – 0.35 × VDD V
voltage
DRST_n pulse width tIN- – 1.0 – – µs
IT_Pow-
er_stable
AC high-level output VOH(AC) All outputs except VTT + (0.15 × VDD) – – V
voltage ALERT_n
AC low-level output VOL(AC) – – VTT + (0.15 × VDD) V
voltage
AC differential out- VOHdiff(AC) Yn_t - Yn_c, BCK_t - – 0.3 × VDD – mV
put high measure- BCK_c
ment level (for out-
put slew rate)
AC differential out- VOLdiff(AC) – –0.3 × VDD – mV
put low measure-
ment level (for out-
put slew rate)
Note: 1. Timing and switching specifications for the register listed are critical for proper opera-
tion of DDR4 SDRAM RDIMMs. These are meant to be a subset of the parameters for the
specific device used on the module. See the JEDEC RCD01 specification for complete op-
erating electrical characteristics. Registering clock driver parametric values are specified
for device default control word settings, unless otherwise stated. The RC0A control
word setting does not affect parametric values.
CCMTD-1725822587-9934
Data Buffer Specifications
Table 18: Data Buffer Electrical Characteristics

DDR4 DB01 devices or equivalent
Parameter Symbol Pins Min Nom Max Unit
DC supply voltage VDD – 1.14 1.2 1.26 V
DC reference voltage BVREFCA BVREF 0.49 × VDD 0.5 × VDD 0.51 × VDD
Low-level VIL(static) BCK_t, 0 – 0.35 × VDD
input voltage BCK_c
(during
clock stop)
Differential input VIX(BCK) –120 – 120 mV
cross point voltage
range
BCK_t,
Extended VIX_EX(BCK) –150 – 150
BCK_c
differential input
cross point voltage
range
Average common VCM(DC) BCK_t, 0.46 × VDD 0.5 × VDD 0.54 × VDD V
mode DC voltage BCK_c
Single-ended VSEH DDR4-1866, 2133 – – mV
high level BCK_t, (VDD/2) + 90
BCK_c DDR4-2400 (VDD/2)
+ 75
Single-ended VSEL – – DDR4-1866, 2133
low level BCK_t, (VDD/2) - 90
BCK_c DDR4-2400 (VDD/2) -
75
AC input high VIH(AC) DDR4-1866, 2133 – – mV
BCK_t, BVREFCA + 90
BCK_c DDR4-2400 BVREFCA
+ 75
AC input low VIL(AC) – – DDR4-1866, 2133
BCK_t, BVREFCA - 90
BCK_c DDR4-2400 BVREFCA -
75
Differential input VIH,diff DDR4-1866, 2133; – – mV
BCK_t,
high 130
BCK_c
DDR4-2400; 100
Differential input low VIL,diff – – DDR4-1866, 2133;
BCK_t,
–130
BCK_c
DDR4-2400; –100
AC differential input VIH,diff(AC) BCK_t, 2 x (VIH(AC).MIN - – – mV
high BCK_c BVREFCA )
AC differential input VIL,diff(AC) BCK_t, – – 2 x (VIL(AC).MAX -
low BCK_c BVREFCA)
CCMTD-1725822587-9934
Table 18: Data Buffer Electrical Characteristics (Continued)

DDR4 DB01 devices or equivalent
Parameter Symbol Pins Min Nom Max Unit
AC output high VOH(AC) – (0.7 + 0.15) x VDD – V
AC output low VOL(AC) – (0.7 - 0.15) x VDD –
DC output high VOH(DC) – 1.1 x VDD – V
DC output mid VOM(DC) All outputs – 0.8 x VDD –
DC output low VOL(DC) except – 0.5 x VDD –
ALERT_n
AC differential VOH,diff(AC) – 0.3 x VDD – V
output high
AC differential VOL,diff(AC) – –0.3 x VDD –
output low
Junction Tj – 0 – 125 C°
temperature
Case temperature TCASE – – – TBD
Input clamp current IIK – – – –50 mA
output clamp IOK – – – ±50
current
Continuous output IO – – – ±50
current
Continuous output ICCC – – – ±100
current each VDD or
VSS pin
Note: 1. Data buffer parametric values are specified for the device default control word settings,
unless otherwise stated.
CCMTD-1725822587-9934
Temperature Sensor with SPD EEPROM

The temperature sensor continuously monitors the module's temperature and can be
read back at any time over the I2C bus shared with the serial presence-detect (SPD) EE-
PROM. Refer to JEDEC JC-42.4 EE1004 and TSE2004 device specifications for complete
details.
SPD Data
For the latest SPD data, refer to Micron's SPD page: micron.com/SPD.
Table 19: Temperature Sensor with SPD EEPROM Operating Conditions
Parameter/Condition Symbol Min Nom Max Units

Supply voltage VDDSPD 1.7 2.5 3.3 V
Input low voltage: Logic 0; All inputs VIL –0.5 – VDDSPD × 0.3 V
Input high voltage: Logic 1; All inputs VIH VDDSPD × 0.7 – VDDSPD + 0.5 V
Output low voltage: 3mA sink current VDDSPD > 2V VOL – – 0.4 V
Input leakage current: (SCL, SDA) VIN = VDDSPD or VSSSPD ILI – – ±5 µA
Output leakage current: VOUT = VDDSPD or VSSSPD, SDA in High-Z ILO – – ±5 µA
Notes: 1. Table is provided as a general reference. Consult JEDEC JC-42.4 TSE2004 device specifica-
tions for complete details.
2. Operation at tSCL > 100 kHz may require VDDSPD ≤ 2.2.
3. All voltages referenced to VDDSPD.
Table 20: Temperature Sensor and EEPROM Serial Interface Timing
Parameter/Condition Symbol Min Max Units

Clock frequency fSCL 10 1000 kHz
Clock pulse width HIGH time tHIGH 260 – ns
Clock pulse width LOW time tLOW 500 – ns
Detect clock LOW timeout tTIMEOUT 25 35 ms
SDA rise time tR – 120 ns
SDA fall time tF – 120 ns
Data-in setup time tSU:DAT 50 – ns
Data-in hold time tHD:DI 0 – ns
Data out hold time tHD:DAT 0 350 ns
Start condition setup time tSU:STA 260 – ns
Start condition hold time tHD:STA 260 – ns
Stop condition setup time tSU:STO 260 – ns
Time the bus must be free before a new transi- tBUF 500 – ns
tion can start
Write time tW – 5 ms
Warm power cycle time off tPOFF 1 – ms
CCMTD-1725822587-9934
Table 20: Temperature Sensor and EEPROM Serial Interface Timing (Continued)
Parameter/Condition Symbol Min Max Units

Time from power-on to first command tINIT 10 – ms
Notes: 1. Table is provided as a general reference. Consult JEDEC JC-42.4 TSE2004 device specifica-
tions for complete details.
2. Operation at tSCL > 100 kHz may require VDDSPD ≤ 2.2.
CCMTD-1725822587-9934
Module Dimensions
Module Dimensions
Figure 4: 288-Pin DDR4 LRDIMM

Front view 3.9 (0.153)
133.48 (5.255) MAX
133.22 (5.244)
U6
U1 U2 U3 U4 U5 U7 U8 U9 U10
U11
0.75 (0.03) R 31.40 (1.236)
(8X) U12 U13 U14 U15 U16 U17 U18 U19 U20 31.10 (1.224)
2.50 (0.098) D 16.1 (0.63)

(2X)
9.5 (0.374) TYP
4.8 (0.189) TYP TYP
0.75 (0.030) R 1.5 (0.059)

Pin 1
1.3 (0.051)
2.20 (0.087) TYP 0.85 (0.033) 0.60 (0.0236)
TYP TYP Pin 144
3.35 (0.132) TYP
(2X)
72.25 (2.84)
TYP
126.65 (4.99)
TYP
Back view 1.25 (0.049) x 45° (2X)
U21 U22 U23 U24 U25 U26 U27 U28 U29
3.0 (0.118) (4X) TYP

U30 U31 U32 U33 U34 U35 U36 U37 U38
14.6 (0.57)
TYP 8.0 (0.315) U39 U40 U41 U42 U43 U44 U45 U46 U47
TYP
0.5 (0.0197) TYP
3.15 (0.124) Pin 288 Pin 145
TYP 10.2 (0.4) 5.95 (0.234) TYP 10.2 (0.4)
22.95 (0.90) TYP 22.95 (0.9) 25.5 (1.0) TYP 28.9 (1.14)
TYP TYP TYP TYP
56.10 (2.21) 64.6 (2.54)

TYP TYP
Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.
CCMTD-1725822587-9934
Module Dimensions
Figure 5: 288-Pin DDR4 LRDIMM

FRONT VIEW 3.9 (0.153)
133.48 (5.255) MAX
133.22 (5.244)
15.0 (0.59) 15.85 (0.624)
TYP (4X) TYP (2X) 27.3 (1.075) TYP
7.18 (0.283) TYP (2X)
U6
U1 U2 U3 U4 U5 U7 U8 U9 U10
2.20 (0.087) TYP
0.75 (0.03) R U16 31.40 (1.236)

(8X) 24.6 (0.97) 31.10 (1.224)
U11 U12 U13 U14 U15 U17 U18 U19 U20 TYP
1.5 (0.059) D 16.1 (0.63)

(2X) 9.5 (0.374) TYP
TYP
2.25 (0.88) TYP
0.75 (0.030) R 1.5 (0.059)
PIN 1
1.75 (0.069) TYP 1.3 (0.051)
0.85 (0.033) 0.60 (0.0236)
TYP TYP PIN 144
3.35 (0.132) TYP
(2X)
72.25 (2.84)
TYP
126.65 (4.99)
TYP
1.0 (0.039) R (8X)

BACK VIEW 1.25 (0.049) x 45° (2X)
0.50 (0.02) R
(4X)
U21 U22 U23 U24 U25 U26 U27 U28 U29 3.1 (0.122) (2X) TYP
23.05 (0.91) 3.0 (0.118) (4X) TYP

TYP U30 U31 U32 U33 U34 U35 U36 U38 U39
14.6 (0.57)
TYP 8.0 (0.315) U39 U40 U41 U42 U43 U44 U45 U46 U47
TYP
0.5 (0.0197) TYP
3.15 (0.124) PIN 288 PIN 145
TYP 10.2 (0.4) 5.95 (0.234) TYP 10.2 (0.4)
22.95 (0.90) TYP 22.95 (0.9) 25.5 (1.0) TYP 28.9 (1.14)
TYP TYP TYP TYP
56.10 (2.21) 64.6 (2.54)

TYP TYP
Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc. TwinDie is a trademark of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
CCMTD-1725822587-9934

Ddr4 Sdram Lrdimm: MTA72ASS8G72LZ - 64GB Features

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64GB (x72, ECC, QR) 288-Pin DDR4 LRDIMM

DDR4 SDRAM LRDIMM

Features Figure 1: 288-Pin LRDIMM (MO-309, R/C-E2)

Table 1: Key Timing Parameters

Data Rate (MT/s)

20\ 18\ 16\ 14\ 12\ 10\ tRCD tRP tRC

Table 1: Key Timing Parameters (Continued)

Data Rate (MT/s)

20\ 18\ 16\ 14\ 12\ 10\ tRCD tRP tRC

Table 3: Part Numbers and Timing Parameters – 64GB Modules

Important Notes and Warnings

Table 4: Pin Assignments

288-Pin DDR4 LRDIMM Front 288-Pin DDR4 LRDIMM Back

Table 5: Pin Descriptions

Symbol Type Description

Table 5: Pin Descriptions (Continued)

Symbol Type Description

Table 5: Pin Descriptions (Continued)

Symbol Type Description

Table 6: Component-to-Module DQ Map, Front

Table 7: Component-to-Module DQ Map, Back

Functional Block Diagram

Figure 3: Functional Block Diagram

Module Manufacturing Location

Table 8: DRAM Module Manufacturing Locations

Manufacturing Site Location Country of Origin Specified on Label

Address Mapping to DRAM

Table 9: Address Mirroring

Edge Connector Pin DRAM Pin, Non-mirrored DRAM Pin, Mirrored

Registering Clock Driver Operation

Data Buffer Operation and Description

Temperature Sensor with SPD EEPROM Operation

SPD EEPROM Operation

Table 10: Absolute Maximum Ratings

Symbol Parameter Min Max Units Notes

Table 11: Operating Conditions

Symbol Parameter Min Nom Max Units Notes

Notes: 1. VDDQ balls on DRAM are tied to VDD.

Table 12: Thermal Characteristics

Symbol Parameter/Condition Value Units Notes

DRAM Operating Conditions

Table 13: Module and Component Speed Grades

IDD, I PP, and I DDQ Specifications

Registering Clock Driver Specifications

Table 17: Registering Clock Driver Electrical Characteristics

Data Buffer Specifications

Table 18: Data Buffer Electrical Characteristics

Table 18: Data Buffer Electrical Characteristics (Continued)

Temperature Sensor with SPD EEPROM

Table 19: Temperature Sensor with SPD EEPROM Operating Conditions

Parameter/Condition Symbol Min Nom Max Units

Table 20: Temperature Sensor and EEPROM Serial Interface Timing

Parameter/Condition Symbol Min Max Units

Parameter/Condition Symbol Min Max Units

Figure 4: 288-Pin DDR4 LRDIMM

2.50 (0.098) D 16.1 (0.63)

0.75 (0.030) R 1.5 (0.059)

Back view 1.25 (0.049) x 45° (2X)

U21 U22 U23 U24 U25 U26 U27 U28 U29