Term Paper Title

Bachelor of Technology
Computer Science and Engineering

Submitted By

ABHIJEET KARMAKAR (13000118141)

MONTH 2019

Techno Main Salt Lake

1. Abstract
2. Introduction
3. Body
i. Flow Chart of Instruction Cycle
ii. Role of Components
iii. Summary of stages
iv. Initiation of instruction cycle
v. Fetch stage
vi. Decode stage
vii. Execute stage
4. Conclusion
5. References

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 ABSTRACT

This term paper is aimed at discussing on the topic of Instruction Cycle also known as fetch
decode cycle which is the basic operational process of a computer. This process is repeated
continuously by CPU from boot up to shut down of computer. We are also going to discuss about
the different phases in an instruction cycle and how each of the phases work. This term paper
helps in elaborative study of Instruction Cycle along with the flow chart for better understanding.

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 INTRODUCTION
The instruction cycle (also known as the fetch–decode–execute cycle or simply the fetch-execute
cycle) is the cycle which the central processing unit (CPU) follows from boot-up until the
computer has shut down in order to process instructions. It is composed of three main stages: the
fetch stage, the decode stage, and the execute stage.

In simpler CPUs, the instruction cycle is executed sequentially, each instruction being processed
before the next one is started. In most modern CPUs, the instruction cycles are instead
executed concurrently, and often in parallel, through an instruction pipeline: the next instruction
starts being processed before the previous instruction has finished, which is possible because the
cycle is broken up into separate steps.

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 FLOW CHART OF INSTRUCTION CYCLE

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 ROLE OF COMPONENTS
The program counter (PC) is a special register that holds the memory address of the next
instruction to be executed. During the fetch stage, the address stored in the PC is copied into
the memory address register (MAR) and then the PC is incremented in order to "point" to the
memory address of the next instruction to be executed. The CPU then takes the instruction at the
memory address described by the MAR and copies it into the memory data register (MDR). The
MDR also acts as a two-way register that holds data fetched from memory or data waiting to be
stored in memory (it is also known as the memory buffer register (MBR) because of this).
Eventually, the instruction in the MDR is copied into the current instruction register (CIR) which
acts as a temporary holding ground for the instruction that has just been fetched from memory.
During the decode stage, the control unit (CU) will decode the instruction in the CIR. The CU
then sends signals to other components within the CPU, such as the arithmetic logic unit
(ALU) and the floating point unit (FPU). The ALU performs arithmetic operations such as
addition and subtraction and also multiplication via repeated addition and division via repeated
subtraction. It also performs logic operations such as AND, OR, NOT, and binary shifts as well.
The FPU is reserved for performing floating-point operations.

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 SUMMARY OF STAGES
Each computer's CPU can have different cycles based on different instruction sets, but will be
similar to the following cycle:

1. Fetch Stage: The next instruction is fetched from the memory address that is currently
stored in the program counter and stored into the instruction register. At the end of the
fetch operation, the PC points to the next instruction that will be read at the next cycle.
2. Decode Stage: During this stage, the encoded instruction present in the instruction
register is interpreted by the decoder.
o Read the effective address: In the case of a memory instruction (direct or
indirect), the execution phase will be during the next clock pulse. If the instruction
has an indirect address, the effective address is read from main memory, and any
required data is fetched from main memory to be processed and then placed into data
registers (clock pulse: T3). If the instruction is direct, nothing is done during this
clock pulse. If this is an I/O instruction or a register instruction, the operation is
performed during the clock pulse.
3. Execute Stage: The control unit of the CPU passes the decoded information as a sequence
of control signals to the relevant function units of the CPU to perform the actions
required by the instruction, such as reading values from registers, passing them to the
ALU to perform mathematical or logic functions on them, and writing the result back to
a register. If the ALU is involved, it sends a condition signal back to the CU. The result
generated by the operation is stored in the main memory or sent to an output device.
Based on the feedback from the ALU, the PC may be updated to a different address from
which the next instruction will be fetched.
4. Repeat Cycle

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 INITIATION OF INSTRUCTION CYCLE
The cycle begins as soon as power is applied to the system, with an initial PC value that is
predefined by the system's architecture (for instance, in Intel IA-32 CPUs, the predefined PC
value is  0xfffffff0 ). Typically, this address points to a set of instructions in read-only
memory (ROM), which begins the process of loading (or booting) the operating system.

FETCH STAGE
The fetch step is the same for each instruction:

1. The CPU sends the contents of the PC to the MAR and sends a read command on the
address bus
2. In response to the read command (with address equal to PC), the memory returns the data
stored at the memory location indicated by PC on the data bus
3. The CPU copies the data from the data bus into its MDR (also known as MBR; see
section Role of components above)
4. A fraction of a second later, the CPU copies the data from the MDR to the instruction
register for instruction decoding
5. The PC is incremented so that it points to the next instruction. This step prepares the CPU
for the next cycle.
The control unit fetches the instruction's address from the memory unit.

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 DECODE STAGE
The decoding process allows the CPU to determine what instruction is to be performed so that
the CPU can tell how many operands it needs to fetch in order to perform the instruction. The
opcode fetched from the memory is decoded for the next steps and moved to the appropriate
registers. The decoding is done by the CPU's Control Unit.
Reading the effective address
This step evaluates which type of operation is to be performed. If it is a memory operation, the
computer checks whether it's a direct or indirect memory operation:

 Direct memory operation - Nothing is done.

EXECUTE STAGE
The function of the instruction is performed. If the instruction involves arithmetic or logic, the
ALU is utilized. This is the only stage of the instruction cycle that is useful from the perspective
of the end user. Everything else is overhead required to make the execute step happen.

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 REFRENCES

1.  Crystal Chen, Greg Novick and Kirk Shimano (2000). "Pipelining".

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