74LVC2T45 74LVCH2T45: 1. General Description

74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state

Rev. 8 — 29 March 2013 Product data sheet
1. General description
The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with
3-state outputs that enable bidirectional level translation. They feature two 2-bits
input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (VCC(A)
and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and
5.5 V making the device suitable for translating between any of the low voltage nodes
(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins nA and DIR are referenced to VCC(A) and
pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a
LOW on DIR allows transmission from nB to nA.
The devices are fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A port and B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH2T45 holds unused or floating data inputs at a valid
logic level.
2. Features and benefits

 Wide supply voltage range:
 VCC(A): 1.2 V to 5.5 V
 VCC(B): 1.2 V to 5.5 V
 High noise immunity
 Complies with JEDEC standards:
 JESD8-7 (1.2 V to 1.95 V)
 JESD8-5 (1.8 V to 2.7 V)
 JESD8C (2.7 V to 3.6 V)
 JESD36 (4.5 V to 5.5 V)
 ESD protection:
 HBM JESD22-A114F Class 3A exceeds 4000 V
 MM JESD22-A115-A exceeds 200 V
 CDM JESD22-C101E exceeds 1000 V
 Maximum data rates:
 420 Mbps (3.3 V to 5.0 V translation)
 210 Mbps (translate to 3.3 V))
 140 Mbps (translate to 2.5 V)
NXP Semiconductors 74LVC2T45; 74LVCH2T45
 Suspend mode
 Latch-up performance exceeds 100 mA per JESD 78 Class II
 24 mA output drive (VCC = 3.0 V)
 Inputs accept voltages up to 5.5 V
 Low power consumption: 16 A maximum ICC
 IOFF circuitry provides partial Power-down mode operation
 Multiple package options
 Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC2T45DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1
74LVCH2T45DC body width 2.3 mm
74LVC2T45GT 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; SOT833-1
74LVCH2T45GT 8 terminals; body 1  1.95  0.5 mm
74LVC2T45GF 40 C to +125 C XSON8 extremely thin small outline package; no leads; SOT1089
74LVCH2T45GF 8 terminals; body 1.35  1  0.5 mm
74LVC2T45GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; SOT996-2
74LVCH2T45GD 8 terminals; body 3  2  0.5 mm
74LVC2T45GM 40 C to +125 C XQFN8 plastic, extremely thin quad flat package; no leads; SOT902-2
74LVCH2T45GM 8 terminals; body 1.6  1.6  0.5 mm
74LVC2T45GN 40 C to +125 C XSON8 extremely thin small outline package; no leads; SOT1116
74LVCH2T45GN 8 terminals; body 1.2  1.0  0.35 mm
74LVC2T45GS 40 C to +125 C XSON8 extremely thin small outline package; no leads; SOT1203
74LVCH2T45GS 8 terminals; body 1.35  1.0  0.35 mm
4. Marking
Table 2. Marking
Type number Marking code[1]
74LVC2T45DC V45
74LVCH2T45DC X45
74LVC2T45GT V45
74LVCH2T45GT X45
74LVC2T45GF V5
74LVCH2T45GF X5
74LVC2T45GD V45
74LVCH2T45GD X45
74LVC2T45GM V45
74LVCH2T45GM X45
74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 29 March 2013 2 of 36

Table 2. Marking …continued

Type number Marking code[1]
74LVC2T45GN V5
74LVCH2T45GN X5
74LVC2T45GS V5
74LVCH2T45GS X5
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
5
DIR
DIR
2
1A
1A
7
1B
1B
3
2A
2A
6
2B
2B
VCC(A) VCC(B)
VCC(A) VCC(B)
001aag577 001aag578
Fig 1. Logic symbol Fig 2. Logic diagram
6. Pinning information
6.1 Pinning
74LVC2T45
74LVCH2T45
VCC(A) 1 8 VCC(B)
1A 2 7 1B
74LVC2T45
74LVCH2T45
2A 3 6 2B
VCC(A) 1 8 VCC(B)
1A 2 7 1B
GND 4 5 DIR
2A 3 6 2B
GND 4 5 DIR 001aai905
001aai904 Transparent top view
Fig 3. Pin configuration SOT765-1 Fig 4. Pin configuration SOT833-1, SOT1089,

SOT1116 and SOT1203

74LVC2T45
74LVCH2T45
VCC(B)
terminal 1
index area
74LVC2T45
8
1B 1 7 VCC(A)
74LVCH2T45
VCC(A) 1 8 VCC(B)
2B 2 6 1A
1A 2 7 1B
2A 3 6 2B DIR 3 5 2A
4
GND 4 5 DIR
GND
001aai906
001aaj617
Transparent top view Transparent top view
Fig 5. Pin configuration SOT996-2 Fig 6. Pin configuration SOT902-2
6.2 Pin description

Table 3. Pin description
Symbol Pin Description
SOT765-1, SOT833-1, SOT1089, SOT902-2
SOT996-2, SOT1116 and SOT1203
VCC(A) 1 7 supply voltage A (port A and DIR)
1A 2 6 data input or output
2A 3 5 data input or output
GND 4 4 ground (0 V)
DIR 5 3 direction control
2B 6 2 data input or output
1B 7 1 data input or output
VCC(B) 8 8 supply voltage B (port B)
7. Functional description
Table 4. Function table[1]
Supply voltage Input Input/output[2]
VCC(A), VCC(B) DIR nA nB
1.2 V to 5.5 V L nA = nB input
1.2 V to 5.5 V H input nB = nA
GND[3] X Z Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2] The input circuit of the data I/O is always active.
[3] When either VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.

8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC(A) supply voltage A 0.5 +6.5 V
VCC(B) supply voltage B 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA
VI input voltage [1] 0.5 +6.5 V
IOK output clamping current VO < 0 V 50 - mA
VO output voltage Active mode [1][2][3] 0.5 VCCO + 0.5 V
Suspend or 3-state mode [1] 0.5 +6.5 V
IO output current VO = 0 V to VCCO [2] - 50 mA
ICC supply current ICC(A) or ICC(B) - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C [4] - 250 mW
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 6.5 V.
[4] For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions

Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Max Unit
VCC(A) supply voltage A 1.2 5.5 V
VCC(B) supply voltage B 1.2 5.5 V
VI input voltage 0 5.5 V
VO output voltage Active mode [1] 0 VCCO V
Suspend or 3-state mode 0 5.5 V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCCI = 1.2 V [2] - 20 ns/V
VCCI = 1.4 V to 1.95 V - 20 ns/V
VCCI = 2.3 V to 2.7 V - 20 ns/V
VCCI = 3 V to 3.6 V - 10 ns/V
VCCI = 4.5 V to 5.5 V - 5 ns/V
[2] VCCI is the supply voltage associated with the input port.

10. Static characteristics

Table 7. Typical static characteristics at Tamb = 25 C
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
VOH HIGH-level output voltage VI = VIH or VIL
IO = 3 mA; VCCO = 1.2 V [1] - 1.09 - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 3 mA; VCCO = 1.2 V [1] - 0.07 - V
II input leakage current DIR input; VI = 0 V to 5.5 V; [2] - - 1 A
VCCI = 1.2 V to 5.5 V
IBHL bus hold LOW current A or B port; VI = 0.42 V; VCCI = 1.2 V [2] - 19 - A
IBHH bus hold HIGH current A or B port; VI = 0.78 V; VCCI = 1.2 V [2] - 19 - A
IBHLO bus hold LOW overdrive A or B port; VCCI = 1.2 V [2][3] - 19 - A
current
IBHHO bus hold HIGH overdrive A or B port; VCCI = 1.2 V [2][3] - 19 - A
current
IOZ OFF-state output current A or B port; VO = 0 V or VCCO; [1] - - 1 A
VCCO = 1.2 V to 5.5 V
IOFF power-off leakage current A port; VI or VO = 0 V to 5.5 V; - - 1 A
VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V
B port; VI or VO = 0 V to 5.5 V; - - 1 A
VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V
CI input capacitance DIR input; VI = 0 V or 3.3 V; - 2.2 - pF
VCC(A) = VCC(B) = 3.3 V
CI/O input/output capacitance A and B port; suspend mode; - 6.0 - pF
VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V
[2] VCCI is the supply voltage associated with the data input port.
[3] To guarantee the node switches, an external driver must source/sink at least IBHLO/IBHHO when the input is in the range VIL to VIH.

Table 8. Static characteristics

Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
VIH HIGH-level data input [1]
input voltage VCCI = 1.2 V 0.8VCCI - 0.8VCCI - V

VCCI = 1.4 V to 1.95 V 0.65VCCI - 0.65VCCI - V
VCCI = 2.3 V to 2.7 V 1.7 - 1.7 - V
VCCI = 3.0 V to 3.6 V 2.0 - 2.0 - V
VCCI = 4.5 V to 5.5 V 0.7VCCI - 0.7VCCI - V
DIR input
VCCI = 1.2 V 0.8VCC(A) - 0.8VCC(A) - V
VCCI = 1.4 V to 1.95 V 0.65VCC(A) - 0.65VCC(A) - V
VCCI = 2.3 V to 2.7 V 1.7 - 1.7 - V
VCCI = 3.0 V to 3.6 V 2.0 - 2.0 - V
VCCI = 4.5 V to 5.5 V 0.7VCC(A) - 0.7VCC(A) - V
VIL LOW-level data input [1]
input voltage VCCI = 1.2 V - 0.2VCCI - 0.2VCCI V

VCCI = 1.4 V to 1.95 V - 0.35VCCI - 0.35VCCI V
VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V
VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V
VCCI = 4.5 V to 5.5 V - 0.3VCCI - 0.3VCCI V
DIR input
VCCI = 1.2 V - 0.2VCC(A) - 0.2VCC(A) V
VCCI = 1.4 V to 1.95 V - 0.35VCC(A) - 0.35VCC(A) V
VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V
VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V
VCCI = 4.5 V to 5.5 V - 0.3VCC(A) - 0.3VCC(A) V
VOH HIGH-level VI = VIH
output voltage IO = 100 A; [2] VCCO  0.1 - VCCO  0.1 - V
VCCO = 1.2 V to 4.5 V
IO = 6 mA; VCCO = 1.4 V 1.0 - 1.0 - V
IO = 8 mA; VCCO = 1.65 V 1.2 - 1.2 - V
IO = 12 mA; VCCO = 2.3 V 1.9 - 1.9 - V
IO = 24 mA; VCCO = 3.0 V 2.4 - 2.4 - V
IO = 32 mA; VCCO = 4.5 V 3.8 - 3.8 - V

Table 8. Static characteristics …continued

Min Max Min Max
VOL LOW-level VI = VIL [2]
output voltage IO = 100 A; - 0.1 - 0.1 V

VCCO = 1.2 V to 4.5 V
IO = 6 mA; VCCO = 1.4 V - 0.3 - 0.3 V
IO = 8 mA; VCCO = 1.65 V - 0.45 - 0.45 V
IO = 12 mA; VCCO = 2.3 V - 0.3 - 0.3 V
IO = 24 mA; VCCO = 3.0 V - 0.55 - 0.55 V
IO = 32 mA; VCCO = 4.5 V - 0.55 - 0.55 V
II input leakage DIR input; VI = 0 V to 5.5 V; - 2 - 10 A
current VCCI = 1.2 V to 5.5 V
IBHL bus hold LOW A or B port [1]
current VI = 0.49 V; VCCI = 1.4 V 15 - 10 - A

VI = 0.58 V; VCCI = 1.65 V 25 - 20 - A
VI = 0.70 V; VCCI = 2.3 V 45 - 45 - A
VI = 0.80 V; VCCI = 3.0 V 100 - 80 - A
VI = 1.35 V; VCCI = 4.5 V 100 - 100 - A
IBHH bus hold HIGH A or B port [1]
current VI = 0.91 V; VCCI = 1.4 V 15 - 10 - A

VI = 1.07 V; VCCI = 1.65 V 25 - 20 - A
VI = 1.60 V; VCCI = 2.3 V 45 - 45 - A
VI = 2.00 V; VCCI = 3.0 V 100 - 80 - A
VI = 3.15 V; VCCI = 4.5 V 100 - 100 - A
IBHLO bus hold LOW A or B port [1][3]
overdrive VCCI = 1.6 V 125 - 125 - A

current
VCCI = 1.95 V 200 - 200 - A
VCCI = 2.7 V 300 - 300 - A
VCCI = 3.6 V 500 - 500 - A
VCCI = 5.5 V 900 - 900 - A
IBHHO bus hold HIGH A or B port [1][3]
overdrive VCCI = 1.6 V 125 - 125 - A

current
VCCI = 1.95 V 200 - 200 - A
VCCI = 2.7 V 300 - 300 - A
VCCI = 3.6 V 500 - 500 - A
VCCI = 5.5 V 900 - 900 - A
IOZ OFF-state A or B port; VO = 0 V or VCCO; [2] - 2 - 10 A
output current VCCO = 1.2 V to 5.5 V

Table 8. Static characteristics …continued

Min Max Min Max
IOFF power-off A port; VI or VO = 0 V to 5.5 V; - 2 - 10 A
leakage VCC(A) = 0 V;
current VCC(B) = 1.2 V to 5.5 V
B port; VI or VO = 0 V to 5.5 V; - 2 - 10 A
VCC(B) = 0 V;
VCC(A) = 1.2 V to 5.5 V
ICC supply current A port; VI = 0 V or VCCI; IO = 0 A [1]
VCC(A), VCC(B) = 1.2 V to 5.5 V - 8 - 8 A

VCC(A), VCC(B) = 1.65 V to 5.5 V - 3 - 3 A
VCC(A) = 5.5 V; VCC(B) = 0 V - 2 - 2 A
VCC(A) = 0 V; VCC(B) = 5.5 V 2 - 2 - A
B port; VI = 0 V or VCCI; IO = 0 A
VCC(A), VCC(B) = 1.2 V to 5.5 V - 8 - 8 A
VCC(A), VCC(B) = 1.65 V to 5.5 V - 3 - 3 A
VCC(B) = 0 V; VCC(A) = 5.5 V 2 - 2 - A
VCC(B) = 5.5 V; VCC(A) = 0 V - 2 - 2 A
A plus B port (ICC(A) + ICC(B));
IO = 0 A; VI = 0 V or VCCI
VCC(A), VCC(B) = 1.2 V to 5.5 V - 16 - 16 A
VCC(A), VCC(B) = 1.65 V to 5.5 V - 4 - 4 A
ICC additional per input;
supply current VCC(A), VCC(B) = 3.0 V to 5.5 V
A port; A port at VCC(A)  0.6 V; [4] - 50 - 75 A
DIR at VCC(A); B port = open
DIR input; DIR at VCC(A)  0.6 V; - 50 - 75 A
A port at VCC(A) or GND;
B port = open
B port; B port at VCC(B)  0.6 V; [4] - 50 - 75 A
DIR at GND; A port = open
[3] To guarantee the node switches, an external driver must source/sink at least IBHLO/IBHHO when the input is in the range VIL to VIH.
[4] For non bus hold parts only (74LVC2T45).

11. Dynamic characteristics

Table 9. Typical dynamic characteristics at VCC(A) = 1.2 V and Tamb = 25 C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for waveforms see Figure 7 and Figure 8.
Symbol Parameter Conditions VCC(B) Unit
1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
tPLH LOW to HIGH A to B 10.6 8.1 7.0 5.8 5.3 5.1 ns
propagation delay B to A 10.6 9.5 9.0 8.5 8.3 8.2 ns
tPHL HIGH to LOW A to B 10.1 7.1 6.0 5.3 5.2 5.4 ns
tPHZ HIGH to OFF-state DIR to A 9.4 9.4 9.4 9.4 9.4 9.4 ns
propagation delay DIR to B 12.0 9.4 9.0 7.8 8.4 7.9 ns
tPLZ LOW to OFF-state DIR to A 7.1 7.1 7.1 7.1 7.1 7.1 ns
tPZH OFF-state to HIGH DIR to A [1] 20.1 17.3 16.7 15.4 15.9 15.2 ns
propagation delay DIR to B [1] 17.7 15.2 14.1 12.9 12.4 12.2 ns
tPZL OFF-state to LOW DIR to A [1] 22.1 18.0 17.1 15.6 16.0 15.5 ns
[1] tPZH and tPZL are calculated values using the formula shown in Section 14.4 “Enable times”.
Table 10. Typical dynamic characteristics at VCC(B) = 1.2 V and Tamb = 25 C

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for waveforms see Figure 7 and Figure 8.
Symbol Parameter Conditions VCC(A) Unit
1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
tPLH LOW to HIGH A to B 10.6 9.5 9.0 8.5 8.3 8.2 ns
tPHL HIGH to LOW A to B 10.1 8.6 8.1 7.8 7.6 7.6 ns
tPHZ HIGH to OFF-state DIR to A 9.4 6.5 5.7 4.1 4.1 3.0 ns
tPLZ LOW to OFF-state DIR to A 7.1 4.9 4.5 3.2 3.4 2.5 ns
tPZH OFF-state to HIGH DIR to A [1] 20.1 15.4 13.6 11.7 11.0 10.7 ns
tPZL OFF-state to LOW DIR to A [1] 22.1 13.2 11.4 9.9 9.5 9.4 ns

Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions VCC(A) and VCC(B) Unit
1.8 V 2.5 V 3.3 V 5.0 V
CPD power dissipation A port: (direction A to B); 2 3 3 4 pF
capacitance B port: (direction B to A)
A port: (direction B to A); 15 16 16 18 pF
B port: (direction A to B)
[1] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of the outputs.
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL =  .
Table 12. Dynamic characteristics for temperature range 40 C to +85 C

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8.
1.5 V  0.1 V 1.8 V  0.15 V 2.5 V  0.2 V 3.3 V  0.3 V 5.0 V  0.5 V
Min Max Min Max Min Max Min Max Min Max
VCC(A) = 1.4 V to 1.6 V
tPLH LOW to HIGH A to B 2.8 21.3 2.4 17.6 2.0 13.5 1.7 11.8 1.6 10.5 ns
propagation delay B to A 2.8 21.3 2.6 19.1 2.3 14.9 2.3 12.4 2.2 12.0 ns
tPHL HIGH to LOW A to B 2.6 19.3 2.2 15.3 1.8 11.8 1.7 10.9 1.7 10.8 ns
tPHZ HIGH to OFF-state DIR to A 3.0 18.7 3.0 18.7 3.0 18.7 3.0 18.7 3.0 18.7 ns
propagation delay DIR to B 3.5 24.8 3.5 23.6 3.0 11.0 3.3 11.3 2.8 10.3 ns
tPLZ LOW to OFF-state DIR to A 2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 ns
tPZH OFF-state to HIGH DIR to A [1] - 39.6 - 36.3 - 24.3 - 22.5 - 21.4 ns
propagation delay DIR to B [1] - 32.7 - 29.0 - 24.9 - 23.2 - 21.9 ns
tPZL OFF-state to LOW DIR to A [1] - 44.1 - 40.9 - 24.2 - 22.6 - 21.3 ns
VCC(A) = 1.65 V to 1.95 V

Table 12. Dynamic characteristics for temperature range 40 C to +85 C …continued
1.5 V  0.1 V 1.8 V  0.15 V 2.5 V  0.2 V 3.3 V  0.3 V 5.0 V  0.5 V
VCC(A) = 2.3 V to 2.7 V
VCC(A) = 3.0 V to 3.6 V
VCC(A) = 4.5 V to 5.5 V

1.5 V  0.1 V 1.8 V  0.15 V 2.5 V  0.2 V 3.3 V  0.3 V 5.0 V  0.5 V
Table 13. Dynamic characteristics for temperature range 40 C to +125 C

1.5 V  0.1 V 1.8 V  0.15 V 2.5 V  0.2 V 3.3 V  0.3 V 5.0 V  0.5 V
VCC(A) = 1.4 V to 1.6 V
VCC(A) = 1.65 V to 1.95 V

1.5 V  0.1 V 1.8 V  0.15 V 2.5 V  0.2 V 3.3 V  0.3 V 5.0 V  0.5 V
VCC(A) = 2.3 V to 2.7 V
VCC(A) = 3.0 V to 3.6 V
VCC(A) = 4.5 V to 5.5 V

1.5 V  0.1 V 1.8 V  0.15 V 2.5 V  0.2 V 3.3 V  0.3 V 5.0 V  0.5 V
12. Waveforms
VI
nA, nB input VM
GND
tPHL tPLH
VOH
nB, nA output VM
VOL 001aaj644
Measurement points are given in Table 14.

VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. The data input (A, B) to output (B, A) propagation delay times
VI
DIR input VM
GND
t PLZ t PZL
VCCO
output
LOW-to-OFF VM
OFF-to-LOW VX
VOL
t PHZ t PZH
VOH
VY
output
HIGH-to-OFF VM
OFF-to-HIGH
GND
outputs outputs outputs
enabled disabled enabled
001aae968
Measurement points are given in Table 14.

VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. Enable and disable times

Table 14. Measurement points

Supply voltage Input[1] Output[2]
VCC(A), VCC(B) VM VM VX VY
1.2 V to 1.6 V 0.5VCCI 0.5VCCO VOL + 0.1 V VOH  0.1 V
tW
VI
90 %
negative
pulse VM VM
10 %
0V
tf tr
tr tf
VI
90 %
positive
pulse VM VM
10 %
0V
tW
VEXT
VCC
RL
VI VO
G DUT
RT CL RL
001aae331
Test data is given in Table 15.

RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance.
VEXT = External voltage for measuring switching times.
Fig 9. Test circuit for measuring switching times
Table 15. Test data

Supply voltage Input Load VEXT
VCC(A), VCC(B) VI[1] t/V[2] CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ[3]
1.2 V to 5.5 V VCCI  1.0 ns/V 15 pF 2 k open GND 2VCCO
[2] dV/dt  1.0 V/ns.

13. Typical propagation delay characteristics
001aai907 001aai908
14 14
tPHL tPLH
(ns) (ns)
12 12 (1)
(1)
10 10
(2)
8 (2) 8 (3)
(3)
(4) (4)
6 6 (5)
(5) (6)
(6)
4 4
2 2
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
CL (pF) CL (pF)
a. HIGH to LOW propagation delay (A to B) b. LOW to HIGH propagation delay (A to B)
001aai909 001aai910
14 14
tPHL tPLH
(ns) (ns)
12 12 (1)
(1) (2)
(3)
10 (2) 10 (4)
(3)
(5)
8 (4) 8
(5) (6)
(6)
6 6
4 4
2 2
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
CL (pF) CL (pF)
c. HIGH to LOW propagation delay (B to A) d. LOW to HIGH propagation delay (B to A)

(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 10. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 1.2 V

001aai911 001aai912
14 14
tPHL tPLH
(ns) (ns)
12 12
(1)
10 (1) 10
8 8 (2)
(2)
(3)
6 (3) 6
(4)
(4) (5)
4 4 (6)
(5)
2 (6) 2
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
CL (pF) CL (pF)
001aai913 001aai914
14 14
tPHL tPLH
(ns) (ns)
12 12
10 10
(1)
8 (1) 8 (2)
(2) (3)
(3) (4)
6 (4) 6
(5)
(5) (6)
4 (6) 4
2 2
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
CL (pF) CL (pF)

(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.

001aai915 001aai916
14 14
tPHL tPLH
(ns) (ns)
12 12
(1)
10 10
(1)
8 8
(2)
(2)
6 6 (3)
(3)
(4)
4 (4) 4 (5)
(5) (6)
(6)
2 2
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
CL (pF) CL (pF)
001aai917 001aai918
14 14
tPHL tPLH
(ns) (ns)
12 12
10 10
8 8 (1)
(1) (2)
6 (2) 6 (3)
(3) (4)
(4) (5)
4 (5) 4 (6)
(6)
2 2
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
CL (pF) CL (pF)

(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.

001aai919 001aai920
14 14
tPHL tPLH
(ns) (ns)
12 12
10 10 (1)
(1)
8 8
(2)
6 (2) 6
(3)
(3)
4 (4) 4 (4)
(5) (5)
(6) (6)
2 2
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
CL (pF) CL (pF)
001aai921 001aai922
14 14
tPHL tPLH
(ns) (ns)
12 12
10 10
8 8
(1)
6 (1) 6
(2)
(2) (3)
4 (3) 4 (4)
(4)
(5)
(5)
(6)
2 (6) 2
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
CL (pF) CL (pF)

(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.

001aai923 001aai924
14 14
tPHL tPLH
(ns) (ns)
12 12
10 10 (1)
(1)
8 8
(2)
6 (2) 6
(3)
(3)
4 (4) 4 (4)
(5) (5)
(6) (6)
2 2
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
CL (pF) CL (pF)
001aai925 001aai926
14 14
tPHL tPLH
(ns) (ns)
12 12
10 10
8 8
6 (1) 6 (1)
(2) (2)
4 (3) 4 (3)
(4) (4)
(5) (5)
2 (6) 2 (6)
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
CL (pF) CL (pF)

(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.

001aai927 001aai928
14 14
tPHL tPLH
(ns) (ns)
12 12
10 10 (1)
(1)
8 8
(2)
6 (2) 6
(3) (3)
4 (4) 4
(4)
(5) (5)
(6) (6)
2 2
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
CL (pF) CL (pF)
001aai929 001aai930
14 14
tPHL tPLH
(ns) (ns)
12 12
10 10
8 8
6 (1) 6
(1)
(2) (2)
4 4
(3) (3)
(4) (4)
2 (5) 2 (5)
(6) (6)
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
CL (pF) CL (pF)

(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 15. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 5 V

14. Application information
14.1 Unidirectional logic level-shifting application

The circuit given in Figure 16 is an example of the 74LVC2T45; 74LVCH2T45 being used
in a unidirectional logic level-shifting application.
VCC1 VCC2
VCC1 VCC(A) VCC(B) VCC2

1 8
1A 1B
2
74LVC2T45 7
2A 74LVCH2T45 2B
3 6
VCC1 GND DIR VCC2

4 5
system-1 system-2
001aai931
Fig 16. Unidirectional logic level-shifting application
Table 16. Description of unidirectional logic level-shifting application

Pin Name Function Description
1 VCC(A) VCC1 supply voltage of system-1 (1.2 V to 5.5 V)
2 1A OUT output level depends on VCC1 voltage
3 2A OUT output level depends on VCC1 voltage
4 GND GND device GND
5 DIR DIR the GND (LOW level) determines B port to A port direction
6 2B IN input threshold value depends on VCC2 voltage
7 1B IN input threshold value depends on VCC2 voltage
8 VCC(B) VCC2 supply voltage of system-2 (1.2 V to 5.5 V)
14.2 Bidirectional logic level-shifting application

Figure 17 shows the 74LVC2T45; 74LVCH2T45 being used in a bidirectional logic
level-shifting application. Since the device does not have an output enable pin, the system
designer should take precautions to avoid bus contention between system-1 and
system-2 when changing directions.

VCC1 VCC1 VCC2 VCC2
VCC(A) VCC(B)
I/O-1 PULL-UP/DOWN 1 8 PULL-UP/DOWN I/O-2
1A 1B
2
74LVC2T45 7
2A 74LVCH2T45 2B
3 6
GND DIR
4 5
DIR CTRL DIR CTRL
system-1 system-2 001aai932
Pull-up or pull-down only needed for 74LVC2T45.

Fig 17. Bidirectional logic level-shifting application
Table 17 gives a sequence that will illustrate data transmission from system-1 to system-2
and then from system-2 to system-1.
Table 17. Description of bidirectional logic level-shifting application[1]

State DIR CTRL I/O-1 I/O-2 Description
1 H output input system-1 data to system-2
2 H Z Z system-2 is getting ready to send data to system-1. I/O-1 and I/O-2
are disabled. The bus-line state depends on bus hold
3 L Z Z DIR bit is set LOW. I/O-1 and I/O-2 still are disabled. The bus-line
state depends on bus hold
4 L input output system-2 data to system-1
[1] H = HIGH voltage level;

L = LOW voltage level;
Z = high-impedance OFF-state.
14.3 Power-up considerations

The device is designed such that no special power-up sequence is required other than
GND being applied first.
Table 18. Typical total supply current (ICC(A) + ICC(B))

VCC(A) VCC(B) Unit
0V 1.8 V 2.5 V 3.3 V 5.0 V
0V 0 <1 <1 <1 <1 A
1.8 V <1 <2 <2 <2 2 A
2.5 V <1 <2 <2 <2 <2 A
3.3 V <1 <2 <2 <2 <2 A
5.0 V <1 2 <2 <2 <2 A

14.4 Enable times

Calculate the enable times for the 74LVC2T45; 74LVCH2T45 using the following
formulas:
• tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)

• tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
• tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
• tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the
time the DIR bit is switched until an output is expected. For example, if the 74LVC2T45;
74LVCH2T45 initially is transmitting from A to B, then the DIR bit is switched, the B port of
the device must be disabled before presenting it with an input. After the B port has been
disabled, an input signal applied to it appears on the corresponding A port after the
specified propagation delay.

15. Package outline
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1
D E A
X
y HE v M A
8 5
A2
A
A1
(A3)
pin 1 index
θ
Lp
L
1 4 detail X
e w M
bp
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A D(1)
UNIT A1 A2 A3 bp c E(2) e HE L Lp Q v w y Z(1) θ
max.
0.15 0.85 0.27 0.23 2.1 2.4 3.2 0.40 0.21 0.4 8°
mm 1 0.12 0.5 0.4 0.2 0.13 0.1
0.00 0.60 0.17 0.08 1.9 2.2 3.0 0.15 0.19 0.1 0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
SOT765-1 MO-187 02-06-07
Fig 18. Package outline SOT765-1 (VSSOP8)

XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1
b
1 2 3 4
4×
L (2)
L1
8 7 6 5
e1 e1 e1
8× A
(2)
A1
terminal 1
index area
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A(1) A1 b D E e e1 L L1
max max
0.25 2.0 1.05 0.35 0.40
mm 0.5 0.04 0.6 0.5
0.17 1.9 0.95 0.27 0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
07-11-14
SOT833-1 --- MO-252 ---
07-12-07
Fig 19. Package outline SOT833-1 (XSON8)

XSON8: extremely thin small outline package; no leads;

8 terminals; body 1.35 x 1 x 0.5 mm SOT1089
terminal 1
index area
D A
A1
detail X
(4×)(2)
e
L
(8×)(2)
b 4 5
e1
1 8
terminal 1
index area L1 X
0 0.5 1 mm
Dimensions scale
Unit A(1) A1 b D E e e1 L L1
max 0.5 0.04 0.20 1.40 1.05 0.35 0.40

mm nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35
min 0.12 1.30 0.95 0.27 0.32
Note
2. Visible depending upon used manufacturing technology. sot1089_po
Outline References European

Issue date
version IEC JEDEC JEITA projection
10-04-09
SOT1089 MO-252
10-04-12
Fig 20. Package outline SOT1089 (XSON8)


XSON8: plastic extremely thin small outline package; no leads;

8 terminals; body 3 x 2 x 0.5 mm SOT996-2
D B A
E A A1
detail X
terminal 1
index area
e1
C
v C A B
L1 e b
w C y1 C y
1 4
L2
8 5
X
0 1 2 mm
scale
Dimensions (mm are the original dimensions)
Unit(1) A A1 b D E e e1 L L1 L2 v w y y1
max 0.05 0.35 2.1 3.1 0.5 0.15 0.6

mm nom 0.5 0.5 1.5 0.1 0.05 0.05 0.1
min 0.00 0.15 1.9 2.9 0.3 0.05 0.4
sot996-2_po

Issue date
07-12-21
SOT996-2
12-11-20
Fig 21. Package outline SOT996-2 (XSON8)

XQFN8: plastic, extremely thin quad flat package; no leads;

8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-2
D B A
terminal 1
index area
E A
A1
detail X
e
C
v C A B
b
w C y1 C y
4
3 5
e1
2 6
1 7
terminal 1 8
index area L metal area
not for soldering
L1
0 1 2 mm
Dimensions scale
Unit(1) A A1 b D E e e1 L L1 v w y y1
max 0.5 0.05 0.25 1.65 1.65 0.35 0.15

mm nom 0.20 1.60 1.60 0.55 0.5 0.30 0.10 0.1 0.05 0.05 0.05
min 0.00 0.15 1.55 1.55 0.25 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. sot902-2_po

Issue date
10-11-02
SOT902-2 --- MO-255 ---
11-03-31
Fig 22. Package outline SOT902-2 (XQFN8)


8 terminals; body 1.2 x 1.0 x 0.35 mm SOT1116
b
1 2 3 4 (4×)(2)
L1 L
8 7 6 5
e1 e1 e1
(8×)(2)
A1 A
terminal 1
index area
0 0.5 1 mm
Dimensions scale
max 0.35 0.04 0.20 1.25 1.05 0.35 0.40

mm nom 0.15 1.20 1.00 0.55 0.3 0.30 0.35
min 0.12 1.15 0.95 0.27 0.32
Note

Issue date
10-04-02
SOT1116
10-04-07


8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203
b
1 2 3 4 (4×)(2)
L1 L
8 7 6 5
e1 e1 e1
(8×)(2)
A1 A
terminal 1
index area
0 0.5 1 mm
Dimensions scale
max 0.35 0.04 0.20 1.40 1.05 0.35 0.40

mm nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35
min 0.12 1.30 0.95 0.27 0.32
Note

Issue date
10-04-02
SOT1203
10-04-06

16. Abbreviations
Table 19. Abbreviations
Acronym Description
CDM Charged Device Model
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
17. Revision history

Table 20. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC_LVCH2T45 v.8 20130329 Product data sheet - 74LVC_LVCH2T45 v.7
Modifications: • For type numbers 74LVC2T45GD and 74LVCH2T45GD XSON8U has changed to XSON8.
Modifications: • For type numbers 74LVC2T45GM and 74LVCH2T45GM the SOT code has changed to
SOT902-2.
Modifications: • Legal pages updated.
74LVC_LVCH2T45 v.1 20081118 Product data sheet - -

18. Legal information
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Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions malfunction of an NXP Semiconductors product can reasonably be expected

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damage. NXP Semiconductors accepts no liability for inclusion and/or use of
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representations or warranties as to the accuracy or completeness of Applications — Applications that are described herein for any of these
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use of such information. representation or warranty that such applications will be suitable for the
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Limited warranty and liability — Information in this document is believed to Limiting values — Stress above one or more limiting values (as defined in
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Semiconductors accepts no liability for inclusion and/or use of standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer 18.4 Trademarks
(a) shall use the product without NXP Semiconductors’ warranty of the
Notice: All referenced brands, product names, service names and trademarks
product for such automotive applications, use and specifications, and (b)
are the property of their respective owners.
whenever customer uses the product for automotive applications beyond
19. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]

20. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Recommended operating conditions. . . . . . . . 5
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 10
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
13 Typical propagation delay characteristics . . 17
14 Application information. . . . . . . . . . . . . . . . . . 23
14.1 Unidirectional logic level-shifting application . 23
14.2 Bidirectional logic level-shifting application. . . 23
14.3 Power-up considerations . . . . . . . . . . . . . . . . 24
14.4 Enable times . . . . . . . . . . . . . . . . . . . . . . . . . . 25
15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26
16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 33
17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 33
18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 34
18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 34
18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 35
19 Contact information. . . . . . . . . . . . . . . . . . . . . 35
20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 29 March 2013
Document identifier: 74LVC_LVCH2T45

74LVC2T45 74LVCH2T45: 1. General Description

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74LVC2T45 74LVCH2T45: 1. General Description

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74LVC2T45; 74LVCH2T45

Dual supply translating transceiver; 3-state

2. Features and benefits

Product data sheet Rev. 8 — 29 March 2013 2 of 36

Table 2. Marking …continued

Fig 1. Logic symbol Fig 2. Logic diagram

001aai904 Transparent top view

Fig 3. Pin configuration SOT765-1 Fig 4. Pin configuration SOT833-1, SOT1089,

Product data sheet Rev. 8 — 29 March 2013 3 of 36

Transparent top view Transparent top view

Fig 5. Pin configuration SOT996-2 Fig 6. Pin configuration SOT902-2

6.2 Pin description

Product data sheet Rev. 8 — 29 March 2013 4 of 36

9. Recommended operating conditions

Product data sheet Rev. 8 — 29 March 2013 5 of 36

10. Static characteristics

Product data sheet Rev. 8 — 29 March 2013 6 of 36

Table 8. Static characteristics

input voltage VCCI = 1.2 V 0.8VCCI - 0.8VCCI - V

input voltage VCCI = 1.2 V - 0.2VCCI - 0.2VCCI V

Product data sheet Rev. 8 — 29 March 2013 7 of 36

Table 8. Static characteristics …continued

output voltage IO = 100 A; - 0.1 - 0.1 V

current VI = 0.49 V; VCCI = 1.4 V 15 - 10 - A

current VI = 0.91 V; VCCI = 1.4 V 15 - 10 - A

overdrive VCCI = 1.6 V 125 - 125 - A

overdrive VCCI = 1.6 V 125 - 125 - A

Product data sheet Rev. 8 — 29 March 2013 8 of 36

Table 8. Static characteristics …continued

VCC(A), VCC(B) = 1.2 V to 5.5 V - 8 - 8 A

Product data sheet Rev. 8 — 29 March 2013 9 of 36

11. Dynamic characteristics

Table 10. Typical dynamic characteristics at VCC(B) = 1.2 V and Tamb = 25 C

Product data sheet Rev. 8 — 29 March 2013 10 of 36

Table 12. Dynamic characteristics for temperature range 40 C to +85 C

Product data sheet Rev. 8 — 29 March 2013 11 of 36

Product data sheet Rev. 8 — 29 March 2013 12 of 36

Table 13. Dynamic characteristics for temperature range 40 C to +125 C

Product data sheet Rev. 8 — 29 March 2013 13 of 36

Product data sheet Rev. 8 — 29 March 2013 14 of 36

Measurement points are given in Table 14.

Measurement points are given in Table 14.

Product data sheet Rev. 8 — 29 March 2013 15 of 36

Table 14. Measurement points

Test data is given in Table 15.

Table 15. Test data

Product data sheet Rev. 8 — 29 March 2013 16 of 36

13. Typical propagation delay characteristics

a. HIGH to LOW propagation delay (A to B) b. LOW to HIGH propagation delay (A to B)

c. HIGH to LOW propagation delay (B to A) d. LOW to HIGH propagation delay (B to A)

Product data sheet Rev. 8 — 29 March 2013 17 of 36

a. HIGH to LOW propagation delay (A to B) b. LOW to HIGH propagation delay (A to B)

c. HIGH to LOW propagation delay (B to A) d. LOW to HIGH propagation delay (B to A)

Product data sheet Rev. 8 — 29 March 2013 18 of 36

a. HIGH to LOW propagation delay (A to B) b. LOW to HIGH propagation delay (A to B)

c. HIGH to LOW propagation delay (B to A) d. LOW to HIGH propagation delay (B to A)

Product data sheet Rev. 8 — 29 March 2013 19 of 36

a. HIGH to LOW propagation delay (A to B) b. LOW to HIGH propagation delay (A to B)

c. HIGH to LOW propagation delay (B to A) d. LOW to HIGH propagation delay (B to A)