Average Current Mode Control of Switching Power Supplies: Application Note U - 1 4 0
Average Current Mode Control of Switching Power Supplies: Application Note U - 1 4 0
Average Current Mode Control of Switching Power Supplies: Application Note U - 1 4 0
APPLICATION NOTE
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APPLICATION NOTE U-140
there is a limit to loop gain at the switching Example 1: Buck Regulator Output Current.
frequency in order to achieve stability. The simple buck regulator shown in Fig. 2 has
3) Noise immunity is excellent. When the the following operating parameters:
clock pulse turns the power switch on, the
oscillator ramp immediately dives to its lowest Switching Frequency, f’ = 100 kHz
level, volts away from the corresponding cur- Input Voltage, V,N = 15 - 30V
rent error level at the input of the PWM Output Voltage, V 0 = 12V
comparator. Output Current, I, = 5A (6A O.L.)
4) The average current mode method can be I n d u c t a n c e , L = 60 PH
used to sense and control the current in any max. MO @ 30V (100 kHz) = 1.2A
circuit branch. Thus it can control input current Sense Resistance, R, = 0.10
accurately with buck and flyback topologies, CFp is temporarily omitted. Zero R, CFz is
and can control output current with boost and well below the switching frequency. Near fs ,
flyback topologies. the amplifier gain is flat. The overall current
Designing the Optimum Control Loop loop has only one active pole (from the induc-
Gain Limitation at f s: Switching power tor).
supply control circuits all exhibit subharmonic The inductor current is sensed through R,.
oscillation problems if the slopes of the wave- (How this is accomplished will be discussed
forms applied to the two inputs of the PWM later.) The inductor current waveform with its
comparator are inappropriately related. sawtooth ripple component is amplified and
With peak current mode control, slope inverted through the CA and applied to the
compensation prevents this instability. comparator. The inductor current downslope
Average current mode control has a very (while the switch is off) becomes an upslope, as
similar problem, but a better solution. The shown in Fig. 2. To avoid subharmonic oscilla-
oscillator ramp effectively provides a great tion, this off-time CA output slope must not
amount of slope compensation. One criterion exceed the oscillator ramp slope. In Fig. 2, the
applies in a single pole system: The amplified off-time CA output slope is much less than the
inductor current downslope at one input of the oscillator ramp slope, indicating that the CA
PWM comparator must not exceed the oscillator gain is less than optimum.
ramp sIope at the other comparator input. This Calculating the slopes:
criterion puts an upper limit on the current Inductor Current Downslope = Vo/L
amplifier gain at the switching frequency, O s c i l l a t o r R a m p S l o p e = Vs/Ts = Vsf s
indirectly establishing the maximum current
loop gain crossover frequency, fc. It is the first Where V s is the oscillator ramp p-p voltage, Ts
thing that needs to be considered in optimizing and fs are the switching period and frequency.
the average current mode
control loop.
In the following exam-
ples, we assume that the
power circuit design has
been completed, and only
the CA c o m p e n s a t i o n
remains to be worked out.
3-358
APPLICATION NOTE U-140
The inductor current downslope is translated to 63°, and boosts the low frequency gain
into a voltage across current sense resistor Rs dramatically, with an integrator gain of 250K/f.
and multiplied by the CA gain, GU This is set It is this characteristic which causes the current
equal to the oscillator ramp slope to determine loop to rapidly and accurately home in on the
the CA gain allowed at fs: average current called for by the outer loop.
Even though the comparator actually turns off
the power switch when a peak inductor current
is reached, this peak current level is adjusted
by the current amplifier so that the average
current is correct.
Applying the values given in the example, and Fig. 3 shows the start-up waveforms of the
with Vs of 5Vpp, the maximum GCA at the voltages at the PWM comparator inputs and
switching frequency is 25 (28dB). The current the inductor current with V,, at 30V and full
error amplifier gain at fs is set to this optimum load. Note how the amplified and inverted
value by making the ratio RJR, = 25. inductor current downslope virtually coincides
The small-signal control-to-output gain of with the oscillator ramp, because the CA gain
the buck regulator current loop power section was set at the optimum level according to
(from vcA at the CA output, to vRS, the voltage Equation (1). Note also that if the CA gain is
across R S ) is: increased further, not only will the off-time
slope exceed the oscillator ramp slope, but the
positive excursion may reach the CA compli-
ance limit, clipping or clamping the waveform.
The overall open loop gain of the current
loop is found by multiplying (1) and (2). The
result is set equal to 1 to solve for the loop
gain crossover frequency, fc :
Setting the CA gain at the limit found in (1), Fig. 3 - Buck Waveforms, Optimized Gain
the crossover frequency will never be less than
one sixth of the switching frequency. (This is Pole R, CFP CFz/(CFP+ CFz) is set at switch-
exactly the same result reported by Middle- ing frequency fs (100 kHz). This pole has one
brook [1] for peak current mode control with purpose-to eliminate noise spikes riding on the
recommended slope compensation.) In this current waveform, the nemesis of peak current
example, fc is 20 kHz with VI, at 15V (D= .8), mode control. The sawtooth CA output wave-
and 40 kHz when V,, at 30V (D= .4). form is also diminished, especially the higher
If the error amplifier had a flat gain charac- order harmonics, and shifted in phase as shown
teristic, the phase margin at crossover would be in Fig. 4. The pole-zero pair (at 100 kHz and
90° -much more than required-and the gain 10 kHz) reduces the phase margin at crossover
at lower frequencies wouldn’t be much better to a very acceptable 45° -see Fig. 5.
than with peak current mode control. But zero The reduced amplitude and slopes of the CA
R, Cn placed at 10 kHz, below the minimum waveform resulting from the 100 kHz pole
crossover frequency, reduces the phase margin might suggest that the CA gain could be in-
3-359
APPLICATION NOTE U-140
Discontinuous Operation. When the load
current I, becomes small, the inductor current
becomes discontinuous. The current level at the
continuous/discontinuous mode boundary is:
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APPLICATION NOTE U-140
Example 2: Boost Regulator Input Current. this application, the maximum G, is 6.58,
A 1 kW off-line preregulator (Fig 6) operates accomplished by making RF/RI = 6.58.
with the following parameters: The small-signal control-to-input gain of the
Switching Frequency, fs = 100 kHz current loop power section (from vGa at the CA
Input Volts, v’N = 90 - 270V rms output, to VRS, the voltage across R,) is:
output Volts, & = 380Vdc
Max. O.L. I IN (@90V) = 12A rms, 17A pk (7)
L = 0.25mH
AIL, AlrN @90V = 3.4A Note that (7) is nearly identical to (2) for
Rs = 0.05n the buck regulator, except the gain depends on
The max. overload line current at min. vlN V. (which is constant), rather than Vl,,, .
corresponds to 1080W input. The max. peak The overall current loop gain is found by
overload 60Hz line current (17A) should-by multiplying (6) and (7). The result is set equal
design-correspond to a limit on the current to 1 to solve for the crossover frequency, fc :
programming signal, I,,. The max peak 100kHz
current through the switch and rectifier is 17A
plus one-half ML: 17 + 3.4/2 = 18.7A
(8)
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APPLICATION NOTE U-140
Referring back to Fig. 6 — when the current current level. However, average current mode
loop is closed, the voltage across current sense control eliminates the peak/average error. A
resistor I& equals the voltage across current small inductance can and should be used to
programming resistor VRcP. In this case, pro- reduce cost, size and weight and improve
grammed with a current source I,, the current current loop bandwidth.
gain of the closed current loop is: Figure 9 shows a boost preregulator pro-
grammed to follow a 60 Hz (rectified) sine
(9) wave input. The lower waveforms show the
programmed and actual line current waveforms.
The closed loop current gain rolls off and (The programmed waveform has been in-
assumes a single pole characteristic at the open creased by 5% to make the two waveforms
loop crossover frequency, fs. visible. The actual waveform leads the pro-
grammed waveform by a small amount and has
less than 0.5% 3rd harmonic distortion! The
upper waveforms show the duty cycles of the
switch and diode throughout the line cycle. The
inductor current is continuous when the current
is high, and the switch and diode duty cycles
add up to 1. But as the current approaches
zero crossing, operation becomes discontinuous
as shown by the appearance of “dead” time
(when neither the switch, the diode, or the
inductor are conducting).
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APPLICATION NOTE U-140
3-363
APPLICATION NOTE U-140
the switch, the inductor, and the rectifier are This is the characteristic of a “normal”
much greater than the 60 Hz peak current-see zero-a -1 slope with 90° phase lag below fi
Fig. 12. The worst case, at low line and max. and flat gain with no phase shift above fi. The
overload input current is: zero frequency may be calculated:
(11)
Add to this one-half ML to obtain the abso- Note that the zero moves inversely with
lute max. peak current through the switch, inductor current and inductance value. This
inductor, and rectifier: 24.2 + 3.6/2 = 26A.
zero has a big effect on loop compensation. To
Compared to the boost converter, the fly-
obtain the best loop response, it is important
back topology requires higher current and
that firni,, be as high as possible, by making the
higher voltage devices and generates a lot more
inductance small. Fortunately, with average
input noise because of the chopped waveform.
current mode control, there is no need to
In its favor, the flyback converter can operate
worry about crossing into discontinuous opera-
with any input/output voltage ratio, can provide
tion. The limit on making the inductance too
current limiting, and input/output isolation.
small is when the inductor ripple current
As discussed in the previous example, the
becomes too large, increasing peak switch and
boost converter amplifier gain at fS was limited
rectifier currents an undesirable amount.
only by the criteria that the inductor current
Using the specific values of this example, the
downslope must not exceed the oscillator ramp
power circuit gain is:
slope. The power circuit control-to-input cur-
rent gain had a simple -1 slope from zero to
fS, making it very easy to compensate.
But with the flyback converter, the chopped
switch current waveform will be averaged. This The minimum zero frequency is 8 kHz,
results in a lower crossover frequency, f,, and which occurs at 24.2A, the max. overload
lower gain-bandwidth for two reasons: inductor current at 90V low line. The gain
above fi is 0.12 (-18.4dB). The power circuit
1. The large amplitude chopped current wave-
gain is shown in the Bode plot of Fig. 13.
form must be integrated by the CA. The
Turning now to the current error amplifier
upslope of the resulting triangular waveform
(Fig. 11), the chopped input (switch) current
at the CA output must not exceed the oscil-
waveform shown in Fig. 12 flows through R,.
lator ramp slope. (The inductor current
The average value of this waveform, chopped
downslope is not relevant.)
at 100 kHz, is compared to the current pro-
2. There is a zero (conventional left half-plane)
gram level across R,and amplified. Assume
in the control-to-input current gain charac-
for the moment that CP,, is zero and C, is
teristic. This zero moves with output current
shorted. The CA gain in the vicinity of 100
level. Loop gain crossover cannot be much
kHz is determined by integrator (R,+R,,)CF,.
higher than the lowest zero frequency.
Averaging is accomplished because the DC
The small-signal control-to-input gain of the gain is high, but the 100 kHz rectangular
flyback current loop power circuit (from vcA at waveform with its harmonics is amplified
the CA output, to vRs , the voltage across R, ) relatively little. The rectangular waveform is
is: converted into a triangular wave as shown in
Fig. 12.
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APPLICATION NOTE U-140
Equating the slopes and solving for CFp:
(12)
The optimum CA integtator gain at 100 kHz The CA integrator gain may now be calcu-
is the gain at which the maximum CA output lated and entered in the Bode plot:
upslope equals the oscillator ramp slope. This is
(13)
the same principle used in the previous two
examples, but in those cases the inductor
(whose current was being controlled) did most The compensation circuit as designed so far
of the averaging. The inductor did the inte- (with C,, zero and CFZ open) has high loop
gration to provide the triangular ripple current gain and is very stable only when the inductor
waveform and the CA gain was flat in the current is high, maintaining the power circuit
vicinity of js. But in this flyback preregulator zero near the position shown in Fig. 13, so that
example, the chopped switch current is being its gain is flat at fc. At lower current levels, the
controlled so the averaging and the triangular power circuit zero slides down to the right and
waveshape are achieved by an integrating
amplifier.
The upslope of the CA output occurs when
the switch is off and the 100 kHz current
waveform is at zero. The CA inputs are both at
program voltage V& . Vc- equates to the
max. overload peak 60Hz input current (17A)
through R,. Therefore, during the switch “off”
time, the maximum current through
R = (R,+R& i s :
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APPLICATION NOTE U-140
the power circuit gain at fC has a -1 slope. With Just as in the previous examples, the closed
the -1 slope of the CA gain, the overall current loop current gain rolls off and assumes a single
loop gain has a slope of -2 at crossover, and pole characteristic at the open loop crossover
will ring excessively. It is necessary to add a frequency, fs. The moving zero of the flyback
pole-zero pair to the CA gain to reduce the power circuit is hidden within the inner current
slope to -1 in the vicinity of fc. Offsetting the loop, and is invisible to the outer voltage
integrator gain by a factor of 5, as shown in the control loop. In fact-regardless of the power
Bode plot, provides a phase bump which in- circuit topology-with average current mode
creases the actual phase margin to 42°, a control, the external characteristics of the cur-
slightly underdamped condition (the Bode rent loops are identical: flat gain, rolling off
approximation is 31°, as shown). with a single pole characteristic above the open
The offset factor of 5 is provided by loop crossover frequency.
cm = 4c, = 340pF. Cn and CFp in parallel Example 4: Buck Regulator Input Current:
set the integrator gain at low frequencies to The buck regulator is sometimes used in high
37,000/f. power factor preregulator applications. It can
The location of the flat portion of the CA only function when V0 is less than l&, so the
gain characteristic is determined by R,. It is output bus voltage must be low. Normally, a
easiest to solve this graphically using the Bode low output voltage should be avoided, because
plot. Ideally, Z1 and P1 should bracket the the bus filter capacitor becomes large and
crossover frequency. Simply slide the flat por- expensive, but in applications such as telephone
tion up and down between the integrator slopes or battery charging this is not a problem
until its gain is equal (but opposite in sign) to and/or there is no choice. With 120V line input
the power circuit gain at the same frequency as and 48 volt output bus, the input current will
the center of the flat potion. That frequency is drop to zero for a substantial portion of each
the crossover frequency, fc In Fig 13, the CA line cycle, each time the instantaneous line
gain in the flat portion is 10 (20dB). This is voltage goes below 48V. Third harmonic distor-
accomplished by: tion will be 7 - 8% at low line, but the power
factor of 0.99 is good enough for most applica-
tions.
Although the flyback topology might be used
The precise value of R, (and fc) is not at all
in the same low voltage output application, the
critical. The phase bump is broad, and the loop
buck topology operates with lower inductor
response is really determined by the integrator
current and lower peak current through the
gain below fc (37,000/f).
switch and rectifier. Peak voltages on the
Finally, an additional pole RPZCPZ is placed at
switch and rectifier are also much lower. But
100kHz to filter out noise spikes. This pole
the flyback topology can provide line isolation
frequency is too high to significantly affect
in the preregulator by using a flyback trans-
phase margin at crossover.
former instead of simple inductor.
Referring back to Fig. 11 — when the cur-
The buck circuit can be almost the same as
rent loop is closed, the voltage across current
the flyback circuit of Fig. 11, interchanging the
sense resistor I& equals the voltage across
inductor and the rectifier (cathode up).
current programming resistor v&P Program-
The control loop design procedure is the
med with a current source Icp the current gain
same as for the flyback in Example 3. The
of the closed current loop is identical to Eq. 9:
buck regulator has the same left half-plane
zero. In fact, the power circuit control-to-input
gain equation is identical to Eq. 10 for the
flyback circuit.
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APPLICATION NOTE U-140
Controlling Average Rectifier Current is sensed and controlled.
Peak current mode control has been used The small-signal control-to-output gain of
with great success in conventional power sup- the flyback current loop power circuit (from
plies using buck-derived topologies. It works vcA at the CA output, to vRs , the voltage across
well because peak current mode control actual- R,) i s :
ly controls inductor current, and the inductor is
located in the output of all buck topologies.
When boost or flyback topologies are used,
peak current mode control functions poorly,
because the wrong current is controlled-the The same equation applies to controlling the
inductor current is not in the output. Although output current of a boost circuit. Note the
peak current mode control eliminates the similarity with Eq. 10 for flyback or buck input
inductor from the small-signal characteristic of current control. In Eq. 16, low frequency gain
the outer loop, the right half-plane zero present d e p e n d s o n V,N rather than V& but more
in boost and flyback outputs remains to plague importantly, the inductor current It has a
outer loop compensation. minus sign, which represents 180° phase lag
In boost or flyback circuits, the diode is in above the zero frequency. This is the character-
the output side, and ideally the diode current istic of a right half-plane zero, and it makes the
should be controlled, not inductor current. This loop compensation much more difficult. It is
is no problem for average current mode con- usually necessary to cross over at a frequency
trol. Its integrating current error amplifier can one half to one fourth of the RHP zero fre-
average the rectangular diode current waveform quency in order to cross over with adequate
in the same way that it averages the switch phase margin. This results in lower closed loop
current in the input of the buck or flyback bandwidth for the current loop than the previ-
preregulators discussed earlier. The right half- ous examples. However, once this is accom-
plane zero forces a lower current loop cross- plished, the RHP zero does not appear in the
over frequency, but the RHP zero is “buried” outer loop.
within the current loop. The outer voltage It is very important to make the inductance
control loop sees only a flat gain characteristic small to achieve the highest possible RHP zero
with a single pole roll-off at the crossover frequency. Fortunately, average current mode
frequency-just the same as all the other topol- control allows the mode boundary to be
ogies previously discussed. A flyback circuit crossed. This permits a much smaller induc-
using average current mode control is shown in tance than with peak current mode control,
Figure 14. resulting in a much higher RHP zero frequency
and higher crossover frequency.
Current Sensing
One important advantage of having a high
gain current error amplifier is that it permits a
very small current sense resistor value resulting
in low power dissipation. The CA can make up
for the gain lost with the small resistor.
In many applications, however, using a
current sense resistor in the direct path of the
Fig. 14 - Flyback Output Current Control
current to be measured is not practical. The
The circuit is almost identical to the flyback tiny R, value may be difficult to implement,
preregulator of Fig. 11, except output current and the power dissipation in a practical sense
3-367
APPLICATION NOTE U-140
resistor is too great. Often, the R, circuit converter because the DC value is lost, and the
location is at a large potential difference from C.T. cannot reset-it will saturate. The same
the control circuit. This is especially a concern problem occurs in a buck regulator circuit,
when current must be sensed on the other side where the C.T. can’t directly sense average
of the isolation boundary. output (inductor) current.
A current sense transformer (C.T.) can The answer to this problem is to use t w o
provide the necessary dielectric isolation and C.T.s–one sensing switch current, the other
eliminate the need for an extreme low-value sensing diode current. By summing their out-
resistor. As shown in Fig. 15, this technique puts as shown in Fig. 16, the true inductor
current is reconstituted. Each C.T. has plenty
of time to reset.
F i g . 1 5
works well for average current mode control
when the current to be sensed and averaged is
a pulse which returns to zero within each
switching period-such as switch current (buck F i g . 1 6
or flyback input current) or diode current
(boost or flyback output current). Although Using Current Sense Transformers:
“transformers can’t couple DC”, a C.T. does It is not difficult to achieve excellent results
couple the entire instantaneous current wave- using low cost commercially available pulse
form including its DC component if the core is transformers. A current sense “inductor” such
reset to zero baseline each time the pulse goes as Pulse Engineering 51688 is a toroidal core
to zero. wound with 200 secondary turns for a second-
Total reset requires the same volt-seconds ary inductance of 80 mH. A 0.18” hole is
(of opposite sign) that were applied to “set” provided to slip the primary wire through.
the core. At duty cycles approaching 1.0-which The pulse voltage across the windings of a
can occur temporarily with most topologies-the current transformer generates a magnetizing
time available for reset may be only a tiny current which starts at zero and increases fairly
fraction of the switching period. Achieving total linearly with time. The magnetizing current
reset in a short time requires a large backswing subtracts from the pulse current delivered to
of voltage across the C.T., so don’t use low the secondary. Initially, the current through R,
voltage diodes to couple the C.T. to R,. is precisely IPRI/N, but as time passes, the
With a boost converter controlling input secondary current drops off more rapidly than
current in a high power factor preregulator it should, This effect is called “droop”. It is
application, a current sense resistor easily ties usually not a problem if certain precautions are
in directly with the control circuit, as shown in observed. The amount of current droop
Fig. 6. Nevertheless, many designers would through the current sense resistor can be
prefer to use a current transformer to minimize calculated:
power loss and allow the use of a much higher
R, value. However, since the input current of
a boost converter is the inductor current, the
input current never goes to zero when operat- where N is the turns ratio, V’ the voltage
ing in the continuous mode. Therefore, a C.T.. across the secondary, L, the secondary induc-
can’t be used to sense input current of a boost tance and At is the max. pulse width. As the
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a
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