Avionics PA Design With Cree's CGHV27030S Amplifier: Eric Bonelli

Avionics PA Design with Cree’s CGHV27030S Amplifier
Eric Bonelli
CREE CONFIDENTIAL & PROPRIETARY © 2018 Cree, Inc. All rights reserved. Cree®, the Cree logo, Wolfspeed®, and the Wolfspeed logo are registered trademarks of Cree, Inc.
Background
• Graduated with my B.A.Sc in Electrical Engineering

from New Jersey Institute of Technology in 2017,
with a concentration in RF and Microwaves.
• Completed my Graduate Certificate in LTE and RF
communications from North Carolina State
University in 2020.
• Worked for Cree for 3 years, and am currently
working as an RF Applications Engineer, focusing on
supporting the aerospace and defense product line.
• Email Address: [email protected]
2 CREE CONFIDENTIAL & PROPRIETARY © 2018 Cree, Inc. All rights reserved. Cree®, the Cree logo, Wolfspeed®, and the Wolfspeed logo are registered trademarks of Cree, Inc.
Introduction
• Today we will discuss the design process for creating a power amplifier using
Cree GaN HEMT RF models in AWR.
• The focus will be on the CGHV27030S, which is a 50V surface mount transistor
housed in a DFN package.
• The design process will cover load pull, creating matching networks, focusing on
performance specific goals, measuring junction temperature, and generating an
accurate EM simulation.
Overview
• Model layout:
– Talk about each probe on the model and setting up the model for simulation.
• Load Pull & Biasing

– Go over setting up the Load Pull template.
– Extracting Load Pull
– Plotting contours for power and efficiency
– Talk about picking bias points
• Design approach
– Ideal LC, Ideal Microstrip, and Real Microstrip
– Measuring Performance
– Rth, Pdiss, Self heating
• EM
– EM’ing final layout
– Setting Up Enclose
– Ports and Meshing
• M2M
– Measured to modeled results.
Model Layout
CGHV27030S
Device Characteristics
• Tcase represents the back of the
case temperature of the device at the
hottest point. To take measurements
at 85°C just change Tcase to 85.
• Rth is the thermal resistance of the

device in the package that is
calculated for this model. The Rth
should be adjusted based on your
operating conditions. The different
values for Rth can be found on our
datasheet.
• Vdn manifests itself in the IV

characteristics of the device, and
represents the operating voltage. To
operate at different voltages, for
example, 28V, you would need to
change Vdn to 28 and the drain
voltage supply on the schematic to
28V as well.
Device Model set up for DFN
• Now that we have a better understanding of the
different ports, we need to set the device up for
simulation.
• Ports 1-3 are tied to a small ideal inductor to help
simulate the inductance of the gate, source, and
drain connects.
• Ports 7-10 are connected to a micro strip that is
tied to a via, this is to help simulate the ground
plane it will be soldered to.
• Port 5 needs to be tied to ground in order to
simulate properly. This port can be used to
measure the intrinsic drain current.
• Ports 4 and 6 are left open. Port 4 can be used to
measure the intrinsic drain voltage and Port 5 can
be used to measure device temperature.
Device Model set up for DFN EM Ground Pad
• To create a more accurate simulation, you can set up the device with
an EM ground pad that you would be using on the PCB for mounting
the device.
• Modeling the source inductance is important because it effects the
device’s stability as well as its high frequency performance.
Loadpull and Biasing
Spec Sheet Parameter Value Comments
Frequency Range 1030MHz –

• Before getting into the design, I 1090MHz
wanted to provide the spec sheet. Output Power 30W
Small Signal Gain > 22dB
Drain Efficiency > 65%
Signal Profile Mode-S Pulsed (32uS ON / 18uS OFF) x 80,
LTDF = 6.4%
Gp > 18dB
Gain Flatness +/- .25dB No More than .5dB Across the Band
Vdd 50V
Return Loss -10 dB Input and Output once matched with
PCB
Output VSWR > 5:1
Operating Temp -40C to 85C *Needs to be stable at -40C 2:1 min. /
Needs to be thermally viable at 85C
Size TBD Use Standard
Export EAR99
10
Classification
Load Pull
• The Load Pull template on AWR, allows

users to derive a locus of different
impedance points.
• These impedances can then be analyzed to
see how the device’s performance changes
under different source and load
impedances.
• To start the Load Pull template, go to
“Scripts” on the toolbar, then “Load Pull”
and then “Create Load Pull Template”.
Load Pull
• The template shown should

come up.
• This template can be
modified and simulated
multiple ways. It can be used
for Load Pull or Source Pull
at fundamental, second, and
third harmonics, and at
different Pin and bias.
Setting Up Load Pull Template
1. Setting up the power:
• Pick an input power that is reasonable for the
design.
• For example a 30W amplifier design that
needs to have 18dB of power gain, an input
power off 27dBm was chosen.
2. Setting the Source and Load tuners:

• At this point we do not know the ideal
impedances, so set everything to 0.
• Make sure the frequency is set to what you
want to measure and Z is set to 50 ohms.
3. Set the schematic Frequency

• This can be done by right clicking on the load
pull schematic and selecting options,
frequencies. Multiple frequencies can be
used, but it is recommended to keep it to a
single frequency for each simulation. For this
design the frequency was set to 1060MHz,
middle of the band.
Setting Up Load Pull Template Cont.
4. Setting up power sources.
• We will be operating at 50V.
• The gate voltage can be adjusted to your
desired bias conditions.
• Using the “annotate” feature you can see your
Idq current at the device. I used Idq = 128mA
for my design.
5. Replacing the DUT:

• Replace the device with the CGHV27030S
model created earlier in the presentation.
6. Setting Up RC Network.
• Before performing load pull it is important to
make sure the device is stable.
• RC is chosen to balance gain vs stability.
• Add in an RC network on the gate side of the
device, after the Source tuner. Then plot the K
Factor of the circuit and adjust the RC
network until K is at least above 1.
Load Pull
• This gives us a starting point

for our ideal load impedance.
• We will enter this into our load

pull tuner in order to conduct a
source pull.
• Later we will discuss picking

an optimum impedance based
on power, and efficiency.
Source Pull
• Here we have a source impedance,

when used with load impedance
gives us an output power of
45.45dBm.
• Well plug this impedance into the

source tuner, and then re-run the
load pull to find a new optimal load
impedance.
• The load and source pull can be re-

run multiple times to converge on an
ideal impedance that satisfies your
goals for efficiency and power.
Picking Impedances
• After running load and source
pull, we are left with contours
representing the achievable
efficiency and power for those
impedances.
• The idea is to pick a load and

source impedance that
achieves your goals.
• In this case, I chose my

source impedance to give
optimal efficiency and the load
impedance to be between
peak power and peak
efficiency.
• Source: 7.97+j9.81
• Load: 36.54+j27.36
Red: Vg = -3.1V
Black: Vg = -2.6V
Picking a Biasing Point Blue: Vg = -2.1V
• Using our Load Pull impedances we can

examine how different bias conditions effect
performance.
• The Vg = -2.6V gives a good balance between
power gain and drain efficiency. This bias also
has good gain flatness over power, providing
good AM/AM.
• At this voltage the device is biased at an Idq =
117mA and is close to the 128mA bias point
we had chosen.
Matching Circuit
Match Approach
• There are three main approaches you can take when creating a matching
network:
– Ideal LC network
– Ideal microstrip network
– Real microstrip network
• Ideal LC is simplest and quickest way to get an idea of what kind matching
network you need. Creating a chain of series inductors with shunted capacitors
and then optimizing the values to the ideal impedance will generate the total
inductance and capacitance you need to create the match. This method is best
when you are not sure where to start, or when designing difficult broad band
networks.
Match Approach
• Ideal Microstrip network will give you a better representation of what your final
matching network will look like. If you started with the LC design, you can simply
convert your LC networks into microstrips using the Txline calculator in AWR.
The main benefit of starting with ideal microstrips over LCs is that you can focus
on the layout when creating your match to ensure the design meets the size
requirements.
• Real microstrip network provides the most accurate performance when
simulating. This is where you need to be no matter which approach you start
with. The real microstrip provides parasitic qualities which will be seen when
testing in the lab. Switching from ideal to real will have some effect on
performance and re-designing the microstrips may be required. At this point you
should also switch from ideal RLC components to real ones. Since this provides
the most accurate simulations, I started my design using real microstrips.
Ideal LC Ideal Microstrip w/ Ideal RLC Real Microstrip w/ Real LC

Input Match
• The idea is to create a network that transforms 50 ohms to the Complex

Conjugate of the Source Impedance chosen from source pull.
• The reflection coefficient of my source impedance was .734 <157.26°, so I want
to match to .734<-157.26°
• I went straight to real microstrips and components for my design. If you do not
have a component included in your library, you can ask the vendor for an
S’parameter file of the component and create a sub circuit block to represent it.
• I included the biasing network in my design, but you could use a bias tee before
adding in the biasing network.
Input Match Circuit
Biasing Network
Source Impedance
to match to
DC Block
RF In
RC Stability
Network
Microstrip Matching
Input Match Layout
• The SMA pad and Gate pad are fixed sizes. This
means you have to design around them.
• The microstrips lengths and widths were chosen to

minimize the use of components while providing a
match from the SMA to the Gate Pad
50-ohm Pad for

SMA Connector
Pad For DFN

Gate Pins
Output Match Circuit
Biasing Network
DC Block
Load Impedance
to match to
RF Out
Microstrip Matching
Output Match Layout
• Once again the SMA pad and Drain pad are

fixed sizes and had to be designed around.
• The microstrips were again chosen to create

the match between the two pads using
minimum components.
50-ohm Pad for

SMA Connector
Pad For DFN

Drain Pins
Simulated Performance: Output Power, Efficiency, & Gain (25C)
• Simulations are done at:

• Pin = 27dBm
• Vdd = 50V
• Idq = 128mA
• Measurements taken under

CW profile. This will provide a
more stressed performance
than the Mode-S signal.
Simulated Performance: Output Power, Efficiency, & Gain (85C)
Simulated Performance: Small Signal Gain and Return Loss (25C)
Simulated Performance: Small Signal Gain and Return Loss (85C)
Simulated Performance
25C 85C -40C
• Measuring stability at -40C is crucial, because it typically represents the most unstable state,
due to the high gain.
Thermal Analysis
• It is important to measure the thermal capabilities of your device, if it is not

thermally viable than the other performance does not matter.
• Cree provides an Rjc for each of their transistors on our datasheets. This
represents the thermal resistance of the die and can be used to calculate
junction temperature. We will go over this in the next couple of slides.
• Junction temperature, Jc, is calculated with the following equation:
– Jc = Pidss*Rth + Operating Temp
• To keep the die in a safe operating condition, we want to keep Jc < 225°C
– The 225C temperature allows for our devices to have a MTTF of over one million hours.
• We also want to take the measurements at an operating temperature of 85C,

this represents the most extreme case that the die will be stressed under.
FEA Simulation
Determining Rth
• Cree uses a dual-mannered approach in determining the
thermal resistance of its wide bandgap transistor & MMIC
products.
– An IR camera is used to take thermal images of the die. These
thermal images capture the top temperature of the die and are
used to correlate and validate the simulations.
– FEA simulation analysis is used to model the junction
temperature. The simulation is validated if the top level
temperature matches closely to what was measured by the IR
camera. IR Measurement
• Once the IR camera and modeling data have been
acquired, thermal resistance of the device is calculated
using:
!" #$%&&'( )'*+',%)-,' .!#(#%0' )'*+',%)-,')
Ø 23003+%)'4 567',
– Figures on the right show an example of how correlation is

33 achieved for a GaN HEMT device.
Calculating Junction Temperature
• The dissipated power can be calculated by measuring the RF output power, efficiency,
and DC power of the amplifier.
– These numbers are pulled from our simulated analysis.
Frequency RF Out Eff (%) DC Out (W) Pdiss (W) 1Rjc (C/W) Tc (C) Jc (C)
(MHz) (W)
1030 31.18 73.77 42.27 11.09 5.1 85 141.56
1060 31.05 72.67 42.73 11.68 5.1 85 144.57
1090 30.41 71.57 42.49 12.08 5.1 85 146.61
NOTE 1: The Rjc for Cree’s demonstration amplifier, CGHV27030S-AMP8, with 33 x 0.011 via
holes designed on a 20 mil thick Rogers 4350B PCB, operating under Mode-S conditions, from
the heat sink to junction is 5.1C/W. Derived from Mode-S Thermal analysis.
EM Analysis
Importance of EM
• AWR’s Axiem EM analysis, provides a detailed electromagnetic simulation that

accurately captures any parasitics, coupling, or other effects occurring when
driving RF through your design.
• In order to have accurate measured to modeled data, you have to EM your
circuit.
• In order to fully capture everything, I like to run the EM simulation on my entire
design, simulating the exact layout I will be using for generating the PCBs.
Creating an EM Layout
• There are two main ways to create an EM layout for your design:
– EM extraction
– Importing a .dxf
• AWR has an EM extraction tool, that will take your microstrip design and generate an EM
layout out of it. This is the quickest way to do it, but your actual board layout might differ
from the microstrip design in your circuit. This method ensures you are EM’ing the matching
network which has the biggest impact on performance.
• Importing a .dxf from autocad is the method I use, because it allows you to incorporate your
actual PCB layout into the EM. I use Autocad for laying out my PCB design, and then import
the design into AWR. This ensures that my EM structure matches my PCB. One issue with
this, is that importing the entire layout can cause your simulations to run for a long time, and
often times there are parts of the layout that have minimal effect on performance.
Setting Up EM Stackup
• It is important to set up your EM

Enclosure to accurately depict the
material used for building the PCB.
• Also it is recommended to set the
frequency of the EM to run from 0-
4GHz, this will cover from DC to the
4th harmonic of the design.
• Here we define our PCB material, &
the copper used for the microstrips.
• We define the layers being

simulated. This helps build the
enclosure, which is made up of
air, 150 mils, and our PCB, 20
mils.
• The 1oz copper is made 1.4mil
thick, that is the thickness we use
when manufacturing our PCBs.
• Line1 represents the copper

plating added to the bottom of
the PCB that separates the
Dielectric from the ground.
• We define the EM layer on which
the copper and vias will be on
and the material used for them.
Setting Up the Simulation
Input RC Network
• Once the stack-up is set, you need to add ports
to the EM Layout in order to simulate it.
• When setting up your ports, it is important to de-
embed the ports to where the point of contact
will be for your component.
– For example, when soldering a capacitor to a board,
part of the pad will lay on the trace, so you want to
de-embed the port to where the edge of the capacitor
meets the trace, not just to the edge of the trace.
• To de-embed an edge port, after placing the port

on the edge of the trace, drag the port inward to
the desired offset.
• Before simulating, make sure you change the De-embedded to edge of capacitor package
port type from “auto” to “lower”. This changes
41 the port plain. CREE CONFIDENTIAL & PROPRIETARY © 2018 Cree, Inc. All rights reserved. Cree®, the Cree logo, Wolfspeed®, and the Wolfspeed logo are registered trademarks of Cree, Inc.
Running the Mesh
• Simulating the mesh gives some insight to the EM simulation before running the full EM.
• Running the mesh will divide your layout into smaller geometries to make the simulation run easier.
• Running the mesh will also signal any errors in your layout or EM simulation, such as port errors.
• Changing the grid size of the EM structure, will also lower the mesh size. This will make larger
shapes when meshing and cutting down on the overall simulation time, but at the cost of accuracy.
Input Match Meshed
EM Layout: Input Match
Gate Bias
Ground
Gate Pad
RF In
Ground
EM Layout: Output Match
Ground
Drain
Bias
Ground
RF Out
Drain Pad
Ground
Measured to Modeled
Modeled to Measured: Large Signal
Power, Drain Efficiency, & Gain Vs Frequency
Pin = 27dBm, Vdd = 50V, Idq = 128mA, PW = 1.536mS, DC = 5.8%, Fix D1
80
75
70
Output Power (dBm), Drain Efficiency (%), Gain (dB)
65
60
55
Pout_Simulated
50
Pout_Measured
45
Eff_Simulated
40
Eff_Measured
35
Gain_Simulated
30
Gain_Measured
25
20
15
10
1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.1
Frequency (GHz)
Modeled to Measured: Small Signal
S'Parameters Vs Frequency
Vdd = 50V, Idq = 128mA, Fix. D1
30
25
20
15
10 S11_Simulated
S11_Measured
Sxx (dB)
5
S22_Simulated
0 S22_Measured
0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
-5 S21_Simulated
S21_Measured
-10
-15
-20
-25
Frequency (GHz)
Worst Case Operating Temperature
Frequency Tc (C) 1Rjc (C/W) Pdiss (W) Jc (C)

(MHz)
1090 25 5.1 17.3 113.23
1090 45 5.1 17.1 132.21
1090 65 5.1 16.6 149.66
1070 85 5.1 16.1 167.11
NOTE 1: The Rjc for Cree’s demonstration amplifier, CGHV27030S-AMP8, with 33 x 0.011 via holes designed on a 20 mil thick
Rogers 4350B PCB, operating under Mode-S conditions, from the heat sink to junction is 5.1C/W. Derived from Mode-S
Thermal analysis.
Finished Product: CGHV27030s-AMP8
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Avionics PA Design with Cree’s CGHV27030S Amplifier

• Graduated with my B.A.Sc in Electrical Engineering

• Load Pull & Biasing

• Rth is the thermal resistance of the

• Vdn manifests itself in the IV

Frequency Range 1030MHz –

• The Load Pull template on AWR, allows

• The template shown should

2. Setting the Source and Load tuners:

3. Set the schematic Frequency

5. Replacing the DUT:

• This gives us a starting point

• We will enter this into our load

• Later we will discuss picking

• Here we have a source impedance,

• Well plug this impedance into the

• The load and source pull can be re-

• The idea is to pick a load and

• In this case, I chose my

• Using our Load Pull impedances we can

Ideal LC Ideal Microstrip w/ Ideal RLC Real Microstrip w/ Real LC

• The idea is to create a network that transforms 50 ohms to the Complex

• The microstrips lengths and widths were chosen to

50-ohm Pad for

Pad For DFN

• Once again the SMA pad and Drain pad are

• The microstrips were again chosen to create

50-ohm Pad for

Pad For DFN

• Simulations are done at:

• Measurements taken under

25C 85C -40C

• It is important to measure the thermal capabilities of your device, if it is not

• We also want to take the measurements at an operating temperature of 85C,

– Figures on the right show an example of how correlation is

• AWR’s Axiem EM analysis, provides a detailed electromagnetic simulation that

• It is important to set up your EM

• We define the layers being

• Line1 represents the copper

• To de-embed an edge port, after placing the port

Input Match Meshed

Frequency Tc (C) 1Rjc (C/W) Pdiss (W) Jc (C)

1090 45 5.1 17.1 132.21

1090 65 5.1 16.6 149.66

1070 85 5.1 16.1 167.11

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