Chapter 7 – Latches and Flip-Flops Page 1 of 18

7. Latches and Flip-Flops

Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit of
information. The main difference between latches and flip-flops is that for latches, their outputs are constantly
affected by their inputs as long as the enable signal is asserted. In other words, when they are enabled, their content
changes immediately when their inputs change. Flip-flops, on the other hand, have their content change only either
at the rising or falling edge of the enable signal. This enable signal is usually the controlling clock signal. After the
rising or falling edge of the clock, the flip-flop content remains constant even if the input changes.
There are basically four main types of latches and flip-flops: SR, D, JK, and T. The major differences in these
flip-flop types are the number of inputs they have and how they change state. For each type, there are also different
variations that enhance their operations. In this chapter, we will look at the operations of the various latches and flip-
flops.

7.1 Bistable Element

The simplest sequential circuit or storage element is a bistable element, which is constructed with two inverters
connected sequentially in a loop as shown in Figure 1. It has no inputs and two outputs labeled Q and Q’. Since the
circuit has no inputs, we cannot change the values of Q and Q’. However, Q will take on whatever value it happens
to be when the circuit is first powered up. Assume that Q = 0 when we switch on the power. Since Q is also the
input to the bottom inverter, Q’, therefore, is a 1. A 1 going to the input of the top inverter will produce a 0 at the
output Q, which is what we started off with. Similarly, if we start the circuit with Q = 1, we will get Q’ = 0, and
again we get a stable situation.
A bistable element has memory in the sense that it can remember the content (or state) of the circuit
indefinitely. Using the signal Q as the state variable to describe the state of the circuit, we can say that the circuit has
two stable states: Q = 0, and Q = 1; hence the name “bistable.”
An analog analysis of a bistable element, however, reveals that it has three equilibrium points and not two as
found from the digital analysis. Assuming again that Q = 1, and we plot the output voltage (Vout1) versus the input
voltage (Vin1) of the top inverter, we get the solid line in Figure 2. The dotted line shows the operation of the bottom
inverter where Vout2 and Vin2 are the output and input voltages respectively for that inverter.
Figure 2 shows that there are three intersection points, two of which corresponds to the two stable states of the
circuit where Q is either 0 or 1. The third intersection point labeled metastable, is at a voltage that is neither a logical
1 nor a logical 0 voltage. Nevertheless, if we can get the circuit to operate at this voltage, then it can stay at that
point indefinitely. Practically, however, we can never operate a circuit at precisely a certain voltage. A slight
deviation from the metastable point as cause by noise in the circuit or other stimulants will cause the circuit to go to
one of the two stable points. Once at the stable point, a slight deviation, however, will not cause the circuit to go
away from the stable point but rather back towards the stable point because of the feedback effect of the circuit.
An analogy of the metastable behavior is a ball on top of a symmetrical hill as depicted in Figure 3. The ball can
stay indefinitely in that precarious position as long as there is absolutely no movement whatsoever. With any slight
force, the ball will roll down to either of the two sides. Once at the bottom of the hill, the ball will stay there until an
external force is applied to it. The strength of this external force will cause the ball to do one of three things. If a
stable
V out1 5
= V in2
Q
metastable

stable
0
Q' 0 V in1 = V o u t 25

Figure 1. Bistable element. Figure 2. Analog analysis of bistable element.

Chapter 7 – Latches and Flip-Flops Page 2 of 18

metastable

stable stable

Figure 3. Ball and hill analogy for metastable behavior.

small force is applied to the ball, it will go partly up the hill and then rolls back down to the same side. If a big
enough force is applied to it, it will go over the top and down the other side of the hill. We can also apply a force
that is just strong enough to push the ball to the top of the hill. Again at this precarious position, it can roll down
either side.
We will find that all latches and flip-flops have this metastable behavior. In order for the element to change
state, we need to apply a strong enough pulse satisfying a given minimum width requirement. Otherwise, the
element will either remain at the current state or go into the metastable state in which case unpredictable results can
occur.

7.2 SR Latch
The bistable element is able to remember or store one bit of information. However, because it does not have any
inputs, we cannot change the information bit that is stored in it. In order to change the information bit, we need to
add inputs to the circuit. The simplest way to add inputs is to replace the two inverters with two NAND gates as
shown in Figure 4(a). This circuit is called a SR latch. In addition to the two outputs Q and Q', there are two inputs S'
and R' for set and reset respectively. Following the convention, the prime in S and R denotes that these inputs are
active low. The SR latch can be in one of two states: a set state when Q = 1, or a reset state when Q = 0.
To make the SR latch go to the set state, we simply assert the S' input by setting it to 0. Remember that 0 NAND
anything gives a 1, hence Q = 1 and the latch is set. If R' is not asserted (R' = 1), then the output of the bottom NAND
gate will give a 0, and so Q' = 0. This situation is shown in Figure 4 (d) at time t0. If we de-assert S' so that S' = R' =
1, the latch will remain at the set state because Q', the second input to the top NAND gate, is 0 which will keep Q = 1
as shown at time t1. At time t2 we reset the latch by making R' = 0. Now, Q' goes to 1 and this will force Q to go to a
0. If we de-assert R' so that again we have S' = R' = 1, this time the latch will remain at the reset state as shown at
time t3. Notice the two times (at t1 and t3) when both S' and R' are de-asserted. At t1, Q is at a 1, whereas, at t3, Q is at

S'
Q
S R Q Qnext Qnext'
0 0 × 1 1
0 1 × 1 0
1 0 × 0 1
1 1 0 0 1
Q'
R' 1 1 1 1 0
(a) (b)
S'

R'
S' Q
Q Undefined
R' Q' Q' Undefined
t0 t1 t2 t3 t4 t5 t6
(c)
(d)
Figure 4. SR latch: (a) circuit using NAND gates; (b) truth table; (c) logic symbol; (d) timing diagram.
Chapter 7 – Latches and Flip-Flops Page 8 of 18

D D Q Qa

Clk E Q'

D Q Qb

Clk
Clk Q '
D

Qa
D Q Qc
Qb
Clk Q ' Qc

(a) (b)

Figure 12. Comparison of a gated latch, a positive-edge-triggered flip-flop, and a negative-edge-triggered flip-
flop: (a) circuit; (b) timing diagram.

Figure 12 compares the different operations between a latch and a flip-flop. In (a), we have a gated D latch, a
positive-edge-triggered D flip-flop and a negative-edge-triggered D flip-flop, all having the same D input and
controlled by the same clock signal. (b) shows a sample trace of the circuit’s operations. Notice that the gated D
latch Qa follows the D input as long as the clock is high. The positive-edge-triggered flip-flop Qb responds to the D
input only at the rising edge of the clock while the negative-edge-triggered flip-flop Qc responds to the D input only
at the falling edge of the clock.

7.7 D Flip-Flop with Enable

A commonly desired function in D flip-flops is the ability to hold the last value stored rather than load in a new
value at the clock edge. This is accomplished by adding an enable input called EN or CE (clock enable) through a
multiplexer as shown in Figure 13(a). When EN = 1, the primary D signal will pass to the D input of the flip-flop,
thus updating the content of the flip-flop. When EN = 0, the bottom AND gate is enabled and so the current content
of the flip-flop, Q, is passed back to the input, thus, keeping its current value. Notice that changes to the flip-flop
value occur only at the rising edge of the clock. The truth table and the logic symbol for the D flip-flop with enabled
is shown in (b) and (c) respectively.

D
EN Clk EN D Q Qnext Qnext'
D Q Q D Q
0 × × 0 0 1
0 × × 1 1 0 Clk
Clk Clk Q ' Q'
1 × × 0 0 1 EN Q'
1 × × 1 1 0
0 × 0 0 1
0 × 1 1 0
1 0 × 0 1 (c)
(a) 1 1 × 1 0

(b)

Figure 13. D flip-flop with enable: (a) circuit; (b) truth table; (c) logic symbol.
Chapter 7 – Latches and Flip-Flops Page 9 of 18

7.8 Asynchronus Inputs

Flip-flops, as we have seen so far, change states at the edge of a synchronizing clock signal. Many circuits
require the initialization of flip-flops to a known state independent of the clock signal. Sequential circuits that
change states whenever a change in input values occurs independent of the clock are referred to as asynchronous
sequential circuits. Synchronous sequential circuits, on the other hand, change states only at the edge of the clock
signal. Asynchronous inputs are usually available for both flip-flops and latches, and they are used to either set or
clear the storage element’s content independent of the clock.
Figure 14(a) shows a D latch with asynchronous PRESET' and CLEAR' inputs, and (b) is the logic symbol for it. (c)
is the circuit for the D edge-triggered flip-flop with asynchronous PRESET' and CLEAR' inputs, and (d) is the logic
symbol for it. When PRESET' is asserted (set to 0) the content of the storage element is set to a 1 immediately, and
when CLEAR' is asserted (set to 0) the content of the storage element is set to a 0 immediately.

Preset'
S
D
Q
Preset'
E D Q

Q' E Q'
R Clear'
Clear'
(a) (b)

Preset'

Clk

Q' Preset'
D Q

D Clk Q '
Clear'
Clear'

(c) (d)
Figure 14. Storage elements with asynchronous inputs: (a) D latch with preset and clear; (b) logic symbol for (a);
(c) D edge-triggered flip-flop with preset and clear; (d) logic symbol for (c).

7.9 Flip-Flop Types

There are basically four main types of flip-flops: SR, D, JK, and T. The major differences in these flip-flop
types are in the number of inputs they have and how they change state. Each type can have different variations such
as active high or low inputs, whether they change state at the rising or falling edge of the clock signal, and whether
they have asynchronous inputs or not. The flip-flops can be described fully and uniquely by its logic symbol,
characteristic table, characteristic equation, state diagram, or excitation table, and are summarized in Figure 15.
Chapter 7 – Latches and Flip-Flops Page 16 of 18

Another way to describe a flip-flop is to use the WAIT statement instead of the IF statement as shown in Figure
26. When execution reaches the WAIT statement, it stops until the condition in the statement is true before
proceeding. Note also that the process sensitivity list is omitted because the WAIT statement implies that the
sensitivity list contains only the clock signal.

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY D_flipflop IS
PORT(D, Clock : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END D_flipflop;

ARCHITECTURE Behavior OF D_flipflop IS

BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock’EVENT AND Clock = '0' -- negative edge triggered
Q <= D;
END PROCESS;
END Behavior;
Figure 26. VHDL code for a negative-edge-triggered D flip-flop using a WAIT statement.

Alternatively, we can write a structural VHDL description for the positive-edge-triggered D flip-flop as shown
in Figure 27. This VHDL code is based on the circuit for a positive-edge-triggered D flip-flop as given in Figure 11.

-- define the behavioral operation of the 2-input NAND gate

LIBRARY ieee;
USE IEEE.std_logic_1164.all;

ENTITY NAND2 IS
PORT(I0, I1 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END NAND2;

ARCHITECTURE Behavioral_NAND2 OF NAND2 IS

BEGIN
O <= I1 NAND I2;
END Behavioral_NAND2;

-- define the behavioral operation of the 3-input NAND gate

LIBRARY ieee;
USE IEEE.std_logic_1164.all;

ENTITY NAND3 IS
PORT(I0, I1, I2 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END NAND3;

ARCHITECTURE Behavioral_NAND3 OF NAND3 IS

BEGIN
O <= NOT (I1 AND I2 AND I3);
END Behavioral_NAND3;
Figure 27. Structural VHDL code for a positive-edge-triggered D flip-flop.
Chapter 7 – Latches and Flip-Flops Page 17 of 18

-- define the structural operation of the SR latch

LIBRARY ieee;
USE IEEE.std_logic_1164.all;

ENTITY SRlatch IS
PORT(SN, RN : IN STD_LOGIC;
Q, QN : OUT STD_LOGIC);
END SRlatch;

ARCHITECTURE Structural_SRlatch OF SRlatch IS

COMPONENT NAND2 PORT (I0, I1 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
BEGIN
U1: NAND2 PORT MAP (SN, QN, Q);
U2: NAND2 PORT MAP (Q, RN, QN);
END Structural_SRlatch;

-- define the structural operation of the positive edge triggered

-- D flip-flop
LIBRARY ieee;
USE IEEE.std_logic_1164.all;

ENTITY positive_edge_triggered_D_flipflop IS
PORT(D, Clock : IN STD_LOGIC;
Q, QN : OUT STD_LOGIC);
END positive_edge_triggered_D_flipflop;

ARCHITECTURE Structural OF positive_edge_triggered_D_flipflop IS

SIGNAL N1, N2, N3, N4 : STD_LOGIC;

COMPONENT SRlatch PORT (SN, RN : IN STD_LOGIC;

Q, QN : OUT STD_LOGIC);
END COMPONENT;
COMPONENT NAND2 PORT (I0, I1 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
COMPONENT NAND3 PORT (I0, I1, I2 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;

BEGIN
U1: SRlatch PORT MAP (N4, Clock, N1, N2); -- set latch
U2: SRlatch PORT MAP (N2, N3, Q, QN); -- output latch
U3: NAND3 PORT MAP (N2, Clock, N4, N3); -- reset latch
U4: NAND2 PORT MAP (N3, D, N4);
END Structural;
Figure 27 (continue). Structural VHDL code for a positive-edge-triggered D flip-flop.
Chapter 7 – Latches and Flip-Flops Page 18 of 18

7.10.4 VHDL Code for a D Flip-Flop with Asynchronous Inputs

Figure shows the VHDL code for a positive-edge-triggered D flip-flop with asynchronous active low reset and
clear inputs. The two asynchronous inputs are checked for independently of the clock event. When either the Reset
or the Clear input is asserted, Q is set to a 1 or 0 respectively immediately. Otherwise Q follows D at the rising edge
of the clock.

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY D_flipflop IS
PORT(D, Clock, Reset, Clear : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END D_flipflop;

ARCHITECTURE Behavior OF D_flipflop IS

BEGIN
PROCESS(Clock, Reset, Clear)
BEGIN
IF Reset = '0' THEN
Q <= '1';
ELSIF Clear = '0' THEN
Q <= '0';
ELSIF Clock’EVENT AND Clock = '1' THEN
Q <= D;
END IF;
END PROCESS;
END Behavior;
Figure 28. VHDL code for a D flip-flop with asynchronous inputs.