Latches and Flip-Flop

Finals – Lecture 2
 Introduction
 A sequential circuit consists of a feedback
path, and employs some memory elements.
Combinational
outputs Memory outputs

Combinational Memory
logic elements

External inputs

Sequential circuit = Combinational logic + Memory Elements

 Introduction
 There are two types of sequential circuits:
 synchronous: outputs change only at specific time
 asynchronous: outputs change at any time
 Multivibrator: a class of sequential circuits. They can be:
 bistable (2 stable states)
 monostable or one-shot (1 stable state)
 astable (no stable state)
 Bistable logic devices: latches and flip-flops.
 Latches and flip-flops differ in the method used for
changing their state.
 Memory Elements
 Memory element: a device which can
remember value indefinitely, or change
value on command from its inputs.
Memory Q
command element stored value

 Characteristic table:
Command Q(t) Q(t+1)
(at time t) Q(t): current state
Set X 1 Q(t+1) or Q+: next state
Reset X 0
Memorise / 0 0
No Change 1 1
 Memory Elements
 Memory element with clock. Flip-flops are
memory elements that change state on
clock signals.
Memory Q
command element stored value

clock
 Clock is usually a square wave.
Positive pulses

Positive edges Negative edges

 Memory Elements
 Two types of triggering/activation:
 pulse-triggered
 edge-triggered
 Pulse-triggered
 latches
 ON = 1, OFF = 0
 Edge-triggered
 flip-flops
 positive edge-triggered (ON = from 0 to 1; OFF = other
time)
 negative edge-triggered (ON = from 1 to 0; OFF =
other time)
 S-R Latch
 Complementary outputs: Q and Q'.
 When Q is HIGH, the latch is in SET state.
 When Q is LOW, the latch is in RESET
state.
 For active-HIGH input S-R latch (also known as
NOR gate latch),
R=HIGH (and S=LOW) a RESET state
S=HIGH (and R=LOW) a SET state
both inputs LOW a no change
both inputs HIGH a Q and Q' both LOW (invalid)!
 S-R Latch
 For active-LOW input S'-R' latch (also known as
NAND gate latch),
R'=LOW (and S'=HIGH) a RESET state
S'=LOW (and R'=HIGH) a SET state
both inputs HIGH a no change
both inputs LOW a Q and Q' both HIGH (invalid)!

 Drawback of S-R latch: invalid condition

exists and must be avoided.
 S-R Latch
 Characteristics table for active-high input S-R
latch:
S R Q Q'
S Q
0 0 NC NC No change. Latch
remained in present state.
1 0 1 0 Latch SET. R Q'
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.

 Characteristics table for active-low input S'-R'

latch:
S' R' Q Q'
S Q
1 1 NC NC No change. Latch
remained in present state.
0 1 1 0 Latch SET. R Q'
1 0 0 1 Latch RESET.
0 0 1 1 Invalid condition.
 S-R Latch
 Active-HIGH input S-R latch
10 100 R S R Q Q'
Q 11000 1 0 1 0 initial
0 0 1 0 (afer S=1, R=0)
0 1 0 1
Q' 0 0 1 1 0 0 0 0 1 (after S=0, R=1)
10 001 S
1 1 0 0 invalid!

 Active-LOW input S’-R’ latch

S' Q
S' R' Q Q'
R' Q' 1 0 0 1 initial
S'
Q 1 1 0 1 (afer S'=1, R'=0)
0 1 1 0
1 1 1 0 (after S'=0, R'=1)
Q'
R' 0 0 1 1 invalid!
 Gated S-R Latch
 S-R latch + enable input (EN) and 2 NAND
gates  gated S-R latch.
S
Q S Q
EN EN
Q' R Q'
R
 Gated S-R Latch
 Outputs change (if necessary) only when
EN is HIGH.
 Under what condition does the invalid
state occur?
 Characteristic
EN=1
table:
S R Q(t+1)
Q(t) S R Q(t+1)
0 0 Q(t) No change
0 0 0 0
0 0 1 0
0 1 0 Reset
0 1 0 1 1 0 1 Set
0 1 1 indeterminate 1 1 indeterminate
1 0 0 1
1 0 1 0 Q(t+1) = S + R'.Q
1 1 0 1 S.R = 0
1 1 1 indeterminate
 Gated D Latch
 Make R input equal to S'  gated D latch.
 D latch eliminates the undesirable
condition of invalid state in the S-R latch.

D
Q D Q
EN EN
Q' Q'
 Gated D Latch
 When EN is HIGH,
D=HIGH  latch is SET
D=LOW  latch is RESET

 Hence when EN is HIGH, Q ‘follows’ the D

(data) input.
 Characteristic table:
EN D Q(t+1)
1 0 0 Reset
1 1 1 Set
0 X Q(t) No change

When EN=1, Q(t+1) = D

Latch Circuits: Not Suitable
 Latch circuits are not suitable in synchronous logic
circuits.
 When the enable signal is active, the excitation inputs are
gated directly to the output Q. Thus, any change in the
excitation input immediately causes a change in the latch
output.
 The problem is solved by using a special timing control
signal called a clock to restrict the times at which the
states of the memory elements may change.
 This leads us to the edge-triggered memory elements
called flip-flops.
 Edge-Triggered Flip-flops
 Flip-flops: synchronous bistable devices
 Output changes state at a specified point
on a triggering input called the clock.
 Change state either at the positive edge
(rising edge) or at the negative edge
(falling edge) of the clock signal.
Clock signal

Positive edges Negative edges

 Edge-Triggered Flip-flops
 S-R, D and J-K edge-triggered flip-flops.
Note the “>” symbol at the clock input.
S Q D Q J Q
C C C
R Q' Q' K Q'

Positive edge-triggered flip-flops

S Q D Q J Q
C C C
R Q' Q' K Q'

Negative edge-triggered flip-flops

 S-R Flip-flop
 S-R flip-flop: on the triggering edge of the clock pulse,
 S=HIGH (and R=LOW) a SET state
 R=HIGH (and S=LOW) a RESET state
 both inputs LOW a no change
 both inputs HIGH a invalid
 Characteristic table of positive edge-triggered S-R flip-flop:
S R CLK Q(t+1) Comments
0 0 X Q(t) No change
0 1  0 Reset
1 0  1 Set
1 1  ? Invalid

X = irrelevant (“don’t care”)

 = clock transition LOW to
HIGH
 S-R Flip-flop
 It comprises 3 parts:
a basic NAND latch
a pulse-steering circuit
a pulse transition detector (or edge detector)
circuit
 The pulse transition detector detects a
rising (or falling) edge and produces a very
short-duration spike.
 S-R Flip-flop
The pulse transition
detector. Pulse
S
Q
CLK transition
detector
Q'
R

CLK' CLK'
CLK CLK* CLK CLK*

CLK CLK

CLK' CLK'

CLK* CLK*

Positive-going transition Negative-going transition

(rising edge) (falling edge)
 D Flip-flop
 D flip-flop: single input D (data)
 D=HIGH a SET state
 D=LOW a RESET state
 Q follows D at the clock edge.
 Convert S-R flip-flop into a D flip-flop: add an inverter.
D S D CLK Q(t+1) Comments
Q
C
1  1 Set
CLK
0  0 Reset
R Q'
 = clock transition LOW to
A positive edge-triggered D flip- HIGH
flop formed with an S-R flip-flop.
 D Flip-flop
 Application: Parallel data transfer.
To transfer logic-circuit outputs X, Y, Z to flip-flops Q1, Q2
and Q3 for storage.
D Q Q1 = X*

CLK
X Q'

Combinational Y D Q Q2 = Y*
logic circuit
Z
CLK
Q'

D Q Q3 = Z*
Transfer CLK
Q'

* After occurrence of negative-going

transition
 J-K Flip-flop
 J-K flip-flop: Q and Q' are fed back to the pulse-steering NAND gates.
 No invalid state.
 Include a toggle state.
 J=HIGH (and K=LOW) a SET state
 K=HIGH (and J=LOW) a RESET state
 both inputs LOW a no change
 both inputs HIGH a toggle
 The JK flip flop was named after Jack Kilby, the Texas Instruments
engineer that invented the integrated circuit in 1958. The modified
RS circuit that eliminated race conditions was named JK in his
honor.
 J-K Flip-flop
 J-K flip-flop.
J
Q
Pulse
CLK transition
detector
Q'
K

 Characteristic table. Q J K Q(t+1)

J K CLK Q(t+1) Comments 0 0 0 0
0 0  Q(t) No change 0 0 1 0
0 1  0 Reset 0 1 0 1
1 0  1 Set 0 1 1 1
1 1  Q(t)' Toggle 1 0 0 1
1 0 1 0
Q(t+1) = J.Q' + K'.Q 1 1 0 1
1 1 1 0
 T Flip-flop
 T flip-flop: single-input version of the J-K flip flop, formed
by tying both inputs together.
T T
Q J
Pulse Q
CLK transition CLK C
detector
Q' K Q'

 Characteristic table.
T CLK Q(t+1) Comments Q T Q(t+1)
0  Q(t) No change 0 0 0
1  Q(t)' Toggle 0 1 1
1 0 1
1 1 0
Q(t+1) = T.Q' + T'.Q
 T Flip-flop
 Application: Frequency division.
High High High

J J QA J QB
Q
CLK C CLK C C

K K K

CLK CLK

Q QA

QB

Divide clock frequency by 2. Divide clock frequency by 4.

 Application: Counter
 Asynchronous Inputs
 S-R, D and J-K inputs are synchronous inputs, as data on
these inputs are transferred to the flip-flop’s output only
on the triggered edge of the clock pulse.
 Asynchronous inputs affect the state of the flip-flop
independent of the clock; example: preset (PRE) and clear
(CLR) [or direct set (SD) and direct reset (RD)]
 When PRE=HIGH, Q is immediately set to HIGH.
 When CLR=HIGH, Q is immediately cleared to LOW.
 Flip-flop in normal operation mode when both PRE and
CLR are LOW.
 Asynchronous Inputs
 A J-K flip-flop with active-LOW preset and clear inputs.
PRE PRE

J
J Q
Q Pulse
C transition
CLK
detector
K Q'
Q'
K

CLR CLR

CLK

PRE

CLR
Q
J = K = HIGH Preset Toggle Clear