Placement:

1.Define placement in physical design?

Placement is the process of placing standard cells in the rows created at floor planning stage.

2. What are the goals of Placement?

• Timing, Power and Area optimizations
• Routable design (minimal global & local congestion)
• No/minimal cell density, pin density & congestion hot-spots
• Minimal timing DRCs

3. What is congestion?
When the available tracks are less than the required tracks this effect will occur.When the
signals are more than the tracks then congestion will occur.

4.How to fix congestion?

 Congestion driven placement.

 Adjust cell density in congested area(high cell density cause congestion).
 Use proper blockage.
 Modify the floor plan design.
5. What are the types of blockages?
Hard blockage:- It does't allow inverters,buffers,standard cells.
Soft blockage:- It allows only inverters and buffers and blocks standard cells.
Partial blockage:- It will allow both buffers and standard cell in a percentage value.
6. What is the difference between Halo and Blockage?
Halo:- It is the region around the boundary of fixed macros in design in which no other
macros or standard cells can be place.If macros moves halo will also move.
Blockage:- It can be specified for any part of the design.If we move the block blockage will
not move.
7. What are the things to be checked before placement stage?Things to be checked
before placement
• Check for any missing or extra placement and routing blockages
• Don’t use cell list and whether it is properly applied in the tool
• Don’t touch on cells and nets (make sure that, these are applied)
• Better to have limit the local density (Otherwise local congestion can create issue in
routing or eco stages)
• Understand all optimization options and placement switches set in the tool
• There should not be any high WNS timing violations
• Make sure that clock is set to ideal network
• Take care of integration guidelines of any special IPs (These won’t be reported in
any of the checks). Have custom scripts to check these guidelines
• Fix all the hard macros and pre-placed cells
• Check the pin access
8. Discuss the congestion reduction techniques in detail?
Following techniques are used for reducing congestion.
• Placement Blockages : Inorder to avoid placement in some areas, placement
blockages are used. Different types of placement blockages are soft blockage: It
restricts placement of standard cells inside the blockage area but allows buffers to be
placed at the time of optimization to meet timing. Hard blockage: It prevents cells from
being placed in this blockage area. Both standard cells as well as buffers are prohibited
inside hard blockage area.
 Partial blockage: The designer can customize the amount of space to inside the blockage
area
.• Macro Padding : Macro padding or halos (keep-out margin) around the macros are
placement blockages around the edge of the macros. This makes sure that no standard cells
are placed near the pins outs of the macros, thereby giving enough space for the macro
pin connections to standard cells.
• Cell Padding : Cell padding refers to placement clearance applied to standard cells in
PnR tools. This is typically done to ease placement congestion to reserve some space for
future use down the ow. For example typically people apply cell padding to the
buffers/inverters used to build clock tree, so that space is reserved to insert decap cells
near them after clock tree synthesis.
• Maximum Utilization Constraint : Some tools will specify maximum core utilization
numbers for specic regions. If any region has routing congestion, utilization there can be
reduced, thus freeing up more area for routing.
9. How to qualify the Placement stage?
• Check legalization for any overlapping.
• Check PG connections for all the cells.
• Check global congestion, pin density and cell density
• Check whether all don't touch cells and nets are preserved.
• Check for setup time violation.
10. What is Scan chain reordering?
It is the process of reconnecting the scan chains in a design to optimize for routing by re-
ordering the scan connection which improves congestion as well as timing. At the time of
placement the optimization may take the scan chain difcult to route due to congestion.
Hence the tool will re-order the chain to reduce congestion. Since logic synthesis
arbitrarily connects the scan chain, we need to perform scan reorder after placement so
that the scan chain routing will be optimal.
11. What is Lockup latch in scan chain and why this is required?
A lock up latch is a sequential circuit which is used to address skew problems when multiple
clock domains are used in a chip. From a DFT perspective it holds the previous scan data,
and delays output transition so that the scan data can be effectively captured.
lock up latch helps prevent problems like clock signal reaching a register too early or later
than its intended time.

12. What is the goal of placement?

Timing, power, area optimization
Routable design
Minimum cell density and pin density(Reduce the congestion due to cells and pins)
Minimum timing DRC’s
13. What are the Inputs and output of placement process?
Inputs
Netlist
Floorplan def
Logical and physical library
Design constraint
Technology file
Output:
Placement def

14. What is keep-out margin?

Keep-out margin: it is a region around the boundary of fixed cells in a block in which no
other cells are placed. The width of the keep-out margin on each side of the fixed cell can be
the same or different. Keeping the placement of cells out of such regions avoids congestion
and net detouring and produces better QOR (quality of results).

15.What is placement bounds?

It is a constraint that controls the placement of groups of leaf cells and hierarchical cells. It
allows you to group cells to minimize wire length and place the cells at most appropriate
locations. When our timing is critical during placement then we create bounds in that area
where two communicating cells are sitting far from another. It is a fixed region in which we
placed a set of cells. It comprises of one or more rectangular or rectilinear shapes which can
be abutted or disjoint. In general we specify the cells and ports to be included in the bound. If
a hierarchical cell is included, all cells in the sub-design belong to the bound.

16. What are the types of bounds?

Soft move bound
Hard move bound
Exclusive move bound

17.Explain the types of bounds

Soft move bound:
In this tool tries to place the cells in the move bound within a specified region, however, there
is no guarantee that the cells are placed inside the bounds.
Create bound –name b0 –type soft –boundary {10 10 20 20} instance_1 #define softbound
for instance_1 with its left corner at (10 10) and its upper-right corner at (20 20).

Hard move bound:

In this tool must place the cells in the move bound within a specified region.
Create bound –name b1 –type soft –boundary {10 10 20 20} instance_2

Exclusive move bound:

In this tool tries to place the cells in the group bound within a floating region, however, there
is no guarantee that the cells are placed inside the bounds
Create bound –name b2 –exclusive –boundary {10 10 20 20} instance_1

18. What is Density controls?

It means how the density of cells can be packed. We can control the overall placement
density for the block or the cell density for specific regions. To control the cell density for
specific regions we can also use partial placement blockages.

19. How will you perform incremental placement and optimization?

Place_opt: This command performs coarse placement, HFNS, optimization and legalization.
In the place_opt command, the –congestion option causes the tool to apply –high effort to
congestion removal for better routability, this will require more runtime and cause area
utilization to be less uniform across the available placement area.

Refine_opt: if congestion is found to be a problem after placement and optimization. It can

improve incrementally with the refine_opt command.

20.What are the stages involved in refine_opt command?

Refine_opt: perform 5 stages:
Initial path optimization: it incrementally moves registers along timing paths to improve
timing.
Incremental placement: to reduce congestion and improve routability.
Incremental optimization: perform incremental timing, area, congestion and leakage power
optimization.
Final placement: final phase of path optimization to improve timing
Legalization: tool legalize the placement.

21. What is Magnet placement?

To improve congestion for a complex floorplan or to improve timing for the design we can
use magnet placement to specify fixed object as a magnet and have the tool place all the
standard cells connected to the magnet object close to it. We can fix macrocells, pins of fixed
macro or IO ports as the magnet object.
For best results perform magnet placement before standard cell placement.
Command: magnet_placement

22. What is Timing driven placement:

Tool tries to place the standard cells along timing critical path close together to reduce net RC
and meet setup timing.

23. What is Congestion driven placement:

Tool tries to spread the cells where the density of cells are more for the reduction of
congestion.

24. What is High Fan-out Net Synthesis (HFNS)

In the placement stage we do this process. The process of buffering the high fan-out to
balance the load because if design has too many loads then it affects delay and transition
time. We know delay is load is directly proportional to the delay. By buffering the HFN the
load can be balanced and this process is called the HFNS.
High fanout nets are mainly reset, preset, scan enable etc. these nets are not synthesized in the
synthesis stage, also make sure you set an appropriate fan-out limit for your library using the
command set_max_fanout 20 [design_name]

25. How to use ideal clock in placement stage

Clock net is also a high fan-out nets but in placement stage we set set_ideal_clock or
set_dont_touch commands on the clock signal. If we don’t take the ideal clock here the clock
constraints like skew, insertion delay of clock buffers are not used and it affects the clock tree
building. The clock network is ideal and does not have a clock buffer tree available for
accurate clock network timing analysis. In ICC we use the following command to make sure
that the clock is ideal not propagated in the placement stage.
Set_ideal_network [all_fanout –flat –clock_tree]

26.What are the checks to be done after placement?

Checks after placement:

Check legalization
Check PG connections for all the cells.
Check congestion, density screens & pin density maps all these should be under control
Timing QOR, there should not be any high WNS violations.
Minimum max Tran and max cap violations.
Check whether all don’t touch cells & nets are preserved.
Check the total utilization of design after placement.

27.What is the reason for TIE cells insertion?

Sometimes in the netlist some unused inputs are tied to VDD/VSS (logic1/logic0). It is not
recommended to connect a gate directly to the power network, so we use TIEHI or TIELO
cells if available in the library. These are single pin cells that effectively ties the pin it
connects high or low.