Placement. Bhagyesh

Placement
Bhagyesh Rabari
What is placement ? What is required
inputs ?
• Placement is the process of placing standard cells in the rows created at floor
planning stage. The goal is to minimize the total area and interconnects cost. The
quality of routing is highly determined by the placement.
• In this stage, all the standard cells are placed in the design (size, shape & macro-
placement is done in floor-plan). Placement will be driven by different criteria like
timing driven, congestion driven, power optimization etc. Timing & Routing
convergence depends a lot on quality of placement. Different tasks in placement
are listed in next slide.
Tasks in placement
• Pre-placement
• Initial placement (Coarse placement)
• Legalizations
• Removing existing buffer trees
• High Fan-out Net Synthesis (HFNS)
• Iterations of timing/power optimizations [cell sizing, moving, net spitting,
gate cloning, buffer insertion, area recovery]
• Area recovery
• Scan-chain re-ordering
• TIE cell insertions
Pre placement
• Spare cell insertion / Metal ECO-able cells
• Magnet placement (IOs / any other interface)
• Custom / manual placement of special cells (very specific to design)
• Insertion of De-Caps (Not everyone follows this)
• Antenna diodes & buffers on block level ports
HFN’s
• All high fan-out nets will be synthesized (buffer tree) except clock nets & nets with don’t touch
attribute. Scan-enable and reset are few examples of high fan-out nets. HFNS honors max fan-out
setting.
• Different techniques used for timing optimization
• Timing converge is one of key task in placement optimization. If timing QoR is bad, then placement
cannot be qualified. Bad timing QoR at placement stage would create difficulties in timing
convergence in further stages.
• Assigning more weight to critical group path
• Timing driven placement– high effort
• Allowing LVT cells for optimizations (<5% of low / ultra low VT cells)
• In most of the designs only 15-25% of the paths will be timing critical. So giving more weight to
these critical paths during optimization will aid in optimizing critical path delays. This can be
achieved by creating group paths and assigning more weight to the critical paths.
• .
• If design is timing critical, then timing driven-placement strategy has to
chosen with high effort of optimization (trade-off with runtime). But timing-
driven placement is some design can create local congestion hot-spots & also
global congestion will increase. Cell-padding, density screens, partial
blockages and bounds can be used to reduce/fix these congestion issues.
• Controlled usage of low-VT cells will help in optimizing timing critical paths.
Most of the PnR tools have the option to control VT usage.
• Congestion reduction techniques
• Cell padding
• Use of density screens, placement blockages
• Congestion driven placement (with high effort @ cost of runtime)
• Congestion is one the major challenge in PNR of high/medium
utilization designs. Placement is first & key step where congestion
analysis begins & it should be under control. Both global & local
congestion should be minimal with no local hotspots. A though
analyses of congestion map, cell density map & pin density will be
help in deciding the quality of placement.
• Local congested hot-spots are very common in timing critical, high
utilization designs. Cluster of AOI/OAI (Boolean function cells) / any
high pin density cells will cause local hot-spots.
Power optimization
• Nowadays most of the designs are targeted to achieve less power
consumption. It’s because of growing demand of hand-held battery
operated devices (smart phones, tabs) & IOT. So we should keep an eye
on static & dynamic power dissipation and make effort to reduce power
dissipation.
• Dynamic power:
• Transition & Load capacitance are the two key parameters which can be
controlled in placement stage to get optimum dynamic power. Iteration
can be performed to arrive at optimum max transition & max
capacitance. Most of the tools have option to optimize the power.
• Dynamic power dissipation is directly proportional to toggle rate
(switching activity). So to get maximum benefit power optimization
should be done on nets with high toggle rate. ‘Low power placement’
helps to identify the net/cells with high toggle rates & load
capacitance (wire length) is optimized (reduced) to reduce power
dissipation.
• Leakage power:
• High VT & Regular VT cells will have less leakage power compared to
low & ultra low VT cells. So it’s good idea to block / allow partial
usage of low & ultra VT cells.
Scan chain re ordering
• DFT tool flow makes a list of all the scanable flops in the design, and
sorts them based on their hierarchy and perform scan stitching (clock
domains, maximum chain length constraints will be considered). Scan-
chain at this stage will not be layout friendly.
• In APR tool scan chains are reordered on the basis of placement of
flops & Q-SI routing. This is nothing but scan-chain reordering. Scan-
chain reordering helps to;
• Reduce congestion, Total wire-length
• Require fewer repeaters in Q-SI path
Scan chain post Synthesis
If scan chain reordering is not done, congestion &
net/wire length will increase.
Same flop placement with scan-chain reordered has
better congestion & wire / net lengths are reduced.
Required inputs
Gate level netlist,
• Floor planned design,
• Design libraries,
• Design constrains,
• Technology file.
• Logical libs
• Physical libs
• DEF from power plan
What if design has a different
voltage area ?
• Placement flow is almost same. But in case of Abutted voltage area designs, an
extra stage “Voltage Area Feed-through” is required, before placement stage.
• Following tasks are done in VA-FT stage:
• Enabling VA-FT creation in tool flow
• Quick placement of the design (Requirement of VA-FT will known only after
placement of all standard cells)
• Global route (To identify where all VA-FTs are required)
• VA-FT creation
• Disable VA-FT
• Continue with place & optimizations
Why Placement ?
• Placement is a key factor in determining the performance of a circuit. Placement largely

determines the length and hence, the delay of interconnects wires. Interconnects delay
can consumes as much as 75% of clock cycle in advance design. Therefore, a good
placement solution can substantially improve the performance of a circuit.
• Placement determines the routing ability of a design. A well constructed placement
solution will have less routing demand(i.e., shorter total wire length) and will distributes
the routing demand more evenly to avoid routing hotspots.
• Placement decides the distribution of heat on a die surface. An uneven temperature
profile can lead to reliability and timing problems.
• Power consumption is also affected by placement. A good placement solution can be
reduce the capacitive load because of the wires (by having shorter wire and larger
separation between adjacent wires). Hence the switching power consumption can be
reduced.
Goal of the placement
• Assign the interconnect area and location of the all the logic cell
within the flexible block.
• Minimize the interconnect length and ASIC Area.
Stages in the Placement
• In placement there are 3 stages
• Global placement
• Legalization
• Detail placement
Global placement
• Global placement aims at generating a rough placement solution that
may violate some placement constrains(e.g., there may be overlaps
among modules) while maintaining a global view of whole netlist.
• Objective ->To minimize the interconnect wire lengths
Legalization
• Legalization makes the rough solution from global placement
legal(i.e., no placement constraint violation) by moving modules
around locally.
Detail Placement
• Detailed placement further improves the legalized placement solution
in an iterative manner by rearranging a small group of modules in a
local region while keeping all other modules fixed.
• Objective -> To meet design constraints such as Timing/Congestion
and to finalize standard cell placement.
Quality parameters.
• Logical equivalence check & low power checks
• Check legalization
• Check PG connections of all the cells
• Check congestion, place density & pin density maps. All these should be
under control
• Timing QoR / Convergence. There should not be any high WNS violations &
TNS, NVP must be under control
• Minimal max tran & max cap violations
• Check whether all don’t touch cells & nets are preserved
• Check for don’t use cells (Should be Zero/ same as post Syn)

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• Placement is a key factor in determining the performance of a circuit. Placement largely

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