Appendix A

Capacitance–Voltage Measurements

C–V measurements are a powerful tool for the characterisation of thin-film dielectrics
and their interfaces with semiconductors. Extensive use of such measurements is
made in this work. This appendix describes the principles underlying C–V measure-
ments, and details the analysis used to extract material parameters of interest. For a
more thorough discussion of the theoretical basis, the interested reader is referred to
the definitive work of Nicollian and Brews [1].

A.1 Principles

A.1.1 The MIS Capacitor

The sample structure used for C–V measurements is the MIS capacitor, shown in
Fig. A.1. This structure typically consists of a semiconductor wafer substrate covered
on one side with a thin-film dielectric layer, over which is deposited a metal gate
contact which defines the device area. The structure is contacted ohmically at the
semiconductor rear and at the gate, which form the two electrodes of the capacitor.
C–V measurements of MIS structures probe the variation of the spatially extended
charge distribution in the semiconductor (the space-charge region) in response to a
time-varying voltage applied to the metal gate. This charge mirrors charges present
at the semiconductor–insulator interface and in the insulator itself, as well as in the
gate contact, and C–V measurements therefore contain information about the charge
centres that give rise to each of these contributions.
The capacitive response of each of these charge components—the free charge in
the semiconductor, interface-trapped charge, and insulator charge—possesses a char-
acteristic dependence on the semiconductor surface potential and on the frequency
of potential variations. Thus, by measuring the C–V characteristics of a given device
across a range of gate bias voltages at both high and low frequencies, the various
charge contributions may be distinguished.

© Springer International Publishing Switzerland 2016 181

L.E. Black, New Perspectives on Surface Passivation: Understanding
the Si–Al2 O3 Interface, Springer Theses, DOI 10.1007/978-3-319-32521-7
182 Appendix A: Capacitance–Voltage Measurements

Fig. A.1 Schematic of the MIS structure used in C–V measurements. Typical dimensions are
indicated

Furthermore, since the relationship between the semiconductor charge distribution

and the gate bias is influenced by the ionised dopant concentration in the semicon-
ductor, as well as the dielectric properties of the insulator layer, C–V measurements
also contain information about these device properties. In the following sections we
describe how these various parameters influence the measured C–V characteristics,
and how they may be systematically extracted from experimental C–V data.

A.1.2 Basic Equations

Figure A.2 shows schematically the energy band diagram of the MIS capacitor under
bias, along with the corresponding distribution of the various charges. The semicon-
ductor potential φ(x) is defined by qφ(x) ≡ E F − E i (x), while the value of φ(x) in
the semiconductor bulk (x → ∞) is called the bulk potential φb . The gate voltage Vg
designates the potential applied to the gate contact with respect to the grounded semi-
conductor substrate, while ψs is the induced potential at the semiconductor surface
relative to φb .
The charge Q g induced at the metal gate by the applied Vg is balanced by the
insulator fixed charge Q f , interface trapped charge Q it , and semiconductor charge
Q s . Charge neutrality dictates that

Q g (ψs ) + Q s (ψs ) + Q f + Q it (ψs ) = 0, (A.1)

where the dependence of the various charges on ψs has been indicated.

Vg is related to ψs and to the charge by

Q s + (1 + xc /ti )Q f + Q it
Vg = − + ψs + Wms , (A.2)
Ci /A
Appendix A: Capacitance–Voltage Measurements 183

Fig. A.2 Energy band

diagram and associated
charge distribution (ρ(x))
diagram of the (p-type) MIS
capacitor under bias
(depletion), showing the
relationship between the
various potentials and
charges described in the text.
Arrows pointing down (up)
denote positive (negative)
potentials

where xc is the location of the insulator charge centroid relative to the semiconductor–
insulator interface, Ci is the insulator capacitance, A is the area of the metal gate, and
Wms is the work-function difference between the metal gate and the semiconductor
bulk. It will be convenient to define a flatband voltage V f b , as the gate voltage
corresponding to ψs = 0. In this case we also have Q s = 0, so that

(1 + xc /ti )Q f + Q it
Vfb = + Wms . (A.3)
Ci /A

The small-signal differential capacitance C of the MIS capacitor is defined by

d Qg
C(Vg ) ≡ A. (A.4)
d Vg

Similarly the semiconductor capacitance Cs and interface state capacitance Cit are
defined by
d Qs
Cs (ψs ) ≡ − A, (A.5)
dψs

d Q it
Cit (ψs ) ≡ − A. (A.6)
dψs

The insulator fixed charge is assumed to be independent of ψs (d Q f /dψs = 0), so

that no capacitive component is associated with this charge.
Combining (A.4)–(A.6) with (A.1) and (A.2), and using d Q f /dψs = 0, the total
low-frequency capacitance Cl f of the MIS capacitor is related to its components by
184 Appendix A: Capacitance–Voltage Measurements

Fig. A.3 a Low frequency, (a) (b)

and b high frequency
equivalent circuits of the
MIS capacitor
Ci
Ci

Cs Cit
Cs

Cl−1 −1 −1
f = C i + (C s + C it ) . (A.7)

The corresponding low-frequency equivalent circuit of the MIS capacitor is shown

in Fig. A.3a. The insulator capacitance Ci is connected in series with the parallel
combination of the semiconductor capacitance Cs and the interface state capacitance
Cit . At high frequencies, interface states are unable to follow variations in the Fermi
level, and (A.7) is reduced to

C h−1f = Ci−1 + Cs−1 , (A.8)

with the corresponding equivalent circuit shown in Fig. A.3b.

The insulator capacitance Ci is given by

Ci = i A/ti , (A.9)

where i is the insulator permittivity, and ti is the insulator thickness. It is common

to refer to an equivalent oxide thickness (EOT), given by calculating ti from (A.9)
with i equal to the value for thermal SiO2 (3.9 × 0 ) [2]
Assuming that Dit is a slowly varying function of energy, Cit is simply related to
Dit by
Cit (ψs ) = q ADit (ψs ). (A.10)

Finally, assuming Fermi–Dirac statistics apply, Q s is given by

     
E F − E c + qψs E F − Ec
Q s = (2kT s ) 1/2
Nc F3/2 − F3/2 +
kT kT
    
E v − E F − qψs Ev − E F
Nv F3/2 − F3/2 +
kT kT
 q
 1/2
(N A − N D ) ψs . (A.11)
kT
Appendix A: Capacitance–Voltage Measurements 185

Fig. A.4 Modelled ideal

C–V curve (no interface
states, V f b = 0 V) of a
silicon MIS capacitor at low
and high frequencies. The
voltage ranges corresponding
to accumulation, depletion,
weak inversion, and strong
inversion are indicated

In the low-frequency case, Cs is then found by substituting Q s from (A.11) in (A.5):

  
qs A E F − E c + qψs
Cs (ψs ) = Nc F1/2 −
Qs kT
  
E v − E F − qψs
Nv F1/2 + NA − ND . (A.12)
kT

For Boltzmann (non-degenerate) statistics, the Fermi integrals in (A.11) and (A.12)
may be replaced with exponential functions.
Figure A.4 shows low-frequency capacitance Cl f versus gate voltage Vg , calcu-
lated from (A.2), (A.7), (A.9), (A.11), and (A.12), with Dit , Q f , and Wms = 0.
In accumulation and strong inversion, Cs is large, and Cl f approaches Ci , while in
depletion and weak inversion Cl f is limited by the much smaller value of Cs .
At high frequencies both the inversion layer charge and the interface state charge
are unable to follow the AC voltage signal, but do follow changes in the gate bias
(although spatial redistribution of the inversion layer charge in response to the AC
signal does occur). As a result the high-frequency capacitance C h f saturates at a low
value in strong inversion rather than increasing as for low frequencies, as shown
in Fig. A.4. The resulting expression for Cs is somewhat more complex than for
the low-frequency case, and we do not attempt to provide a derivation here. Exact
expressions for the non-degenerate case are given by Nicollian and Brews [1].
Thus, to the first approximation, Ci is independent of the applied bias and fre-
quency (though see the following section on the frequency dispersion of the permit-
tivity), while Cs and Cit are strong functions of both. These different dependencies
may be exploited in order to determine the value of each component.
186 Appendix A: Capacitance–Voltage Measurements

A.2 Measurement Corrections

Measured C–V data is subject to systematic errors and non-idealities that must be
taken into account to allow an accurate analysis. This section details the correction
procedure applied to measured C–V data in this work.

A.2.1 Parallel and Series Representations

The complex admittance measured by the LCR meter is a vector quantity with real
and imaginary components that can be described using a number of equivalent rep-
resentations. In general for C–V analysis it is most conveniently described as the
parallel combination of one capacitive and one conductive component. We shall
refer to the measured values of these components as Cmp and G mp respectively. The
corresponding equivalent circuit is shown in Fig. A.5a.
In some situations, however, it is useful to convert this representation into an
equivalent series form, with capacitive and resistive components Cms and Rms , as
shown in Fig. A.5b. The following set of relationships may be used to convert between
the two equivalent forms.
G 2mp + ω2 Cmp
2
Cms = , (A.13)
ω2 Cmp

G mp
Rms = , (A.14)
G 2mp + ω2 Cmp
2

Cms
Cmp = , (A.15)
1 + (ω Rms Cms )2

(a) (b)

Cms

Cmp Gmp

Rms

Fig. A.5 a Parallel and b series equivalent circuits

Appendix A: Capacitance–Voltage Measurements 187

1
G mp = 2 −1
. (A.16)
Rms + (ω2 R ms C ms )

A.2.2 Parasitic Circuit Elements

A real C–V measurement contains contributions from parasitic elements external

to the MIS sample, arising from non-idealities in the measurement system, wires,
probes, rear contact, and chuck. These may be described by additional elements in
the equivalent circuit of the measurement, as shown in Fig. A.6. Parasitic elements
which may be present include parallel capacitance and conductance due to the mea-
surement setup (C pp and G pp ), contact capacitance and resistance (Cc and Rc ), and
equivalent series resistance and inductance (Rs and L). C pp and G pp are corrected for
by calibration of the capacitance meter, while Cc and Rc can be made negligible with
proper ohmic contacting. This leaves Rs and L as generally non-negligible parasitic
elements that must be evaluated and corrected for in careful measurements.
The equivalent series resistance Rs is usually due largely to the resistance of
the semiconductor bulk between the rear contact and the edge of the space-charge
region. The effect of Rs is to decrease Cmp and increase G mp at high frequencies.
Rs is most straightforwardly determined from the admittance in accumulation. In
strong accumulation, the resistance contribution of interface states is shunted by the
large semiconductor capacitance, and Rs = Rms , where Rms may be determined
from (A.14) [1].

Fig. A.6 a Full equivalent

L Rs
circuit corresponding to the
C–V measurement, including
parasitic elements of the
measurement system

Gpp
Cp Gp

Cc Rc
Cpp
188 Appendix A: Capacitance–Voltage Measurements

In addition to series resistance, series inductance L within the measurement circuit

is often a significant source of error, acting to increase the measured capacitance
at high frequencies. Like Rs , L is most easily determined in accumulation, where
the impedance of the device itself is minimised. Unlike Rs however, L cannot be
determined from measurements at a single frequency, since L appears in series with
the device capacitance. Instead, measurements at two or more frequencies must be
used to distinguish the inductive and capacitive components through their different
frequency dependence.
Figure A.7 shows an example of the determination of L by this method. Cms is
measured as a function of frequency in accumulation, and L is determined by fitting
the measured capacitance with an equivalent circuit model including a frequency-
dependent capacitance (see the later part of this section on the frequency dispersion
of the permittivity) in series with an inductance. For the measurement system used
in this work, L was found to be a function of the capacitance of the device under
test. This dependence was assessed by evaluating L for capacitor test structures with
nominal capacitances ranging from 47 to 1000 pF, in the same way as shown in
−1
Fig. A.7. The results are plotted in Fig. A.8 as a function of Cms . It was found that L
−1
possessed a linear dependence on Cms , given by
−1
L = a + bCms , (A.17)

where a = 1.46 µH and b = 1.65 × 10−16 FH.1 Rather than assess L in each
individual case, this empirical relationship was subsequently used to determine L
for samples measured with this system.
The measured admittance is most straightforwardly corrected for equivalent series
resistance and inductance by first converting to its series form via (A.13) and (A.14).
 
Corrected series resistance and capacitance Rms and Cms may then be calculated
from

Rms = Rms − Rs , (A.18)

and
1 1

= + ω2 L . (A.19)
Cms Cms

Corrected parallel capacitance Cmp , and conductance G mp , may subsequently be
 
calculated from Cms and Rms via (A.15) and (A.16). These values are those used in
subsequent analysis.

1 Wenote that the values of a and b are likely to depend on the details of the measurement setup,
and would therefore need to be newly determined if significant changes were made to this setup.
Appendix A: Capacitance–Voltage Measurements 189

Fig. A.7 Experimental Cms

versus frequency f for an
n-type Al2 O3 MIS sample in
accumulation. Fits using an
equivalent circuit model with
and without the inclusion of
series inductance are also
shown. The linear slope of
Cms with log f at lower
frequencies is due to
frequency dispersion of the
insulator permittivity. At
higher frequencies, Cms
increases sharply due to
inductance

Fig. A.8 Equivalent series

inductance L versus 1/Cms
for capacitor test structures
with a range of nominal
capacitances, measured by
the system used in this work

A.2.3 Quasi-Static Capacitance Correction

While the low-frequency capacitance is not subject to the same parasitic effects as
the high-frequency measurement, it can suffer from other sources of error. Because
of the practical difficulties in performing true low-frequency AC capacitance mea-
surements,2 the “low-frequency” capacitance is instead commonly measured using

2 It
should be noted that “low-frequency” is defined relative to the response of the interface states
and the semiconductor minority carriers. At low-frequency these should be in thermal equilibrium
190 Appendix A: Capacitance–Voltage Measurements

Fig. A.9 Quasi-static

capacitance measured for an
Al2 O3 MIS capacitor in
accumulation, as a function
of the inverse voltage sweep
rate. The corrected device
capacitance is found from
the intercept of the linear fit
at (d Vg /dt)−1 = 0

the linear voltage-ramp method (a so-called “quasi-static” capacitance3 ) [3]. In this

method, the capacitance is calculated from the displacement current Id that flows in
response to a linear voltage sweep with sweep rate d Vg /dt, using the relationship
C = Id (d Vg /dt)−1 . However, besides the displacement current, additional contribu-
tions to the measured current may be present due either to leakage current between
the semiconductor and the gate, or to uncompensated background current within the
measurement system. These currents may be distinguished from the displacement
current by the fact that they are independent of the sweep rate, and thus constitute a
static current Is . In the presence of such currents the measured capacitance Cm may
be expressed as [4, 5]
Cm = C + Is (d Vg /dt)−1 . (A.20)

Equation (A.20) implies that the corrected capacitance C may be determined from
measurements at two or more different sweep rates. Figure A.9 shows this graphically
by plotting experimentally determined Cm as a function of inverse sweep rate for a
p-type Al2 O3 MIS capacitor in accumulation. As expected from (A.20), Cm shows a
linear dependence on (d Vg /dt)−1 , with a slope equal to Is (in this particular case Is
can be shown to be due to the measurement system rather than to leakage current).
The corrected device capacitance C is given by the intercept at (d Vg /dt)−1 = 0.

(Footnote 2 continued)
with the surface potential over the full C–V curve. This condition is usually not achieved at the
low-frequency limit of typical AC capacitance meters at room temperature.
3 The term “quasi-static” is generally used elsewhere in this work when referring to low-frequency

C–V measurements performed by the voltage-ramp method.

Appendix A: Capacitance–Voltage Measurements 191

(a) (b)

Fig. A.10 Experimental examples of the use of quasi-static C–V measurements at different sweep
rates to correct for the effects of a non-zeroed background current within the measurement system,
and b leakage current through the dielectric

In general, measurements at two different sweep rates are sufficient to correct

the quasi-static capacitance for static current contributions via (A.20).4 Figure A.10
shows examples of such a correction applied to experimental quasi-static C–V data.
This procedure is routinely applied to C–V measurements presented in this work.

A.2.4 Permittivity Frequency Dispersion

In conventional C–V analysis it is implicitly assumed that Ci is independent of the

measurement frequency, so that high- and low-frequency (or quasi-static) C–V mea-
surements may be directly compared. In fact, the insulator permittivity is usually
significantly frequency-dependent in the frequency range of the measurement, due
to broad frequency dispersion of the (dipolar) dielectric response. This may readily be
observed by measuring the accumulation capacitance as a function of frequency, as
shown in Fig. A.7. Such frequency dispersion of the permittivity is a general feature
of dielectric materials [6], and is well-attested for Al2 O3 [7–9]. As a consequence,
the accumulation capacitance measured at low frequencies or under quasi-static con-
ditions is expected to be greater than that measured at high frequencies.5
Therefore, in comparing measurements made at high and low frequencies, we
need to take into account that Ci is frequency-dependent. The simplest way of doing

4 Alternatively, Is may also be determined by separate current–voltage measurements.

5 While this is indeed commonly observed in experimental data within the literature, it is typically
attributed to measurement error when it is noted at all.
192 Appendix A: Capacitance–Voltage Measurements

Fig. A.11 Example of

correction procedure applied (a) (b)
to experimental
high-frequency (1 MHz)
capacitance. The measured
parallel capacitance is shown
a without corrections, b after
correction for equivalent
series resistance and c
inductance, and d after
adjusting for the frequency (c) (d)
dispersion of the insulator
permittivity via (A.21)

this is to adjust one or other measurement for the difference in Ci . For C–V analysis,
we are primarily interested in the static (zero frequency) permittivity, since this is the
value which is relevant for the determination of the insulator fixed charge Q f from
the flatband voltage shift. This value is most closely approached under the conditions
of the low-frequency or quasi-static capacitance measurement. Therefore we choose
to calculate an adjusted high-frequency capacitance C h f according to
 −1
C h f = C h−1f + Ci,l
−1
f − C −1
i,h f , (A.21)

where Ci,h f and Ci,l f are the insulator capacitances at high and low frequencies
−1 −1 
respectively. The value of Ci,l f − C i,h f in (A.21) is chosen such that C h f = Cl f in
strong accumulation. Figure A.11 shows an example of such an adjustment applied
to experimental data.

A.3 Parameter Extraction

Having corrected the experimental data for measurement errors and inconsistencies,
we next wish to analyse it in order to extract various physical parameters of inter-
est. These include the insulator capacitance, dopant concentration, flatband voltage
(and by extension, the insulator charge), and the interface state density. This section
describes the procedure used to extract these parameters in this work.
Appendix A: Capacitance–Voltage Measurements 193

A.3.1 Insulator Capacitance

In the expression for the high-frequency MIS capacitance (Eq. (A.8)), the insulator
capacitance Ci appears in series with the semiconductor capacitance Cs . In order
to extract Ci it is therefore necessary to make some assumption about Cs . Most
commonly, it is assumed that Cs  Ci in strong accumulation, so that Ci is simply
given by the maximum measured capacitance in accumulation. This approximation
is commonly used because of its simplicity, and is reasonable for thicker dielectrics
(100 nm), for which Ci is small. However, it becomes an increasingly poor approx-
imation as insulator thickness is decreased, especially for high-κ materials.
A number of more sophisticated approximations have been proposed for extraction
of Ci [10–15]. In this work we use that of McNutt and Sah [11], as extended by Walstra
and Sah [13]. These authors derived the following expression for Ci based on the
Boltzmann approximation for the carrier statistics in strong accumulation:

 1/2 −1
kT dC
Ci = C 1 − −2 C −1 . (A.22)
q d Vg

Equation (A.22) implies that a plot of (−2kT /qC −1 (dC/d Vg ))1/2 versus C in non-
degenerate strong accumulation will have a slope of −Ci−1 and an intercept of Ci
at dC/d Vg = 0. In practice, the value derived from the intercept is significantly
less sensitive to the assumed carrier statistics, and is therefore preferred. Figure A.12
shows an experimental example of such a plot, together with the fit used to extract
Ci . For this sample, use of (A.22) to determine Ci results in a value 8 % higher

Fig. A.12 Example of Ci

extraction from experimental
C–V data via Eq. (A.22)
194 Appendix A: Capacitance–Voltage Measurements

than the maximum measured capacitance. The relative difference increases as film
thickness is reduced. Equation (A.22) is still an approximation, because it is based on
Boltzmann statistics, and hence neglects degeneracy and surface quantisation effects.
Because of this, it is still expected to underestimate Ci , though to a significantly lesser
extent than when Ci is taken as equal to the maximum measured capacitance.

A.3.2 Dopant Concentration

The dopant concentration Ndop is most accurately determined from the slope of the
capacitance in depletion, according to [1]

 −1  
d 1 1 − Cl f /Ci
Ndop = 2 qs A2 , (A.23)
d Vg C h2 f 1 − C h f /Ci

where the latter term accounts for voltage stretch-out due to interface states. The
corresponding depletion layer width w D is given by

w D = s A(C h−1f − Ci−1 ). (A.24)

Using (A.23) and (A.24), Ndop may be plotted as a function of distance from the
semiconductor surface.
Figure A.13 shows Ndop versus w D calculated in this way for samples with two
different Al2 O3 films fabricated on the same 8.2  cm p-type substrate. The apparent

Fig. A.13 Experimental

Ndop profiles calculated
using Eqs. (A.23) and
(A.24). Data are shown for
two samples processed on
the same p-type substrate
with different Al2 O3 films,
distinguished by the value of
Dit at midgap. Closed (open)
symbols show Ndop with
(without) correction for
stretch-out due to interface
states
Appendix A: Capacitance–Voltage Measurements 195

rise of Ndop near the surface is due to the failure of the depletion approximation—
which underlies Eqs. (A.23) and (A.24)—for small departures from flatbands [1].
The subsequent dip in Ndop , visible most prominently for the sample with higher
Dit , is due to the distortion of the 1 MHz high-frequency capacitance by interface
state response near flatbands [1]. Its magnitude thus depends on Dit . Ndop should be
extracted from the flat part of the profile following the dip. Figure A.13 also shows
that neglecting the interface state correction term in (A.23) results in significant error
in the apparent Ndop , especially as Dit increases.

A.3.3 Flatband Voltage and Charge

A widely used method of determining V f b is to calculate the theoretical capacitance

at flatbands from Ci and Ndop using (A.8) and (A.12), and then to find the voltage
corresponding to this capacitance on the experimental high-frequency C–V curve.
This method is commonly used because of its simplicity. However, it is subject to
systematic error due to the failure of the high-frequency assumption at flatbands
for typical measurement frequencies. That is, interface state response at flatbands is
non-zero, and Cit > 0. This results in systematic over(under)estimation of V f b for
p-type (n-type) substrates. This error increases with increasing Dit .
As proposed by [1], a better point of comparison is the capacitance in depletion,
where interface state response is slower, and the assumption of high-frequency con-
ditions is more usually valid. The most straightforward way to make this comparison
is to calculate a gate voltage Vg0 corrected for stretch-out due to interface states
 Vg
Ci + Cs
Vg0 = d V. (A.25)
Vfb Ci + Cs + Cit

We begin by calculating Vg0 from (A.25) making an arbitrary initial guess for V f b .
By plotting 1/C 2 versus Vg0 calculated in this way, and an ideal 1/C 2 versus Vg0
calculated from (A.2), (A.8), and (A.12), with Dit , Q f , and Wms = 0, we should
obtain two parallel linear curves in depletion, with a slope given by 2(qs Ndop )−1 .
We label the voltage shift of the measured plot relative to the ideal plot Vg0 . V f b
is then found as the value of Vg for which Vg0 calculated from (A.25) is equal to
Vg0 . Figure A.14 shows an experimental example of the determination of Vg0 in
this manner.
To make use of (A.25) to determine V f b , we must know Cit as a function of gate
voltage. The formulation given by [1] for Vg0 uses Cit derived from the combined
high–low frequency capacitance method [16]. This has the advantage of allowing an
explicit determination of Vg0 , since Dit determined by this method is independent
of V f b . However, it results in systematic error in V f b , due to the fact that Dit near
flatbands is systematically underestimated by this method. In this work, we instead
use Dit calculated from (A.29) for the purpose of determining (A.25). Since Dit
196 Appendix A: Capacitance–Voltage Measurements

Fig. A.14 Example of

experimental determination
of Vg0 using (A.25).
Closed (open) symbols show
experimental data plotted
against Vg0 (Vg ), where the
latter is uncorrected for
stretch-out due to interface
states

from (A.29) depends on V f b , this approach requires an iterative solution, but it

avoids systematic error in V f b .
From (A.3), V f b is related to the insulator fixed charge Q f and interface state
trapped charge Q it by

(1 + xc /ti )Q f + Q it
Vfb = + Wms . (A.26)
Ci /A

Assuming xc = 0 (i.e. Q f is located at the semiconductor–dielectric interface), we

may write
Ci
Q tot = Q f + Q it = (V f b − Wms ). (A.27)
A
Given V f b , Eq. (A.27) may thus be used to assess the sum of Q f and Q it , designated
Q tot . When Q it is negligible (e.g. for samples with low Dit ), Q tot ≈ Q f .
The metal–semiconductor work-function difference Wms is given by

Wms = φm − (φs − φb ), (A.28)

where φm and φs are the metal and semiconductor work-functions (the latter defined
with respect to E i ), and φb is the semiconductor bulk potential which is determined
by the dopant concentration. The values of φm and φs used in this work are those
recommended by Kawano [17] of 4.23 V for Al, 4.71 V for intrinsic 100 Si, and
4.79 V for intrinsic 111 Si.
Appendix A: Capacitance–Voltage Measurements 197

A.3.4 Interface State Density

From (A.7) and (A.10), Dit may be related to the low-frequency (quasi-static) capac-
itance Cl f by [18]

q ADit (ψs ) = Cit = (Cl−1 −1 −1

f − Ci ) − Cs (ψs ). (A.29)

Cs in (A.29) may be calculated using (A.12), following determination of ψs (Vg ).

The latter may be calculated from the low-frequency C–V curve via [18]
 Vg  
Cl f
ψs (Vg ) = 1− d V. (A.30)
Vfb Ci

Alternatively, Cs may be determined directly from the difference between Cl f and

C h f . Combining (A.8) with (A.29) leads to [16]

q ADit (ψs ) = Cit = (Cl−1 −1 −1

f − Ci ) − (C h−1f − Ci−1 )−1 . (A.31)

This has the advantage of avoiding the need to calculate Cs theoretically. However
the use of (A.31) results in systematic underestimation of Dit near flatbands due
to non-zero interface state response at practical measurement frequencies [1]. Dit
determined by (A.29) is more accurate in this range.
Dit can also be calculated from the voltage stretch-out of the high-frequency C–V
curve as described by Terman [19]. However, this method is also subject to significant
error near flatbands due to non-zero interface state response, and additionally requires
accurate knowledge of the dopant concentration, which cannot be determined reliably
from C h f alone when interface states are present [1]. Consequently, the use of (A.29)
or even (A.31) to determine Dit is preferable. The former is used in this thesis.

A.3.5 General Procedure

The general procedure followed in this work for parameter extraction from corrected
C–V data is as follows:
1. Ci is determined from (A.22).
2. Ndop is determined from (A.23).
3. An initial guess value for V f b is determined using the theoretical flatband capac-
itance calculated from (A.8) and (A.12).
4. ψs (Vg ) is determined from (A.30).
5. Dit (ψs ) is determined from (A.29).
6. V f b is determined from (A.25).
7. Steps 4–6 are iterated to determine V f b and Dit (ψs ) self-consistently.
8. Q tot is evaluated from V f b and Ci via (A.27).
198 Appendix A: Capacitance–Voltage Measurements

References
[1] Nicollian, E.H., Brews, J.R.: MOS (Metal Oxide Semiconductor) Physics and Technology.
Wiley, New York (1982)
[2] Sze, S.M.: Semiconductor Devices: Physics and Technology, 3rd edn. Wiley, Hoboken (2002)
[3] Kuhn, M.: A quasi-static technique for MOS C-V and surface state measurements. Solid-State
Electron. 13, 873–885 (1970)
[4] Monderer, B., Lakhani, A.A.: Measurement of the quasi-static C-V curves of an MIS structure
in the presence of charge leakage. Solid-State Electron. 28, 447–451 (1985)
[5] Schmitz, J., Weusthof, M.H.H., Hof, A.J.: Leakage current correction in quasi-static C-V mea-
surements. In: Proceedings of the International Conference Microelec-tronic Test Structures,
IEEE Electron Devices Society, pp. 179–181 (2004)
[6] Jonscher, A.K.: Dielectric relaxation in solids. J. Phys. D: Appl. Phys. 32, R57 (1999)
[7] Aboaf, J.A.: Deposition and properties of aluminum oxide obtained by pyrolytic decomposi-
tion of an aluminum alkoxide. J. Electrochem. Soc. 114, 948–952 (1967)
[8] Duffy, M.T., Revesz, A.G.: Interface properties of Si-(SiO2 )-Al2 O3 structures. J. Electrochem.
Soc. 117, 372–377 (1970)
[9] Rüße, S., Lohrengel, M., Schultze, J.: Ion migration and dielectric effects in aluminum oxid-
efflms. Solid State Ionics 72(Part 2), 29–34 (1994)
[10] Maserjian, J., Petersson, G., Svensson, C.: Saturation capacitance of thin oxide MOS structures
and the effective surface density of states of silicon. Solid-State Electron. 17, 335–339 (1974)
[11] McNutt, M.J., Sah, C.T.: Determination of the MOS oxide capacitance. J. Appl. Phys. 46,
3909–3913 (1975)
[12] Walstra, S.V., Sah, C.-T., Thin oxide thickness extrapolation from capacitance-voltage mea-
surements. IEEE Trans. Electron Devices 44, 1136–1142 (1997)
[13] Walstra, S.V., Sah, C.-T.: Extension of the McNutt-Sah method for measuring thin oxide
thicknesses of MOS devices. Solid-State Electron. 42, 671–673 (1998)
[14] Vincent, E., Ghibaudo, G., Morin, G., Papadas, C.: On the oxide thickness extraction in
deep-submicron technologies. In: Proceedings of the IEEE International Conference Micro-
electronic Test Structures, pp. 105–110 (1997)
[15] Ghibaudo, G., Bruyere, S., Devoivre, T., DeSalvo, B., Vincent, E.: Improved method for
the oxide thickness extraction in MOS structures with ultrathin gate dielectrics. IEEE Trans.
Semicond. Manuf. 13, 152–158 (2000)
[16] Castagné, R., Vapaille, A.: Description of the SiO2 –Si interface properties by means of very
low frequency MOS capacitance measurements. Surf. Sci. 28, 157–193 (1971)
[17] Kawano, H.: Effective work functions for ionic and electronic emissions from mono- and
polycrystalline surfaces. Prog. Surf. Sci. 83, 1–165 (2008)
[18] Berglund, C.N.: Surface states at steam-grown silicon-silicon dioxide interfaces. IEEE Trans.
Electron Devices 13, 701–705 (1966)
[19] Terman, L.M.: An investigation of surface states at a silicon/silicon oxide interface employing
metal-oxide-silicon diodes. Solid-State Electron. 5, 285–299 (1962)
Appendix B
The Conductance Method

The C–V method (Appendix A) may be used to evaluate the energetic distribution
of interface states, but provides only limited information concerning their capture
cross-sections, which determine their effectiveness as recombination centres. For
this purpose, other, related techniques must be employed, such as DLTS (which
examines the temperature dependence of time-domain capacitance transients), or
measurements of the MIS parallel conductance as a function of frequency. The latter
technique, generally referred to as the conductance method, is the subject of this
appendix.
The use of the conductance method to determine interface state properties was
pioneered by Nicollian and Goetzberger [1, 2], and subsequently employed by numer-
ous authors, particularly for the characterisation of the Si–SiO2 interface. A detailed
exposition of the method, together with a comprehensive survey of work up to that
date, was given by [3].
We first briefly describe the principles of the method, before presenting the relevant
theory and equations. Following Cooper and Schwartz [4], we include minority
carrier effects in our treatment of the equivalent circuit of the interface states. These
are usually neglected, which unnecessarily limits the range of validity of the method.
The derivation of the equations closely follows that of [4], except that here full
expressions for all of the elements of the equivalent circuit are given explicitly rather
than simply implied.

B.1 Principles

The principle of the conductance method is based on the energy loss that occurs when
interface state capture and emission occurs out of phase with an AC variation of the
surface Fermi level. At low frequencies, the interface states are able to change their
occupancy in response to Fermi-level variations in order to maintain equilibrium,
and no energy loss occurs. At very high frequencies, Fermi-level variations occur
too quickly for the interface states to follow at all, so that energy loss is again zero.

© Springer International Publishing Switzerland 2016 199

L.E. Black, New Perspectives on Surface Passivation: Understanding
the Si–Al2 O3 Interface, Springer Theses, DOI 10.1007/978-3-319-32521-7
200 Appendix B: The Conductance Method

However, at intermediate frequencies, interface state response occurs out of phase

with the applied signal, leading to energy loss as electrons transition from higher to
lower energy states.
This energy loss manifests as an increase of the small-signal parallel conductance
G p of the MIS capacitor. The component of G p due to the interface state branch of
the MIS equivalent circuit, designated G p , is given by

G p ωCi2 G p
= 2 . (B.1)
ω G p + ω2 (Ci − C p )2

When plotted as G p /ω versus frequency on a log scale, this contribution forms

a peaked function with a peak frequency corresponding to the time constant for
majority carrier capture, and an integrated area proportional to the interface state
density. The peak width is broadened relative to that expected from single-time-
constant behaviour due to short-range statistical fluctuations of the surface potential,
described by the standard deviation of surface potential σs . Minority carrier contri-
butions alter the shape of the peak at lower frequencies.
Parameter extraction requires fitting such experimental G p /ω data over a range
of frequencies with a numerical model. The following section describes the equivalent
circuit model used for this purpose.

B.2 Equivalent Circuit

The small-signal equivalent circuit of the MIS capacitor including an energetic distri-
bution of interface states is shown in Fig. B.1. Each state may exchange charge with
the valence and conduction bands via capture resistances R ps and Rns for holes and
electrons, and may store charge on a capacitance Cit connected to the displacement
current line of the semiconductor. C I and C D are the capacitances of the inversion
layer and depletion region respectively. The values of R ps , Rns , and Cit are given by
 q −1
R ps = q ADit f t σ p vth ps , (B.2)
kT
 q −1
Rns = q ADit (1 − f t )σn vth n s , (B.3)
kT
q
Cit = q ADit f t (1 − f t ), (B.4)
kT
where   −1
Et − E F
f t = 1 + exp (B.5)
kT

is the Fermi occupation function for interface states of energy E t .

Appendix B: The Conductance Method 201

Ci CD

CB


Rns

CI Rns

Cit VB

Cit

Rps

Rps

Fig. B.1 Equivalent circuit of the (n-type) MIS capacitor with a distribution of interface states
throughout the semiconductor bandgap (in this case two states are shown, but an arbitrary number
may be present)

By performing a Y - transformation, the equivalent circuit of Fig. B.1 becomes

a parallel network of lumped admittance elements Ydp , Ydn , and Y pn as shown in
Fig. B.2. These elements are given by

jω Rns Cit
Ydp = , (B.6)
Rns + R ps + jω Rns R ps Cit

jω R ps Cit
Ydn = , (B.7)
Rns + R ps + jω Rns R ps Cit

1
Y pn = . (B.8)
Rns + R ps + jω Rns R ps Cit

The total lumped admittance between each node may then simply be calculated as
 
the sum of the individual Ydp , Ydn , and Y pn elements (i.e. Ydp + Ydp + Ydp + . . .).
Because each admittance depends both on the interface state energy and on the surface
carrier concentration (which varies locally due to surface potential fluctuations), this
involves a double integration over both bandgap energy and surface potential, where
the latter integral is weighted by the surface potential probability density function
202 Appendix B: The Conductance Method

Ci CD

CB

Ydp

Ydp 
Ypn
CI

Ypn

Ydn VB

Ydn

Fig. B.2 Parallel equivalent circuit of the (n-type) MIS capacitor following a Y - transformation

P(ψs ), where
 
(ψs − ψ̄s )2
P(ψs ) = (2π σs2 )−1/2 exp −(kT /q)−2 , (B.9)
2σs2

ψ̄s is the mean surface potential, and σs2 is the variance of band bending in units of
kT /q. Writing the real and imaginary parts of these admittances separately, we have
 ∞ 
G dp Ec
ω R ps Cit
= Cit P(ψs ) d E t dψs , (B.10)
ω −∞ Ev (1 + R ps /Rns )2 + (ω R ps Cit )2
 ∞  Ec
1 + R ps /Rns
Cdp = Cit P(ψs ) d E t dψs , (B.11)
−∞ Ev (1 + R ps /Rns )2 + (ω R ps Cit )2
 ∞ 
G dn Ec
ω Rns Cit
= Cit P(ψs ) d E t dψs , (B.12)
ω −∞ Ev (1 + Rns /R ps )2 + (ω Rns Cit )2
 ∞  Ec
1 + Rns /R ps
Cdn = Cit P(ψs ) d E t dψs , (B.13)
−∞ Ev (1 + Rns /R ps )2 + (ω Rns Cit )2
Appendix B: The Conductance Method 203
 ∞  Ec
Rns + R ps
G pn = P(ψs ) d E t dψs , (B.14)
−∞ Ev (Rns + R ps )2 + (ω Rns R ps Cit )2
 ∞  Ec
Rns R ps Cit
C pn = P(ψs ) d E t dψs . (B.15)
−∞ Ev (Rns + R ps )2 + (ω Rns R ps Cit )2

Finally, the total semiconductor admittance including the interface states is given
(for n-type doping) by
 
−1 −1
Ys = jωC D + Ydn + ( jωC I + Ydp )−1 + Y pn . (B.16)

Solving for the real and imaginary components gives

 
(G dp + G pn ) G dp G pn − ω2 C pn (C I + Cdp )
 
+ ω2 (C I + Cdp + C pn ) G dp C pn + G pn (C I + Cdp )
G p = G dn + , (B.17)
(G dp + G pn )2 + ω2 (C I + Cdp + C pn )2

and
 
(G dp + G pn ) G dp C pn + G pn (C I + Cdp )
 
− (C I + Cdp + C pn ) G dp G pn − ω2 C pn (C I + Cdp )
C p = C D + Cdn + .
(G dp + G pn )2 + ω2 (C I + Cdp + C pn )2
(B.18)
Analogous expressions apply for the case of p-type doping.
In order to determine Dit , σ p , σn , and σs , by the conductance method, these
parameters must be adjusted to provide a good fit between G p /ω calculated from
Eq. (B.17), and experimental data measured over a range of frequencies. In this work,
automated least-squares fitting of G p /ω data was performed using the Levenberg–
Marquardt algorithm. Interface states at different energies are probed by performing
measurements over a range of gate biases in depletion and weak inversion. C I is
generally negligible at these biases and thus may be neglected when calculating
G p /ω from (B.17). The surface potential ψs must be determined independently as
a function of gate bias using C–V measurements, as described in Appendix A. This
may then be used to calculate ps and n s in (B.2) and (B.3).

B.3 General Procedure

The general procedure followed in this work for parameter extraction from conduc-
tance measurements is as follows:
1. High- and low-frequency C–V curves are measured, and Ci , Ndop , and ψs (Vg )
are determined as described in Appendix A.
204 Appendix B: The Conductance Method

2. G p and C p are measured as a function of frequency at a bias in depletion or weak

inversion (correcting for parasitic effects as described in Appendix A).
3. G p /ω versus ω is determined from (B.1).
4. A theoretical G p /ω versus ω curve is calculated from (B.17), using initial guess
values for Dit , σ p , σn , and σs .
5. Dit , σ p , σn , and σs are determined by varying their values using a non-linear least-
squares solver (Levenberg–Marquardt) in order to minimise the mean squared
error between the measured and modelled G p /ω versus ω.
6. Steps 2–5 are repeated to determine Dit , σ p , σn , and σs for a range of energies in
the bandgap.

References
1 Nicollian, E.H., Goetzberger, A.: MOS conductance technique for measuring surface state para-
meters. Appl. Phys. Lett. 7, 216–219 (1965)
2 Nicollian, E.H., Goetzberger, A.: The Si–SiO2 interface - electrical properties as determined by
the metal-insulator-silicon conductance technique. Bell Syst. Tech. J. 46, 1055–1133 (1967)
3 Nicollian, E.H., Brews, J.R.: MOS (Metal Oxide Semiconductor) Physics and Technology. Wiley,
New York (1982)
4 Cooper, Jr. J.A., Schwartz, R.J.: Electrical characteristics of the SiO2 -Si interface near midgap
and in weak inversion. Solid-State Electron. 17, 641–654 (1974)