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    Experiment No: - 4 Date: - 04/10/2010

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    poushali_2010
    The document summarizes an experiment to design an n-channel MOSFET using Microwind layout tool. The objectives are to (1) draw a 0.5um x 0.25um nMOS transistor and simulate its characteristics, and (2) generate a netlist file. The procedure involves selecting the 0.25um technology in Microwind, drawing the n diffusion, polysilicon gate, contacts and metal layers, and simulating the static and dynamic behavior of the designed MOSFET. Screenshots of the different layout steps and output characteristics are provided.

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    Experiment No: - 4 Date: - 04/10/2010

    Uploaded by

    poushali_2010
    68 views6 pages
    The document summarizes an experiment to design an n-channel MOSFET using Microwind layout tool. The objectives are to (1) draw a 0.5um x 0.25um nMOS transistor and simulate its characteristics, and (2) generate a netlist file. The procedure involves selecting the 0.25um technology in Microwind, drawing the n diffusion, polysilicon gate, contacts and metal layers, and simulating the static and dynamic behavior of the designed MOSFET. Screenshots of the different layout steps and output characteristics are provided.

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    Exp 4

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    The document summarizes an experiment to design an n-channel MOSFET using Microwind layout tool. The objectives are to (1) draw a 0.5um x 0.25um nMOS transistor and simulate its characteristics, and (2) generate a netlist file. The procedure involves selecting the 0.25um technology in Microwind, drawing the n diffusion, polysilicon gate, contacts and metal layers, and simulating the static and dynamic behavior of the designed MOSFET. Screenshots of the different layout steps and output characteristics are provided.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    68 views6 pages

    Experiment No: - 4 Date: - 04/10/2010

    Uploaded by

    poushali_2010
    The document summarizes an experiment to design an n-channel MOSFET using Microwind layout tool. The objectives are to (1) draw a 0.5um x 0.25um nMOS transistor and simulate its characteristics, and (2) generate a netlist file. The procedure involves selecting the 0.25um technology in Microwind, drawing the n diffusion, polysilicon gate, contacts and metal layers, and simulating the static and dynamic behavior of the designed MOSFET. Screenshots of the different layout steps and output characteristics are provided.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    of 6

    Experiment No: - 4

    Date: - 04/10/2010

    Name of the Experiment: -

    Familiarization With Layout Tool ( Microwind ) &


    Design Rules.

    Objective:-
    (i) Draw the Layout of a n-channel MOSFET with width 0.5um
    and length 0.25um using Microwind and simulate it for
    MOS characteristics curves.

    (ii) Generate the netlist file.

    Procedure:-
    (i) By double clicking on Microwind icon, open microwind. We
    will see a black window with grid points and a palette on
    the right side with different layers for layout assigned with
    different colors. The layout window features grid scale in λ
    units.

    (ii) Selecting the technology: Go to file  Select Foundry.


    From the ‘rules’ folder, select the cmos025.rul file. The
    0.25um technology thus gets selected. This means 1 grid
    point spacing is λ =0.25/2=0.125um on the window.

    (iii) Select current layer into N+ diffusion by a click on the


    palette of the Diffusion N+ button. Draw an n-diffusion box
    at the bottom of the drawing as in Figure 1. N diffusion
    boxes are represented in green. The width of this n-
    diffusion box is 0.5um = 4 λ. The length of the box is 14 λ.

    (iv) Now select the Polysilicon from the palette. Fix the first
    corner of the box with the mouse. While keeping the
    mouse button pressed, move the mouse to the opposite
    corner of the box. Release the button. This creates a box in
    polysilicon layer as shown in Figure2. The box width should
    not be inferior to 2 λ =0.25um, which is the minimum
    width of the polysilicon box. Thus the length of the
    transistor is 0.25 um.

    (v) Draw the contact layer of 2 λ*2 λ by selecting contact from


    the palette.

    (vi) Draw the metal layer as shown in fig: 3.This completes the
    drawing of the MOSFET.

    Fig1: The n diffusion box drawn.

    Fig2: The polysilicon box drawn.


    Fig3: The Layout of the MOSFET.

    Vertical Aspect of the MOS:


    Click on this icon to access process simulation (Command Simulate ->
    Process section in 2D). The cross section is given by a click of the mouse at
    the first point and the release of the mouse at the second point.

    MOS Static Characteristic:-


    Click on MOS characteristics icon. The screen shown in Fig 4 appears. It
    represents the Id/Vd static characteristics of the nMOS device. In addition it
    shows the length and width of the transistor formed is 0.5um and length is
    0.25um.
    Fig4: MOS characteristics of the drawn MOSFET.

    Dynamic MOS Behavior:-


    (a) Apply a clock to the gate. Click on the Clock icon and then, click on the
    polysilicon gate. The clock menu appears again. Change the name into
    << clock 1 >> and click on ok to apply a clock.

    (b) Apply a clock to the drain. Click on Clock icon, click on the left
    diffusion. The clock menu appears again. Change the name into <<
    clock 2 >> and click on ok to apply a clock.

    (c) Watch the output: Click on the Visible icon and then, click on the right
    diffusion. Click Ok. The Visible property is then sent to the node. The
    associated text << s1>> is in italic, meaning that the waveform of this
    node will appear at the next simulation.

    Click on File  Save as. Anew window appears, into which you
    enter the design name. Type my MOS. Then click ‘Save’. The
    design is saved under that file name.
    Fig5: Analog Simulation of the MOS Device.

    Discussion:-
    When the gate is at zero, no channel exists so the nodes s1 is disconnected
    from the drain. When the gate is on, the source copies the drain. It can be
    observed that the nMOS device drives well at zero but poorly at high voltage.
    The highest value of s1 is around 2.0V that is Vdd minus the threshold
    voltage. This means that the n-channel MOS device do not drives well logic
    signal 1.

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