Royal Institute of Technology (KTH)

School for Information and Communication Technology (ICT)

IL1203/2B1430 LSI Design Laboration 3 State Machine Physical Layout with MicroWind

Student Name: ............................................................................. ID number: ............................................................. Date of Laboration: ............................................... Teacher: ........................................................................ HT2009
2009-08-11

O. Thessn L. Hellberg

Lab contents
Introduction to the Laboration. Physical design with the layout editor MicroWind Section 1
Creation of data structure and start of program MicroWind

page
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User domain, Account. Start of Microwind on PC. Work directory. Copying of files from the web. Choice of CMOS teknology - Select Foundary. Insertion a layout from the CMOS Cell Library - File>Insert Section 2 Laboration tasks Layout for two in serie connected inverters Check of design rules - Design Rule Checker Name assignment for nodes to be visible at simulation - Visible

5 6

Section 3

Simulation of two in serie connected inverters. Specifying a clock signal 6 Choice of MOS model (Level 3) and Power supply value (2.5V) for simulation. Extraction of netlist for circuit simulation - Extract Simultion of inverters - Simulate. Voltage vs. Time (Default) 7 Determination of pulse delay time (Simulate > Delay) between two nodes with Microwind 8 Determination of node capacitance (View Node) Layout. Generation of Pads. Connection of two inverters in serie with a Pad 9 Unbuffered driving a capacitive load. Determination of node capacitances (View Node) Simultion inverters (without buffer driver) with output port connected to Pad. Voltage vs Time 9 Pulse delay times when the output signal node is capacitively loaded by a Pad 10 Buffered driving with a capacitively loaded Pad. Inverter in serie with a buffer stage 11-13 consisting of channel width up scaled inverters . Determining node capacitances and determination of the parameters x = CL/C1 and the scaling faktor u Simulation of inverters with a buffer stage - Voltage vs Time Plot of node signals and determination of pulse delay between the nodes s0, s1, s2 and s3 FSM. Logic synthesis for a synchronously clocked sequential circuit, bit-sequence detector Introduction to laboration tasks of Section 9, 10, 11 and 12. FSM. Simulation of the combinational logic for generation of the output signal u FSM. Simulation of the combinational logic which generates the variable q1next. FSM. Simulation of a Master Slave D-flip flop FSM. Simulation of the complete state machine for the bit-sequence detektor 14-15 15 16

Section 4

Section 5

Section 6

Section 7

Section 8

Section 9 Section 10 Section 11 Section 12

17 18 19-21 22

Pre-study and preparation 1 Wiring of the combinational logic parts with 2-level NAND-NAND-logic 23 Pre-study and preparation 2 Truth table for the state machine combinational logic 24 Enclosure Appendix Appendix FSM. Design synthsis solution for the bit-sequence detector 25-27 Circuit connection diagram for the Finite State Machine (FSM) 28 Layout print outs for Section 4 and Section 6 29 Print out of Bit-Sequence Detector Layout. The msk-layout file: NotreadyFSM.MSK 30

O. Thessn L. Hellberg -- 2009

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Introduction to the Laboration

The laboration is designed to work with 0.25 m CMOS technology. The first thing to do after having started Microwind is to select foundry. Secondly you will insert the layout of two CMOS inverters in serie and check that design rules for the 0.25m CMOS process have been followed by using the built-in design rule checker. Then you can extract the circuit netlist for the circuit simulator and view the netlist. The circuit of the two inverters layout may then be simulated and this should result in a plot of a signal voltage vs time graph Note: The command Run simulation will automatically start to extract the netlist but you can do it once to view the netlist first. The purpose with the laboration is to show characteristic behaviour of the CMOS inverter, unbuffered and buffered, with different capacitive load and how you can design buffers to improve the drive capability. You will also orientate yourself in a given layout of a sequential digital circuit, a bit-sequence detector, not yet finished with respect to connection wiring, a task that you will have to solve. This should give you some experience with the IC layout editor in MicroWind.

Microwind
Microwind is a computer-aided design program for layout editing, circuit extraction and circuit simulation of micro electronic circuits on a physical layout level. The implemented version of Microwind (2.6k) program runs on Windows XP (Note: This is not the most recent release of Microwind, but has worked well for our education). The development of Microwind was initiated by professor Etienne Sicard in France at lInstitut National des Sciences Appliques de Toulouse (INSA). The program has been used to a large extent worldwide for introductory courses in CMOS design both for engineers in industry as well as university students in many countries. The layout editor contains a large number of commands for integrated circuit layout editing, for example copy, cut, past, duplicate, stretch, move etc. commands which will be used in later laborations and for your project work. The IC layout can be shown in different so called views. You can for example plot the transfer characteristic of MOS transistors and view 2-dimensional cuts through the geometry of semicomductor devices you made in a layout. The layout program contains a built-in circuit simulator similar to the wellknown Spice circuit simulator. Therefore, to make a circuit simulation in MicroWind, you need no external simulator. With the built-in circuit simulator you will be able to simulate a circuit model of the designed layout, after you have done a circuit extraction from your layout that will generate a PSpice netlist from the physical layout. The built-in simulator contains a model library for circuit simulation with a number of different geometrical and physical model aspects (classified by a LEVEL number) for the descriptions for MOS transistors. The circuit simulator calculates voltages and currents as a function of time using real circuit delays calculated based on layout geometry and component data extracted from the geometric description and the model for the physical layout. The power consumption for a given circuit with given input signal stimuli can be calculated as well. The circuit simulator can manage a wide spectrum of technologies from 1.2 m down to 70 nm.

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There is a function in Microwind to show MOS characteristics. The function has a user friendly interactive interface and is started with command: Start> MOS characteristics The function lets you change model parameter values and find out the effect of these changes for example for current vs voltage characteristics ID-VDS, ID-VGS or threshold voltage Vt vs channel length (L). For example using model LEVEL 3 the changeable parameters are : VTO (Long channel threshold voltage[V]), LD (Lateral diffusion into channel [m]), U0 (Mobility [cm2/ Vs]), TOX (Oxide thickness[m]), PHI (Surface potential[V]), GAMMA (Bulk threshold parameter[V]), KAPPA (Saturation field factor[V-1]), THETA (Mobility degradation factor[V-1]),VMAX (Maximum drift velocity[m/s]), NSS (Surface state density[atoms/cm2]). Running Microwind under Windows XP operating system will show a main menu row with submenues on top of the main screen (Figure 1). A submenu may contain several commands with options for example to select foundry (a CMOS fabrication process ), to insert a layout from a mask file and to edit the layout with commands like copy, cut, past, duplicate, move etc. In the palette you will find contact commands for connecting different layout layers, a MOS device layout generator to create transistors of N- and P-type as well as a pad generator. The 3D-viewer offer you a tool to learn to understand deep submicron technology i.e. structures of MOS transistor circuits where the channel length L of the individual transistors (roughly the distance between drain and source) is in the nanometer range with lithography < 0.5 m. With the 3D-viewer you can view the step-by-step fabrication of an arbitrary chosen part of the layout for example how contacts are manufactured, how metal layers are made or how a polysilicon gate of the self-alignment type is fabricated. The 2D-viewer of Microwind is a tool which is useful for understanding the building up of the oxide structure. You can zoom the layout to study oxide and lateral (surface) MOS structure. The electric signals, power supply voltages VDD and VSS and the clock signals are shown in the 2-D view.A manual for Microwind can be downloaded from the WEB. This manual contains MOS theory and MOS model parameter information.

The Microwind display window at initialization stage with a layout of a CMOS inverter is shown in Figure 1. The main menu is located at the top of the window. The menues (See Figure 3a) are File, View, Edit, Simulate, Compile, Analysis and Help. The submenu of the File menu in Figure 1 shows that you may choose to open a new layout file (New) or open an existing layout file (Open), insert a stored layout in the work area window (Insert) where you are creating a new design, select foundry i.e. the lithography of the technology (Select Foundry), save changes made to the layout (Save layout), save the layout with a new name (Save As) and finish the execution opf the program (Leave MicroWind).

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Figure 1

In a row below the main menu you find a number of icons for execution of commands that are useful and most frequently used (Figure 2). When you move the mouse arrow over an icon you will see a text that tells you which command the icon represent. The icon list in Figure 2 represents in order from the left side the following commands: Open File, Save this file, Draw Box, Delete some Layout, Copy elements, StretchMove, Zoom In (enlarge an object), Zoom Out (diminish an object), View All, View electrical node, Run Simulation, Measure distance, 2D vertical cross-section, Process steps in 3D, Design Rule Checker, Add Text to Layout, Connect layers, Simulate MOS Characteristics, Show Palette, See upper/lower/left/right layout.

Figure 2 Icon menu with useful commands in Microwind

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Figure 3a) Submenues of menu: File, View, Edit, Simulate, Compile, Analysis and Help The palette shown to the right in the display window (Figure 1) can be fetched from the palette icon or with the View command of the main menu : View >Palette of Layers The top row of the palette (See Figure 3b) shows icons usable for generating contacts. Starting from the left the icons represents: Contact metal/poly, Contact N+diff/Metal1, Contact P+diff/Metal1, Contact Metal1/Metal2, Contact metal/Metal2 The transistor icon of the second row from the top of the palette in left position represent a MOS layout generator. With this command (icon) you can open a second command level, where you can choose to create several kinds of structures for the layout you are working with using the new commands : Pads, Inductor, Contacts, MOS-transistor, Path, Logo, Bus, Res, Diode, Capa.

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Figure 3b Palette The palette shown to the right in the display window (Figure 1) can be fetched from the palette icon or with the View command of the main menu : View >Palette of Layers The top row of the palette (See Figure 3b) shows icons usable for generating contacts. Starting from the left the icons represents: Contact metal/poly, Contact N+diff/Metal1, Contact P+diff/Metal1, Contact Metal1/Metal2, Contact metal/Metal2 The transistor icon of the second row from the top of the palette in left position represent a MOS layout generator. With this command (icon) you can open a second command level, where you can choose to create several kinds of structures for the layout you are working with using the new commands : Pads, Inductor, Contacts, MOS-transistor, Path, Logo, Bus, Res, Diode, Capa. Command pads gives you possibility to create individual pads of arbitrary size or a rectangular sized box of pads for the whole chip.Command inductor generates a coil (inductance) in a metal layer. Command contacts offers a possibility to layout the four types of contacts mentioned above as well as different combinations of metal-to-metalcontacts.Command MOS gives a possibility to generate a PMOS or NMOS transistor of arbitrary channel length (L) and channel width (W) and then insert the transistor in your layout. Command path will generate individual metal wires which can be laid out in different geometrical forms in your layout. Command logo will generate a text of your choice in a metal layer for example to identify your chip. Command bus generate and place an arbitrary number of metal wires horizontally in parallel or split up in several horizontal-vertical parts. Command Res gives a possibility to generate a resistor with a certain resistance value. Command Diode generates diode contacts in an arbitrary number of rows and columns. Command Capa generates the layout of a capacitor between poly/poly2 or between metal layers of your choice.

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The icons of the third row from top of the palette represent in order starting from the left: Vdd Supply, High voltage Supply, Ground, Add a clock, Add a pulse, Add a sinus, Visible node. The lower part of the palette, a column with a number of layers and two contacts, is used for the specification of which layers (and contacts) you choose to work with at the time beeing in your layout. Note: When you want to modify parts of a layout on a certain layer, it is sometimes very much an advantage to protect parts of the layout on other layers in the neighbourhood in order to be able to delete some parts on the layer you had choosen to modify and at the same time avoid to modifying some parts you wanted to be untouched What you can do in such a case is to inactivate those layers you do not want to be changed. Command Protect all and command Unprotect all are very usable now when you want to protect many layers. They can be found on the submenu of menu Edit. Use first the command: Edit > Protect all and then, with the palette on the display window, you will see that the key beside all layers (and the two contacts) change colour to red. Then push the red key beside the type of layer you want to work with. It should then change colour to gray which indicate that the layer is possible to edit. After you have made the modifications give the command: Edit > Unprotect all and all layers will be unprotected again and you can work again with your layout tool.

User account, ready made files for the problems and start of Microwind version 2.6k program
Section 1 User account and start of Microwind version 2.6k :
The computers in the laboratory work with the Windows XP operating system. a) In the first place you must activate your PC account to be allowed to use KTH.SE computer domain. To activate means in this case that You sign at Helpdesk, which you will find in Kista on the main entrance level 4 in the Forum Building, a responsibility contract that you accept to follow the rules for using the computer network in Kista.

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Laboration experiments
The following text comprising Section 2 until 8 considers the problem to drive a large capacitive load. In Section 8 until 13 you are given the layout (in an .MSK file) of a synchronously clocked sequential circuit, a finite state machine (FSM). The layout of the circuit is not completely finished with regard to wiring, and you have to finish the wiring and make a simulation to show that the behaviour specification was obtained.

Section 2 Two inverters connected in serie

a) Choose in the first place by command File>Open as your work area the directory H:\ LSIWORK\LAB3\Microwind Workspace vt2006. b) Use again (in your work area) the command File>Open to open the layout library CMOS Buffer Design Problem. Mark all files of this folder and to copy the MSK files ,the ready made layouts, to your work area. c) Select now (i.e. mark) from the work area the file called Invs0s1.MSK and load this layout into the display window of Microwind by using the command File>Insert The layout of Invs0s1.MSK should show two inverters connected in serie.

Minimi inverter to drive the output pad A In 1 CIn s0 C0 B 1 s1 C1 = CL

Pad

Minimi inverter connected to drive node s0 with a not ideal signal source

Pad constitute a large capacitive load for node s1

Figure 4 : A ideal clock signal (= voltage source In with source resistance RS = 0 ) is connected to the input of a minimi inverter A with output signal node s0. Drive voltage of node s0 from the non-ideal source i.e. inverter A with a source resistance RS > 0 , is connected to the minimi inverter B with output signal node s1.

A simulation of the layout (circuit ) with the two inverters connected in serie has been prepared by connecting a clock signal (In) to the input port and give the node after the first inverter the name s0 and the output node the name s1. The nodes s0 and s1 are defined as Visable and will therefore be plotted. Note: See node attribute on the third row from top in the palette (Figure 3b)

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Section 3 Simulation of two inverters connected in serie

The clock signal of the input port is specified to be a periodic square wave voltage: Time high = Time low = 1 ns and Rise time = Fall time = 0.01 ns. Low level = 0.00 V and High level = 2.50 V.

Contact

VDD
PMOS transistor

N-well

PMOS channel width Wp

IN

UT
NMOS channel width Wn

Input

Output

VSS

NMOS transistor

a)

b)

clock signal A
In

B
s0

1
CIn

1
C0

s1

no loading pad
C1

c)

Figure 5 : a) Schematic of CMOS inverter with the MOS transistor channel width Wp of PMOS respectively Wn of NMOS. Wp / Wn = b) Layout of CMOS inverter with PMOS- and NMOS transistor. c) Two CMOS minimi inverters connected in serie. Not loaded output s1.

Note.: When you use the command Simulate>Run simulation ... an extraction of the netlist for a circuit simulation will automatically be done from the layout

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Give command: Simulate > Run simulation ... Choose voltage vs time

Diagram 1 : Input signal. A ideal voltage generator (Rs = 0 ohm)

Draw the input signal In in the diagram! Write axis scales and variable name !

Diagram 2 : s0 signal. A non-ideal voltage generator (Rs > 0 ohm)

Draw the signal s0 in the diagram! Write axis scales and variable name !

Diagram 3 : s1 signal (output signal with NO pad)

Draw the output signal s1 in the diagram! Write axis scales and variable name !

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Definition of pulse delay times

In the figure below the pulse propagation delay times of an inverter are defined. You will now with Microwind measure the pulse propagation delay times for the signa propagation from node s0 and to node s1. VIH 0,5 (VIH + VIL ) tpHL tpLH VIL VOH 0,5 (VOH + VOL ) VOL Figure 6 : Definition of the pulse propagation delay times tpLH and tpHL Note: The mean pulse propagation delay time td = ( tpLH + tpHL )/2 . Index LH in tpLH indicate that the output signal changes from low (L) to high (H) level. Index HL in tpHL indicate that the output signal changes from high (H) to low (L) level. Measure the pulse propagation delay time from s0 to s1 . Adjust in Simultion window parameter Delay : Start node= s0 and Stop node= s1. tpLH = .................... and mean value td = ( tpLH + tpHL )/2 = tpHL = .................... ........................

Input signal Output signal

Measure the capacitances (use View > View Node) of circuit nodes In, s0 and s1: Note.: Notation f = 10-15 ( femto) ( fF = femtofarad) Answere: CIn = ................ fF C0 = ................ fF C1 = ................ fF

Task: Select the file named Invs0s1Cuts.MSK and insert the layout into the display window of Microwind. The layout of Invs0s1Cuts.MSK shows the two inverters connected in serie. The wiring of the layout is broken on some places and you can therefore with command ( View > View Node ) See the Navigator window! Question: Mainly, which capacitances constitute capacitance C0 of Figure 5c) ? Hint: Measure capacitance of PMOS- and NMOS- transistor outputs of inverter A and capacitance of PMOS- and NMOS- transistors of input of inverter B:s ingng. Answere : ........................................................................................................................ ........................................................................................................................

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Section 4 Unbuffered output -- capacitively loaded with pad

Insert the file Invs0s1pad.MSK into the display window. The output of the inverter B is now capacitively loaded by a pad. Measure the height (h) and width (w) of the pad and report the result in m. Answere: Pad height h = ...................... m and width w = ........................ m

A
In

B
s0 C0

1
CIn

s1 C1 = CL

Pad h x w m

Figure 7: CMOS inverter B driving a capacitively loading pad on the output

Measure with the pad connected the node capacitances ( View > View Node) of the two circuit nodes s0 and s1 : Answere: C0 = ............................ fF C1 = ............................. fF

Section 5 Simulation of unbuffered output -- capacitively loaded with pad

With a pad connected to the output you shall now simulate the behaviour of the circuit. Note.: The frequency of the pulse signal source in the file Invs0s1pad.MSK (Figure 7) has been lowered in order to increase the time for charging/discharging to obtain a for the output signal a more pulseformed look (then what otherwise have been the case).The time scale will then be changed compared to experiment in Section 3, Diagram 3 Give the command: Simulate > Run simulation... Choose voltage vs time Diagram 4 : Input signal. A ideal voltage generator (Rs = 0 ohm)

Draw the input signal In in the diagram above ! Write axis scales and variable name !

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Diagram 5 : s0 signal. A non-ideal voltage generator (Rs >0 ohm)

Draw the signal s0 in the diagram above ! Write axis scales and variable name ! Diagram 6: s1 output signal (WITH capacitively loading pad)

Draw the signal s1 in the diagram above ! Write axis scales and variable name ! Measure the pulse propagation delay time for inverter (B) from node s0 to the output (s1) when the output is capacitively loaded with a pad (i.e. large metal area). The pulse propagation delay times from node s0 to node s1 are : tpLH = ......................... tpHL = ........................

Compare the results of values of pulse propagation delay times for the two cases with and without a loading pad (See Section 3 and Section 5 ) Comment: .................................................................................................................... ....................................................................................................................................... Question: How would the form of output signal s1 change with the pad connected, if the time period and pulse width of the input signal source had been identical as for the case when the output node was not loaded with a pad ?

Answere :.................................................................................................................... ..................................................................................................................................

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Section 6 Design of a buffer stage (inverter chain) to drive a capacitively loaded pad (= a large capacitance compared to the capacitance that a minimi inverter would drive for fanout = 1).
M stages N-stages buffer (N = M + 1 )

A
In 1 CIn
fanout=1

B
s0 C0 1 s1 C1 u s2 C2 u2 sN-1 CN-1 uN-1 sN Out CN = CL

Figure 8 : CMOS inverters with a factor u gradually wider channel. This design is supposed to result in a reasonable pulse delay when diving a large capacitance CL connected loading the output. The capacitance CL is assumed to be large compared to input capacitance C0 of minimi inverter (B). Note: Minimi inverters A and B gives well defined capacitances in node s0 and a signal source with resistance RS > 0 .

Theory: A minimization of the pulse propagation delay time when driving a capacitive load of a pad can be realized by a design which results in equally large pulse propagation time of inverters in a chain of gradually larger inverters (Figure 8). The total pulse propagation time will then be the sum of a number (N) equally large delays. The design of the N=M+1 in serie connected inverters, the minimi inverter (B) + M extra buffer inverters, is done in such a way that each pair of two following in serie connected inverters will increase the drive capability with the same scaling factor (u) from the input where the first inverter has a capacitance C0 until the load with capacitance CL. Let us determine the scaling factor u, given that the load capacitance CL and the minimi inverter gate capacitance C0 are known and that the implementation of the buffer circuit is going to be done with N inverters including the from the one minimi inverter (B) that was given from the start. Definitions and assumptions: (I) Define number x as the ratio between the capacitance value CL of the load and the gate capacitance value C0 of the first inverter (B) : x = CL/C0 (See Figure 8) (II) Suppose the buffer chain is going to be designed with N inverters and that for two following inverters the channel width of the PMOS- and NMOS-transistors gradually shall increase with the scaling factor u. (III) Suppose the gate capacitance Ck of inverter number k is directly proportionel to the width-length ratio Wk/Lk of a transistor of inverter k, where Wk = channel width and Lk= channel length.

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Now it is true that {Wi/Li}/{Wi-1/Li-1} = u for every index i (i = 0,....,N-1) . Often the channel length Li+1 = Li > Lmin = determined by lithography. The ratio between output and input capacitance for each inverter stage is then approximatively: Ci+1/Ci = u The output is loaded with the capacitance : CN = CL A relation between x and u can now be formulated ( def. & assump. (I) and (II) ). First use the approximation above, thus: for i = 0,1,2,...,N-1 applies Ci+1/Ci = u . A multiplication of using this ratio N times can be written : C1/C0 *C2/C1 * C3/C2 * C4/C3 *......* CN-2/CN-3 *CN-1/CN-2 * CN/CN-1 = uN Pairwise division gives us an expression for the drive capability = uN : uN = CN/C0 , which can be written (def. & assump. I, II, III) : uN = CL/C0 . According to the definition (I) x = CL/C0 so we arrive at the formula: x = uN When the number of inverter stages N has been determined in advance the scaling faktor u can be calculated from the formula : ln(u) = ln [(x) /N] or expressed with capacitances : ln(u) = ln [(CL/C0)/N]
Buffer stage N = 3 ( N = M + 1 = 2 +1 = 3)

I0
In 1 CIn s0

I1
1 s1 C1

I2
u s2 C2 u2

I3
s3 C3 = CL

Pad

C0

tpLH och tpHL from node s0-to-node s3

Figure 9 : CMOS inverter chain with capacitively loading pad on the output

Design of buffer stage (inverter chain)

Load (insert) the file Bufpad_s0123.MSK. The layout describes the circuit shown in Figure 9. In the layout file Bufpad_s0123.MSK the minimi inverter driving the large pad has been supported with an extra buffer drive stage. Measure with the pad connected to the output the node capacitances ( use command View Node) of the four circuit nodes s0, s1, s2 och s3: Answere: C0 = ............ fF; C1 = .............fF; C2 = ............. fF; C3 = ............fF; (Note: C3 is mesured here. Below is assumed pad cap. value dominates : CL = C3 ) Calculate scaling factors : u10 = C1 / C0 = ............times ; u21 = C2 / C1 = .............times ; u32 = C3 / C2 = ............ times ; umedel = ( u10 + u21 + u32 ) / 3 = .............times Assume pad dominates load capacitance ( CL = C3 ) and calculate ratio x = CL/ C0 ! Answere: x = CL/ C0 = ...................... times; - 14 -

For the layout applies: N = M + 1 = 2 +1 = 3 (two extra inverters + mini inverter (B)) With N = 3 and the x-value of the measured capacitance ratio CL/ C0 you can now determine the real scaling factor ur from expressiont: ln ( ur ) = ln [(CL/ C0) /N] . Measurement based real scaling factor : ur = eln [(CL/ C0) /N] = .................. times; Measure for the inverters I1, I2 and I3, the channel width Wp of the PMOS transistor respectively Wn of the NMOS transistor : Wp1 = ............... m; Wn1 = .................. m; Wp2 = .............. m; Wn2 = .............. m; Wp3 = ............. m; Wn3 = ................ m; Measure for inverter I3 and I2 from the layout the geometric values of the ratio between the PMOS transistors channel width (scaling factor): u32 = Wp3 / Wp2 = ................ times; Measure likewise for inverter I2 and I1 from the layout the geometric values of the ratio between the PMOS transistors channel width (scaling factor): u21 = Wp2 / Wp1 = ................ times; Comment: ............................................................................................................ For design of the inverter buffer chain to drive capacitively loading pad, the number of extra inverters was chosen to M = N-1 = 3-1=2 and the channel width ratio (= scaling factor Wp,i+1 / Wp,i )to u = 4 The real value of the scaling factor u, i.e. the value (ur ) which for the given layout was calculated based on measured ratio of CL/C0 will give a value which differ somewhat from the aimed at design value of u. Calculate for u = 4 the relative error of value u ( procent; %) after having measured the capacitance of of node s0 and node s3 ! Answere: The procentual relative error of value u : {| u - ur | / u } = .................. % Comment: ............................................................................................................ Determine the ratio between the P- and N-MOS transistors channel widths: 1 =Wp1 / Wn1 = ..................times ; 2 = Wp2./.Wn2 = ..................times;

3 = Wp3 / Wn3 = ........................times ; Comment: ........................................................................................................

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Section 7 Simultion of buffered driven capacitively loading pad

For the layout with buffer stages we will now make a simulation Give command: Simulate > Run simulation ... Choose voltage vs time Diagram 7 : Input signal. A ideal voltage generator (Rs = 0 ohm)

Draw the input signal In in the diagram above ! Write axis scales and variable name !

Diagram 8 : s0 signal. A non-ideal voltage generator (Rs >0 ohm)

Draw the signal s0 in the diagram above ! Write axis scales and variable name !

Diagram 9 : s1 signal

Draw the signal s1 in the diagram above ! Write axis scales and variable name !

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Diagram 10 : s2-signalen.

Draw the signal s2 in the diagram above ! Write axis scales and variable name !

Diagram 11 : s3 output signal (buffered drive of capacitive pad)

Draw the signal s3 in the diagram above ! Write axis scales and variable name ! Measure the pulse propagation delay times in each stage of inverters i.e. s0-to-s1, s1-to-s2 and s2-to-s3. Pulse propagation delay times from s0-to-s1 : tpLH = .................... ; tpHL = ....................; td = ( tpLH + tpHL )/2 = ........................ Pulse propagation delay times from s1-to-s2 : tpLH = .................... ; tpHL = ....................; td = ( tpLH + tpHL )/2 = ........................ Pulse propagation delay times from s2-to-s3 : tpLH = .................... ; tpHL = ....................; td = ( tpLH + tpHL )/2 = ........................ Pulse propagation delay times from In-to-s0 : tpLH = .................... ; tpHL = ....................; td = ( tpLH + tpHL )/2 = ........................

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Section 8 Logic synthesis for a synchronously clocked sequential circuit

Sequential circuit
Clk

Figure 10 : Bit-sequence detector I this Section the design problem given is to synthesise a bit-sequence-detector. The specification and a solution to the theoretical part of the design propblem is given in Appendix. In the layout library CMOS Bitsequence Detector FSM you will find a number of ready made layouts of the combinational logic to generate the output signal u, to drive the data inputs of the flip-flops D1 =q1+ and D0 = q0+ . There you will also find a MSK-file for a D-flip flop as well as a MSK-file which describes the complete Bit-sequence detector. Note: In the MSK-filen which describes the complete Bit-sequence detector (NotreadyFSM.MSK) the wiring is NOT READY. It will be Your Task to finish the wiring in such a way that your circuit will behave according to specifications given.

You will also verify with simulations the behaviour of some smaller layout parts (MSK files given) which are used to build the complete circuit: the D-flip flop, the combinational logic for signal q1+ and the logic to generate the output signal u.

When You have completed the wiring of the detector (the file NotreadyFSM.MSK with your additional wirings) you will have to simulate Your ReadyFSM.MSK and show a signal plot from which you must be able to interpretate the behaviour of the circuit and draw the state transition graph of the sequential circuit.

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Section 9 Simulation of combinatorial logic for output signal u

Enter the layout from file Kombu.MSK with the layout of the combinational circuit which generates the output signal u. The file is found in the directory with layout files for the state machine (CMOS Bitsequence Detector FSM ).

Figure 11 :

The layout of file Kombu.MSK

Write the boolean expression of the output signal u. Answere : u = ........................................................................................

Simulate the layouten Kombu.MSK. Fill in the value of the output signal u in the truth table for the layout (combinational circuit) shown above (Figure 11) with input signals q1and q0 . Truth table of Kombu.MSK q1 0 0 1 1 Table 1: Result of simulation q0 0 1 0 1 u

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Section 10 Simulation of the combinatorial logic generating signal q1+

Enter the layout from file Kombu1next.MSK with the layout for the combinational circuit which generates signal q1+ . The file is found in the directory with layout files for the state machine (CMOS Bitsequence Detector FSM ).

Figure 12 :

The layout of file Kombq1next.MSK

Simulate the layouten Kombq1next.MSK. Fill in the value of the signal q1+ in the truth table for the layout (the combinational circuit) shown above (Figure 12) with input signals x, q1 and q0 . Truth table of Kombq1next.MSK x 0 0 0 0 1 1 1 1 Table 2: Result of simulation q1 0 0 1 1 0 0 1 1 q0 0 1 0 1 0 1 0 1 q1+

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Section 11 Simulation of Master-Slave flip-flop

Enter from file Dff.MSK the layout of the MS D-flip flop. The file is found in the directory with layout files for the state machine (CMOS Bitsequence Detector FSM ). The MS D-flip flops are synchronously clocked (clock) and each D-flip flop has one data output (Dout) .

Figure 13 : The layout of file Dff.MSK for the MS D-flip flop

Simulate the MS D-flip flop: Simulate > Run simulation... Choose Time scale= 50ns and Step = 4ps Note: If N-well region is floating then Choose Polarize Nwell to VDD

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Draw signals clock, insignal, Halfway and Dout in diagrams 12,13,14 and 15 below ! Diagram 12 : clock-signal

Diagram 13 : insignal-signal

Diagram 14 : Halfway-signalen.

Diagram 15 : Dout-signalen

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Determine the time of one clock period T = .........................................

The output signal Dout follows the input signal insignal ! --On which clock pulse edge (positive/negative) will the Master D-flip flop make the data signal ( insignal ) available to the Slave D-flip flop input (Halfway) ? Answere: ..............................................................

On which clock pulse edge (positive/negative) will the Slave D-flip flop make the data signal ( Dout ) available on the output ? Answere: ...............................................................

How large is the pulse delay (time) from the MS D-flip flop input (insignalen) to the output (Dout) of the MS D-flip flop ? (See layout Figure 13 page 21) : Pulse delay times from insignal to Dout

tpLH = ................................

tpHL = ................................

and mean value

td = ( tpLH + tpHL )/2 =

........................................

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Section 12 Wiring and simulation of Bitsequence Detector, FSM

Enter the layout of the entire bit-sequence detector from file NotreadyFSM.MSK where the wiring of the layout is NOT completely finished. The file is found in the directory with layout files for the state machine (CMOS Bitsequence Detector FSM ). (1) Save the file NotreadyFSM.MSK with the new name ReadyFSM.MSK (Save As). (2) Add to the layout necessary (missing) wires and contacts ! (3) After you have made the necessary changes, by adding wires and contacts in order to connect the combinational logic circuit to the flip-flops and for connection of the output, you have to check the design rules again ! Run the design rule checker : Analysis>>Design Rule Checker If the DRC-program detects errors in the drawn layout You have to correct the layout and run the DRC-program again (...and again) until everything is correct ! (4) Simulate the Finite State Machine....the corrected finished file ReadyFSM.MSK (5) Draw/complete the State Transition Graph (below) with the help of the result from the circuit simulation you made with the corrected finished file ReadyFSM.MSK

Figur: 14 : State transition graph corresponding to results of signal behaviour from Figure a circuit simulation with the corrected file ReadyFSM.MSK

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Pre-study and preparation

Pre-study and preparation 1 Wiring of the combinational logic parts. The layout ( See Figure 15 ) of the Finite State Machine is given but Not Complete. Prepare the wiring which you are going to add with Microwind by drawing needed connections in the plot of the layout which is shown below. Hint: Boolean expressions of signals (q1+och q0+ ) of the combinational logic feedback network and the output signal (u) of the finite state machine are found in the solution of the synthesis problem (See page 25-28).

Figure 15: In this layout print of the finite state machine you should draw the wiring to complete the connections of the combinational parts (file: NotreadyFSM.MSK)

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Pre-study and preparation 2 Truth tables for the combinational logic

Given boolean expressions for the combinational circuits (See solution page 25-28) the feedback circuit signals (q1+och q0+ ) and the output signal (u). Determine and enter a value of the output signal for each one of the combinational logic networks ! Truth table: q1+ = q1 q0 + x q0 x 0 0 0 0 1 1 1 1 q1 0 0 1 1 0 0 1 1 q0 0 1 0 1 0 1 0 1 q1+ Truth table: q0+ = q1 q 0 + x q0 + x q0 x 0 0 0 0 1 1 1 1 q1 0 0 1 1 0 0 1 1 q0 0 1 0 1 0 1 0 1 q0+

Truth table: u = q1 q0 q1 0 0 1 1 q0 0 1 0 1 u

Figure 16 : Truth tables for the combinational logic circuits of the FSM

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Appendix. Problem solution. Synthesis of the bit-sequence detector

x

Sequential circuit
Clk

Figure 17 : Bit-sequence detector

Specification of the behaviour of the Sequential circuit A synchronously clocked sequential Moore-machine is to be designed. The machine is going to work as a bit sequence pattern detector. The circuit must besides the clock signal (Clk) have a data input signal (x) and a data output signal (u). The data output signal (u) of the sequential Moore-machine shall respond by rising the output signal (u) to high logic level, u = 1, each third time when the input signal (x) becomes high (x =1). For all other time the output shall be low ( u = 0). The system shall be implemented with Master Slave D-flip flops (MS DFF) and with no more than four binary states Q = (q1, q0), where the variables q1 and q0 are output signals from DFF n:o 1 respectively DFF n:o 0. The data inputs shall be called D1 respectively D0 . The flip-flops are supposed to have complementary outputs, which means that besides the signals q1 and q0 output signals q1 and q0 available. The binary state machine coding must be choosen in the following way: A = (0, 0); B = (0, 1); C = (1, 1,); D = (1, 0). Assume that the state machine is in the state A, when the sequential circuit starts to receive the binary input data sequences.

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Solution of the synthesis problem The state transition graph of the sequential circuit is shown in Figure 18 x =1 (first one) A/0 Start x=0 B/0 x= 0

x =0

The meaning of states : A; zeroes ; u = 0 B; one one ; u = 0 C; two ones; u = 0 D; three ones; u = 1 The graph shows a Moore-

x =1 ( first one ) D/1 x =1 (third one) C/0

x =1 machine. (second one)

x=0

The state defines uniquely the output signal and the value on output signal u is written in respektively state. The value of the input signal x is written on the arrows.

Figure 18 : State machine transition graph

In the state table below all state transitions of the garph are shown on one hand in a table with the uncoded states ( Figure 19) : A, B, C , D and on the other hand in a table with the states coded (Figure 20) : A = (0, 0); B = (0, 1); C = (1, 1,); D = (1, 0) State table for uncoded states: A, B, C, D State A B C D present state Figure 19 x=0 A B C A x=1 B C D B State table for binary state coding: A = (0, 0); B = (0, 1); C = (1, 1); D = (1, 0) Q = (q1, q0) 0 0 1 1 0 1 1 0 x=0 0 0 1 0 0 1 1 0 Q+ Figure 20 x=1 0 1 1 0 1 1 0 1

next state

(q1, q0 )

(q1+, q0+

(q1+, q0+

Q+

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The present state is denoted Q = (q1, q0). The next state is denoted Q+ = (q1+, q0+ ). The next state Q+ is the state which the output signal Q enters a short time after the clock signal event. As is evident from the state table the next state Q+ depends on the present value of input signal x and the state of Q when the clock event occur.

In order to implement the system two MS D-flip flops are needed. With two flip-flops you can get four binary states Q = (q1, q0). The variables q1 and q0 are output signals from the flip-flops. The DFF:s are designed with complementary output signals, which means that besides q1 and q0 the signals q1 and q0 are available. The sequential circuit is synthesised using D-type flip flops. Truth tables of the combinatorial logic networks which are used to control the D-flip flops according to the behaviour shown in Table A, is shown for the coded states in Table B.

The Karnaugh maps used to generate the state variables q1+ and q0+ that is the logical values for the data inputs D1 and D0 for all binary combinations of x, q1 and q0 . The output signal u is uniquely determined by the state variables q1 and q0 only for the case q1 = 1; q0 = 0; that is in state D the output signal will be u = 1. Therefore the boolean expression for the output signal is: u = q1 q0 ( logic AND operation).

0 1

00 0 0

q1q0 11 01 0 1 1 1

10 0 0

0 1

00 0 1

q1q0 11 01 1 1 1 0

10 0 1

q1+ = q1 q0 + x q0

q0+ = q1 q 0 + x q0 + x q0

Figure 21 : Boolean expression for the data inputs of the DFF:s (D1 and D0) on a sum-of-product form (SP-form).

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x x

q1 q1 q0 q0 & & & & &

q1+

D1 q1 q1

& & & & q0+ D0 q0 q0

Clk

q1 q1 q0 q0
The schematic logic diagram above shows how to realise the logic circuit . The wiring in the given layout file (MSK-file) is Not Ready and must be added by you with the Microwind program. Those in the layout of the MSK-file (NotreadyFSM.MSK ) not yet existing wires and contacts in order to get a circuit with a behaviour that agrees to the specification of the design concern connections within the dotted rectangle in the schematic logic diagram above.

Figure 22 Connection diagram for the state machine

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Appendix Layout pictures for Section 4 and Section 6.

Figure 23 File name : Invs1s2pad.MSK See Section 4 page 9.

Figure 24 File name : Bufpad_s0123.MSK See Section 6 page 12. Note: The pad in figure 24 is of the same size as in figure 23, where the layout picture have been enlarged somewhat.

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Appendix Bitsequence detector layout

(Not finished)

The state machine layout is given, but Not Complete (See picture of layout below). Prepare the wiring which you are going to add with Microwind by drawing needed connections with a pencil in the plot of the layout which is shown below. Hint: Boolean expressions of signals (q1+och q0+ ) of the combinational logic feedback network and the output signal (u) of the finite state machine are found in the solution of the synthesis problem (See page 25-28)

Figure 25 File name : NotreadyFSM.MSK Use a pencil to draw missing wires and mark where contacts are needed. Use for example the poly layer (red) to draw wires with the layout editorn Microwind (Protect other layers with the help of the Palette ( See Figure 3 page 3).

...at the keyboard O.Thessn 090811 ( file: D:\---0 ENGLISH LSI LABTEXT for ht2009\ LSILAB3 after SUMMER 2009\English text_Lab3_FSM_ChipDesign_090811_q2.fm )

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