Fairchild - Semiconductor FDMC8884 Datasheet
Fairchild - Semiconductor FDMC8884 Datasheet
Fairchild - Semiconductor FDMC8884 Datasheet
May 2008
FDMC8884 tm
®
N-Channel Power Trench MOSFET
30V, 15A, 19mΩ
Features General Description
Max rDS(on) = 19mΩ at VGS = 10V, ID = 9.0A This N-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced Power Trench® process that has
Max rDS(on) = 30mΩ at VGS = 4.5V, ID = 7.2A
been especially tailored to minimize the on-state resistance. This
High performance trchnology for extremely low rDS(on) device is well suited for Power Management and load switching
applications common in Notebook Computers and Portable
Termination is Lead-free and RoHS Compliant
Battery Packs.
Application
High side in DC - DC Buck Converters
Notebook battery power management
Load switch in Notebook
Top Bottom
S Pin 1
S D 5 4 G
S
G D 6 3 S
D 7 2 S
D
D D 8 1 S
D
D
Power 33
Thermal Characteristics
RθJC Thermal Resistance, Junction to Case 6.6
°C/W
RθJA Thermal Resistance, Junction to Ambient (Note 1a) 53
Off Characteristics
BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 30 V
∆BVDSS Breakdown Voltage Temperature
ID = 250µA, referenced to 25°C 22 mV/°C
∆TJ Coefficient
VDS = 24V, VGS = 0V 1
IDSS Zero Gate Voltage Drain Current µA
TJ = 125°C 250
IGSS Gate to Source Leakage Current VGS = ±20V, VDS = 0V ±100 nA
On Characteristics
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 1.2 1.9 2.5 V
∆VGS(th) Gate to Source Threshold Voltage
ID = 250µA, referenced to 25°C -6 mV/°C
∆TJ Temperature Coefficient
VGS = 10V, ID = 9.0A 16 19
rDS(on) Static Drain to Source On Resistance VGS = 4.5V, ID = 7.2A 22 30 mΩ
VGS = 10V, ID = 9.0A, TJ = 125°C 22 30
gFS Forward Transconductance VDD = 5V, ID = 9.0A 24 S
Dynamic Characteristics
Ciss Input Capacitance 513 685 pF
VDS = 15V, VGS = 0V,
Coss Output Capacitance 110 150 pF
f = 1MHz
Crss Reverse Transfer Capacitance 76 115 pF
Rg Gate Resistance f = 1MHz 1.4 2.1 Ω
Switching Characteristics
td(on) Turn-On Delay Time 6 12 ns
tr Rise Time VDD = 15V, ID = 9.0A, 2 10 ns
td(off) Turn-Off Delay Time VGS = 10V, RGEN = 6Ω 15 27 ns
tf Fall Time 2 10 ns
Total Gate Charge VGS = 0V to 10V 10 14 nC
Qg(TOT)
Total Gate Charge VGS = 0V to 4.5V VDD = 15V 5.0 7.0 nC
Qgs Total Gate Charge ID = 9.0A 1.8 nC
Qgd Gate to Drain “Miller” Charge 2.2 nC
2. Pulse Test: Pulse Width < 300µs, Duty cycle < 2.0%.
3. Starting TJ = 25oC; N-ch: L = 1mH, IAS = 7A, VDD = 30V, VGS = 10V.
NORMALIZED
PULSE DURATION = 80µs VGS = 4V
DUTY CYCLE = 0.5%MAX VGS = 4.5V
20 2
VGS = 3.5V
10 1
VGS = 10V
VGS = 6V
0 0
0.0 0.5 1.0 1.5 2.0 0 10 20 30 40
VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT(A)
1.8 80
ID = 9.0A
DRAIN TO SOURCE ON-RESISTANCE
1.2 40
TJ = 125oC
1.0
20
0.8
TJ = 25oC
0.6 0
-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10
TJ, JUNCTION TEMPERATURE (oC) VGS, GATE TO SOURCE VOLTAGE (V)
40 60
PULSE DURATION = 80µs
IS, REVERSE DRAIN CURRENT (A)
VDS = 5V
1 TJ = 150oC
20 TJ = 25oC
0.1
TJ = 150oC TJ = 25oC TJ = -55oC
10
0.01
TJ = -55oC
0 0.001
0 1 2 3 4 5 0.0 0.2 0.4 0.6 0.8 1.0 1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
8 VDD = 20V
Ciss
CAPACITANCE (pF)
VDD = 15V
6
VDD = 10V
Coss
4
100
2
f = 1MHz
VGS = 0V Crss
0 50
0 3 6 9 12 0.1 1 10 30
Qg, GATE CHARGE(nC) VDS, DRAIN TO SOURCE VOLTAGE (V)
20 25
IAS, AVALANCHE CURRENT(A)
20
ID, DRAIN CURRENT (A)
10
VGS = 10V
TJ = 25oC
15
Limited by Package
TJ = 100oC 10
TJ = 125oC VGS = 4.5V
5
o
RθJC = 6.6 C/W
1 0
0.01 0.1 1 10 100 25 50 75 100 125 150
o
tAV, TIME IN AVALANCHE(ms) TC, CASE TEMPERATURE ( C)
60 100
P(PK), PEAK TRANSIENT POWER (W)
Figure 11. Forward Bias Safe Figure 12. Single Pulse Maximum
Operating Area Power Dissipation
2
DUTY CYCLE-DESCENDING ORDER
1
NORMALIZED THERMAL
D = 0.5
IMPEDANCE, ZθJA
0.2
0.1 PDM
0.05
0.02
0.1
0.01
t1
t2
SINGLE PULSE NOTES:
o DUTY FACTOR: D = t1/t2
RθJA = 125 C/W PEAK TJ = PDM x ZθJA x RθJA + TA
0.01
-3 -2 -1 0 1
10 10 10 10 10 100 1000
t, RECTANGULAR PULSE DURATION (s)
* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
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(a) are intended for surgical implant into the body or (b) device, or system whose failure to perform can be reasonably
support or sustain life, and (c) whose failure to perform when expected to cause the failure of the life support device or
properly used in accordance with instructions for use provided system, or to affect its safety or effectiveness.
in the labeling, can be reasonably expected to result in a
significant injury of the user.